LINER LTC2499 24-bit 8-/16-channel î î£ adc with easy drive input current cancellation and i2c interface Datasheet

LTC2499
24-Bit 8-/16-Channel
ΔΣ ADC with Easy Drive Input Current
Cancellation and I2C Interface
DESCRIPTION
FEATURES
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Up to Eight Differential or 16 Single-Ended Inputs
Easy Drive™ Technology Enables Rail-to-Rail
Inputs with Zero Differential Input Current
Directly Digitizes High Impedance Sensors with
Full Accuracy
2-Wire I2C Interface with 27 Addresses Plus One
Global Address for Synchronization
600nV RMS Noise
Integrated High Accuracy Temperature Sensor
GND to VCC Input/Reference Common Mode Range
Programmable 50Hz, 60Hz or Simultaneous 50Hz/
60Hz Rejection Mode
2ppm INL, No Missing Codes
1ppm Offset and 15ppm Full-Scale Error
2x Speed/Reduced Power Mode (15Hz Using Internal
Oscillator and 80μA at 7.5Hz Output)
No Latency: Digital Filter Settles in a Single Cycle,
Even After a New Channel Is Selected
Single Supply 2.7V to 5.5V Operation (0.8mW)
Internal Oscillator
Tiny 5mm × 7mm QFN Package
APPLICATIONS
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Direct Sensor Digitizer
Direct Temperature Measurement
Instrumentation
Industrial Process Control
The LTC®2499 is a 16-channel (eight differential), 24-bit,
No Latency ΔΣ™ ADC with Easy Drive technology and a
2-wire, I2C interface. The patented sampling scheme eliminates dynamic input current errors and the shortcomings
of on-chip buffering through automatic cancellation of
differential input current. This allows large external source
impedances and rail-to-rail input signals to be directly
digitized while maintaining exceptional DC accuracy.
The LTC2499 includes a high accuracy, temperature
sensor and an integrated oscillator. This device can be
configured to measure an external signal (from combinations of 16 analog input channels operating in singleended or differential modes) or its internal temperature
sensor. The integrated temperature sensor offers 1/30th°C
resolution and 2°C absolute accuracy.
The LTC2499 allows a wide common mode input range
(0V to VCC), independent of the reference voltage. Any
combination of single-ended or differential inputs can
be selected and the first conversion, after a new channel
is selected, is valid. Access to the multiplexer output enables optional external amplifiers to be shared between all
analog inputs and auto calibration continuously removes
their associated offset and drift.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
No Latency Δ∑ and Easy Drive are trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
TYPICAL APPLICATION
Data Acquisition System with Temperature Compensation
Integrated High Performance Temperature Sensor
2.7V TO 5.5V
5
4
TEMPERATURE
SENSOR
MUXOUT/
ADCIN
VCC
10μF
REF+
IN+
1.7k
24-BIT $3 ADC
WITH EASY DRIVE
IN–
0.1μF
SDA
SCL
REF–
2-WIRE
I2C INTERFACE
3
ABSOLUTE ERROR (°C)
CH0
CH1
•
•
•
CH7
CH8 16-CHANNEL
MUX
•
•
•
CH15
COM
2
1
0
–1
–2
–3
MUXOUT/
ADCIN
fO
OSC
2499 TA01
–4
–5
–55
–30
–5
20
45
70
TEMPERATURE (°C)
95
120
2499 TA02
2499fc
1
LTC2499
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
GND
GND
GND
fO
CA0
CA2
CA1
TOP VIEW
Supply Voltage (VCC) ................................... –0.3V to 6V
Analog Input Voltage
(CH0-CH15, COM) ....................–0.3V to (VCC + 0.3V)
REF +, REF – ...............................–0.3V to (VCC + 0.3V)
ADCINN, ADCINP, MUXOUTP,
MUXOUTN ................................–0.3V to (VCC + 0.3V)
Digital Input Voltage......................–0.3V to (VCC + 0.3V)
Digital Output Voltage ...................–0.3V to (VCC + 0.3V)
Operating Temperature Range
LTC2499C ................................................ 0°C to 70°C
LTC2499I..............................................–40°C to 85°C
Storage Temperature Range...................–65°C to 150°C
38 37 36 35 34 33 32
GND 1
31 GND
SCL 2
30 REF–
SDA 3
29 REF+
GND 4
28 VCC
NC 5
27 MUXOUTN
GND 6
26 ADCINN
39
COM 7
25 ADCINP
CH0 8
24 MUXOUTP
CH1 9
23 CH15
CH2 10
22 CH14
CH3 11
21 CH13
20 CH12
CH4 12
CH11
CH10
CH9
CH8
CH7
CH6
CH5
13 14 15 16 17 18 19
UHF PACKAGE
38-LEAD (5mm s 7mm) PLASTIC QFN
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD (PIN #39) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2499CUHF#PBF
LTC2499CUHF#TRPBF
2499
38-Lead (5mm × 7mm) Plastic QFN
0°C to 70°C
LTC2499IUHF#PBF
LTC2499IUHF#TRPBF
2499
38-Lead (5mm × 7mm) Plastic QFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS (NORMAL SPEED)
The l denotes the specifications which
apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution (No Missing Codes)
0.1V ≤ VREF ≤ VCC, –FS ≤ VIN ≤ +FS (Note 5)
Integral Nonlinearity
5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6)
2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6)
l
l
2
1
10
ppm of VREF
ppm of VREF
Offset Error
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 13)
l
0.5
2.5
μV
Offset Error Drift
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC
2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF , IN– = 0.25VREF
2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF , IN– = 0.25VREF
2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF , IN– = 0.75VREF
2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF , IN– = 0.75VREF
25
ppm of VREF
Positive Full-Scale Error
Positive Full-Scale Error Drift
Negative Full-Scale Error
Negative Full-Scale Error Drift
24
Bits
10
l
nV/°C
0.1
l
ppm of VREF/°C
25
0.1
ppm of VREF
ppm of VREF/°C
2499fc
2
LTC2499
ELECTRICAL CHARACTERISTICS (NORMAL SPEED)
The l denotes the specifications which
apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
Total Unadjusted Error
5V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V
5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V
2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V
MIN
TYP
15
15
15
ppm of VREF
ppm of VREF
ppm of VREF
Output Noise
2.7V < VCC < 5.5V, 2.5V ≤ VREF ≤ VCC,
GND ≤ IN+ = IN– ≤ VCC (Note 12)
0.6
μVRMS
Internal PTAT Signal
TA = 27°C (Note 13)
27.8
MAX
28.0
Internal PTAT Temperature Coefficient
UNITS
28.2
mV
93.5
μV/°C
ELECTRICAL CHARACTERISTICS (2X SPEED)
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution (No Missing Codes)
0.1V ≤ VREF ≤ VCC, –FS ≤ VIN ≤ +FS (Note 5)
Integral Nonlinearity
5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6)
2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6)
l
2
1
10
ppm of VREF
ppm of VREF
Offset Error
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 13)
l
0.2
2
mV
Offset Error Drift
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC
2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF , IN– = 0.25VREF
2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF , IN– = 0.25VREF
2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF , IN– = 0.75VREF
2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF , IN– = 0.75VREF
5V ≤ VCC ≤ 5.5V, VREF = 5V, GND ≤ IN+ = IN– ≤ VCC
25
ppm of VREF
Positive Full-Scale Error
Positive Full-Scale Error Drift
Negative Full-Scale Error
Negative Full-Scale Error Drift
Output Noise
24
Bits
100
nV/°C
l
0.1
ppm of VREF/°C
l
25
ppm of VREF
0.1
ppm of VREF/°C
0.85
μVRMS
CONVERTER CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
PARAMETER
CONDITIONS
Input Common Mode Rejection DC
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 5)
l
140
dB
Input Common Mode Rejection 50Hz ±2%
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 7)
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 8)
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 7)
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 8)
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 9)
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 5)
VREF = 2.5V, IN+ = IN– = GND
VREF = 2.5V, IN+ = IN– = GND (Notes 7, 8, 9)
l
140
dB
l
140
dB
l
110
120
dB
l
110
120
dB
Input Common Mode Rejection 60Hz ±2%
Input Normal Mode Rejection 50Hz ±2%
Input Normal Mode Rejection 60Hz ±2%
Input Normal Mode Rejection 50Hz/60Hz ±2%
Reference Common Mode Rejection DC
Power Supply Rejection DC
Power Supply Rejection, 50Hz ±2%, 60Hz ±2%
MIN
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87
l
120
TYP
MAX
UNITS
dB
140
dB
120
dB
120
dB
ANALOG INPUT AND REFERENCE
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
IN+
Absolute/Common Mode IN+ Voltage
(IN+ Corresponds to the Selected Positive Input Channel)
CONDITIONS
GND – 0.3V
MIN
TYP
VCC + 0.3V
MAX
UNITS
V
IN–
Absolute/Common Mode IN– Voltage
(IN– Corresponds to the Selected Negative Input Channel)
GND – 0.3V
VCC + 0.3V
V
2499fc
3
LTC2499
ANALOG INPUT AND REFERENCE
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
VIN
Input Differential Voltage Range (IN+ – IN–)
l
–FS
FS
Full Scale of the Differential Input (IN+ – IN–)
l
0.5VREF
LSB
Least Significant Bit of the Output Code
l
FS/224
REF+
Absolute/Common Mode REF+ Voltage
l
0.1
VCC
V
REF–
Absolute/Common Mode REF– Voltage
l
GND
REF+ – 0.1V
V
l
0.1
+FS
V
V
VREF
Reference Voltage Range (REF+ – REF–)
CS(IN+)
IN+ Sampling Capacitance
CS(IN–)
IN– Sampling Capacitance
11
pF
CS(VREF)
VREF Sampling Capacitance
11
pF
IDC_LEAK(IN+)
IN+ DC Leakage Current
Sleep Mode, IN+ = GND
l
–10
1
10
nA
IDC_LEAK(IN–)
IDC_LEAK(REF+)
IDC_LEAK(REF–)
IN– DC Leakage Current
Sleep Mode, IN– = GND
l
–10
1
10
nA
REF+ DC Leakage Current
Sleep Mode, REF+ = V
l
–100
1
100
nA
REF– DC Leakage Current
Sleep Mode, REF– = GND
l
–100
1
100
nA
tOPEN
MUX Break-Before-Make
QIRR
MUX Off Isolation
VCC
V
11
CC
VIN = 2VP-P DC to 1.8MHz
pF
50
ns
120
dB
I2C INPUTS AND DIGITAL OUTPUTS
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
VIH
High Level Input Voltage
l
VIL
Low Level Input Voltage
l
VIHA
Low Level Input Voltage for Address Pins CA0, CA1, CA2
l
VILA
High Level Input Voltage for Address Pins CA0, CA1, CA2
l
RINH
Resistance from CA0, CA1, CA2 to VCC to Set Chip Address
Bit to 1
l
10
kΩ
RINL
Resistance from CA0, CA1, CA2 to GND to Set Chip Address
Bit to 0
l
10
kΩ
RINF
Resistance from CA0, CA1, CA2 to GND or VCC to Set Chip
Address Bit to Float
l
II
Digital Input Current
VHYS
Hysteresis of Schmitt Trigger Inputs
–10
0.05VCC
I = 3mA
l
Output Fall Time VIH(MIN) to VIL(MAX)
Bus Load CB 10pF to
400pF (Note 14)
l
IIN
Input Leakage
0.1VCC ≤ VIN ≤ VCC
CCAX
External Capacitative Load on Chip Address Pins (CA0, CA1,
CA2) for Valid Float
V
0.3VCC
V
0.05VCC
V
V
2
l
Low Level Output Voltage (SDA)
UNITS
0.95VCC
l
VOL
MAX
0.7VCC
(Note 5)
tOF
TYP
MΩ
10
μA
V
0.4
V
250
ns
l
1
μA
l
10
pF
20 + 0.1CB
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
VCC
Supply Voltage
l
Supply Current
l
l
l
ICC
CONDITIONS
Conversion Current (Note 11)
Temperature Measurement (Note 11)
Sleep Mode (Note 11)
MIN
TYP
2.7
160
200
1
MAX
UNITS
5.5
V
275
300
2
μA
μA
μA
2499fc
4
LTC2499
DIGITAL INPUTS AND DIGITAL OUTPUTS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
(Note 16)
MIN
fEOSC
External Oscillator Frequency Range
tHEO
External Oscillator High Period
tLEO
External Oscillator Low Period
tCONV_1
Conversion Time for 1x Speed Mode
50Hz Mode
60Hz Mode
Simultaneous 50Hz/60Hz Mode
External Oscillator (Note 10)
tCONV_2
Conversion Time for 2x Speed Mode
50Hz Mode
60Hz Mode
Simultaneous 50Hz/60Hz Mode
External Oscillator (Note 10)
TYP
MAX
UNITS
l
10
4000
kHz
l
0.125
100
μs
l
0.125
100
μs
l
l
l
157.2
131
144.1
160.3
133.6
146.9
41036/fEOSC (in kHz)
163.5
136.3
149.9
ms
ms
ms
ms
l
l
l
78.7
65.6
72.2
80.3
66.9
73.6
81.9
68.2
75.1
ms
ms
ms
ms
20556/fEOSC (in kHz)
I2C TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3, 15)
SYMBOL
PARAMETER
fSCL
SCL Clock Frequency
CONDITIONS
l
MIN
0
tHD(SDA)
Hold Time (Repeated) Start Condition
l
0.6
μs
tLOW
Low Period of the SCL Pin
l
1.3
μs
tHIGH
High Period of the SCL Pin
l
0.6
μs
tSU(STA)
Set-Up Time for a Repeated Start Condition
l
0.6
μs
tHD(DAT)
Data Hold Time
l
0
tSU(DAT)
Data Set-Up Time
l
100
tr
Rise Time for SDA Signals
(Note 14)
l
20 + 0.1CB
300
ns
tf
Fall Time for SDA Signals
(Note 14)
l
20 + 0.1CB
300
ns
0.6
μs
1.3
μs
tSU(STO)
Set-Up Time for Stop Condition
l
tBUF
Bus Free Time Between a Second Start Condition
l
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: Unless otherwise specified: VCC = 2.7V to 5.5V
VREFCM = VREF/2, FS = 0.5VREF
VIN = IN+ – IN–, VIN(CM) = (IN+ – IN–)/2,
where IN+ and IN– are the selected input channels.
Note 4: Use internal conversion clock or external conversion clock source
with fEOSC = 307.2kHz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
TYP
MAX
UNITS
400
kHz
0.9
μs
ns
Note 7: 50Hz mode (internal oscillator) or fEOSC = 256kHz ±2% (external
oscillator).
Note 8: 60Hz mode (internal oscillator) or fEOSC = 307.2kHz ±2% (external
oscillator).
Note 9: Simultaneous 50Hz/60Hz mode (internal oscillator) or fEOSC =
280kHz ±2% (external oscillator).
Note 10: The external oscillator is connected to the fO pin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 11: The converter uses its internal oscillator.
Note 12: The output noise includes the contribution of the internal
calibration operations.
Note 13: Guaranteed by design and test correlation.
Note 14: CB = capacitance of one bus line in pF (10pF ≤ CB ≤ 400pF).
Note 15: All values refer to VIH(MIN) and VIL(MAX) levels.
Note 16: Refer to Applications Information section for Performance vs
Data Rate graphs.
2499fc
5
LTC2499
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity
(VCC = 5V, VREF = 5V)
1
–45°C
2
25°C
0
85°C
–1
Integral Nonlinearity
(VCC = 2.7V, VREF = 2.5V)
3
VCC = 5V
VREF = 2.5V
VIN(CM) = 1.25V
fO = GND
1
2
INL (ppm of VREF)
INL (ppm of VREF)
2
3
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
fO = GND
INL (ppm of VREF)
3
Integral Nonlinearity
(VCC = 5V, VREF = 2.5V)
–45°C, 25°C, 85°C
0
–1
–3
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5
INPUT VOLTAGE (V)
2
–3
–1.25
2.5
1
–45°C, 25°C, 85°C
0
–1
–2
–2
–2
VCC = 2.7V
VREF = 2.5V
VIN(CM) = 1.25V
fO = GND
–0.75
–0.25
0.25
0.75
INPUT VOLTAGE (V)
–3
–1.25
1.25
–0.75
1.25
–0.25
0.25
0.75
INPUT VOLTAGE (V)
2499 G03
2499 G02
2499 G01
Total Unadjusted Error
(VCC = 5V, VREF = 2.5V)
TUE (ppm of VREF)
8
12
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
fO = GND
VCC = 5V
VREF = 2.5V
VIN(CM) = 1.25V
fO = GND
8
85°C
25°C
TUE (ppm of VREF)
12
4
0
–45°C
–4
Total Unadjusted Error
(VCC = 2.7V, VREF = 2.5V)
12
85°C
8
25°C
TUE (ppm of VREF)
Total Unadjusted Error
(VCC = 5V, VREF = 5V)
4
–45°C
0
–4
–8
2
2.5
–12
–1.25
–0.75
–0.25
0.25
0.75
INPUT VOLTAGE (V)
2499 G04
Noise Histogram (6.8sps)
–4
1.25
–12
–1.25
–0.75
–0.25
0.25
0.75
INPUT VOLTAGE (V)
1.25
2499 G06
Noise Histogram (7.5sps)
14
12
12
10,000 CONSECUTIVE
READINGS
RMS = 0.60μV
VCC = 5V
AVERAGE = –0.69μV
VREF = 5V
10 VIN = 0V
TA = 25°C
NUMBER OF READINGS (%)
NUMBER OF READINGS (%)
85°C
–45°C
0
2499 G05
14
8
6
4
2
10,000 CONSECUTIVE
READINGS
RMS = 0.59μV
VCC = 2.7V
AVERAGE = –0.19μV
VREF = 2.5V
10 VIN = 0V
TA = 25°C
8
6
4
2
0
–3 –2.4 –1.8 –1.2 –0.6 0 0.6
OUTPUT READING (μV)
25°C
4
–8
–8
–12
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5
INPUT VOLTAGE (V)
VCC = 2.7V
VREF = 2.5V
VIN(CM) = 1.25V
fO = GND
1.2
1.8
2499 G07
0
–3 –2.4 –1.8 –1.2 –0.6 0 0.6
OUTPUT READING (μV)
1.2
1.8
2499 G08
2499fc
6
LTC2499
TYPICAL PERFORMANCE CHARACTERISTICS
RMS Noise
vs Input Differential Voltage
5
TA = 25°C
VCC = 5V
VREF = 5V RMS NOISE = 0.60μV
VIN = 0V
VIN(CM) = 2.5V
4
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
TA = 25°C
fO = GND
0.9
2
RMS NOISE (μV)
ADC READING (μV)
3
1
0
–1
–2
–3
RMS Noise vs VIN(CM)
1.0
1.0
0.8
VCC = 5V
VREF = 5V
VIN = 0V
TA = 25°C
fO = GND
0.9
RMS NOISE (μV)
Long-Term ADC Readings
0.7
0.6
0.8
0.7
0.6
0.5
0.5
–4
–5
0
10
30
40
20
TIME (HOURS)
50
0.4
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2
INPUT DIFFERENTIAL VOLTAGE (V)
60
2499 G09
0.6
0 15 30 45 60
TEMPERATURE (°C)
75
0.8
0.7
0.6
0.4
2.7
90
0.8
0.7
0.6
3.5
3.9 4.3
VCC (V)
4.7
5.1
0
5.5
1
2
3
VREF (V)
4
5
2499 G14
2499 G13
Offset Error vs Temperature
0.3
OFFSET ERROR (ppm of VREF)
VCC = 5V
VREF = 5V
VIN = 0V
TA = 25°C
fO = GND
0.1
6
0.4
3.1
Offset Error vs VIN(CM)
0.2
5
4
0.5
2499 G12
0.3
3
2
VIN(CM) (V)
VCC = 5V
VIN = 0V
VIN(CM) = GND
TA = 25°C
fO = GND
0.9
0.5
0.5
0.4
–45 –30 –15
VREF = 2.5V
VIN = 0V
VIN(CM) = GND
TA = 25°C
fO = GND
RMS NOISE (μV)
0.7
1
RMS Noise vs VREF
1.0
0.9
RMS NOISE (μV)
0.8
0
2499 G11
RMS Noise vs VCC
1.0
VCC = 5V
VREF = 5V
VIN = 0V
VIN(CM) = GND
fO = GND
OFFSET ERROR (ppm of VREF)
RMS NOISE (μV)
0.9
–1
2499 G10
RMS Noise vs Temperature (TA)
1.0
0.4
2.5
0
0.2
0.1
VCC = 5V
VREF = 5V
VIN = 0V
VIN(CM) = GND
fO = GND
0
–0.1
–0.1
–0.2
–0.3
–1
0
1
3
2
VIN(CM) (V)
4
5
6
2499 G15
–0.2
–0.3
–45 –30 –15
0 15 30 45 60
TEMPERATURE (°C)
75
90
2499 G16
2499fc
7
LTC2499
TYPICAL PERFORMANCE CHARACTERISTICS
0.2
0.1
0.3
REF+ = 2.5V
REF– = GND
VIN = 0V
VIN(CM) = GND
TA = 25°C
fO = GND
OFFSET ERROR (ppm of VREF)
OFFSET ERROR (ppm of VREF)
0.3
On-Chip Oscillator Frequency
vs Temperature
Offset Error vs VREF
0
0.2
0.1
–0.2
0
–0.3
3.1
3.9 4.3
VCC (V)
3.5
4.7
5.1
5.5
0
1
2
3
VREF (V)
302
2.5
3.0
3.5
4.0
VCC (V)
4.5
5.0
5.5
VCC = 4.1V DC
VREF = 2.5V
IN+ = GND
IN– = GND
fO = GND
TA = 25°C
–20
–40
–20
–40
–60
–80
–120
–120
–140
10
10k 100k
1k
100
FREQUENCY AT VCC (Hz)
2499 G20
CONVERSION CURRENT (μA)
REJECTION (dB)
200
VCC = 4.1V DC ±0.7V
= 2.5V
V
–20 INREF
+ = GND
– = GND
IN
–40 fO = GND
TA = 25°C
–60
–80
–100
–120
30700
30750
FREQUENCY AT VCC (Hz)
2499 G22
Conversion Current
vs Temperature
0
30650
0 20 40 60 80 100 120 140 160 180 200 220
FREQUENCY AT VCC (Hz)
2499 G21
PSRR vs Frequency at VCC
–140
30600
1M
VCC = 4.1V DC ±1.4V
VREF = 2.5V
IN+ = GND
IN– = GND
fO = GND
TA = 25°C
–80
–100
1
90
–60
–100
–140
75
PSRR vs Frequency at VCC
0
REJECTION (dB)
304
0
REJECTION (dB)
306
0 15 30 45 60
TEMPERATURE (°C)
2499 G19
PSRR vs Frequency at VCC
VREF = 2.5V
VIN = 0V
VIN(CM) = GND
fO = GND
TA = 25°C
VCC = 4.1V
VREF = 2.5V
VIN = 0V
VIN(CM) = GND
fO = GND
2499 G18
On-Chip Oscillator Frequency
vs VCC
308
304
300
–45 –30 –15
5
4
2499 G17
310
306
302
–0.2
–0.3
2.7
FREQUENCY (kHz)
308
–0.1
–0.1
300
310
VCC = 5V
REF– = GND
VIN = 0V
VIN(CM) = GND
TA = 25°C
fO = GND
FREQUENCY (kHz)
Offset Error vs VCC
30800
2499 G23
fO = GND
180
VCC = 5V
160
140
VCC = 2.7V
120
100
–45 –30 –15
0 15 30 45 60
TEMPERATURE (°C)
75
90
2499 G24
2499fc
8
LTC2499
TYPICAL PERFORMANCE CHARACTERISTICS
Sleep Mode Current
vs Temperature
500
fO = GND
1.6
SUPPLY CURRENT (μA)
SLEEP MODE CURRENT (μA)
1.8
Integral Nonlinearity (2x Speed
Mode; VCC = 5V, VREF = 5V)
1.4
1.2
VCC = 5V
1.0
0.8
0.6
VCC = 2.7V
0.4
VREF = VCC
+
450 IN– = GND
IN = GND
400 fO = EXT OSC
TA = 25°C
350
3
VCC = 5V
VCC = 3V
0
–45 –30 –15
–1
–45°C
–2
100
0 15 30 45 60
TEMPERATURE (°C)
75
90
2499 G26
Integral Nonlinearity (2x Speed
Mode; VCC = 5V, VREF = 2.5V)
85°C
0
–45°C, 25°C
–2
1
85°C
0
–45°C, 25°C
–2
–0.75
–0.25
0.25
0.75
INPUT VOLTAGE (V)
1.25
–3
–1.25
–0.75
8
6
4
0
179
1.25
–0.25
0.25
0.75
INPUT VOLTAGE (V)
2499 G28
181.4
183.8
186.2
OUTPUT READING (μV)
2499 G29
188.6
2499 G30
Offset Error vs VIN(CM)
(2x Speed Mode)
RMS Noise vs VREF
(2x Speed Mode)
200
1.0
198
196
0.8
0.6
0.4
VCC = 5V
VIN = 0V
VIN(CM) = GND
fO = GND
TA = 25°C
0.2
0
RMS = 0.85μV
10,000 CONSECUTIVE
AVERAGE = 0.184mV
14 READINGS
VCC = 5V
12 VREF = 5V
VIN = 0V
T = 25°C
10 A
2
OFFSET ERROR (μV)
–3
–1.25
16
VCC = 2.7V
VREF = 2.5V
VIN(CM) = 1.25V
fO = GND
–1
2.5
Noise Histogram
(2x Speed Mode)
NUMBER OF READINGS (%)
INL (ppm OF VREF)
2
1
RMS NOISE (μV)
INL (ppm OF VREF)
3
2
2499 G27
Integral Nonlinearity (2x Speed
Mode; VCC = 2.7V, VREF = 2.5V)
VCC = 5V
VREF = 2.5V
VIN(CM) = 1.25V
fO = GND
–1
–3
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5
INPUT VOLTAGE (V)
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
0
2499 G25
2
25°C, 90°C
0
200
150
0.2
3
1
300
250
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
fO = GND
2
INL (μV)
2.0
Conversion Current
vs Output Data Rate
0
1
194
VCC = 5V
VREF = 5V
VIN = 0V
fO = GND
TA = 25°C
192
190
188
186
184
182
180
3
2
VREF (V)
4
5
2499 G31
–1
0
1
3
2
VIN(CM) (V)
4
5
6
2499 G32
2499fc
9
LTC2499
TYPICAL PERFORMANCE CHARACTERISTICS
Offset Error vs VCC
(2x Speed Mode)
Offset Error vs Temperature
(2x Speed Mode)
250
VCC = 5V
VREF = 5V
VIN = 0V
VIN(CM) = GND
fO = GND
220
200
OFFSET ERROR (μV)
230
210
200
190
180
240
VREF = 2.5V
VIN = 0V
VIN(CM) = GND
fO = GND
TA = 25°C
150
100
220
210
200
190
180
50
170
170
0
0 15 30 45 60
TEMPERATURE (°C)
75
2
90
2.5
3
4
3.5
VCC (V)
4.5
0
VCC = 4.1V DC
REF+ = 2.5V
REF– = GND
IN+ = GND
IN– = GND
fO = GND
TA = 25°C
–60
–20
RREJECTION (dB)
–40
–80
–40
–60
–80
–120
2499 G36
–140
5
–80
–120
1M
4
VCC = 4.1V DC ±0.7V
REF+ = 2.5V
REF– = GND
IN+ = GND
–40 IN– = GND
fO = GND
–60 TA = 25°C
–120
10k 100k
1k
100
FREQUENCY AT VCC (Hz)
3
VREF (V)
–20
–100
10
2
0
VCC = 4.1V DC ±1.4V
REF+ = 2.5V
REF– = GND
IN+ = GND
IN– = GND
fO = GND
TA = 25°C
–100
1
1
PSRR vs Frequency at VCC
(2x Speed Mode)
–100
–140
0
2499 G35
PSRR vs Frequency at VCC
(2x Speed Mode)
PSRR vs Frequency at VCC
(2x Speed Mode)
–20
160
5.5
2499 G34
2499 G33
0
5
REJECTION (dB)
160
–45 –30 –15
REJECTION (dB)
VCC = 5V
VIN = 0V
VIN(CM) = GND
fO = GND
TA = 25°C
230
OFFSET ERROR (μV)
240
OFFSET ERROR (μV)
Offset Error vs VREF
(2x Speed Mode)
0 20 40 60 80 100 120 140 160 180 200 220
FREQUENCY AT VCC (Hz)
2499 G37
–140
30600
30650
30700
30750
FREQUENCY AT VCC (Hz)
30800
2499 G38
2499fc
10
LTC2499
PIN FUNCTIONS
GND (Pins 1, 4, 6, 31, 32, 33, 34): Ground. Multiple
ground pins internally connected for optimum ground current flow and VCC decoupling. Connect each one of these
pins to a common ground plane through a low impedance
connection. All seven pins must be connected to ground
for proper operation.
SCL (Pin 2): Serial Clock Pin of the I2C Interface. The
LTC2499 can only act as a slave and the SCL pin only accepts an external serial clock. Data is shifted into the SDA
pin on the rising edges of the SCL clock and output through
the SDA pin on the falling edges of the SCL clock.
SDA (Pin 3): Bidirectional Serial Data Line of the I2C Interface. In the transmitter mode (Read), the conversion result
is output through the SDA pin, while in the receiver mode
(Write), the device channel select and configuration bits
are input through the SDA pin. The pin is high impedance
during the data input mode and is an open drain output
(requires an appropriate pull-up device to VCC) during the
data output mode.
NC (Pin 5): No Connect. This pin can be left floating or
tied to GND.
COM (Pin 7): The Common Negative Input (IN –) for All
Single-Ended Multiplexer Configurations. The voltage on
CH0-CH15 and COM pins can have any value between
GND – 0.3V to VCC + 0.3V. Within these limits, the two
selected inputs (IN+ and IN– ) provide a bipolar input range
(VIN = IN+ – IN– ) from –0.5 • VREF to 0.5 • VREF . Outside
this input range, the converter produces unique overrange
and underrange output codes.
ADCINP (Pin 25): Positive ADC Input. Connect to the
output of a buffer/amplifier driven by MUXOUTP or short
directly to MUXOUTP.
ADCINN (Pin 26): Negative ADC Input. Connect to the
output of a buffer/amplifier driven by MUXOUTN or short
directly to MUXOUTN
MUXOUTN (Pin 27): Negative Multiplexer Output. Connect to the input of an external buffer/amplifier or short
directly to ADCINN.
VCC (Pin 28): Positive Supply Voltage. Bypass to GND with
a 10μF tantalum capacitor in parallel with a 0.1μF ceramic
capacitor as close to the part as possible.
REF+, REF – (Pin 29, Pin 30): Differential Reference Input.
The voltage on these pins can have any value between
GND and VCC as long as the reference positive input, REF+,
remains more positive than the negative reference input,
REF–, by at least 0.1V. The differential voltage (VREF = REF+
– REF –) sets the full-scale range for all input channels.
When performing an on-chip measurement, the minimum
value of REF = 2V.
fO (Pin 35): Frequency Control Pin. Digital input that
controls the internal conversion clock rate. When fO is
connected to GND, the converter uses its internal oscillator running at 307.2kHz. The conversion clock may also
be overridden by driving the fO pin with an external clock
in order to change the output rate and the digital filter
rejection null.
CH0 to CH15 (Pin 8-Pin 23): Analog Inputs. May be programmed for single-ended or differential mode.
CA0, CA1, CA2 (Pins 36, 37, 38): Chip Address Control
Pins. These pins are configured as a three-state (LOW,
HIGH, Floating) address control bits for the device I2C
address.
MUXOUTP (Pin 24): Positive Multiplexer Output. Connect
to the input of external buffer/amplifier or short directly
to ADCINP.
Exposed Pad (Pin 39): Ground. This pin is ground and
must be soldered to the PCB ground plane. For prototyping
purposes, this pin may remain floating.
2499fc
11
LTC2499
FUNCTIONAL BLOCK DIAGRAM
TEMP
SENSOR
INTERNAL
OSCILLATOR
VCC
GND
–
CH0
CH1
CH15
COM
•
•
•
MUX
fO
(INT/EXT)
AUTOCALIBRATION
AND CONTROL
MUXOUTP ADCINP
REF+
REF–
+
DIFFERENTIAL
3RD ORDER
$3 MODULATOR
I2C
2-WIRE
INTERFACE
SDA
SCL
DECIMATING FIR
ADDRESS
2499 BD
MUXOUTN ADCINN
2499fc
12
LTC2499
APPLICATIONS INFORMATION
CONVERTER OPERATION
Converter Operation Cycle
The LTC2499 is a multichannel, low power, delta-sigma
analog-to-digital converter with a 2-wire, I2C interface.
Its operation is made up of four states (see Figure 1).
The converter operating cycle begins with the conversion, followed by the sleep state and ends with the data
input/output cycle .
Initially, at power-up, the LTC2499 performs a conversion.
Once the conversion is complete, the device enters the
sleep state. While in the sleep state, power consumption is
reduced by two orders of magnitude. The part remains in
the sleep state as long it is not addressed for a read/write
operation. The conversion result is held indefinitely in a
static shift register while the part is in the sleep state.
The device will not acknowledge an external request during the conversion state. After a conversion is finished,
the device is ready to accept a read/write request. Once
the LTC2499 is addressed for a read operation, the device
begins outputting the conversion result under the control
of the serial clock (SCL). There is no latency in the conversion result. The data output is 32 bits long and contains a
24-bit plus sign conversion result. Data is updated on the
falling edges of SCL allowing the user to reliably latch data
on the rising edge of SCL. A new conversion is initiated
by a stop condition following a valid write operation or an
incomplete read operation. The conversion automatically
begins at the conclusion of a complete read cycle (all 32
bits read out of the device).
Ease of Use
The LTC2499 data output has no latency, filter settling
delay, or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog inputs is straightforward. Each conversion, immediately following a newly selected input or
mode, is valid and accurate to the full specifications of
the device.
The LTC2499 automatically performs offset and full-scale
calibration every conversion cycle independent of the input
channel selected. This calibration is transparent to the user
POWER-ON RESET
DEFAULT CONFIGURATION:
IN+ = CH0, IN– = CH1
50Hz/60Hz REJECTION
1x OUTPUT
CONVERSION
SLEEP
NO
ACKNOWLEDGE
YES
DATA OUTPUT/INPUT
NO
STOP
OR READ
32 BITS
YES
2499 F01
Figure 1. State Transition Table
and has no effect on the operation cycle described above.
The advantage of continuous calibration is extreme stability
of offset and full-scale readings with respect to time, supply
voltage variation, input channel and temperature drift.
Easy Drive Input Current Cancellation
The LTC2499 combines a high precision, delta-sigma ADC
with an automatic, differential, input current cancellation
front end. A proprietary front-end passive sampling network
transparently removes the differential input current. This
enables external RC networks and high impedance sensors to directly interface to the LTC2499 without external
amplifiers. The remaining common mode input current
is eliminated by either balancing the differential input impedances or setting the common mode input equal to the
common mode reference (see the Automatic Differential
Input Current Cancellation section). This unique architecture does not require on-chip buffers, thereby enabling
signals to swing beyond ground and VCC. Moreover, the
2499fc
13
LTC2499
APPLICATIONS INFORMATION
cancellation does not interfere with the transparent offset
and full-scale auto-calibration and the absolute accuracy
(full scale + offset + linearity + drift) is maintained even
with external RC networks.
Power-Up Sequence
The LTC2499 automatically enters an internal reset state
when the power supply voltage VCC drops below approximately 2.0V. This feature guarantees the integrity of the
conversion result and input channel selection.
When VCC rises above this threshold, the converter creates
an internal power-on reset (POR) signal with a duration
of approximately 4ms. The POR signal clears all internal
registers. The conversion immediately following a POR
cycle is performed on the input channel IN+ = CH0, IN – =
CH1 with simultaneous 50Hz/60Hz rejection and 1x output
rate. The first conversion following a POR cycle is accurate
within the specification of the device if the power supply
voltage is restored to (2.7V to 5.5V) before the end of the
POR interval. A new input channel, rejection mode, speed
mode, or temperature selection can be programmed into
the device during this first data input/output cycle.
Reference Voltage Range
This converter accepts a truly differential external reference
voltage. The absolute/common mode voltage range for
REF+ and REF – pins covers the entire operating range of
the device (GND to VCC). For correct converter operation,
VREF must be positive (REF+ > REF –).
The LTC2499 differential reference input range is 0.1V to
VCC. For the simplest operation, REF+ can be shorted to VCC
and REF – can be shorted to GND. The converter output noise
is determined by the thermal noise of the front-end circuits
and, as such, its value in nanovolts is nearly constant with
reference voltage. A decrease in reference voltage will not
significantly improve the converter’s effective resolution.
On the other hand, a decreased reference will improve the
converter’s overall INL performance.
Input Voltage Range
The analog inputs are truly differential with an absolute,
common mode range for the CH0-CH15 and COM input
pins extending from GND – 0.3V to VCC + 0.3V. Outside
these limits, the ESD protection devices begin to turn on
and the errors due to input leakage current increase rapidly.
Within these limits, the LTC2499 converts the bipolar differential input signal VIN = IN+ – IN– (where IN+ and IN – are
the selected input channels), from – FS = – 0.5 • VREF
to + FS = 0.5 • VREF where VREF = REF+ - REF–. Outside
this range, the converter indicates the overrange or the
underrange condition using distinct output codes (see
Table 1).
Signals applied to the input (CH0-CH15, COM) may extend
300mV below ground and above VCC. In order to limit
any fault current, resistors of up to 5k may be added in
series with the input. The effect of series resistance on
the converter accuracy can be evaluated from the curves
presented in the Input Current/Reference Current sections.
In addition, series resistors will introduce a temperature
dependent error due to input leakage current. A 1nA
input leakage current will develop a 1ppm offset error
on a 5k resistor if VREF = 5V. This error has a very strong
temperature dependency.
MUXOUT/ADCIN
The outputs of the multiplexer (MUXOUTP/MUXOUTN) and
the inputs to the ADC (ADCINP/ADCINN) can be used to
perform input signal conditioning on any of the selected
input channels or simply shorted together for direct
digitization. If an external amplifier is used, the LTC2499
automatically calibrates both the offset and drift of this
circuit and the Easy Drive sampling scheme enables a
wide variety of amplifiers to be used.
In order to achieve optimum performance, if an external
amplifier is not used, short these pins directly together
(ADCINP to MUXOUTP and ADCINN to MUXOUTN) and
minimize their capacitance to ground.
2499fc
14
LTC2499
APPLICATIONS INFORMATION
I2C INTERFACE
The LTC2499 communicates through an I2C interface. The
I2C interface is a 2-wire open-drain interface supporting
multiple devices and multiple masters on a single bus. The
connected devices can only pull the data line (SDA) low
and can never drive it high. SDA is required to be externally
connected to the supply through a pull-up resistor. When
the data line is not being driven, it is high. Data on the
I2C bus can be transferred at rates up to 100kbits/s in the
standard mode and up to 400kbits/s in the fast mode.
Each device on the I2C bus is recognized by a unique
address stored in that device and can operate either as a
transmitter or receiver, depending on the function of the
device. In addition to transmitters and receivers, devices
can also be considered as masters or slaves when performing data transfers. A master is the device which initiates a
data transfer on the bus and generates the clock signals
to permit that transfer. Devices addressed by the master
are considered a slave.
The LTC2499 can only be addressed as a slave. Once
addressed, it can receive configuration bits (channel
selection, rejection mode, speed mode) or transmit the
last conversion result. The serial clock line, SCL, is always
an input to the LTC2499 and the serial data line SDA is
bidirectional. The device supports the standard mode and
the fast mode for data transfer speeds up to 400kbits/s.
Figure 2 shows the definition of the I2C timing.
The Start and Stop Conditions
A Start (S) condition is generated by transitioning SDA from
high to low while SCL is high. The bus is considered to be
busy after the Start condition. When the data transfer is
finished, a Stop (P) condition is generated by transitioning
SDA from low to high while SCL is high. The bus is free
after a Stop is generated. Start and Stop conditions are
always generated by the master.
When the bus is in use, it stays busy if a Repeated Start
(Sr) is generated instead of a Stop condition. The repeated
Start timing is functionally identical to the Start and is
used for writing and reading from the device before the
initiation of a new conversion.
Data Transferring
After the Start condition, the I2C bus is busy and data
transfer can begin between the master and the addressed
slave. Data is transferred over the bus in groups of nine
bits, one byte followed by one acknowledge (ACK) bit.
The master releases the SDA line during the ninth SCL
clock cycle. The slave device can issue an ACK by pulling
SDA low or issue a Not Acknowledge (NAK) by leaving
the SDA line high impedance (the external pull-up resistor
will hold the line high). Change of data only occurs while
the clock line (SCL) is low.
DATA FORMAT
After a Start condition, the master sends a 7-bit address
followed by a read/write (R/W) bit. The R/W bit is 1 for a
read request and 0 for a write request. If the 7-bit address
matches the hard wired LTC2499’s address (one of 27
pin-selectable addresses) the device is selected. When
the device is addressed during the conversion state, it will
not acknowledge R/W requests and will issue a NAK by
leaving the SDA line high. If the conversion is complete,
the LTC2499 issues an ACK by pulling the SDA line low.
SDA
tLOW
tf
tSU(DAT)
tr
tHD(SDA)
tf
tSP
tBUF
tr
SCL
tHD(SDA)
S
tHD(DAT)
tHIGH
tSU(STA)
tSU(STO)
Sr
P
S
2499 F02
Figure 2. Definition of Timing for Fast/Standard Mode Devices on the I2C Bus
2499fc
15
LTC2499
APPLICATIONS INFORMATION
The LTC2499 has two registers. The output register (32
bits long) contains the last conversion result. The input
register (16 bits long) sets the input channel, selects the
temperature sensor, rejection mode, and speed mode.
are HIGH, the differential input voltage is equal to or above
+FS. If both bits are set low, the input voltage is below –FS.
The function of these bits is summarized in Table 2. The
24 bits following the MSB bit are the conversion result in
binary two’s, complement format. The remaining six bits
are sub LSBs below the 24-bit level.
DATA OUTPUT FORMAT
As long as the voltage on the selected input channels (IN+
and IN–) remains between –0.3V and VCC + 0.3V (absolute
maximum operating range) a conversion result is generated for any differential input voltage VIN from –FS = –0.5
• VREF to +FS = 0.5 • VREF . For differential input voltages
greater than +FS, the conversion result is clamped to the
value corresponding to +FS. For differential input voltages
below –FS, the conversion result is clamped to the value
–FS – 1LSB.
The output register contains the last conversion result.
After each conversion is completed, the device automatically enters the sleep state where the supply current is
reduced to 1μA. When the LTC2499 is addressed for a read
operation, it acknowledges (by pulling SDA low) and acts
as a transmitter. The master/receiver can read up to four
bytes from the LTC2499. After a complete read operation
(4 bytes), a new conversion is initiated. The device will
NAK subsequent read operations while a conversion is
being performed.
Table 2. LTC2499 Status Bits
The data output stream is 32 bits long and is shifted out
on the falling edges of SCL (see Figure 3a). The first bit is
the conversion result sign bit (SIG) (see Tables 1 and 2).
This bit is high if VIN ≥ 0 and low if VIN < 0 (where VIN
corresponds to the selected input signal IN+ – IN–). The
second bit is the most significant bit (MSB) of the result.
The first two bits (SIG and MSB) can be used to indicate
over and under range conditions (see Table 2). If both bits
BIT 31
SIG
BIT 30
MSB
1
1
0V ≤ VIN < FS
1/ 0
0
–FS ≤ VIN < 0V
0
1
VIN < –FS
0
0
INPUT RANGE
VIN ≥ FS
Table 1. Output Data Format
DIFFERENTIAL INPUT VOLTAGE
VIN*
BIT 31
SIG
BIT 30
MSB
BIT 29
BIT 28
BIT 27
…
BIT 6
LSB
BITs 5-0
Sub LSBs
VIN* ≥ FS**
1
1
0
0
0
…
0
00000
FS** – 1LSB
1
0
1
1
1
…
1
XXXXX
0.5 • FS**
1
0
1
0
0
…
0
XXXXX
0.5 • FS** – 1LSB
1
0
0
1
1
…
1
XXXXX
1/ 0†
0
0
0
0
…
0
XXXXX
–1LSB
0
1
1
1
1
…
1
XXXXX
–0.5 • FS**
0
1
1
0
0
…
0
XXXXX
0
–0.5 • FS** – 1LSB
0
1
0
1
1
…
1
XXXXX
–FS**
0
1
0
0
0
…
0
XXXXX
VIN* < –FS**
0
0
1
1
1
…
1
11111
*The differential input voltage VIN = IN+ – IN–.
**The full-scale voltage FS = 0.5 • VREF . Sub LSBs are below the 24-bit level. They may be included in averaging, or discarded without loss of resolution.
†The sign bit changes state during the 0 output code when the device is operating in the 2x speed mode.
2499fc
16
LTC2499
APPLICATIONS INFORMATION
INPUT DATA FORMAT
If the first three bits are 000 or 100, the following data
is ignored (don’t care) and the previously selected input
channel remains valid for the next conversion
The serial input word to the LTC2499 is 13 bits long and
is written into the device input register in two 8-bit words.
The first word (SGL, ODD, A2, A1, A0) is used to select
the input channel. The second word of data (IM, FA, FB,
SPD) is used to select the frequency rejection, speed mode
(1x, 2x), and temperature measurement.
If the first three bits shifted into the device are 101, then
the next five bits select the input channel for the next
conversion cycle (see Table 3).
The first input bit (SGL) following the 101 sequence determines if the input selection is differential (SGL = 0) or
single-ended (SGL = 1). For SGL = 0, two adjacent channels can be selected to form a differential input. For SGL
= 1, one of 16 channels is selected as the positive input.
The negative input is COM for all single-ended operations.
The remaining four bits (ODD, A2, A1, A0) determine
which channel(s) is/are selected and the polarity (for a
differential input).
After power-up, the device initiates an internal reset cycle
which sets the input channel to CH0-CH1 (IN+ = CH0, IN– =
CH1), the frequency rejection to simultaneous 50Hz/60Hz,
and 1x output rate (auto-calibration enabled). The first
conversion automatically begins at power-up using this
default configuration. Once the conversion is complete,
up to two words may be written into the device.
The first three bits of the first input word consist of two
preamble bits and one enable bit. Valid settings for these
three bits are 000, 100, and 101. Other combinations
should be avoided.
1
…
7
8
7-BIT
ADDRESS
9
R
1
2
SGN
MSB
…
9
1
2
DIS
ACK BY
LTC2499
START BY
MASTER
Once the first word is written into the device, a second
word may be input in order to select a configuration mode.
3
4
5
6
7
8
9
LSB
ACK BY
MASTER
SUB LSBs
SLEEP
NAK BY
MASTER
DATA OUTPUT
2499 F03a
Figure 3a. Timing Diagram for Reading from the LTC2499
1
SCL
2
…
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
FA
FB
SPD
6
7
8
9
SDA
7-BIT ADDRESS
1
W
ACK BY
LTC2499
START BY
MASTER
SLEEP
0
EN
SGL ODD
A2
A1
A0
EN2
ACK
LTC2499
IM
(OPTIONAL 2ND BYTE)
ACK
LTC2499
DATA INPUT
2499 F03b
Figure 3b. Timing Diagram for Writing to the LTC2499
2499fc
17
LTC2499
APPLICATIONS INFORMATION
Table 3. Channel Selection
MUX ADDRESS
ODD/
SGL SIGN
A2
A1
CHANNEL SELECTION
A0
0
1
IN+
IN–
*0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
IN–
2
3
IN+
IN–
4
5
IN+
IN–
6
7
IN+
IN–
8
9
IN+
IN–
10
11
IN+
IN–
12
13
IN+
IN–
14
15
IN+
IN–
IN–
IN+
COM
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
*Default at power up
2499fc
18
LTC2499
APPLICATIONS INFORMATION
The first bit of the second word is the enable bit for the
conversion configuration (EN2). If this bit is set to 0, then
the next conversion is performed using the previously
selected converter configuration.
up to 15Hz with no latency). When IM = 1 (temperature
measurement) SPD will be ignored and the device will
operate in 1x mode.
The configuration remains valid until a new input word with
EN = 1 (the first three bits are 101 for the first word) and EN2
= 1 (for the second write byte) is shifted into the device.
A new configuration can be loaded into the device by
setting EN2 = 1 (see Table 4). The first bit (IM) is used
to select the internal temperature sensor. If IM = 1, the
following conversion will be performed on the internal
temperature sensor rather than the selected input channel.
The next two bits (FA and FB) are used to set the rejection
frequency. The final bit (SPD) is used to select either the
1x output rate if SPD = 0 (auto-calibration is enabled and
the offset is continuously calibrated and removed from
the final conversion result) or the 2x output rate if SPD
= 1 (offset calibration disabled, multiplexing output rates
Rejection Mode (FA, FB)
The LTC2499 includes a high accuracy on-chip oscillator
with no required external components. Coupled with an
integrated fourth order digital lowpass filter, the LTC2499
rejects line frequency noise. In the default mode, the
LTC2499 simultaneously rejects 50Hz and 60Hz by at least
87dB. If more rejection is required, the LTC2499 can be
configured to reject 50Hz or 60Hz to better than 110dB.
Table 4. Converter Configuration
1
0
EN
SGL
ODD
A2
A1
A0
EN2
IM
FA
FB
SPD
CONVERTER CONFIGURATION
1
0
0
X
X
X
X
X
X
X
X
X
X
Keep Previous
1
0
1
X
X
X
X
X
0
X
X
X
X
Keep Previous
0
0
1
X
X
X
X
X
X
X
X
X
X
Keep Previous
1
0
1
X
X
X
X
X
1
0
0
0
0
External Input (See Table 3)
50Hz/60Hz Rejection, 1x
1
0
1
X
X
X
X
X
1
0
0
1
0
External Input (See Table 3)
50Hz Rejection, 1x
1
0
1
X
X
X
X
X
1
0
1
0
0
External Input (See Table 3)
60Hz Rejection, 1x
1
0
1
X
X
X
X
X
1
0
0
0
1
External Input (See Table 3)
50Hz/60Hz Rejection, 2x
1
0
1
X
X
X
X
X
1
0
0
1
1
External Input (See Table 3)
50Hz Rejection, 2x
1
0
1
X
X
X
X
X
1
0
1
0
1
External Input (See Table 3)
60Hz Rejection, 2x
1
0
1
X
X
X
X
X
1
1
0
0
X
Measure Temperature
50Hz/60Hz Rejection, 1x
1
0
1
X
X
X
X
X
1
1
0
1
X
Measure Temperature
50Hz Rejection, 1x
1
0
1
X
X
X
X
X
1
1
1
0
X
Measure Temperature
60Hz Rejection, 1x
1
0
1
X
X
X
X
X
1
X
1
1
X
Reserved, Do Not Use
2499fc
19
LTC2499
APPLICATIONS INFORMATION
Speed Mode (SPD)
Every conversion cycle, two conversions are combined
to remove the offset (default mode). This result is free
from offset and drift. In applications where the offset is
not critical, the auto-calibration feature can be disabled
with the benefit of twice the output rate.
While operating in the 2x mode (SPD = 1), the linearity
and full-scale errors are unchanged from the 1x mode
performance. In both the 1x and 2x mode there is no
latency. This enables input steps or multiplexer changes
to settle in a single conversion cycle, easing system overhead and increasing the effective conversion rate. During
temperature measurements, the 1x mode is always used
independent of the value of SPD.
Temperature Sensor
The LTC2499 includes an integrated temperature sensor.
The temperature sensor is selected by setting IM = 1.
During temperature readings, MUXOUTN/MUXOUTP
remains connected to the selected input channel. The
ADC internally connects to the temperature sensor and
performs a conversion.
The digital output is proportional to the absolute temperature of the device. This feature allows the converter
to perform cold junction compensation for external
thermocouples or continuously remove the temperature
effects of external sensors.
The internal temperature sensor output is 28mV at 27°C
(300°K), with a slope of 93.5μV/°C independent of VREF
(see Figures 4 and 5). Slope calibration is not required if
the reference voltage (VREF) is known. A 5V reference has
a slope of 314 LSBs24/°C. The temperature is calculated
from the output code (where DATAOUT24 is the decimal
representation of the 24-bit result) for a 5V reference using
the following formula:
TK =
DATAOUT24
in Kelvin
314
If a different value of VREF is used, the temperature
output is:
TK =
DATAOUT24 • VREF
in Kelvin
1570
If the value of VREF is not known, the slope is determined
by measuring the temperature sensor at a known temperature TN (in K) and using the following formula:
This value of slope can be used to calculate further temperature readings using:
TK =
DATAOUT24
SLOPE
All Kelvin temperature readings can be converted to TC
(°C) using the fundamental equation:
TC = TK – 273
140000
5
VCC = 5V
VREF = 5V
120000 SLOPE = 314 LSB /K
24
4
ABSOLUTE ERROR (°C)
3
100000
DATAOUT24
DATAOUT24
TN
SLOPE =
80000
60000
40000
2
1
0
–1
–2
–3
20000
0
–4
0
100
200
300
TEMPERATURE (K)
400
2499 F04
Figure 4. Internal PTAT Digital Output vs Temperature
–5
–55
–30
–5
20
45
70
TEMPERATURE (°C)
95
120
2499 F05
Figure 5. Absolute Temperature Error
2499fc
20
LTC2499
APPLICATIONS INFORMATION
Initiating a New Conversion
When the LTC2499 finishes a conversion, it automatically
enters the sleep state. Once in the sleep state, the device is
ready for a read operation. After the device acknowledges
a read request, the device exits the sleep state and enters
the data output state. The data output state concludes and
the LTC2499 starts a new conversion once a Stop condition is issued by the master or all 32 bits of data are read
out of the device.
During the data read cycle, a Stop command may be issued
by the master controller in order to start a new conversion
and abort the data transfer. This Stop command must be
issued during the ninth clock cycle of a byte read when
the bus is free (the ACK/NAK cycle).
LTC2499 Address
The LTC2499 has three address pins (CA0, CA1, CA2).
Each may be tied high, low, or left floating enabling one
of 27 possible addresses (see Table 5).
In addition to the configurable addresses listed in Table 5,
the LTC2499 also contains a global address (1110111)
which may be used for synchronizing multiple LTC2499s or
other LTC24XX delta-sigma I2C devices (see Synchronizing
Multiple LTC2499s with a Global Address Call section).
Operation Sequence
The LTC2499 acts as a transmitter or receiver, as shown
in Figure 6. The device may be programmed to perform
several functions. These include input channel selection,
measure the internal temperature, selecting the line frequency rejection (50Hz, 60Hz, or simultaneous 50Hz and
60Hz), and a 2x speed mode.
Continuous Read
In applications where the input channel/configuration does
not need to change for each cycle, the conversion can be
continuously performed and read without a write cycle
(see Figure 7). The configuration/input channel remains
unchanged from the last value written into the device. If
the device has not been written to since power up, the
configuration is set to the default value. At the end of a
read operation, a new conversion automatically begins.
At the conclusion of the conversion cycle, the next result
Table 5. Address Assignment
CA2
CA1
CA0
ADDRESS
LOW
LOW
LOW
0010100
LOW
LOW
HIGH
0010110
LOW
LOW
FLOAT
0010101
LOW
HIGH
LOW
0100110
LOW
HIGH
HIGH
0110100
LOW
HIGH
FLOAT
0100111
LOW
FLOAT
LOW
0010111
LOW
FLOAT
HIGH
0100101
LOW
FLOAT
FLOAT
0100100
HIGH
LOW
LOW
1010110
HIGH
LOW
HIGH
1100100
HIGH
LOW
FLOAT
1010111
HIGH
HIGH
LOW
1110100
HIGH
HIGH
HIGH
1110110
HIGH
HIGH
FLOAT
1110101
HIGH
FLOAT
LOW
1100101
HIGH
FLOAT
HIGH
1100111
HIGH
FLOAT
FLOAT
1100110
FLOAT
LOW
LOW
0110101
FLOAT
LOW
HIGH
0110111
FLOAT
LOW
FLOAT
0110110
FLOAT
HIGH
LOW
1000111
FLOAT
HIGH
HIGH
1010101
FLOAT
HIGH
FLOAT
1010100
FLOAT
FLOAT
LOW
1000100
FLOAT
FLOAT
HIGH
1000110
FLOAT
FLOAT
FLOAT
1000101
may be read using the method described above. If the
conversion cycle is not concluded and a valid address
selects the device, the LTC2499 generates a NAK signal
indicating the conversion cycle is in progress.
Continuous Read/Write
Once the conversion cycle is concluded, the LTC2499 can
be written to and then read from using the Repeated Start
(Sr) command.
Figure 8 shows a cycle which begins with a data Write, a
repeated Start, followed by a Read and concluded with a
Stop command. The following conversion begins after all
2499fc
21
LTC2499
APPLICATIONS INFORMATION
S
CONVERSION
ACK
R/W
7-BIT ADDRESS
DATA
SLEEP
Sr
DATA TRANSFERRING
P
DATA INPUT/OUTPUT
CONVERSION
2499 F05
Figure 6. Conversion Sequence
S
7-BIT ADDRESS
R ACK
READ
P
S
7-BIT ADDRESS
R ACK
READ
P
CONVERSION
CONVERSION
SLEEP
DATA OUTPUT
SLEEP
DATA OUTPUT
CONVERSION
2499 F07
Figure 7. Consecutive Reading with the Same Input/Configuration
S
7-BIT ADDRESS
CONVERSION
W ACK
SLEEP
WRITE
Sr
7-BIT ADDRESS
DATA INPUT
R ACK
ADDRESS
READ
DATA OUTPUT
P
CONVERSION
2499 F08
Figure 8. Write, Read, Start Conversion
S
7-BIT ADDRESS
CONVERSION
W ACK
SLEEP
WRITE (OPTIONAL)
DATA INPUT
P
CONVERSION
2499 F09
Figure 9. Start a New Conversion Without Reading Old Conversion Result
2499fc
22
LTC2499
APPLICATIONS INFORMATION
32 bits are read out of the device or after a Stop command.
The following conversion will be performed using the
newly programmed data. In cases where the same speed
(1x/2x mode) and rejection frequency (50Hz, 60Hz, 50Hz
and 60Hz) is used but the channel is changed, a Stop or
Repeated Start may be issued after the first byte (channel
selection data) is written into the device.
Discarding a Conversion Result and Initiating a New
Conversion with Optional Write
At the conclusion of a conversion cycle, a write cycle
can be initiated. Once the write cycle is acknowledged, a
Stop command will start a new conversion. If a new input
channel or conversion configuration is required, this data
can be written into the device and a Stop command will
initiate the next conversion (see Figure 9).
Synchronizing Multiple LTC2499s with a Global
Address Call
In applications where several LTC2499s (or other I2C
delta-sigma ADCs from Linear Technology Corporation)
are used on the same I2C bus, all converters can be synchronized through the use of a global address call. Prior
to issuing the global address call, all converters must have
completed a conversion cycle. The master then issues a
Start, followed by the global address 1110111, and a write
request. All converters will be selected and acknowledge
the request. The master then sends a write byte (optional)
followed by the Stop command. This will update the channel selection (optional) converter configuration (optional)
and simultaneously initiate a start of conversion for all
delta-sigma ADCs on the bus (see Figure 10). In order
SCL
SDA
LTC2499
S
LTC2499
GLOBAL ADDRESS
…
W ACK
LTC2499
WRITE (OPTIONAL)
P
ALL LTC2499s IN SLEEP
CONVERSION OF ALL LTC2499s
DATA INPUT
2499 F10
Figure 10. Synchronize Multiple LTC2499s with a Global Address Call
IIN+
IN+
INPUT
MULTIPLEXER
INTERNAL
SWITCH
NETWORK
EXTERNAL
CONNECTION
100Ω
( )
10kΩ
MUXOUTP
I IN+
ADCINP
(
I REF +
IIN–
IN–
IREF+
AVG
100Ω
(
0.5•REQ
1.5VREF + VREF(CM) – VIN(CM)
0.5 • REQ
)–
VIN2
VREF • REQ
REF + – REF VREF(CM) = 2
CEQ
12μF
10kΩ
IREF–
REF–
VIN(CM) VREF(CM)
=
VREF = REF + REF ADCINN
EXTERNAL
CONNECTION
REF+
AVG
AVG
where:
10kΩ
MUXOUTN
)
( )
= I IN–
VIN = IN+ IN , WHERE IN+ AND IN ARE THE SELECTED INPUT CHANNELS
IN+ – IN VIN(CM) = 2
REQ = 2.71M INTERNAL OSCILLATOR 60Hz MODE
REQ = 2.98M INTERNAL OSCILLATOR 50Hz/60Hz MODE
10kΩ
2499 F11
(
)
REQ = 0.833• 1012 /fEOSC EXTERNAL OSCILLATOR
SWITCHING FREQUENCY
fSW = 123kHz INTERNAL OSCILLATOR
fSW = 0.4 • fEOSC EXTERNAL OSCILLATOR
Figure 11. Equivalent Analog Input Circuit
2499fc
23
LTC2499
APPLICATIONS INFORMATION
to synchronize multiple converters without changing
the channel or configuration, a Stop may be issued after
acknowledgement of the global write command. Global
read commands are not allowed and the converters will
NAK a global read request.
Driving the Input and Reference
The input and reference pins of the LTC2499 are connected
directly to a switched capacitor network. Depending on
the relationship between the differential input voltage and
the differential reference voltage, these capacitors are
switched between these four pins. Each time a capacitor
is switched between two of these pins, a small amount
of charge is transferred. A simplified equivalent circuit is
shown in Figure 11.
When using the LTC2499’s internal oscillator, the input
capacitor array is switched at 123kHz. The effect of the
charge transfer depends on the circuitry driving the input/reference pins. If the total external RC time constant
is less than 580ns the errors introduced by the sampling
process are negligible since complete settling occurs.
Typically, the reference inputs are driven from a low
impedance source. In this case, complete settling occurs
even with large external bypass capacitors. The inputs
(CH0-CH15, COM), on the other hand, are typically driven
from larger source resistances. Source resistances up
to 10k may interface directly to the LTC2499 and settle
completely; however, the addition of external capacitors
at the input terminals in order to filter unwanted noise
(antialiasing) results in incomplete settling.
The LTC2499 offers two methods of removing these
errors. The first is an automatic differential input current
cancellation (Easy Drive) and the second is the insertion
of an external buffer between the MUXOUT and ADCIN
pins, thus isolating the input switching from the source
resistance.
Automatic Differential Input Current Cancellation
In applications where the sensor output impedance is
low (up to 10kΩ with no external bypass capacitor or up
to 500Ω with 0.001μF bypass), complete settling of the
input occurs. In this case, no errors are introduced and
direct digitization is possible.
For many applications, the sensor output impedance
combined with external input bypass capacitors produces
RC time constants much greater than the 580ns required
for 1ppm accuracy. For example, a 10kΩ bridge driving a
0.1μF capacitor has a time constant an order of magnitude
greater than the required maximum.
The LTC2499 uses a proprietary switching algorithm
that forces the average differential input current to zero
independent of external settling errors. This allows direct
digitization of high impedance sensors without the need
for buffers.
The switching algorithm forces the average input current
on the positive input (IIN+) to be equal to the average input
current on the negative input (IIN–). Over the complete
conversion cycle, the average differential input current
(IIN+ – IIN–) is zero. While the differential input current is
zero, the common mode input current (IIN+ + IIN–)/2 is
proportional to the difference between the common mode
input voltage (VIN(CM)) and the common mode reference
voltage (VREF(CM)).
In applications where the input common mode voltage is
equal to the reference common mode voltage, as in the
case of a balanced bridge, both the differential and common mode input current are zero. The accuracy of the
converter is not compromised by settling errors.
In applications where the input common mode voltage is
constant but different from the reference common mode
voltage, the differential input current remains zero while
the common mode input current is proportional to the
difference between VIN(CM) and VREF(CM). For a reference
common mode voltage of 2.5V and an input common mode
of 1.5V, the common mode input current is approximately
0.74μA (in simultaneous 50Hz/60Hz rejection mode). This
common mode input current does not degrade the accuracy
if the source impedances tied to IN+ and IN– are matched.
Mismatches in source impedance lead to a fixed offset
error but do not effect the linearity or full-scale reading.
A 1% mismatch in a 1k source resistance leads to a 74μV
shift in offset voltage.
In applications where the common mode input voltage
varies as a function of the input signal level (single-ended
type sensors), the common mode input current varies
proportionally with input voltage. For the case of balanced
2499fc
24
LTC2499
APPLICATIONS INFORMATION
input impedances, the common mode input current effects
are rejected by the large CMRR of the LTC2499, leading
to little degradation in accuracy. Mismatches in source
impedances lead to gain errors proportional to the difference between the common mode input and common
mode reference. 1% mismatches in 1k source resistances
lead to gain errors on the order of 15ppm. Based on the
stability of the internal sampling capacitors and the accuracy of the internal oscillator, a one-time calibration will
remove this error.
source impedances are not possible. One pair of external
buffers/amplifiers can be shared between all 17 analog
inputs. The LTC2499 performs an internal offset calibration
every conversion cycle in order to remove the offset and
drift of the ADC. This calibration is performed through a
combination of front end switching and digital processing. Since the external amplifier is placed between the
multiplexer and the ADC, it is inside this correction loop.
This results in automatic offset correction and offset drift
removal of the external amplifier.
In addition to the input sampling current, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (±10nA max), results
in a small offset shift. A 1k source resistance will create a
1μV typical and a 10μV maximum offset voltage.
The LTC6078 is an excellent amplifier for this function.
It operates with supply voltages as low as 2.7V and its
noise level is 18nV/√Hz. The Easy Drive input technology
of the LTC2499 enables an RC network to be added directly
to the output of the LTC6078. The capacitor reduces the
magnitude of the current spikes seen at the input to the
ADC and the resistor isolates the capacitor load from the
op amp output enabling stable operation. The LTC6078
can also be biased at supply rails beyond those used by
the LTC2499. This allows the external sensor to swing railto-rail (–0.3V to VCC + 0.3V) without the need of external
level-shift circuitry.
Automatic Offset Calibration of External Buffers/
Amplifiers
In addition to the Easy Drive input current cancellation,
the LTC2499 allows an external amplifier to be inserted
between the multiplexer output and the ADC input (see
Figure 12). This is useful in applications where balanced
LTC2499
$3 ADC
WITH
EASY DRIVE
INPUTS
MUXOUTN
INPUT
MUX
MUXOUTP
ANALOG 17
INPUTS
2
–
1/2 LTC6078
3
6
+
+
SCL
1k
0.1μF
–
1/2 LTC6078
5
1
SDA
7
1k
2499 F12
0.1μF
Figure 12. External Buffers Provide High Impedance Inputs
and Amplifier Offsets are Automatically Cancelled
2499fc
25
LTC2499
APPLICATIONS INFORMATION
Reference Current
Similar to the analog inputs, the LTC2499 samples the
differential reference pins (REF+ and REF–) transferring
small amounts of charge to and from these pins, thus
producing a dynamic reference current. If incomplete settling occurs (as a function the reference source resistance
and reference bypass capacitance) linearity and gain errors
are introduced.
For relatively small values of external reference capacitance
(CREF < 1nF), the voltage on the sampling capacitor settles
90
60
50
0
CREF = 0.01μF
CREF = 0.001μF
CREF = 100pF
CREF = 0pF
40
30
20
–20
–30
–40
–50
VCC = 5V
–60 VREF = 5V
V + = 1.25V
–70 VIN– = 3.75V
IN
–80 fO = GND
TA = 25°C
–90
10
0
10
0
–10
0
10
CREF = 0.01μF
CREF = 0.001μF
CREF = 100pF
CREF = 0pF
–10
–FS ERROR (ppm)
+FS ERROR (ppm)
70
In cases where large bypass capacitors are required on
the reference inputs (CREF > .01μF), full-scale and linearity errors are proportional to the value of the reference
resistance. Every ohm of reference resistance produces
a full-scale error of approximately 0.5ppm (while operating in simultaneous 50Hz/60Hz mode (see Figures 15
and 16)). If the input common mode voltage is equal to
10
VCC = 5V
VREF = 5V
VIN+ = 3.75V
VIN– = 1.25V
fO = GND
TA = 25°C
80
for reference impedances of many kΩ (if CREF = 100pF up
to 10kΩ will not degrade the performance (see Figures 13
and 14)).
1k
100
RSOURCE (Ω)
10k
100k
1k
100
RSOURCE (Ω)
10k
2499 F13
Figure 13. +FS Error vs RSOURCE at VREF (Small CREF)
VCC = 5V
VREF = 5V
VIN+ = 3.75V
VIN– = 1.25V
fO = GND
TA = 25°C
+FS ERROR (ppm)
400
300
Figure 14. –FS Error vs RSOURCE at VREF (Small CREF)
0
CREF = 1μF, 10μF
–100
CREF = 0.1μF
200
CREF = 0.01μF
100
0
2499 F14
–FS ERROR (ppm)
500
CREF = 0.01μF
–200
CREF = 1μF, 10μF
–300
VCC = 5V
VREF = 5V
VIN+ = 1.25V
VIN– = 3.75V
fO = GND
TA = 25°C
–400
0
200
100k
600
400
RSOURCE (Ω)
800
1000
2499 F15
Figure 15. +FS Error vs RSOURCE at VREF (Large CREF)
–500
0
200
CREF = 0.1μF
600
400
RSOURCE (Ω)
800
1000
2499 F16
Figure 16. –FS Error vs RSOURCE at VREF (Large CREF)
2499fc
26
LTC2499
APPLICATIONS INFORMATION
When using the internal oscillator, the LTC2499 is designed to reject line frequencies. As shown in Figure 20,
rejection nulls occur at multiples of frequency fN, where
fN is determined by the input control bits FA and FB
(fN = 50Hz or 60Hz or 55Hz for simultaneous rejection).
Multiples of the modulator sampling rate (fS = fN • 256)
only reject noise to 15dB (see Figure 21); if noise sources
are present at these frequencies antialiasing will reduce
their effects.
10
R = 1k
2
R = 500Ω
0
R = 100Ω
–2
–4
–6
–8
–10
–0.5
–0.3
0.1
–0.1
VIN/VREF
0.3
0.5
0
2499 F17
Figure 17. INL vs Differential Input Voltage and
Reference Source Resistance for CREF > 1μF
the reference common mode voltage, a linearity error of
approximately 0.67ppm per 100Ω of reference resistance
results (see Figure 17). In applications where the input
and reference common mode voltages are different, the
errors increase. A 1V difference in between common mode
input and common mode reference results in a 6.7ppm
INL error for every 100Ω of reference resistance.
In addition to the reference sampling charge, the reference
ESD protection diodes have a temperature dependent leakage current. This leakage current, nominally 1nA (±10nA
max) results in a small gain error. A 100Ω reference
resistance will create a 0.5μV full-scale error.
INPUT NORMAL MODE REJECTION (dB)
INL (ppm OF VREF)
VCC = 5V
8 VREF = 5V
VIN(CM) = 2.5V
6 T = 25°C
A
4 CREF = 10μF
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS11fS12fS
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2499 F18
Figure 18. Input Normal Mode Rejection, Internal
Oscillator and 50Hz Rejection Mode
One of the advantages delta-sigma ADCs offer over
conventional ADCs is on-chip digital filtering. Combined
with a large oversample ratio, the LTC2499 significantly
simplifies antialiasing filter requirements. Additionally,
the input current cancellation feature allows external low
pass filtering without degrading the DC performance of
the device.
SINC4
digital filter provides excellent normal mode
The
rejection at all frequencies except DC and integer multiples
of the modulator sampling frequency (fS) (see Figures 18
and 19). The modulator sampling frequency is fS =
15,360Hz while operating with its internal oscillator and
fS = fEOSC/20 when operating with an external oscillator
of frequency fEOSC .
INPUT NORMAL MODE REJECTION (dB)
0
Normal Mode Rejection and Antialiasing
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2499 F19
Figure 19. Input Normal Mode Rejection, Internal
Oscillator and 60Hz Rejection Mode
2499fc
27
LTC2499
APPLICATIONS INFORMATION
The user can expect to achieve this level of performance
using the internal oscillator, as shown in Figures 22, 23,
and 24. Measured values of normal mode rejection are
shown superimposed over the theoretical values in all
three rejection modes.
Traditional high order delta-sigma modulators suffer from
potential instabilities at large input signal levels. The
proprietary architecture used for the LTC2499 third-order
INPUT NORMAL MODE REJECTION (dB)
0
modulator resolves this problem and guarantees stability
with input signals 150% of full scale. In many industrial
applications, it is not uncommon to have microvolt level
signals superimposed over unwanted error sources with
several volts if peak-to-peak noise. Figures 25 and 26 show
measurement results for the rejection of a 7.5V peakto-peak noise source (150% of full scale) applied to the
LTC2499. These curves show that the rejection performance
is maintained even in extremely noisy environments.
fN = fEOSC/5120
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
fN
2fN 3fN 4fN 5fN 6fN 7fN
INPUT SIGNAL FREQUENCY (Hz)
8fN
2499 F20
Figure 20. Input Normal Mode Rejection at DC
INPUT NORMAL MODE REJECTION (dB)
0
–10
fN = fEOSC/5120
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
250fN 252fN 254fN 256fN 258fN 260fN 262fN
INPUT SIGNAL FREQUENCY (Hz)
2499 F21
Figure 21. Input Normal Mode Rejection at fS = 256 • fN
2499fc
28
LTC2499
APPLICATIONS INFORMATION
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
VIN(P-P) = 5V
TA = 25°C
MEASURED DATA
CALCULATED DATA
–20
–40
–60
–80
–100
–120
0
15
30
45
60
75
0
NORMAL MODE REJECTION (dB)
NORMAL MODE REJECTION (dB)
0
–20
–40
–80
–100
0
12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
INPUT FREQUENCY (Hz)
2498 F22
NORMAL MODE REJECTION (dB)
0
MEASURED DATA
CALCULATED DATA
–20
–40
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
VIN(P-P) = 5V
TA = 25°C
–60
–80
–100
–120
0
20
40
60
80
100
120
140
INPUT FREQUENCY (Hz)
160
180
200
220
2498 F23
Figure 23. Input Normal Mode Rejection vs Input Frequency with
Input Perturbation of 100% (50Hz Notch)
0
NORMAL MODE REJECTION (dB)
Figure 22. Input Normal Mode Rejection vs Input Frequency with
Input Perturbation of 100% (60Hz Notch)
VIN(P-P) = 5V
VIN(P-P) = 7.5V
(150% OF FULL SCALE)
–20
–60
–80
–100
–120
0
15
30
45
60
75
90 105 120 135 150 165 180 195 210 225 240
INPUT FREQUENCY (Hz)
2498 F26
Figure 25. Measure Input Normal Mode Rejection vs Input
Frequency with Input Perturbation of 150% (60Hz Notch)
NORMAL MODE REJECTION (dB)
0
VIN(P-P) = 5V
VIN(P-P) = 7.5V
(150% OF FULL SCALE)
–20
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
TA = 25°C
–40
2498 F24
Figure 24. Input Normal Mode Rejection vs Input Frequency with
Input Perturbation of 100% (50Hz/60Hz Notch)
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
VIN(P-P) = 5V
TA = 25°C
–60
–120
90 105 120 135 150 165 180 195 210 225 240
INPUT FREQUENCY (Hz)
MEASURED DATA
CALCULATED DATA
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
TA = 25°C
–40
–60
–80
–100
–120
0
12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
INPUT FREQUENCY (Hz)
2498 F27
Figure 26. Measure Input Normal Mode Rejection vs Input
Frequency with Input Perturbation of 150% (50Hz Notch)
2499fc
29
LTC2499
APPLICATIONS INFORMATION
Using the 2X speed mode of the LTC2499 alters the rejection
characteristics around DC and multiples of fS. The device
bypasses the offset calibration in order to increase the output
rate. The resulting rejection plots are shown in Figures 27
and 28. 1x type frequency rejection can be achieved using the 2x mode by performing a running average of the
previoius two conversion results (see Figure 29).
Output Data Rate
When using its internal oscillator, the LTC2499 produces
up to 7.5 samples per second (sps) with a notch frequency
of 60Hz. The actual output data rate depends upon the length
of the sleep and data output cycles which are controlled
by the user and can be made insignificantly short. When
operating with an external conversion clock (fO connected
to an external oscillator), the LTC2499 output data rate
can be increased. The duration of the conversion cycle is
41036/fEOSC. If fEOSC = 307.2kHz, the converter behaves
as if the internal oscillator is used.
An increase in fEOSC over the nominal 307.2kHz will translate into a proportional increase in the maximum output
data rate (up to a maximum of 100sps). The increase in
output rate leads to degradation in offset, full-scale error,
and effective resolution as well as a shift in frequency
rejection. When using the integrated temperature sensor,
the internal oscillator should be used or an external oscillator fEOSC = 307.2kHz maximum.
A change in fEOSC results in a proportional change in the
internal notch position. This leads to reduced differential
mode rejection of line frequencies. The common mode
rejection of line frequencies remains unchanged, thus fully
differential input signals with a high degree of symmetry
on both the IN+ and IN – pins will continue to reject line
frequency noise.
An increase in fEOSC also increases the effective dynamic
input and reference current. External RC networks will
continue to have zero differential input current, but the
time required for complete settling (580ns for fEOSC =
307.2kHz) is reduced, proportionally.
Once the external oscillator frequency is increased above
1MHz (a more than 3x increase in output rate) the effectiveness of internal auto calibration circuits begins to degrade.
This results in larger offset errors, full-scale errors, and
decreased resolution, as seen in Figures 30-37.
0
INPUT NORMAL REJECTION (dB)
INPUT NORMAL REJECTION (dB)
0
–20
–40
–60
–80
–100
–120
0
fN
2fN 3fN 4fN 5fN 6fN 7fN
INPUT SIGNAL FREQUENCY (fN)
8fN
2499 F27
Figure 27. Input Normal Mode Rejection 2x Speed Mode
–20
–40
–60
–80
–100
–120
248 250 252 254 256 258 260 262 264
INPUT SIGNAL FREQUENCY (fN)
2499 F28
Figure 28. Input Normal Mode Rejection 2x Speed Mode
2499fc
30
LTC2499
APPLICATIONS INFORMATION
50
OFFSET ERROR (ppm OF VREF)
NORMAL MODE REJECTION (dB)
–80
NO AVERAGE
–90
WITH
RUNNING
AVERAGE
–100
–110
–120
–130
3500
VIN(CM) = VREF(CM)
VCC = VREF = 5V
VIN = 0V
fO = EXT CLOCK
40
3000
+FS ERROR (ppm OF VREF)
–70
30
TA = 85°C
20
10
2500
TA = 85°C
2000
1500
0
500
–10
0
60
62
54 56
58
48 50
52
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
TA = 25°C
1000
TA = 25°C
–140
VIN(CM) = VREF(CM)
VCC = VREF = 5V
fO = EXT CLOCK
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2499 F30
2499 F29
Figure 29. Input Normal Mode
Rejection 2x Speed Mode with and
Without Running Averaging
2499 F31
Figure 30. Offset Error vs Output Data
Rate and Temperature
Figure 31. +FS Error vs Output Data
Rate and Temperature
24
0
22
TA = 25°C
–500
22
–1000
20
20
TA = 25°C
–1500
TA = 85°C
–2000
–2500
–3500
VIN(CM) = VREF(CM)
VCC = VREF = 5V
fO = EXT CLOCK
18
16
14
12
10
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
VIN(CM) = VREF(CM)
VCC = VREF = 5V
VIN = 0V
fO = EXT CLOCK
RES = LOG 2 (VREF/NOISERMS)
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
TA = 25°C
14
2499 F34
Figure 33. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Temperature
24
20
VIN(CM) = VREF(CM)
VIN = 0V
15 fO = EXT CLOCK
TA = 25°C
Figure 34. Resolution (INLMAX ≤ 1LSB)
vs Output Data Rate and Temperature
22
VCC = VREF = 5V
22
RESOLUTION (BITS)
OFFSET ERROR (ppm OF VREF)
TA = 85°C
16
2499 F33
2499 F32
Figure 32.–FS Error vs Output Data
Rate and Temperature
10
VCC = VREF = 5V
5
0
20
20
VCC = 5V, VREF = 2.5V
18
16
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
14 VIN(CM) = VREF(CM)
VIN = 0V
fO = EXT CLOCK
12 T = 25°C
A
RES = LOG 2 (VREF/NOISERMS)
10
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2499 F35
2499 F36
–5
VCC = 5V, VREF = 2.5V
–10
18
VIN(CM) = VREF(CM)
12 VCC = VREF = 5V
fO = EXT CLOCK
RES = LOG 2 (VREF/INLMAX)
10
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
Figure 35. Offset Error vs Output
Data Rate and Temperature
RESOLUTION (BITS)
–3000
RESOLUTION (BITS)
RESOLUTION (BITS)
–FS ERROR (ppm OF VREF)
TA = 85°C
Figure 36. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Temperature
18
VCC = VREF = 5V
16
VCC = 5V, VREF = 2.5V
VIN(CM) = VREF(CM)
14
VIN = 0V
REF– = GND
12 fO = EXT CLOCK
TA = 25°C
RES = LOG 2 (VREF/INLMAX)
10
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2499 F37
Figure 37. Resolution (INLMAX ≤ 1LSB)
vs Output Data Rate and Temperature
2499fc
31
LTC2499
PACKAGE DESCRIPTION
UHF Package
38-Lead Plastic QFN (5mm × 7mm)
(Reference LTC DWG # 05-08-1701 Rev C)
0.70 p 0.05
5.50 p 0.05
5.15 ± 0.05
4.10 p 0.05
3.00 REF
3.15 ± 0.05
PACKAGE
OUTLINE
0.25 p 0.05
0.50 BSC
5.5 REF
6.10 p 0.05
7.50 p 0.05
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
5.00 p 0.10
0.75 p 0.05
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 s 45o CHAMFER
3.00 REF
37
0.00 – 0.05
38
0.40 p0.10
PIN 1
TOP MARK
(SEE NOTE 6)
1
2
5.15 ± 0.10
7.00 p 0.10
5.50 REF
3.15 ± 0.10
(UH) QFN REF C 1107
0.200 REF 0.25 p 0.05
0.50 BSC
R = 0.125
TYP
R = 0.10
TYP
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE
OUTLINE M0-220 VARIATION WHKD
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
2499fc
32
LTC2499
REVISION HISTORY
REV
DATE
DESCRIPTION
C
11/09
Update Tables 1 and 2
(Revision history begins at Rev C)
PAGE NUMBER
16
2499fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
33
LTC2499
TYPICAL APPLICATION
External Buffers Provide High Impedance Inputs and
Amplifier Offsets are Automatically Cancelled
ΔΣ ADC
WITH
EASY DRIVE
INPUTS
MUXOUTN
2
–
1/2 LTC6078
3
6
+
+
SCL
1k
0.1μF
–
1/2 LTC6078
5
1
SDA
7
1k
2499 TA03
INPUT
MUX
MUXOUTP
LTC2499
ANALOG 17
INPUTS
0.1μF
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1236A-5
Precision Bandgap Reference, 5V
0.05% Max Initial Accuracy, 5ppm/°C Drift
LT1460
Micropower Series Reference
0.075% Max Initial Accuracy, 10ppm/°C Max Drift
LT1790
Micropower SOT-23 Low Dropout Reference Family
0.05% Max Initial Accuracy, 10ppm/°C Max Drift
LTC2400
24-Bit, No Latency ΔΣ ADC in SO-8
0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200μA
LTC2410
24-Bit, No Latency ΔΣ ADC with Differential Inputs
0.8μVRMS Noise, 2ppm INL
LTC2411/
LTC2411-1
24-Bit, No Latency ΔΣ ADCs with Differential Inputs in MSOP
1.45μVRMS Noise, 4ppm INL, Simultaneous 50Hz/60Hz
Rejection (LTC2411-1)
LTC2413
24-Bit, No Latency ΔΣ ADC with Differential Inputs
Simultaneous 50Hz/60Hz Rejection, 800nVRMS Noise
LTC2440
24-Bit, High Speed, Low Noise ΔΣ ADC
3.5kHz Output Rate, 200nV Noise, 24.6 ENOBs
LTC2442
24-Bit, High Speed, 2-/4-Channel ΔΣ ADC with Integrated
Amplifier
8kHz Output Rate, 200nV Noise, Simultaneous 50Hz/60Hz
Rejection
LTC2449
24-Bit, High Speed, 8-/16-Channel ΔΣ ADC
8kHz Output Rate, 200nV Noise, Simultaneous 50Hz/60Hz
Rejection
LTC2480/LTC2482/
LTC2484
16-Bit/24-Bit ΔΣ ADCs with Easy Drive Inputs, 600nV Noise,
Programmable Gain, and Temperature Sensor
Pin Compatible with 16-Bit and 24-Bit Versions
LTC2481/LTC2483/
LTC2485
16-Bit/24-Bit ΔΣ ADCs with Easy Drive Inputs, 600nV Noise,
I2C Interface, Programmable Gain, and Temperature Sensor
Pin Compatible with 16-Bit and 24-Bit Versions
LTC2496
16-Bit 8-/16-Channel ΔΣ ADC with Easy Drive Inputs and
SPI Interface
Pin-Compatible with LTC2498/LTC2449
LTC2497
16-Bit 8-/16-Channel ΔΣ ADC with Easy Drive Inputs and
I2C Interface
Pin-Compatible with LTC2499
LTC2498
24-Bit 8-/16-Channel ΔΣ ADC with Easy Drive Inputs and
SPI Interface, Temperature Sensor
Pin-Compatible with LTC2496/LTC2449
2499fc
34 Linear Technology Corporation
LT 1109 REV C • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
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© LINEAR TECHNOLOGY CORPORATION 2006