SLAS340G − MAY 2001 − REVISED JUNE 2004
D Low Supply-Voltage Range, 1.8 V . . . 3.6 V
D Ultralow-Power Consumption:
D
D
D
D
D
D
D
D
D
D Serial Onboard Programming,
− Active Mode: 200 µA at 1 MHz, 2.2 V
− Standby Mode: 0.7 µA
− Off Mode (RAM Retention): 0.1 µA
Five Power-Saving Modes
Wake-Up From Standby Mode in less
than 6 µs
Frequency-Locked Loop, FLL+
16-Bit RISC Architecture, 125-ns
Instruction Cycle Time
16-Bit Timer_A With Three† or Five‡
Capture/Compare Registers
Integrated LCD Driver for 96 Segments
On-Chip Comparator
Brownout Detector
Supply Voltage Supervisor/Monitor Programmable Level Detection on
MSP430F415/417 devices only
D
D
D
D
No External Programming Voltage Needed
Programmable Code Protection by Security
Fuse
Bootstrap Loader in Flash Devices
Family Members Include:
− MSP430C412: 4KB ROM, 256B RAM
− MSP430C413: 8KB ROM, 256B RAM
− MSP430F412: 4KB + 256B Flash
256B RAM
− MSP430F413: 8KB + 256B Flash
256B RAM
− MSP430F415: 16KB + 256B Flash
512B RAM
− MSP430F417: 32KB + 256B Flash
1KB RAM
Available in 64-Pin Quad Flat Pack (QFP)
and 64-pin QFN
For Complete Module Descriptions, Refer
to the MSP430x4xx Family User’s Guide,
Literature Number SLAU056
† ’x412 and ’x413 devices
‡ ’F415 and ’F417 devices
description
The Texas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low power
modes is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6µs.
The MSP430x41x series are microcontroller configurations with one or two built-in 16-bit timers, a comparator,
96 LCD segment drive capability, and 48 I/O pins.
Typical applications include sensor systems that capture analog signals, convert them to digital values, and
process the data and transmit them to a host system. The comparator and timer make the configurations ideal
for industrial meters, counter applications, handheld meters, etc.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
−40°C to 85°C
PLASTIC 64-PIN QFP (PM)
PLASTIC 64-PIN QFN (RTD)
MSP430C412IPM
MSP430C413IPM
MSP430F412IPM
MSP430F413IPM
MSP430F415IPM
MSP430F417IPM
MSP430C412IRTD§
MSP430C413IRTD§
MSP430F412IRTD
MSP430F413IRTD
MSP430F415IRTD§
MSP430F417IRTD§
§ Preliminary
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2001 − 2004, Texas Instruments Incorporated
!" #!$% &"'
&! #" #" (" " " !"
&& )*' &! #"+ &" ""%* %!&"
"+ %% #""'
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1
SLAS340G − MAY 2001 − REVISED JUNE 2004
AVCC
DVSS
AVSS
P6.2
P6.1
P6.0
RST/NMI
TCK
TMS
TDI/TCLK
TDO/TDI
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1
P1.3/SVSOUT
P1.4
pin designation, MSP430x412, MSP430x413
1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
2
47
3
46
4
45
5
44
6
43
7
42
8
MSP430x412
MSP430x413
9
41
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P1.5/TACLK/ACLK
P1.6/CA0
P1.7/CA1
P2.0/TA2
P2.1
P5.7/R33
P5.6/R23
P5.5/R13
R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P2.2/S23
P2.3/S22
P2.4/S21
P4.4/S5
P4.3/S6
P4.2/S7
P4.1/S8
P4.0/S9
P3.7/S10
P3.6/S11
P3.5/S12
P3.4/S13
P3.3/S14
P3.2/S15
P3.1/S16
P3.0/S17
P2.7/S18
P2.6/CAOUT/S19
P2.5/S20
DVCC
P6.3
P6.4
P6.5
P6.6
P6.7
NC
XIN
XOUT
NC
NC
P5.1/S0
P5.0/S1
P4.7/S2
P4.6/S3
P4.5/S4
NC − No internal connection. External connection to VSS recommended.
2
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SLAS340G − MAY 2001 − REVISED JUNE 2004
AVCC
DVSS
AVSS1
P6.2
P6.1
P6.0
RST/NMI
TCK
TMS
TDI/TCLK
TDO/TDI
P1.0/TA0.0
P1.1/TA0.0/MCLK
P1.2/TA0.1
P1.3/TA1.0/SVSOUT
P1.4/TA1.0
pin designation, MSP430x415, MSP430x417
1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
2
47
3
46
4
45
5
44
6
43
7
42
8
MSP430x415
MSP430x417
9
41
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P1.5/TA0CLK/ACLK
P1.6/CA0
P1.7/CA1
P2.0/TA0.2
P2.1/TA1.1
P5.7/R33
P5.6/R23
P5.5/R13
R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P2.2/TA1.2/S23
P2.3/TA1.3/S22
P2.4/TA1.4/S21
P4.4/S5
P4.3/S6
P4.2/S7
P4.1/S8
P4.0/S9
P3.7/S10
P3.6/S11
P3.5/S12
P3.4/S13
P3.3/S14
P3.2/S15
P3.1/S16
P3.0/S17
P2.7/S18
P2.6/CAOUT/S19
P2.5/TA1CLK/S20
DVCC
P6.3
P6.4
P6.5
P6.6
P6.7
NC
XIN
XOUT
AVSS2
NC
P5.1/S0
P5.0/S1
P4.7/S2
P4.6/S3
P4.5/S4
NC − No internal connection. External connection to VSS recommended.
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SLAS340G − MAY 2001 − REVISED JUNE 2004
functional block diagram, MSP430x412, MSP430x413
XIN
XOUT
DVCC
DVSS
AVCC
P1
AVSS RST/NMI
P2
8
Oscillator
FLL+
ACLK
4KB/8KB
256B RAM
P3
8
I/O Port 1/2
16 I/Os,
with
Interrupt
Capability
SMCLK Flash-F41x
ROM-C41x
P4
8
P5
8
I/O Port 3/4
16 I/Os
P6
8
8
I/O Port 5/6
16 I/Os
MCLK
Test
MAB,
4 Bit
MAB,MAB,
16 Bit16-Bit
JTAG
CPU
MCB
Emulation
Module
Incl. 16 Reg.
Bus
Conv
MDB,
16-Bit
MDB,
16 Bit
MDB, 8 Bit
4
TMS
Watchdog
Timer
TCK
Timer_A3
POR/
SVS/
Brownout
3 CC Reg
TDI/TCLK
Comparator
A
Basic
Timer 1
15/16-Bit
1 Interrupt
Vector
TDO/TDI
LCD
96
Segments
1,2,3,4 MUX
fLCD
functional block diagram, MSP430x415, MSP430x417
XIN
XOUT
DVCC
DVSS
AVCC AVSS1 AVSS2
P1
RST/NMI
P2
8
Oscillator
FLL+
ACLK
16KB Flash
512B RAM
SMCLK 32KB Flash
1KB RAM
P3
8
I/O Port 1/2
16 I/Os,
with
Interrupt
Capability
P4
8
P5
8
I/O Port 3/4
16 I/Os
P6
8
8
I/O Port 5/6
16 I/Os
MCLK
Test
MAB,
4 Bit
MAB,MAB,
16 Bit16-Bit
JTAG
CPU
MCB
Emulation
Module
Incl. 16 Reg.
Bus
Conv
MDB,
16-Bit
MDB,
16 Bit
MDB, 8 Bit
4
TMS
TCK
TDI/TCLK
Watchdog
Timer
Timer0_A3
Timer1_A5
3 CC Reg
5 CC Reg
15/16-Bit
POR/
Multilevel
SVS/
Brownout
TDO/TDI
Comparator
A
Basic
Timer 1
1 Interrupt
Vector
LCD
96
Segments
1,2,3,4 MUX
fLCD
4
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SLAS340G − MAY 2001 − REVISED JUNE 2004
Terminal Functions
MSP430x412, MSP430x413
TERMINAL
NAME
NO.
I/O
DESCRIPTION
AVCC
64
Positive terminal that supplies SVS, brownout, oscillator, FLL+, comparator_A, port 1, and LCD
resistive divider circuitry; must not power up prior to DVCC.
AVSS
62
Negative terminal that supplies SVS, brownout, oscillator, FLL+, comparator_A. Needs to be externally
connected to DVSS.
DVCC
1
Digital supply voltage, positive terminal. Supplies all parts, except those which are supplied via AVCC.
DVSS
63
Digital supply voltage, negative terminal. Supplies all digital parts, except those which are supplied via
AVCC/AVSS.
Not internally connected. Connection to VSS recommended.
NC
7, 10, 11
P1.0/TA0
53
I/O
General-purpose digital I/O/Timer_A. Capture: CCI0A input, compare: Out0 output/BSL transmit
P1.1/TA0/MCLK
52
I/O
General-purpose digital I/O/Timer_A. Capture: CCI0B input/MCLK output. Note: TA0 is only an input
on this pin/BSL receive
P1.2/TA1
51
I/O
General-purpose digital I/O/Timer_A, capture: CCI1A input, compare: Out1 output
P1.3/SVSOUT
50
I/O
General-purpose digital I/O/SVS: output of SVS comparator
P1.4
49
I/O
General-purpose digital I/O
P1.5/TACLK/ ACLK
48
I/O
General-purpose digital I/O/input of Timer_A clock/output of ACLK
P1.6/CA0
47
I/O
General-purpose digital I/O/Comparator_A input
P1.7/CA1
46
I/O
General-purpose digital I/O/Comparator_A input
P2.0/TA2
45
I/O
General-purpose digital I/O/ Timer_A capture: CCI2A input, compare: Out2 output
P2.1
44
I/O
General-purpose digital I/O
P2.2/S23
35
I/O
General-purpose digital I/O/LCD segment output 23 (see Note 1)
P2.3/S22
34
I/O
General-purpose digital I/O/LCD segment output 22 (see Note 1)
P2.4/S21
33
I/O
General-purpose digital I/O/LCD segment output 21 (see Note 1)
P2.5/S20
32
I/O
General-purpose digital I/O/LCD segment output 20 (see Note 1)
P2.6/CAOUT/S19
31
I/O
General-purpose digital I/O/Comparator_A output/LCD segment output 19 (see Note 1)
P2.7/S18
30
I/O
General-purpose digital I/O/LCD segment output 18 (see Note 1)
P3.0/S17
29
I/O
General-purpose digital I/O/ LCD segment output 17 (see Note 1)
P3.1/S16
28
I/O
General-purpose digital I/O/ LCD segment output 16 (see Note 1)
P3.2/S15
27
I/O
General-purpose digital I/O/ LCD segment output 15 (see Note 1)
P3.3/S14
26
I/O
General-purpose digital I/O/ LCD segment output 14 (see Note 1)
P3.4/S13
25
I/O
General-purpose digital I/O/LCD segment output 13 (see Note 1)
P3.5/S12
24
I/O
General-purpose digital I/O/LCD segment output 12 (see Note 1)
P3.6/S11
23
I/O
General-purpose digital I/O/LCD segment output 11 (see Note 1)
P3.7/S10
22
I/O
General-purpose digital I/O/LCD segment output 10 (see Note 1)
NOTE 1: LCD function selected automatically when applicable LCD module control bits are set, not with PxSEL bits.
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SLAS340G − MAY 2001 − REVISED JUNE 2004
Terminal Functions (Continued)
MSP430x412, MSP430x413 (continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
P4.0/S9
21
I/O
General-purpose digital I/O/LCD segment output 9 (see Note 1)
P4.1/S8
20
I/O
General-purpose digital I/O/LCD segment output 8 (see Note 1)
P4.2/S7
19
I/O
General-purpose digital I/O/LCD segment output 7 (see Note 1)
P4.3/S6
18
I/O
General-purpose digital I/O/LCD segment output 6 (see Note 1)
P4.4/S5
17
I/O
General-purpose digital I/O/LCD segment output 5 (see Note 1)
P4.5/S4
16
I/O
General-purpose digital I/O/LCD segment output 4 (see Note 1)
P4.6/S3
15
I/O
General-purpose digital I/O/LCD segment output 3 (see Note 1)
P4.7/S2
14
I/O
General-purpose digital I/O/LCD segment output 2 (see Note 1)
P5.0/S1
13
I/O
General-purpose digital I/O/LCD segment output 1 (see Note 1)
P5.1/S0
12
I/O
General-purpose digital I/O/LCD segment output 0 (see Note 1)
COM0
36
O
Common output. COM0−3 are used for LCD backplanes
P5.2/COM1
37
I/O
General-purpose digital I/O/common output. COM0−3 are used for LCD backplanes
P5.3/COM2
38
I/O
General-purpose digital I/O/common output. COM0−3 are used for LCD backplanes
P5.4/COM3
39
I/O
General-purpose digital I/O/common output. COM0−3 are used for LCD backplanes
R03
40
I
P5.5/R13
41
I/O
General-purpose digital I/O/input port of third most positive analog LCD level (V4 or V3)
P5.6/R23
42
I/O
General-purpose digital I/O/input port of second most positive analog LCD level (V2)
P5.7/R33
43
I/O
General-purpose digital I/O/output port of most positive analog LCD level (V1)
P6.0
59
I/O
General-purpose digital I/O
P6.1
60
I/O
General-purpose digital I/O
P6.2
61
I/O
General-purpose digital I/O
P6.3
2
I/O
General-purpose digital I/O
P6.4
3
I/O
General-purpose digital I/O
P6.5
4
I/O
General-purpose digital I/O
P6.6
5
I/O
General-purpose digital I/O
P6.7
6
I/O
General-purpose digital I/O
RST/NMI
58
I
Reset input or nonmaskable interrupt input port
TCK
57
I
Test clock. TCK is the clock input port for device programming and test.
TDI/TCLK
55
I
Test data input or test clock input. The device protection fuse is connected to TDI.
TDO/TDI
54
I/O
TMS
56
I
Test mode select. TMS is used as an input port for device programming and test.
XIN
8
I
Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
9
O
Output terminal of crystal oscillator XT1.
NA
NA
XOUT
QFN Pad
Input port of fourth positive (lowest) analog LCD level (V5)
Test data output port. TDO/TDI data output or programming data input terminal.
QFN package pad connection to VSS recommended.
NOTE 1: LCD function selected automatically when applicable LCD module control bits are set, not with PxSEL bits.
6
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SLAS340G − MAY 2001 − REVISED JUNE 2004
Terminal Functions (Continued)
MSP430x415, MSP430x417
TERMINAL
NAME
NO.
I/O
DESCRIPTION
AVCC
64
Positive terminal that supplies SVS, brownout, oscillator, FLL+, comparator_A, port 1, and LCD
resistive divider circuitry; must not power up prior to DVCC.
AVSS1
62
Negative terminal that supplies SVS, brownout, oscillator, FLL+, comparator_A. Needs to be externally
connected to DVSS.
DVCC
1
Digital supply voltage, positive terminal. Supplies all parts, except those which are supplied via AVCC.
DVSS
63
AVSS2
10
Digital supply voltage, negative terminal. Supplies all digital parts, except those which are supplied via
AVCC/AVSS.
Negative terminal that supplies SVS, brownout, oscillator, FLL+, comparator_A. Needs to be externally
connected to DVSS.
NC
7, 11
Not internally connected. Connection to VSS recommended.
P1.0/TA0.0
53
I/O
General-purpose digital I/O/Timer0_A. Capture: CCI0A input, compare: Out0 output/BSL transmit
P1.1/TA0.0/MCLK
52
I/O
General-purpose digital I/O/Timer0_A. Capture: CCI0B input/MCLK output. Note: TA0 is only an input
on this pin/BSL receive
P1.2/TA0.1
51
I/O
General-purpose digital I/O/Timer0_A, capture: CCI1A input, compare: Out1 output
P1.3/TA1.0/
SVSOUT
50
I/O
General-purpose digital I/O/Timer1_A, capture: CCI0B input/SVS: output of SVS comparator
P1.4/TA1.0
49
I/O
General-purpose digital I/O/Timer1_A, capture: CCI0A input, compare: Out0 output
P1.5/TA0CLK/
ACLK
48
I/O
General-purpose digital I/O/input of Timer0_A clock/output of ACLK
P1.6/CA0
47
I/O
General-purpose digital I/O/Comparator_A input
P1.7/CA1
46
I/O
General-purpose digital I/O/Comparator_A input
P2.0/TA0.2
45
I/O
General-purpose digital I/O/ Timer0_A capture: CCI2A input, compare: Out2 output
P2.1/TA1.1
44
I/O
General-purpose digital I/O/Timer1_A, capture: CCI1A input, compare: Out1 output
P2.2/TA1.2/S23
35
I/O
General-purpose digital I/O/Timer1_A, capture: CCI2A input, compare: Out2 output/LCD segment
output 23 (see Note 1)
P2.3/TA1.3/S22
34
I/O
General-purpose digital I/O/Timer1_A, capture: CCI3A input, compare: Out3 output/LCD segment
output 22 (see Note 1)
P2.4/TA1.4/S21
33
I/O
General-purpose digital I/O/Timer1_A, capture: CCI4A input, compare: Out4 output/LCD segment
output 21 (see Note 1)
P2.5/TA1CLK/S20
32
I/O
General-purpose digital I/O/input of Timer1_A clock/LCD segment output 20 (see Note 1)
P2.6/CAOUT/S19
31
I/O
General-purpose digital I/O/Comparator_A output/LCD segment output 19 (see Note 1)
P2.7/S18
30
I/O
General-purpose digital I/O/LCD segment output 18 (see Note 1)
P3.0/S17
29
I/O
General-purpose digital I/O/ LCD segment output 17 (see Note 1)
P3.1/S16
28
I/O
General-purpose digital I/O/ LCD segment output 16 (see Note 1)
P3.2/S15
27
I/O
General-purpose digital I/O/ LCD segment output 15 (see Note 1)
P3.3/S14
26
I/O
General-purpose digital I/O/ LCD segment output 14 (see Note 1)
P3.4/S13
25
I/O
General-purpose digital I/O/LCD segment output 13 (see Note 1)
P3.5/S12
24
I/O
General-purpose digital I/O/LCD segment output 12 (see Note 1)
P3.6/S11
23
I/O
General-purpose digital I/O/LCD segment output 11 (see Note 1)
P3.7/S10
22
I/O
General-purpose digital I/O/LCD segment output 10 (see Note 1)
NOTE 1: LCD function selected automatically when applicable LCD module control bits are set, not with PxSEL bits.
POST OFFICE BOX 655303
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SLAS340G − MAY 2001 − REVISED JUNE 2004
Terminal Functions (Continued)
MSP430x415, MSP430x417 (continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
P4.0/S9
21
I/O
General-purpose digital I/O/LCD segment output 9 (see Note 1)
P4.1/S8
20
I/O
General-purpose digital I/O/LCD segment output 8 (see Note 1)
P4.2/S7
19
I/O
General-purpose digital I/O/LCD segment output 7 (see Note 1)
P4.3/S6
18
I/O
General-purpose digital I/O/LCD segment output 6 (see Note 1)
P4.4/S5
17
I/O
General-purpose digital I/O/LCD segment output 5 (see Note 1)
P4.5/S4
16
I/O
General-purpose digital I/O/LCD segment output 4 (see Note 1)
P4.6/S3
15
I/O
General-purpose digital I/O/LCD segment output 3 (see Note 1)
P4.7/S2
14
I/O
General-purpose digital I/O/LCD segment output 2 (see Note 1)
P5.0/S1
13
I/O
General-purpose digital I/O/LCD segment output 1 (see Note 1)
P5.1/S0
12
I/O
General-purpose digital I/O/LCD segment output 0 (see Note 1)
COM0
36
O
Common output. COM0−3 are used for LCD backplanes
P5.2/COM1
37
I/O
General-purpose digital I/O/common output. COM0−3 are used for LCD backplanes
P5.3/COM2
38
I/O
General-purpose digital I/O/common output. COM0−3 are used for LCD backplanes
P5.4/COM3
39
I/O
General-purpose digital I/O/common output. COM0−3 are used for LCD backplanes
R03
40
I
P5.5/R13
41
I/O
General-purpose digital I/O/input port of third most positive analog LCD level (V4 or V3)
P5.6/R23
42
I/O
General-purpose digital I/O/input port of second most positive analog LCD level (V2)
P5.7/R33
43
I/O
General-purpose digital I/O/output port of most positive analog LCD level (V1)
P6.0
59
I/O
General-purpose digital I/O
P6.1
60
I/O
General-purpose digital I/O
P6.2
61
I/O
General-purpose digital I/O
P6.3
2
I/O
General-purpose digital I/O
P6.4
3
I/O
General-purpose digital I/O
P6.5
4
I/O
General-purpose digital I/O
P6.6
5
I/O
General-purpose digital I/O
P6.7/SVSIN
6
I/O
General-purpose digital I/O/SVS, analog input
RST/NMI
58
I
Reset input or nonmaskable interrupt input port
TCK
57
I
Test clock. TCK is the clock input port for device programming and test.
TDI/TCLK
55
I
Test data input or test clock input. The device protection fuse is connected to TDI.
TDO/TDI
54
I/O
TMS
56
I
Test mode select. TMS is used as an input port for device programming and test.
XIN
8
I
Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
9
O
Output terminal of crystal oscillator XT1.
NA
NA
XOUT
QFN Pad
Input port of fourth positive (lowest) analog LCD level (V5)
Test data output port. TDO/TDI data output or programming data input terminal.
QFN package pad connection to VSS recommended.
NOTE 1: LCD function selected automatically when applicable LCD module control bits are set, not with PxSEL bits.
8
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short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
Program Counter
PC/R0
Stack Pointer
SP/R1
SR/CG1/R2
Status Register
Constant Generator
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The
remaining registers are general-purpose
registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
instruction set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
Table 1. Instruction Word Formats
Dual operands, source-destination
e.g. ADD R4,R5
R4 + R5 −−−> R5
Single operands, destination only
e.g. CALL
PC −−>(TOS), R8−−> PC
Relative jump, un/conditional
e.g. JNE
R8
Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE
S D
Indirect
D
D
D
D
D
Indirect
autoincrement
Register
Indexed
Symbolic (PC relative)
Absolute
Immediate
NOTE: S = source
D
D
D
D
SYNTAX
EXAMPLE
MOV Rs,Rd
MOV R10,R11
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
OPERATION
R10
−−> R11
M(2+R5)−−> M(6+R6)
MOV EDE,TONI
M(EDE) −−> M(TONI)
MOV &MEM,&TCDAT
M(MEM) −−> M(TCDAT)
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) −−> M(Tab+R6)
D
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) −−> R11
R10 + 2−−> R10
D
MOV #X,TONI
MOV #45,TONI
#45
−−> M(TONI)
D = destination
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operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
D Active mode AM;
−
All clocks are active
D Low-power mode 0 (LPM0);
−
CPU is disabled
ACLK and SMCLK remain active, MCLK is available to modules
FLL+ Loop control remains active
D Low-power mode 1 (LPM1);
−
CPU is disabled
ACLK and SMCLK remain active, MCLK is available to modules
FLL+ Loop control is disabled
D Low-power mode 2 (LPM2);
−
CPU is disabled
MCLK and FLL+ loop control and DCOCLK are disabled
DCO’s dc-generator remains enabled
ACLK remains active
D Low-power mode 3 (LPM3);
−
CPU is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc-generator is disabled
ACLK remains active
D Low-power mode 4 (LPM4);
−
10
CPU is disabled
ACLK is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc-generator is disabled
Crystal oscillator is stopped
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interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the ROM with an address range
0FFFFh − 0FFE0h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction
sequence.
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD ADDRESS
PRIORITY
Power-up
External Reset
Watchdog
Flash memory
WDTIFG
KEYV
(see Note 1)
Reset
0FFFEh
15, highest
NMI
Oscillator Fault
Flash memory access violation
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1 and 3)
(Non)maskable
(Non)maskable
(Non)maskable
0FFFCh
14
Timer1_A5 (see Note 4)
TA1CCR0 CCIFG (see Note 2)
Maskable
0FFFAh
13
Timer1_A5 (see Note 4)
TA1CCR1 to TA1CCR4
CCIFGs and TA1CTL TAIFG
(see Notes 1 and 2)
Maskable
0FFF8h
12
Comparator_A
CMPAIFG
Maskable
0FFF6h
11
Watchdog Timer
WDTIFG
Maskable
0FFF4h
10
0FFF2h
9
0FFF0h
8
Timer_A3/Timer0_A3
TACCR0/TA0CCR0 CCIFG
(see Note 2)
0FFEEh
7
Maskable
0FFECh
6
Timer_A3/Timer0_A3
TACCR1/TA0CCR1 and
TACCR2/TA0CCR2 CCIFGs,
and TACLT/TA0CTL TAIFG
(see Notes 1 and 2)
Maskable
0FFEAh
5
I/O port P1 (eight flags)
P1IFG.0 to P1IFG.7
(see Notes 1 and 2)
Maskable
0FFE8h
4
0FFE6h
3
0FFE4h
2
I/O port P2 (eight flags)
P2IFG.0 to P2IFG.7
(see Notes 1 and 2)
Maskable
0FFE2h
1
Basic Timer1
BTIFG
Maskable
0FFE0h
0, lowest
NOTES: 1.
2.
3.
4.
Multiple source flags
Interrupt flags are located in the module.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt-enable cannot.
Implemented in MSP430x415 and MSP430x417 devices only.
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special function registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
that are not allocated to a functional purpose are not physically present in the device. Simple software access
is provided with this arrangement.
interrupt enable 1 and 2
7
Address
6
0h
5
4
ACCVIE
NMIIE
rw-0
7
Address
1h
6
3
2
rw-0
5
1
0
OFIE
WDTIE
rw-0
4
3
2
rw-0
1
0
BTIE
rw-0
WDTIE:
Watchdog-timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval timer mode.
OFIE:
Oscillator-fault-interrupt enable
NMIIE:
Nonmaskable-interrupt enable
ACCVIE:
Flash access violation interrupt enable
BTIE:
Basic Timer1 interrupt enable
interrupt flag register 1 and 2
7
Address
6
5
02h
4
3
2
NMIIFG
rw-0
7
Address
3h
6
5
1
0
OFIFG
WDTIFG
rw-1
4
3
2
rw-(0)
1
0
BTIFG
rw-0
WDTIFG:
Set on watchdog-timer overflow (in watchdog mode) or security key violation. Reset with VCC power-up,
or a reset condition at the RST/NMI pin in reset mode.
OFIFG:
Flag set on oscillator fault
NMIIFG:
Set via RST/NMI pin
BTIFG:
Basic Timer1 interrupt flag
module enable registers 1 and 2
Address
7
6
5
4
3
04h/05h
Legend: rw:
rw-0:
12
Bit Can Be Read and Written
Bit Can Be Read and Written. It Is Reset by PUC.
SFR Bit Not Present in Device
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memory organization
MSP430F412
MSP430F413
MSP430F415
MSP430F417
Size
Flash
Flash
4KB
0FFFFh − 0FFE0h
0FFFFh − 0F000h
8KB
0FFFFh − 0FFE0h
0FFFFh − 0E000h
16KB
0FFFFh − 0FFE0h
0FFFFh − 0C000h
32KB
0FFFFh − 0FFE0h
0FFFFh − 08000h
Information memory
Size
Flash
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
Boot memory
Size
ROM
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
Size
256 Byte
02FFh − 0200h
256 Byte
02FFh − 0200h
512 Byte
03FFh − 0200h
1 KB
05FFh − 0200h
16-bit
8-bit
8-bit SFR
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
Memory
Interrupt vector
Code memory
RAM
Peripherals
MSP430C412
MSP430C413
Size
ROM
ROM
4KB
0FFFFh − 0FFE0h
0FFFFh − 0F000h
8KB
0FFFFh − 0FFE0h
0FFFFh − 0E000h
Information memory
Size
NA
NA
Boot memory
Size
NA
NA
Size
256 Byte
02FFh − 0200h
256 Byte
02FFh − 0200h
16-bit
8-bit
8-bit SFR
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
Memory
Interrupt vector
Code memory
RAM
Peripherals
bootstrap loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of the features of the BSL and its implementation, see the Application report Features of the MSP430
Bootstrap Loader, Literature Number SLAA089.
BSL Function
PM, RTD Package Pins
Data Transmit
53 - P1.0
Data Receive
52 - P1.1
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flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D Flash memory has n segments of main memory and two segments of information memory (A and B) of 128
bytes each. Each segment in main memory is 512 bytes in size.
D Segments 0 to n may be erased in one step, or each segment may be individually erased.
D Segments A and B can be erased individually, or as a group with segments 0−n.
Segments A and B are also called information memory.
D New devices may have some bytes programmed in the information memory (needed for test during
manufacturing). The user should perform an erase of the information memory prior to the first use.
4KB
0FFFFh
8KB
16KB
0FFFFh 0FFFFh
32KB
0FFFFh
0FE00h 0FE00h 0FE00h 0FE00h
0FDFFh 0FDFFh 0FDFFh 0FDFFh
Segment 0
With Interrupt Vectors
Segment 1
0FC00h 0FC00h 0FC00h 0FC00h
0FBFFh 0FBFFh 0FBFFh 0FBFFh
Segment 2
0FA00h
0F9FFh
0FA00h
0F9FFh
0FA00h
0F9FFh
0FA00h
0F9FFh
Main Memory
0F3FFh
0E400h 0C400h
0E3FFh 0C3FFh
083FFh
0F200h
0F1FFh
0E200h 0C200h
0E1FFh 0C1FFh
08200h
081FFh
0F000h
010FFh
0E000h
010FFh
0C000h
010FFh
08000h
010FFh
01080h
0107Fh
01080h
0107Fh
01080h
0107Fh
01080h
0107Fh
0F400h
08400h
Segment n−1
Segment n
Segment A
Information Memory
Segment B
01000h
14
01000h
01000h
01000h
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peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions. For complete module descriptions, refer to the MSP430x4xx Family User’s Guide, literature
number SLAU056.
oscillator and system clock
The clock system in the MSP430x41x family of devices is supported by the FLL+ module that includes support
for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency
crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low system cost and
low-power consumption. The FLL+ features a digital frequency locked loop (FLL) hardware which in conjunction
with a digital modulator stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency.
The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 µs. The FLL+ module
provides the following clock signals:
D
D
D
D
Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal.
Main clock (MCLK), the system clock used by the CPU.
Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8.
brownout, supply voltage supervisor
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a fixed
level or user selectable level (MSP430x415 & MSP430x417 only) and supports both supply voltage supervision
(the device is automatically reset) and supply voltage monitoring (SVM, the device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not
have ramped to VCC(min) at that time. The user must insure the default FLL+ settings are not changed until VCC
reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).
digital I/O
There are six 8-bit I/O ports implemented—ports P1 through P6:
D
D
D
D
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
Read/write access to port-control registers is supported by all instructions.
Basic Timer1
The Basic Timer1 has two independent 8-bit timers which can be cascaded to form a 16-bit timer/counter. Both
timers can be read and written by software. The Basic Timer1 can be used to generate periodic interrupts and
clock for the LCD module.
LCD drive
The LCD driver generates the segment and common signals required to drive an LCD display. The LCD
controller has dedicated data memory to hold segment drive information. Common and segment signals are
generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral.
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watchdog timer
The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
comparator_A
The primary function of the comparator_A module is to support precision slope analog−to−digital conversions,
battery−voltage supervision, and monitoring of external analog signals.
timer_A3/timer0_A3
Timer_A3/Timer0_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3/Timer0_A3 can
support multiple capture/compares, PWM outputs, and interval timing. Timer_A3/Timer0_A3 also has extensive
interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of
the capture/compare registers.
Timer_A3/Timer0_A3 Signal Connections
Input Pin Number
Device Input Signal
Module Input Name
48 - P1.5
TACLK/TA0CLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
48 - P1.5
TACLK/TA0CLK
INCLK
53 - P1.0
TA0/TA0.0
CCI0A
52 - P1.1
TA0/TA0.0
CCI0B
DVSS
DVCC
GND
51 - P1.2
45 - P2.0
16
TA1/TA0.1
VCC
CCI1A
CAOUT (internal)
CCI1B
DVSS
DVCC
GND
TA2/TA0.2
VCC
CCI2A
ACLK (internal)
CCI2B
DVSS
DVCC
GND
Module Block
Module Output Signal
Timer
NA
53 - P1.0
CCR0
TA0/TA0.0
51 - P1.2
CCR1
TA1/TA0.1
45 - P2.0
CCR2
VCC
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timer1_A5 (MSP430x415 and MSP430x417 only)
Timer1_A5 is a 16-bit timer/counter with five capture/compare registers. Timer1_A5 can support multiple
capture/compares, PWM outputs, and interval timing. Timer1_A5 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer1_A5 Signal Connections
Input Pin Number
Device Input Signal
Module Input Name
32 - P2.5
TA1CLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
32 - P2.5
TA1CLK
INCLK
49 - P1.4
TA1.0
CCI0A
50 - P1.3
TA1.0
CCI0B
DVSS
DVCC
GND
44 - P2.1
35 - P2.2
34 - P2.3
33 - P2.4
TA1.1
VCC
CCI1A
CAOUT (internal)
CCI1B
DVSS
DVCC
GND
TA1.2
VCC
CCI2A
Not Connected
CCI2B
DVSS
DVCC
GND
TA1.3
VCC
CCI3A
Not Connected
CCI3B
DVSS
DVCC
GND
TA1.4
VCC
CCI4A
Not Connected
CCI4B
DVSS
DVCC
GND
Module Block
Module Output Signal
Timer
NA
Output Pin Number
49 - P1.4
CCR0
TA1.0
44 - P2.1
CCR1
TA1.1
35 - P2.2
CCR2
TA1.2
34 - P2.3
CCR3
TA1.3
33 - P2.4
CCR4
TA1.4
VCC
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peripheral file map
PERIPHERALS WITH WORD ACCESS
Watchdog
Watchdog Timer control
WDTCTL
0120h
Timer1_A5
(MSP430x415 and
MSP430x417 only)
Timer1_A interrupt vector
TA1IV
011Eh
Timer1_A control
TA1CTL
0180h
Capture/compare control 0
TA1CCTL0
0182h
Capture/compare control 1
TA1CCTL1
0184h
Capture/compare control 2
TA1CCTL2
0186h
Capture/compare control 3
TA1CCTL3
0188h
Capture/compare control 4
TA1CCTL4
018Ah
Reserved
018Ch
Reserved
018Eh
Timer1_A register
TA1R
0190h
Capture/compare register 0
TA1CCR0
0192h
Capture/compare register 1
TA1CCR1
0194h
Capture/compare register 2
TA1CCR2
0196h
Capture/compare register 3
TA1CCR3
0198h
Capture/compare register 4
TA1CCR4
019Ah
Reserved
019Ch
Reserved
Timer_A3/Timer0_A3
019Eh
Timer_A/Timer0_A interrupt vector
TAIV/TA0IV
012Eh
Timer_A/Timer0_A control
TACTL/TA0CTL
0160h
Capture/compare control 0
TACCTL0/TA0CCTL0
0162h
Capture/compare control 1
TACCTL1/TA0CCTL1
0164h
Capture/compare control 2
TACCTL2/TA0CCTL2
0166h
Reserved
0168h
Reserved
016Ah
Reserved
016Ch
Reserved
016Eh
Timer_A/Timer0_A register
TAR/TA0R
0170h
Capture/compare register 0
TACCR0/TA0CCR0
0172h
Capture/compare register 1
TACCR1/TA0CCR1
0174h
Capture/compare register 2
TACCR2/TA0CCR2
0176h
Reserved
0178h
Reserved
017Ah
Reserved
017Ch
Reserved
Flash
18
017Eh
Flash control 3
FCTL3
012Ch
Flash control 2
FCTL2
012Ah
Flash control 1
FCTL1
0128h
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peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS
LCD
Comparator_A
LCD memory 20
LCDM20
0A4h
:
:
:
LCD memory 16
LCDM16
0A0h
LCD memory 15
LCDM15
09Fh
:
:
:
LCD memory 1
LCDM1
091h
LCD control and mode
LCDCTL
090h
Comparator_A port disable
CAPD
05Bh
Comparator_A control2
CACTL2
05Ah
Comparator_A control1
CACTL1
059h
Brownout, SVS
SVS control register
SVSCTL
056h
FLL+ Clock
FLL+ Control1
FLL_CTL1
054h
FLL+ Control0
FLL_CTL0
053h
System clock frequency control
SCFQCTL
052h
System clock frequency integrator
SCFI1
051h
System clock frequency integrator
SCFI0
050h
BT counter2
BTCNT2
047h
BT counter1
BTCNT1
046h
BT control
BTCTL
040h
Port P6 selection
P6SEL
037h
Port P6 direction
P6DIR
036h
Port P6 output
P6OUT
035h
Port P6 input
P6IN
034h
Port P5 selection
P5SEL
033h
Port P5 direction
P5DIR
032h
Port P5 output
P5OUT
031h
Port P5 input
P5IN
030h
Port P4 selection
P4SEL
01Fh
Port P4 direction
P4DIR
01Eh
Port P4 output
P4OUT
01Dh
Port P4 input
P4IN
01Ch
Port P3 selection
P3SEL
01Bh
Port P3 direction
P3DIR
01Ah
Port P3 output
P3OUT
019h
Port P3 input
P3IN
018h
Port P2 selection
P2SEL
02Eh
Port P2 interrupt enable
P2IE
02Dh
Port P2 interrupt-edge select
P2IES
02Ch
Port P2 interrupt flag
P2IFG
02Bh
Port P2 direction
P2DIR
02Ah
Port P2 output
P2OUT
029h
Port P2 input
P2IN
028h
Basic Timer1
Port P6
Port P5
Port P4
Port P3
Port P2
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peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS (CONTINUED)
Port P1
Special Functions
Port P1 selection
P1SEL
026h
Port P1 interrupt enable
P1IE
025h
Port P1 interrupt-edge select
P1IES
024h
Port P1 interrupt flag
P1IFG
023h
Port P1 direction
P1DIR
022h
Port P1 output
P1OUT
021h
Port P1 input
P1IN
020h
SFR module enable 2
ME2
005h
SFR module enable 1
ME1
004h
SFR interrupt flag2
IFG2
003h
SFR interrupt flag1
IFG1
002h
SFR interrupt enable2
IE2
001h
SFR interrupt enable1
IE1
000h
absolute maximum ratings†
Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to + 4.1 V
Voltage applied to any pin (see Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VCC + 0.3 V
Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA
Storage temperature (unprogrammed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
Storage temperature (programmed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE: All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied
to the TDI/TCLK pin when blowing the JTAG fuse.
20
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS340G − MAY 2001 − REVISED JUNE 2004
recommended operating conditions
PARAMETER
MIN
NOM
MAX
UNITS
Supply voltage during program execution, SVS disabled
VCC (AVCC = DVCC = VCC)
MSP430x41x
1.8
3.6
V
Supply voltage during program execution, SVS enabled (see Note 1),
VCC (AVCC = DVCC = VCC)
MSP430x41x
2.2
3.6
V
Supply voltage during programming of flash memory,
VCC (AVCC = DVCC = VCC)
MSP430F41x
2.7
3.6
V
0
0
V
MSP430x41x
−40
85
°C
Supply voltage, VSS (AVSS/1/2 = DVSS = VSS)
Operating free-air temperature range, TA
LFXT1 crystal frequency, f(LFXT1)
(see Note 2)
LF selected, XTS_FLL=0
Watch crystal
32768
XT1 selected, XTS_FLL=1
Ceramic resonator
XT1 selected, XTS_FLL=1
Crystal
VCC = 1.8 V
VCC = 3.6 V
Processor frequency (signal MCLK), f(System)
Hz
450
8000
kHz
1000
8000
kHz
DC
4.15
DC
8
MHz
f(System) − Maximum Processor Frequency − MHz
NOTES: 1. The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing supply voltage.
POR is going inactive when the supply voltage is raised above minimum supply voltage plus the hysteresis of the SVS circuitry.
2. The LFXT1 oscillator in LF-mode requires a watch crystal.
f (MHz)
Supply Voltage Range
During Programming of
the Flash Memory
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
8 MHz
Supply Voltage Range, x41x
During Program Execution
4.15 MHz
2.7 V
1.8 V
3V
3.6 V
VCC − Supply Voltage − V
Figure 1. Frequency vs Supply Voltage
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
21
SLAS340G − MAY 2001 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
supply current into AVCC + DVCC excluding external current, (see Note 1)
PARAMETER
TEST CONDITIONS
Active mode,
f(MCLK) = f(SMCLK) = 1 MHz,
f(ACLK) = 32,768 Hz, XTS_FLL = 0
(F41x: Program executes in flash)
I(AM)
I(LPM0)
I(LPM0)
I(LPM2)
NOM
MAX
VCC = 2.2 V
160
200
VCC = 3 V
240
300
VCC = 2.2 V
200
250
VCC = 3 V
300
350
VCC = 2.2 V
32
45
VCC = 3 V
55
70
VCC = 2.2 V
57
70
VCC = 3 V
92
100
VCC = 2.2 V
11
14
VCC = 3 V
17
22
0.95
1.4
0.8
1.3
0.7
1.2
TA = 60°C
0.95
1.4
TA = 85°C
1.6
2.3
TA = −40°C
1.1
1.7
TA = −10°C
1.0
1.6
C41x
° to 85°C
°
TA = −40°C
F41x
Low-power mode, (LPM0)
f(MCLK) = f(SMCLK) = 0.5 MHz,
f(ACLK) = 32,768 Hz, XTS_FLL = 0
FN_8=FN_4=FN_3=FN_2=0
° to 85°C
°
TA = −40°C
C41x
F41x
Low-power mode, (LPM0)
f(MCLK) = f(SMCLK) = 1 MHz,
f(ACLK) = 32,768 Hz, XTS_FLL = 0
FN_8=FN_4=FN_3=FN_2=0
° to 85°C
°
TA = −40°C
° to 85°C
°
TA = −40°C
Low-power mode, (LPM2)
Low-power mode, (LPM3) (see Note 2)
TA = 25°C
VCC = 2.2 V
0.9
1.5
TA = 60°C
1.1
1.7
TA = 85°C
2.0
2.6
0.1
0.5
0.1
0.5
0.8
2.5
VCC = 3 V
TA = −40°C
I(LPM4)
TA = 25°C
Low-power mode, (LPM4)
µA
µA
TA = −10°C
TA = 25°C
UNIT
µA
TA = −40°C
I(LPM3)
MIN
VCC = 2.2 V/3 V
TA = 85°C
µA
µA
µA
NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current. The current consumption is measured with active Basic
Timer1 and LCD (ACLK selected).
The current consumption of the Comparator_A and the SVS module are specified in the respective sections.
2. The LPM3 currents are characterized with a KDS Daishinku DT−38 (6 pF) crystal.
current consumption of active mode versus system frequency, F version
I(AM) = I(AM) [1 MHz] × f(System) [MHz]
current consumption of active mode versus supply voltage, F version
I(AM) = I(AM) [3 V] + 140 µA/V × (VCC – 3 V)
22
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS340G − MAY 2001 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Schmitt-trigger inputs − Ports P1, P2, P3, P4, P5, and P6
PARAMETER
VIT+
Positive-going input threshold voltage
VIT−
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ − VIT−)
VCC
2.2 V
MIN
TYP
MAX
1.1
1.5
3V
1.5
1.9
2.2 V
0.4
0.9
3V
0.9
1.3
2.2 V
0.3
1.1
3V
0.45
1
VCC
MIN
UNIT
V
V
V
standard inputs − RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI
PARAMETER
VIL
VIH
Low-level input voltage
2.2 V/3 V
High-level input voltage
TYP
VSS
0.8×VCC
MAX
VSS+0.6
VCC
UNIT
V
V
inputs Px.x, TAx/TAx.x
PARAMETER
t(int)
TEST CONDITIONS
Port P1, P2: P1.x to P2.x, External
trigger signal for the interrupt flag,
(see Note 1)
External interrupt timing
t(cap)
Timer_A, capture timing
TAx/TAx.y
f(TAext)
Timer_A clock frequency externally
applied to pin
TACLK/TAxCLK, INCLK t(H) = t(L)
f(TAint)
Timer_A clock frequency
SMCLK or ACLK signal selected
VCC
2.2 V/3 V
MIN
TYP
MAX
1.5
2.2 V
62
3V
50
2.2 V
62
3V
50
UNIT
cycle
ns
ns
2.2 V
8
3V
10
2.2 V
8
3V
10
MHz
MHz
NOTES: 1. The external signal sets the interrupt flag every time the minimum t(int) cycle and time parameters are met. It may be set even with
trigger signals shorter than t(int). Both the cycle and timing specifications must be met to ensure the flag is set. t(int) is measured in
MCLK cycles.
leakage current (see Note 1)
PARAMETER
Ilkg(P1.x)
Ilkg(P6.x)
Leakage current
TEST CONDITIONS
Port P1
Port P6
V(P1.x) (see Note 2)
V(P6.x) (see Note 2)
VCC
MIN
NOM
2.2 V/3 V
MAX
±50
±50
UNIT
nA
NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
2. The port pin must be selected as an input.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
23
SLAS340G − MAY 2001 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs − Ports P1, P2, P3, P4, P5, and P6
PARAMETER
VOH
VOL
High-level output voltage
Low-level output voltage
TEST CONDITIONS
MIN
IOH(max) = −1.5 mA,
IOH(max) = −6 mA,
VCC = 2.2 V,
VCC = 2.2 V,
See Note 1
IOH(max) = −1.5 mA,
IOH(max) = −6 mA,
VCC = 3 V,
VCC = 3 V,
See Note 1
IOL(max) = 1.5 mA,
IOL(max) = 6 mA,
VCC = 2.2 V,
VCC = 2.2 V,
See Note 1
IOL(max) = 1.5 mA,
IOL(max) = 6 mA,
VCC = 3 V,
VCC = 3 V,
See Note 1
See Note 2
See Note 2
TYP
MAX
VCC−0.25
VCC−0.6
VCC
VCC
VCC−0.25
VCC−0.6
VCC
VCC
VSS
VSS
VSS+0.25
VSS+0.6
VSS
VSS
VSS+0.25
VSS+0.6
See Note 2
See Note 2
UNIT
V
V
NOTES: 1. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±12 mA to satisfy the maximum
specified voltage drop.
2. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±24 mA to satisfy the maximum
specified voltage drop.
output frequency
PARAMETER
TEST CONDITIONS
fPx.y
(1 ≤ x ≤ 6, 0 ≤ y ≤ 7)
CL = 20 pF,
IL = ± 1.5mA
fACLK,
fMCLK,
fSMCLK
P1.1/TA0/MCLK, P1.5/TACLK/ACLK
CL = 20 pF
VCC = 2.2 V
VCC = 3 V
DC
12
UNIT
MHz
8
MHz
Duty cycle of output frequency
POST OFFICE BOX 655303
MAX
10
VCC = 3 V
P1.1/TA0/MCLK,
CL = 20 pF,
VCC = 2.2 V / 3 V
24
TYP
DC
VCC = 2.2 V
P1.5/TACLK/ACLK,
CL = 20 pF
VCC = 2.2 V / 3 V
tXdc
MIN
fACLK = fLFXT1 = fXT1
fACLK = fLFXT1 = fLF
12
40%
60%
30%
70%
fACLK = fLFXT1/n
50%
fMCLK = fLFXT1/n
50%−
15 ns
50%
50%+
15 ns
fMCLK = fDCOCLK
50%−
15 ns
50%
50%+
15 ns
• DALLAS, TEXAS 75265
SLAS340G − MAY 2001 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
MSP430x412, MSP430x413 outputs − Ports P1, P2, P3, P4, P5, and P6 (see Note)
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
25
TA = 25°C
VCC = 2.2 V
P1.0
14
12
IOL − Typical Low-Level Output Current − mA
IOL − Typical Low-Level Output Current − mA
16
TA = 85°C
10
8
6
4
2
0
0.0
0.5
1.0
1.5
2.0
VCC = 3 V
P1.0
20
TA = 85°C
15
10
5
0
0.0
2.5
TA = 25°C
0.5
VOL − Low-Level Output Voltage − V
1.0
Figure 2
3.0
3.5
0
VCC = 2.2 V
P1.0
IOH − Typical High-Level Output Current − mA
IOH − Typical High-Level Output Current − mA
2.5
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0
−4
−6
−8
−10
TA = 85°C
−12
TA = 25°C
−14
0.0
2.0
Figure 3
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
−2
1.5
VOL − Low-Level Output Voltage − V
0.5
1.0
1.5
2.0
2.5
VOH − High-Level Output Voltage − V
VCC = 3 V
P1.0
−5
−10
−15
−20
TA = 85°C
−25
−30
0.0
TA = 25°C
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOH − High-Level Output Voltage − V
Figure 4
Figure 5
NOTE A: One output loaded at a time
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
25
SLAS340G − MAY 2001 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
MSP430x415, MSP430x417 outputs − Ports P1, P2, P3, P4, P5, and P6 (see Note)
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
40
20
TA = 85°C
15
10
5
0
0.0
d
TA = 25°C
VCC = 2.2 V
P2.4
IOL − Typical Low-Level Output Current − mA
IOL − Typical Low-Level Output Current − mA
25
0.5
1.0
1.5
2.0
VCC = 3 V
P2.4
35
TA = 85°C
30
25
20
15
10
5
0
0.0
2.5
TA = 25°C
0.5
VOL − Low-Level Output Voltage − V
1.0
Figure 6
IOH − Typical High-Level Output Current − mA
IOH − Typical High-Level Output Current − mA
3.0
3.5
0
VCC = 2.2 V
P2.4
−5
−10
−15
TA = 85°C
TA = 25°C
0.5
1.0
1.5
2.0
2.5
−5
VCC = 3 V
P2.4
−10
−15
−20
−25
−30
−35
TA = 85°C
−40
−45
TA = 25°C
−50
0.0
VOH − High-Level Output Voltage − V
0.5
1.0
1.5
2.0
Figure 9
NOTE B: One output loaded at a time
POST OFFICE BOX 655303
2.5
3.0
VOH − High-Level Output Voltage − V
Figure 8
26
2.5
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0
−25
0.0
2.0
Figure 7
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
−20
1.5
VOL − Low-Level Output Voltage − V
• DALLAS, TEXAS 75265
3.5
SLAS340G − MAY 2001 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
wake-up LPM3
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
f = 1 MHz
td(LPM3)
f = 2 MHz
Delay time
UNIT
6
6
VCC = 2.2 V/3 V
f = 3 MHz
µs
6
RAM (see Note 1)
PARAMETER
TEST CONDITIONS
VRAMh
MIN
CPU halted (see Note 1)
TYP
MAX
1.6
UNIT
V
NOTE 1: This parameter defines the minimum supply voltage when the data in the program memory RAM remain unchanged. No program
execution should take place during this supply voltage condition.
LCD
PARAMETER
V(33)
V(23)
V(13)
V(33) − V(03)
Voltage at P5.5/R13
R03 = VSS
Input leakage
P5.5/R13 = VCC/3
P5.6/R23 = 2 × VCC/3
Segment line
voltage
I(Sxx) = −3 µA,
A,
V(Sxx3)
POST OFFICE BOX 655303
MAX
VCC +0.2
2.5
(V33−V03) × 2/3 + V03
(V(33)−V(03)) × 1/3 + V(03)
VCC +0.2
UNIT
V
±20
No load at all
segment and
common lines,
VCC = 3 V
VCC = 3 V
TYP
2.5
VCC = 3 V
Voltage at R33/R03
I(R23)
V(Sxx0)
V(Sxx1)
V(Sxx2)
MIN
Voltage at P5.6/R23
Analog voltage
I(R03)
I(R13)
TEST CONDITIONS
Voltage at P5.7/R33
±20
nA
±20
V(03)
V(13)
V(03) − 0.1
V(13) − 0.1
V(23)
V(33)
V(23) − 0.1
V(33) + 0.1
• DALLAS, TEXAS 75265
V
27
SLAS340G − MAY 2001 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Comparator_A (see Note 1)
PARAMETER
TEST CONDITIONS
I(CC)
CAON = 1, CARSEL = 0, CAREF = 0
I(Refladder/RefDiode)
CAON = 1, CARSEL = 0,
CAREF = 1/2/3,
No load at P1.6/CA0 and P1.7/CA1
MIN
TYP
MAX
VCC = 2.2 V
VCC = 3 V
25
40
45
60
VCC = 2.2 V
30
50
VCC = 3 V
45
71
UNIT
µA
A
µA
A
V(Ref025)
Voltage @ 0.25 V CC node PCA0 = 1, CARSEL = 1, CAREF = 1,
No load at P1.6/CA0 and P1.7/CA1
V CC
VCC = 2.2 V / 3 V
0.23
0.24
0.25
V(Ref050)
Voltage @ 0.5 V CC node
PCA0 = 1, CARSEL = 1, CAREF = 2,
No load at P1.6/CA0 and P1.7/CA1
VCC = 2.2V / 3 V
0.47
0.48
0.50
(see Figure 10 and
Figure 11)
PCA0 = 1, CARSEL = 1, CAREF = 3,
No load at P1.6/CA0 and P1.7/CA1;
TA = 85°C
VCC = 2.2 V
390
480
540
V(RefVT)
VCC = 3.0 V
400
490
550
V(IC)
Common-mode input
voltage range
CAON = 1
VCC = 2. 2V/3 V
0
VCC−1.0
Offset voltage
See Note 2
VCC = 2.2 V/3 V
−30
30
mV
Input hysteresis
CAON = 1
VCC = 2.2 V / 3 V
VCC = 2.2 V
0
0.7
1.4
mV
160
210
300
80
150
240
1.4
1.9
3.4
0.9
1.5
2.6
130
210
300
80
150
240
1.4
1.9
3.4
V(offset)
Vhys
V CC
TA = 25
25°C,
C,
Overdrive 10 mV, without filter: CAF = 0
t(response LH)
TA = 25
25°C
C
Overdrive 10 mV, with filter: CAF = 1
TA = 25
25°C
C
Overdrive 10 mV, without filter: CAF = 0
t(response HL)
TA = 25
25°C,
C,
Overdrive 10 mV, with filter: CAF = 1
mV
VCC = 3 V
VCC = 2.2 V
VCC = 3 V
VCC = 2.2 V
VCC = 3 V
VCC = 2.2 V
V
ns
µss
ns
µss
VCC = 3.0 V
0.9
1.5
2.6
NOTES: 1. The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification.
2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements.
The two successive measurements are then summed together.
28
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS340G − MAY 2001 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE
REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE
650
650
VCC = 2.2 V
V(RefVT) − Reference Voltage − mV
V(RefVT) − Reference Voltage − mV
VCC = 3 V
600
Typical
550
500
450
400
−45
−25
−5
15
35
55
75
600
Typical
550
500
450
400
−45
95
−25
−5
35
55
75
95
Figure 11
Figure 10
0 V VCC
0
15
TA − Free-Air Temperature − °C
TA − Free-Air Temperature − °C
CAF
1
CAON
Low Pass Filter
V+
V−
+
_
0
0
1
1
To Internal
Modules
CAOUT
Set CAIFG
Flag
τ ≈ 2 µs
Figure 12. Block Diagram of Comparator_A Module
VCAOUT
Overdrive
V−
400 mV
V+
t(response)
Figure 13. Overdrive Definition
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
29
SLAS340G − MAY 2001 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
POR brownout, reset (see Notes 1 and 2)
PARAMETER
TEST CONDITIONS
td(BOR)
VCC(start)
V(B_IT−)
Vhys(B_IT−)
MIN
dVCC/dt ≤ 3 V/s (see Figure 14)
Brownout
TYP
MAX
UNIT
2000
µs
0.7 × V(B_IT−)
dVCC/dt ≤ 3 V/s (see Figure 14, Figure 15, Figure 16)
dVCC/dt ≤ 3 V/s (see Figure 14)
70
130
V
1.71
V
180
mV
Pulse length needed at RST/NMI pin to accepted reset internally,
2
µs
VCC = 2.2 V/3 V
NOTES: 1. The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT−)
+ Vhys(B_IT−) is ≤ 1.8 V.
2. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT−) + Vhys(B_IT−). The default
FLL+ settings must not be changed until VCC ≥ VCC(min). See the MSP430x4xx Family User’s Guide (SLAU056) for more information
on the brownout/SVS circuit.
t(reset)
VCC
Vhys(B_IT−)
V(B_IT−)
VCC(start)
1
0
td(BOR)
Figure 14. POR/Brownout Reset (BOR) vs Supply Voltage
30
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS340G − MAY 2001 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
VCC
2
VCC (min) − V
tpw
3V
V cc = 3 V
Typical Conditions
1.5
1
VCC(min)
0.5
0
0.001
1
1000
1 ns
tpw − Pulse Width − µs
1 ns
tpw − Pulse Width − µs
Figure 15. VCC(min) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
VCC
VCC (min) − V
2
1.5
tpw
3V
V cc = 3 V
Typical Conditions
1
VCC(min)
0.5
tf = tr
0
0.001
1
1000
tf
tr
tpw − Pulse Width − µs
tpw − Pulse Width − µs
Figure 16. VCC(min) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
SVS (supply voltage supervisor/monitor, see Notes 1 and 2) MSP430x412, MSP430x413 only
PARAMETER
TEST CONDITIONS
td(SVSR)
td(SVSon)
V(SVSstart)
V(SVS_IT−)
Vhys(SVS_IT−)
ICC(SVS)
(see Note 1)
MIN
dVCC/dt > 30V/ms (see Note 2)
dVCC/dt ≤ 30V/ms (see Note 2)
SVSon, switch from 0 to 1, VCC = 3 V (see Note 2)
SVS
TYP
5
20
MAX
UNIT
150
µs
2000
µs
150
µs
1.7
V
dVCC/dt ≤ 3 V/s (see Figure 17)
dVCC/dt ≤ 3 V/s (see Figure 17)
1.8
1.95
2.2
V
dVCC/dt ≤ 3 V/s (see Figure 17)
70
100
155
mV
10
15
µA
1.55
VLD ≠ 0 (VLD bits are in SVSCTL register), VCC = 2.2V/ 3V
NOTES: 1. The current consumption of the SVS module is not included in the ICC current consumption data.
2. The SVS is not active at power up.
POST OFFICE BOX 655303
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31
SLAS340G − MAY 2001 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SVS (supply voltage supervisor/monitor, see Notes 1 and 2) MSP430x415, MSP430x417 only
PARAMETER
TEST CONDITIONS
MIN
td(SVSR)
dVCC/dt > 30 V/ms (see Figure 17)
dVCC/dt ≤ 30 V/ms
5
td(SVSon)
tsettle
SVSon, switch from VLD=0 to VLD ≠ 0, VCC = 3 V
VLD ≠ 0‡
20
V(SVSstart)
VLD ≠ 0, VCC/dt ≤ 3 V/s (see Figure 17)
NOM
1.55
VLD = 1
VCC/dt ≤ 3 V/s (see Figure 17)
VLD = 2 .. 14
Vhys(SVS_IT−)
VCC/dt ≤ 3 V/s (see Figure 17), external voltage applied
on SVSIN
VCC/dt ≤ 3 V/s (see Figure 17)
V(SVS_IT−)
VCC/dt ≤ 3 V/s (see Figure 17), external voltage applied
on SVSIN
VLD = 15
70
120
V(SVS_IT−)
x 0.004
MAX
UNIT
150
µs
2000
µs
150
µs
12
µs
1.7
V
155
mV
V(SVS_IT−)
x 0.008
4.4
10.4
VLD = 1
1.8
1.9
2.05
VLD = 2
1.94
2.1
2.25
VLD = 3
2.05
2.2
2.37
VLD = 4
2.14
2.3
2.48
VLD = 5
2.24
2.4
2.6
VLD = 6
2.33
2.5
2.71
VLD = 7
2.46
2.65
2.86
VLD = 8
2.58
2.8
3
VLD = 9
2.69
2.9
3.13
VLD = 10
2.83
3.05
3.29
VLD = 11
2.94
3.2
VLD = 12
3.11
3.35
VLD = 13
3.24
VLD = 14
3.43
3.5
3.7†
3.42
3.61†
3.76†
VLD = 15
1.1
1.2
mV
V
3.99†
1.3
ICC(SVS)
VLD ≠ 0, VCC = 2.2 V/3 V
10
15
µA
(see Note 1)
† The recommended operating voltage range is limited to 3.6 V.
‡ tsettle is the settling time that the comparator o/p needs to have a stable level after VLD is switched VLD ≠ 0 to a different VLD value somewhere
between 2 and 15. The overdrive is assumed to be > 50 mV.
NOTES: 1. The current consumption of the SVS module is not included in the ICC current consumption data.
2. The SVS is not active at power up.
32
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS340G − MAY 2001 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Software Sets VLD>0:SVS is Active
VCC
V
(SVS_IT−)
V(SVSstart)
Vhys(SVS_IT−)
Vhys(B_IT−)
V(B_IT−)
VCC(start)
Brownout
Brownout
Region
Brownout
Region
1
0
td(BOR)
SVS out
td(BOR)
SVS Circuit is Active From VLD > to VCC < V(B_IT−)
1
0
td(SVSon)
Set POR
1
td(SVSR)
Undefined
0
Figure 17. SVS Reset (SVSR) vs Supply Voltage
VCC
3V
tpw
2
Rectangular Drop
VCC(min)
VCC(min) − V
1.5
Triangular Drop
1
1 ns
1 ns
VCC
3V
0.5
tpw
0
1
10
100
1000
tpw − Pulse Width − µs
VCC(min)
tf = tr
tf
tr
t − Pulse Width − µs
Figure 18. VCC(min) With a Square Voltage Drop and a Triangle Voltage Drop to Generate an SVS Signal
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
33
SLAS340G − MAY 2001 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
DCO
PARAMETER
f(DCOCLK)
TEST CONDITIONS
VCC
2.2 V/3 V
MIN
TYP
2.2 V
0.3
0.65
1.25
3V
0.3
0.7
1.3
2.2 V
2.5
5.6
10.5
3V
2.7
6.1
11.3
2.2 V
0.7
1.3
2.3
3V
0.8
1.5
2.5
2.2 V
5.7
10.8
18
3V
6.5
12.1
20
2.2 V
1.2
2
3
3V
1.3
2.2
3.5
2.2 V
9
15.5
25
3V
10.3
17.9
28.5
2.2 V
1.8
2.8
4.2
3V
2.1
3.4
5.2
2.2 V
13.5
21.5
33
3V
16
26.6
41
2.2 V
2.8
4.2
6.2
3V
4.2
6.3
9.2
2.2 V
21
32
46
3V
30
46
70
1 < TAP ≤ 20
1.06
TAP = 27
1.07
2.2 V
–0.2
–0.3
–0.4
3V
–0.2
–0.3
–0.4
0
5
15
N(DCO)=01E0h, FN_8=FN_4=FN_3=FN_2=0, D = 2; DCOPLUS= 0
f(DCO2)
FN_8=FN_4=FN_3=FN_2=0 ; DCOPLUS = 1
f(DCO27)
FN_8=FN_4=FN_3=FN_2=0; DCOPLUS = 1, (see Note 1)
f(DCO2)
FN_8=FN_4=FN_3=0, FN_2=1; DCOPLUS = 1
f(DCO27)
FN_8=FN_4=FN_3=0, FN_2=1; DCOPLUS = 1, (see Note 1)
f(DCO2)
FN_8=FN_4=0, FN_3= 1, FN_2=x; DCOPLUS = 1
f(DCO27)
FN_8=FN_4=0, FN_3= 1, FN_2=x; DCOPLUS = 1, (see Note 1)
f(DCO2)
FN_8=0, FN_4= 1, FN_3= FN_2=x; DCOPLUS = 1
f(DCO27)
FN_8=0, FN_4=1, FN_3= FN_2=x; DCOPLUS = 1, (see Note 1)
f(DCO2)
FN_8=1, FN_4=FN_3=FN_2=x; DCOPLUS = 1
f(DCO27)
FN_8=1,FN_4=FN_3=FN_2=x; DCOPLUS = 1, (see Note 1)
Sn
Step size between adjacent DCO taps:
Sn = fDCO(Tap n+1) / fDCO(Tap n), (see Figure 20 for taps 21 to 27)
Dt
Temperature drift, N(DCO) = 01E0h, FN_8=FN_4=FN_3=FN_2=0
D = 2; DCOPLUS = 0, (see Note 2)
DV
Drift with VCC variation, N(DCO) = 01E0h, FN_8=FN_4=FN_3=FN_2=0
D = 2; DCOPLUS = 0 (see Note 2)
MAX
1
UNIT
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
1.11
1.17
%/_C
%/V
NOTES: 1. Do not exceed the maximum system frequency.
2. This parameter is not production tested.
f
f
f
(DCO)
f
(DCO3V)
(DCO)
(DCO205C)
1.0
1.0
0
1.8
2.4
3.0
3.6
VCC − V
−40
−20
0
20
40
60
Figure 19. DCO Frequency vs Supply Voltage VCC and vs Ambient Temperature
34
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
85
TA − °C
SLAS340G − MAY 2001 − REVISED JUNE 2004
Sn - Stepsize Ratio between DCO Taps
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
1.17
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
Max
1.11
1.07
1.06
Min
1
20
27
DCO Tap
Figure 20. DCO Tap Step Size
f(DCO)
Legend
Tolerance at Tap 27
DCO Frequency
Adjusted by Bits
29 to 25 in SCFI1 {N{DCO}}
Tolerance at Tap 2
Overlapping DCO Ranges:
Uninterrupted Frequency Range
FN_2=0
FN_3=0
FN_4=0
FN_8=0
FN_2=1
FN_3=0
FN_4=0
FN_8=0
FN_2=x
FN_3=1
FN_4=0
FN_8=0
FN_2=x
FN_3=x
FN_4=1
FN_8=0
FN_2=x
FN_3=x
FN_4=x
FN_8=1
Figure 21. Five Overlapping DCO Ranges Controlled by FN_x Bits
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
35
SLAS340G − MAY 2001 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
crystal oscillator, LFXT1 oscillator (see Notes 1 and 2)
PARAMETER
CXIN
CXOUT
VIL
VIH
Integrated load capacitance
Integrated load capacitance
Input levels at XIN
TEST CONDITIONS
OSCCAPx = 0h
VCC
2.2 V/3 V
OSCCAPx = 1h
2.2 V/3 V
10
OSCCAPx = 2h
2.2 V/3 V
14
OSCCAPx = 3h
2.2 V/3 V
18
OSCCAPx = 0h
2.2 V/3 V
0
OSCCAPx = 1h
2.2 V/3 V
10
OSCCAPx = 2h
2.2 V/3 V
14
OSCCAPx = 3h
2.2 V/3 V
see Note 3
2.2 V/3 V
MIN
TYP
MAX
UNIT
0
pF
pF
18
VSS
0.8×VCC
0.2×VCC
VCC
V
NOTES: 1. The parasitic capacitance from the package and board may be estimated to be 2pF. The effective load capacitor for the crystal is
(CXIN x CXOUT) / (CXIN + CXOUT). It is independent of XTS_FLL.
2. To improve EMI on the low-power LFXT1 oscillator, particularly in the LF mode (32 kHz), the following guidelines must be
observed:
• Keep as short a trace as possible between the ’x41x and the crystal.
• Design a good ground plane around oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
• Avoid running PCB traces underneath or adjacent to XIN an XOUT pins.
• Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
• If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
• Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation.
This signal is no longer required for the serial programming adapter.
3. Applies only when using an external logic-level clock source. XTS_FLL must be set. Not applicable when using a crystal or resonator.
36
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS340G − MAY 2001 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Flash Memory
TEST
CONDITIONS
PARAMETER
VCC(PGM/
ERASE)
VCC
MIN
NOM
MAX
UNIT
Program and Erase supply voltage
2.7
3.6
V
fFTG
IPGM
Flash Timing Generator frequency
257
476
kHz
Supply current from DVCC during program
2.7 V/ 3.6 V
3
5
mA
IERASE
tCPT
Supply current from DVCC during erase
2.7 V/ 3.6 V
3
7
mA
Cumulative program time
see Note 1
2.7 V/ 3.6 V
4
ms
tCMErase
Cumulative mass erase time
see Note 2
2.7 V/ 3.6 V
Program/Erase endurance
TJ = 25°C
200
104
ms
105
tRetention
Data retention duration
tWord
tBlock, 0
Word or byte program time
Block program time for 1st byte or word
tBlock, 1-63
tBlock, End
Block program time for each additional byte or word
tMass Erase
tSeg Erase
Mass erase time
5297
Segment erase time
4819
Block program end-sequence wait time
cycles
100
years
35
30
21
see Note 3
tFTG
6
NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
2. The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/fFTG,max = 5297x1/476kHz). To
achieve the required cumulative mass erase time the Flash Controller’s mass erase operation can be repeated until this time is met.
(A worst case minimum of 19 cycles are required).
3. These values are hardwired into the Flash Controller’s state machine (tFTG = 1/fFTG).
JTAG Interface
TEST
CONDITIONS
PARAMETER
fTCK
TCK input frequency
see Note 1
RInternal
Internal pull-up resistance on TMS, TCK, TDI/TCLK
see Note 2
VCC
MIN
2.2 V
0
NOM
MAX
UNIT
5
MHz
3V
0
10
MHz
2.2 V/ 3 V
25
60
90
kΩ
MIN
NOM
MAX
NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected.
2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions.
JTAG Fuse (see Note 1)
TEST
CONDITIONS
PARAMETER
VCC(FB)
VFB
IFB
tFB
Supply voltage during fuse-blow condition
TA = 25°C
VCC
2.5
Voltage level on TDI/TCLK for fuse-blow - ’C41x
3.5
Voltage level on TDI/TCLK for fuse-blow - ’F41x
6
Supply current into TDI/TCLK during fuse blow
Time to blow fuse
UNIT
V
3.9
7
V
V
100
mA
1
ms
NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched
to bypass mode.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
37
SLAS340G − MAY 2001 − REVISED JUNE 2004
APPLICATION INFORMATION
input/output schematic
Port P1, P1.0 to P1.5, input/output with Schmitt-trigger
Pad Logic
CAPD.x
P1SEL.x
0: Input
1: Output
0
P1DIR.x
Direction Control
From Module
P1OUT.x
1
0
P1.x
1
Module X OUT
Bus
keeper
MSP430x412,
MSP430x413 only
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1
P1.3/SVSOUT
P1.4
P1.5/TACLK/ACLK
P1IN.x
EN
D
Module X IN
P1IE.x
P1IRQ.x
P1IFG.x
Q
EN
MSP430x415,
MSP430x417 only
P1.0/TA0.0
P1.1/TA0.0/MCLK
P1.2/TA0.1
P1.3/TA1.0/SVSOUT
P1.4/TA1.0
P1.5/TA0CLK/ACLK
Interrupt
Edge
Select
Set
P1IES.x
P1SEL.x
NOTE: 0 ≤ x ≤ 5.
Port Function is Active if CAPD.x = 0
PnSEL.x
PnDIR.x
Direction
Control
From Module
PnOUT.x
Module X
OUT
PnIN.x
Module X IN
PnIE.x
PnIFG.x
PnIES.x
P1SEL.0
P1DIR.0
P1DIR.0
P1OUT.0
Out0 Sig.†
P1IN.0
CCI0A†
P1IE.0
P1IFG.0
P1IES.0
P1SEL.1
P1DIR.1
P1DIR.1
P1OUT.1
MCLK
P1IN.1
CCI0B†
P1IE.1
P1IFG.1
P1IES.1
P1SEL.2
P1DIR.2
P1DIR.2
P1OUT.2
Out1 Sig.†
P1IN.2
CCI1A†
P1IE.2
P1IFG.2
P1IES.2
P1SEL.3
P1DIR.3
P1DIR.3
P1OUT.3
SVSOUT
P1IN.3
Unused
P1IE.3
P1IFG.3
P1IES.3
P1IN.4
Unused§
CCI0A‡
P1IE.4
P1IFG.4
P1IES.4
P1IN.5
TACLK†
P1IE.5
P1IFG.5
P1IES.5
P1SEL.4
P1DIR.4
P1DIR.4
P1OUT.4
DVSS§
Out0 Sig.‡
P1SEL.5
P1DIR.5
P1DIR.5
P1OUT.5
ACLK
† Timer_A3/Timer0_A3
‡ Timer1_A5 (MSP430x415, MSP430x417 only)
§ MSP430x412, MSP430x413 only
38
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS340G − MAY 2001 − REVISED JUNE 2004
APPLICATION INFORMATION
input/output schematic (continued)
Port P1, P1.6, P1.7 input/output with Schmitt-trigger
Pad Logic
Note: Port Function Is Active if CAPD.6 = 0
CAPD.6
P1SEL.6
0: Input
1: Output
0
P1DIR.6
1
P1DIR.6
P1.6/
CA0
0
P1OUT.6
1
DVSS
Bus
Keeper
P1IN.6
EN
unused
D
P1IE.7
P1IRQ.07
EN
Interrupt
Edge
Select
Q
P1IFG.7
Set
P1IES.x
P1SEL.x
Comparator_A
P2CA
AVcc
CAREF
CAEX
CA0
CAF
CCI1B
+
to Timer_Ax
−
CA1
2
Reference Block
CAREF
Pad Logic
Note: Port Function Is Active if CAPD.7 = 0
CAPD.7
P1SEL.7
0: Input
1: Output
0
P1DIR.7
1
P1.7/
CA1
P1DIR.7
0
P1OUT.7
1
DVSS
Bus
Keeper
P1IN.7
EN
unused
D
P1IE.7
P1IRQ.07
EN
Q
P1IFG.7
Set
Interrupt
Edge
Select
P1IES.7
P1SEL.7
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
39
SLAS340G − MAY 2001 − REVISED JUNE 2004
APPLICATION INFORMATION
input/output schematic (continued)
port P2, P2.0 to P2.7, input/output with Schmitt-trigger
P2.0, P2.1
LCDM.5
LCDM.6
P2.2 to P2.5
LCDM.7
0: Port Active
1: Segment xx
Function Active
P2.6, P2.7
Pad Logic
Segment xx
P2SEL.x
0: Input
1: Output
0
P2DIR.x
Direction Control
From Module
P2OUT.x
1
0
P2.x
1
Module X OUT
MSP430x412,
MSP430x413 only
P2.0/TA2
P2.1
P2.2/S23
P2.3/S22
P2.4/S21
P2.5/S20
P2.6/CAOUT/S19
P2.7/S18
Bus
keeper
P2IN.x
EN
Module X IN
D
P2IE.x
P2IRQ.x
P2IFG.x
Q
EN
Set
Interrupt
Edge
Select
P2IES.x
NOTE: 0 ≤ x ≤ 7
MSP430x415,
MSP430x417 only
P2.0/TA0.2
P2.1/TA1.1
P2.2/TA1.2/S23
P2.3/TA1.3/S22
P2.4/TA1.4/S21
P2.5/TA1CLK/S20
P2.6/CAOUT/S19
P2.7/S18
P2SEL.x
PnSEL.x
PnDIR.x
Direction
Control
From Module
PnOUT.x
Module X
OUT
PnIN.x
Module X IN
PnIE.x
PnIFG.x
PnIES.x
P2SEL.0
P2DIR.0
P2DIR.0
P2OUT.0
Out2 Sig.†
P2IN.0
CCI2A†
P2IE.0
P2IFG.0
P2IES.0
P2SEL.1
P2DIR.1
P2DIR.1
P2OUT.1
P2IN.1
Unused§
CCI1A‡
P2IE.1
P2IFG.1
P2IES.1
P2SEL.2
P2DIR.2
P2DIR.2
P2OUT.2
DVSS§
Out1 Sig.‡
DVSS§
Out2 Sig.‡
P2IN.2
Unused§
CCI2A‡
P2IE.2
P2IFG.2
P2IES.2
P2SEL.3
P2DIR.3
P2DIR.3
P2OUT.3
DVSS§
Out3 Sig.‡
P2IN.3
Unused§
CCI3A‡
P2IE.3
P2IFG.3
P2IES.3
P2SEL.4
P2DIR.4
P2DIR.4
P2OUT.4
DVSS§
Out4 Sig.‡
P2IN.4
Unused§
CCI4A‡
P2IE.4
P2IFG.4
P2IES.4
P2SEL.5
P2DIR.5
P2DIR.5
P2OUT.5
DVSS
P2IN.5
Unused§
TA1CLK‡
P2IE.5
P2IFG.5
P2IES.5
P2SEL.6
P2DIR.6
P2DIR.6
P2OUT.6
CAOUT
P2IN.6
Unused
P2IE.6
P2IFG.6
P2IES.6
P2SEL.7
P2DIR.7
P2DIR.7
P2OUT.7
DVSS
P2IN.7
Unused
P2IE.7
P2IFG.7
P2IES.7
† Timer_A3/Timer0_A3
‡ Timer1_A5 (MSP430x415, MSP430x417 only)
§ MSP430x412, MSP430x413 only
40
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS340G − MAY 2001 − REVISED JUNE 2004
APPLICATION INFORMATION
input/output schematic (continued)
port P3, P3.0, P3.7, input/output with Schmitt-trigger
LCDM.5
LCDM.6
LCDM.7
P3.2 to P3.7
P3.0, P3.1
0: Port Active
1: Segment xx
Function Active
Pad Logic
Segment xx
P3SEL.x
0: Input
1: Output
0
P3DIR.x
Direction Control
From Module
P3OUT.x
1
0
1
Module X OUT
P3.x
Bus
keeper
P3.0/S17
P3.1/S16
P3.2/S15
P3.3/S14
P3.4/S13
P3.5/S12
P3.6/S11
P3.7/S10
P3IN.x
EN
D
Module X IN
NOTE: 0 ≤ x ≤ 7
PnSEL.x
PnDIR.x
Direction
Control
From Module
PnOUT.x
Module X
OUT
PnIN.x
Module X IN
P3SEL.0
P3DIR.0
P3DIR.0
P3OUT.0
DVSS
P3IN.0
Unused
P3SEL.1
P3DIR.1
P3DIR.1
P3OUT.1
DVSS
P3IN.1
Unused
P3SEL.2
P3DIR.2
P3DIR.2
P3OUT.2
DVSS
P3IN.2
Unused
P3SEL.3
P3DIR.3
P3DIR.3
P3OUT.3
DVSS
P3IN.3
Unused
P3SEL.4
P3DIR.4
P3DIR.4
P3OUT.4
DVSS
P3IN.4
Unused
P3SEL.5
P3DIR.5
P3DIR.5
P3OUT.5
DVSS
P3IN.5
Unused
P3SEL.6
P3DIR.6
P3DIR.6
P3OUT.6
DVSS
P3IN.6
Unused
P3SEL.7
P3DIR.7
P3DIR.7
P3OUT.7
DVSS
P3IN.7
Unused
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
41
SLAS340G − MAY 2001 − REVISED JUNE 2004
APPLICATION INFORMATION
input/output schematic (continued)
port P4, P4.0 to P4.7, input/output with Schmitt-trigger
LCDM.5
LCDM.6
LCDM.7
0: Port Active
1: Segment xx
Function Active
Pad Logic
Segment xx
P4SEL.x
0: Input
1: Output
0
P4DIR.x
Direction Control
From Module
P4OUT.x
1
0
1
Module X OUT
P4.x
Bus
keeper
P4.0/S9
P4.1/S8
P4.2/S7
P4.3/S6
P4.4/S5
P4.5/S4
P4.6/S3
P4.7/S2
P4IN.x
EN
D
Module X IN
NOTE: 0 ≤ x ≤ 7
42
PnSEL.x
PnDIR.x
Direction
Control
From Module
PnOUT.x
Module X
OUT
PnIN.x
Module X IN
P4SEL.0
P4DIR.0
P4DIR.0
P4OUT.0
DVSS
P4IN.0
Unused
P4SEL.1
P4DIR.1
P4DIR.1
P4OUT.1
DVSS
P4IN.1
Unused
P4SEL.2
P4DIR.2
P4DIR.2
P4OUT.2
DVSS
P4IN.2
Unused
P4SEL.3
P4DIR.3
P4DIR.3
P4OUT.3
DVSS
P4IN.3
Unused
P4SEL.4
P4DIR.4
P4DIR.4
P4OUT.4
DVSS
P4IN.4
Unused
P4SEL.5
P4DIR.5
P4DIR.5
P4OUT.5
DVSS
P4IN.5
Unused
P4SEL.6
P4DIR.6
P4DIR.6
P4OUT.6
DVSS
P4IN.6
Unused
P4SEL.7
P4DIR.7
P4DIR.7
P4OUT.7
DVSS
P4IN.7
Unused
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS340G − MAY 2001 − REVISED JUNE 2004
APPLICATION INFORMATION
input/output schematic (continued)
port P5, P5.0, P5.1, input/output with Schmitt-trigger
LCDM.5
LCDM.6
LCDM.7
0: Port Active
1: Segment
Function Active
Pad Logic
Segment xx or
COMx or Rxx
P5SEL.x
0: Input
1: Output
0
P5DIR.x
Direction Control
From Module
P5OUT.x
1
0
1
Module X OUT
P5.x
Bus
keeper
P5.0/S1
P5.1/S0
P5IN.x
EN
D
Module X IN
NOTE: x = 0, 1
PnSEL.x
PnDIR.x
Direction
Control
From Module
PnOUT.x
Module X
OUT
PnIN.x
Module X IN
Segment
P5SEL.0
P5DIR.0
P5DIR.0
P5OUT.0
DVSS
P5IN.0
Unused
S1
P5SEL.1
P5DIR.1
P5DIR.1
P5OUT.1
DVSS
P5IN.1
Unused
S0
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
43
SLAS340G − MAY 2001 − REVISED JUNE 2004
APPLICATION INFORMATION
input/output schematic (continued)
port P5, P5.2, P5.4, input/output with Schmitt-trigger
0: Port Active
1: COMx Function
Active
Pad Logic
COMx
P5SEL.x
0: Input
1: Output
0
P5DIR.x
Direction Control
From Module
P5OUT.x
1
0
1
Module X OUT
P5.x
Bus
keeper
P5.2/COM1
P5.3/COM2
P5.4/COM3
P5IN.x
EN
D
Module X IN
NOTE: 2 ≤ x ≤ 4
PnSEL.x
PnDIR.x
Direction
Control
From Module
PnOUT.x
Module X
OUT
PnIN.x
Module X IN
COMx
P5SEL.2
P5DIR.2
P5DIR.2
P5OUT.2
DVSS
P5IN.2
Unused
COM1
P5SEL.3
P5DIR.3
P5DIR.3
P5OUT.3
DVSS
P5IN.3
Unused
COM2
P5SEL.4
P5DIR.4
P5DIR.4
P5OUT.4
DVSS
P5IN.4
Unused
COM3
NOTE:
The direction control bits P5SEL.2, P5SEL.3, and P5SEL.4 are used to distinguish between port
and common functions. Note that a 4MUX LCD requires all common signals COM3 to COM0, a
3MUX LCD requires COM2 to COM0, 2MUX LCD requires COM1 to COM0, and a static LCD
requires only COM0.
44
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS340G − MAY 2001 − REVISED JUNE 2004
APPLICATION INFORMATION
input/output schematic (continued)
port P5, P5.5 to P5.7, input/output with Schmitt-trigger
0: Port Active
1: Rxx Function
Active
Pad Logic
Rxx
P5SEL.x
0: Input
1: Output
0
P5DIR.x
Direction Control
From Module
P5OUT.x
1
0
1
Module X OUT
P5.x
Bus
keeper
P5.5/R13
P5.6/R23
P5.7/R33
P5IN.x
EN
D
Module X IN
NOTE: 5 ≤ x ≤ 7
PnSEL.x
PnDIR.x
Direction
Control
From Module
PnOUT.x
Module X
OUT
PnIN.x
Module X IN
Rxx
P5SEL.5
P5DIR.5
P5DIR.5
P5OUT.5
DVSS
P5IN.5
Unused
R13
P5SEL.6
P5DIR.6
P5DIR.6
P5OUT.6
DVSS
P5IN.6
Unused
R23
P5SEL.7
P5DIR.7
P5DIR.7
P5OUT.7
DVSS
P5IN.7
Unused
R33
NOTE:
The direction control bits P5SEL.5, P5SEL.6, and P5SEL.7 are used to distinguish between port
and LCD analog level functions. Note that 4MUX and 3MUX LCDs require all Rxx signals R33 to
R03, a 2MUX LCD requires R33, R13, and R03, and a static LCD requires only R33 and R03.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
45
SLAS340G − MAY 2001 − REVISED JUNE 2004
APPLICATION INFORMATION
input/output schematic (continued)
port P6, P6.0 to P6.6, input/output with Schmitt-trigger
P6SEL.x
0: Input
1: Output
0
P6DIR.x
Direction Control
From Module
P6OUT.x
1
0
1
Module X OUT
P6.x
P6.
P6.0
P6.1
P6.
P6.2
P6.3
P6.4
P6.
P6.5
P6.
P6.6
P6.
P6IN.x
EN
Module X IN
D
NOTE: 0 ≤ x ≤ 6
46
PnSEL.x
PnDIR.x
Direction
Control
From Module
PnOUT.x
Module X
OUT
PnIN.x
Module X IN
P6SEL.0
P6DIR.0
P6DIR.0
P6OUT.0
DVSS
P6IN.0
Unused
P6SEL.1
P6DIR.1
P6DIR.1
P6OUT.1
DVSS
P6IN.1
Unused
P6SEL.2
P6DIR.2
P6DIR.2
P6OUT.2
DVSS
P6IN.2
Unused
P6SEL.3
P6DIR.3
P6DIR.3
P6OUT.3
DVSS
P6IN.3
Unused
P6SEL.4
P6DIR.4
P6DIR.4
P6OUT.4
DVSS
P6IN.4
Unused
P6SEL.5
P6DIR.5
P6DIR.5
P6OUT.5
DVSS
P6IN.5
Unused
P6SEL.6
P6DIR.6
P6DIR.6
P6OUT.6
DVSS
P6IN.6
Unused
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS340G − MAY 2001 − REVISED JUNE 2004
APPLICATION INFORMATION
input/output schematic (continued)
port P6, P6.7 input/output with Schmitt-trigger
MSP430x412/413 only
P6SEL.7
0: Input
1: Output
0
P6DIR.7
Direction Control
From Module
P6OUT.7
1
0
1
Module X OUT
P6.x
P6.7
P6IN.7
EN
Module X IN
D
PnSEL.x
PnDIR.x
Direction
Control
From Module
PnOUT.x
Module X
OUT
PnIN.x
Module X IN
P6SEL.7
P6DIR.7
P6DIR.7
P6OUT.7
DVSS
P6IN.7
Unused
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
47
SLAS340G − MAY 2001 − REVISED JUNE 2004
APPLICATION INFORMATION
input/output schematic (continued)
port P6, P6.7 input/output with Schmitt-trigger
MSP430F415/417 only
SVS VLDx=15
P6SEL.7
P6DIR.7
0
1
0: Input
1: Output
Pad Logic
0
P6OUT.7
DVss
P6.7/SVSIN
1
Bus Keeper
P6IN.7
EN
Module X IN
D
SVS VLDx=15
1
To SVS
NOTE: Analog signals applied to digital gates can cause current flow from the positive to the negative terminal. The throughput current flows if
the analog signal is in the range of transitions 0→1 or 1→0. The value of the throughput current depends on the driving capability of the
gate. For MSP430, it is approximately 100 µA.
Use P6SEL.x=1 to prevent throughput current. P6SEL.x should be set, if an analog signal is applied to the pin.
48
SVS VLDx = 15
P6SEL.7
P6DIR.7
0
0
0
P6.7 Input
0
0
1
P6.7 Output
0
1
X
Undefined
1
X
X
SVSIN
POST OFFICE BOX 655303
Port Function
• DALLAS, TEXAS 75265
SLAS340G − MAY 2001 − REVISED JUNE 2004
APPLICATION INFORMATION
JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt-trigger or output
TDO
Controlled by JTAG
Controlled by JTAG
TDO/TDI
JTAG
Controlled
by JTAG
DVCC
TDI
Burn and Test
Fuse
TDI/TCLK
Test
and
Emulation
DVCC
TMS
Module
TMS
DVCC
TCK
TCK
RST/NMI
Tau ~ 50 ns
Brownout
TCK
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
G
D
U
S
G
D
U
S
49
SLAS340G − MAY 2001 − REVISED JUNE 2004
APPLICATION INFORMATION
JTAG fuse check mode
MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity
of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current, ITF , of 1.8 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse is not burned. Care must be
taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the
TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check
mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the
fuse check mode has the potential to be activated.
The fuse check current only flows when the fuse check mode is active and the TMS pin is in a low state (see
Figure 22). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition).
The JTAG pins are terminated internally, and therefore do not require external termination.
Time TMS Goes Low After POR
TMS
ITDI/TCLK
ITF
Figure 22. Fuse Check Mode Current, MSP430C41x, MSP430F41x
50
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996
PM (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
0,08 M
33
48
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
12,20
SQ
11,80
0,25
0,05 MIN
0°– 7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040152 / C 11/96
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Falls within JEDEC MS-026
May also be thermally enhanced plastic with leads connected to the die pads.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
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