Integral IN74LV373D Octal d-type transparent latch (3-state) Datasheet

IN74LV373
OCTAL D-TYPE TRANSPARENT LATCH (3-STATE)
•
•
•
•
•
•
IN74LV373 are compatible by pinning with IN74HC373A and
IN74HCT373A series. Input voltage levels are compatible with
standard CMOS levels.
Output voltage levels are compatible with input levels of CMOS,
NMOS and TTL ICS
Voltage supply range: 2.0 to 3.2 V
LOW input current: 1.0 µА; 0.1 µА at Т = 25 °С
Input current LOW/HIGH: 8 mА
Latch current: not less than 150 mА at Т = 125 °С
ESD acceptable value: not less than 2000 V as per HBM and not
less than 200 V as per MM
•
ORDERING INFORMATION
IN74LV373N Plastic DIP
IN74LV373D SOIC
TA = -40° to 125° C
for all packages
PIN ASSIGNMENT
BLOCK DIAGRAM
OE
D0
D1
D2
D3
D4
D5
D6
D7
LE
OE
03
02
04
05
07
06
08
09
13
12
14
15
17
16
18
19
Q0
Q1
Q2
VCC
01
20
Q0 02
19
Q7
D0 03
18
D7
D1 04
17
D6
16
Q6
Q1 05
373
Q3
Q2 06
15
Q5
Q4
D2 07
14
D5
D3 08
13
D4
Q3 09
12
Q4
GND 10
11
LE
Q5
Q6
Q7
11
01
Pin 20=VCC
Pin 10 = GND
OE
L
L
L
H
1
FUNCTION TABLE
Inputs
Output
LE
Dn
Qn
H
H
H
H
L
L
L
X
no change
X
X
Z
IN74LV373
ABSOLUTE MAXIMUM RATINGS*
Symbol
Parameter
Rating
Unit
VCC
Supply voltage
-0.5 to +5.0
V
1
IIK *
Input diode current
mА
±20
IOK *2
Output diode current
mА
±50
IO *3
Output source or sink current
mА
±35
ICC
VCC current
mА
±70
IGND
GND current
mА
±70
mW
PD
Power
dissipation
per
package:
750
Plastic
DIP
*4
4
500
SOIC *
Tstg
Storage temperature range
-65 to +150
°C
*
In absolute maximum ratings modes functioning is not guaranteed. Upon lifting the
absolute maximum ratings functioning is guarateed at the recommended operatng
conditions.
*1 Provided VI < -0.5 V or VI > VCC + 0.5 V.
*2 Provided VO < -0.5 V or VO > VCC + 0.5 V.
*3 Provided -0.5 V < VO < VCC + 0.5 V.
*4 When operating in the temperature range of 70°С to 125°C power dissipation value
decreses:
- for Plastic DIP by 12 mW/°C
- for SOIC by 8 mW/°C
RECOMMENDED OPERAING CONDITIONS
Symbol
Parameter
VCC
Supply voltage
VIN
Input voltage
VOUT
Output voltage
TA
Operating
ambient
temperature
range.
For all types of packages
tLH, tHL
Input rise and fall times
VCC =1.2 V
VCC =2.0 V
VCC =3.0 V
VCC =3.6 V
2
Min
1.2
0
0
-40
Max
3.6
VCC
VCC
125
Unit
V
V
V
°C
0
1000
700
500
400
ns
IN74LV373
DC CHARACTERISTICS
Symbol
Parameter
Test
conditions
VIH
HIGH
voltage
level VO =
0.1 V
VIL
LOW
voltage
level
VOH
HIGH
level
output voltage
VOL
LOW
level
output voltage
II
Input current
IOZ
OFF-state
output current
ICC
Supply current
VCC,
V
VCC- 1.2
2.0
3.0
3.6
VO =0.1 V
1.2
2.0
3.0
3.6
VI = VIH or VIL 1.2
2.0
IO = -50 µА
3.0
3.6
VI = VIH or VIL 3.0
IO = -8 mА
VI = VIH or VIL 1.2
2.0
IO = 50 µА
3.0
3.6
VI = VIH or VIL 3.0
IO = 8 mА
VI = VCC or 3.6
0V
3.6
3-state
outputs
VI = VIL or VIH
VO =VCC or
0V
VI =VCC or 3.6
0V
IO = 0 µА
Limits
25°C
-40°C to 85°C
125°C
min ma min
max min max
x
0.9
0.9
0.9
1.4
1.4
1.4
2.1
2.1
2.1
2.5
2.5
2.5
0.3
0.3
0.3
0.6
0.6
0.6
0.9
0.9
0.9
1.1
1.1
1.1
1.0
1.0
1.1
1.9
1.9
1.92 2.9
2.9
2.92 3.5
3.5
3.52 2.48 2.34
2.20
-
Unit
V
V
V
V
V
-
0.09
0.09
0.09
0.09
0.33
-
0.1
0.1
0.1
0.1
0.4
-
0.1
0.1
0.1
0.1
0.5
V
-
±0.1
-
±1.0
-
±1.0
µА
-
±0.5
-
±5
-
±10
µА
-
8.0
-
80
-
160
µА
3
IN74LV373
AC CHARACTERISTICS (CL=50 pF, tLH = tHL = 6.0 ns)
Test
VCC,
Symbol
Parameter
conditions
V
25°C
tPHL, tPLH
from Dn to
Qn
tPHL, tPLH
from LE to
Qn
tPHZ tPLZ
from OE to
Qn
tPZH tPZL
from OE to
Qn
tTHL, tTLH
tW
tSU
Propagation
delay
Figure 1
Propagation
delay
Figure 2
3-state
output Figure 4
enable time
3-state
time
disable Figure 4
Figures 1,2
HIGH-to-LOW
and
LOW-toHIGH transition
time
Clock
pulse Figure 2
width HIGH or
LOW
Set-up time Dn Figure 3
to LE
tH
Hold time Dn to Figure 3
LE
CI
Input
capacitance
Power
dissipation
capacitance
(per flip-flop)
CPD
1.2
2.0
3.0
1.2
2.0
3.0
1.2
2.0
3.0
1.2
2.0
3.0
1.2
2.0
3.0
Limits
-40°C to
125°C
85°C
min ma min max min max
x
220
190
- 150 58
48
38
35
29
23
270
230
- 180 68
56
45
41
34
27
240
200
- 160 45
43
35
32
28
23
240
200
- 160 60
50
40
36
30
24
120
100
75
24
20
16
15
13
10
-
1.2
2.0
3.0
1.2
2.0
3.0
1.2
2.0
3.0
3.0
250
30
18
45
15
9
25
5
5
-
7
350
34
20
50
17
10
25
5
5
-
-
450
41
24
100
15
12
25
5
5
-
-
-
80
-
-
-
-
VI = 0 V or 3.0
VCC
4
Unit
ns
pF
IN74LV373
tLH
tHL
0.9
0.9
Dn
V1
VCC
V1
0.1
tPL
0.1
tPH
H
L
0.9
GND
0.9
V1
V1
Qn
0.1
tTHL
tTLH
0V
0.1
V1 = 0.5VCC
Figure 1 - Time diagram
tLH
VCC
0.9
V1
V1
LE
V1
tW
0.1
GND
tPL
tPH
H
L
0.9
0.9
V1
V1
Qn
0.1
tTHL
tTLH
V1 = 0.5VCC
Figure 2 - Time diagram.
5
0.1
0V
IN74LV373
VCC
V1
Dn
V1
t SU
V1
tH
t SU
V1
GND
tH
VCC
LE
V1
V1
GND
V1 = 0.5V CC
Figure 3 - Time diagram
tLH
tHL
0.9
OE
VCC
0.9
V1
V1
0.1
0.1
tPZ
0.9
H
VOH
tPH
V1
Qn
GND
Z
0V
tPLZ
Qn
VCC
V1
tPZL
0.1
VOL
V1 = 0.5VCC
Figure 4 -Time diagram
6
IN74LV373
Drawing of the chip
1.66 mm
18
17
16
15
14
1.68 mm
19
13
12
20
11
74LV373/374
1
2
3
10
On-chip marking
4
5
6
9
7
Pads allocation Table
Pad
coordinates (counted from lower left corner),
number
mm
X
Y
01
0.142
0.628
02
0.142
0.377
03
0.142
0.125
04
0.498
0.125
05
0.693
0.125
06
0.871
0.125
07
1.095
0.125
08
1.423
0.130
09
1.423
0.329
10
1.423
0.587
11
1.423
0.949
12
1.423
1.198
13
1.423
1.447
14
1.085
1.447
15
0.868
1.447
16
0.696
1.447
17
0.461
1.447
18
0.142
1.447
19
0.142
1.245
20
0.142
0.997
7
8
Pad size, mm
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
Similar pages