ON NCP12600AAASN65T1G Multi-mode controller for offline power supply Datasheet

NCP12600
Multi-Mode Controller for
Offline Power Supplies
The NCP12600 is a peak−current controller operating at a 65−kHz
or 100−kHz fixed frequency. In high power conditions, the part
operates in continuous conduction mode (CCM). As the load current
reduces, the converter enters the discontinuous conduction mode
(DCM) of operation and synchronizes the turn−on event with the
minimum of the drain voltage. The NCP12600 implements valley
switching mode with a proprietary lockout scheme ensuring
noise−free operations. As output power further reduces, the controller
folds the switching frequency back and ensures stable valley switching
operations down to the 32nd valley provided the ringing is of sufficient
amplitude. The controller then enters a proprietary Quiet−Skip
skip−mode at small peak currents which reduces acoustic noise and
optimizes no−load standby power.
Adjustable over power protection ensures a flat output power level
regardless of the operating input voltage. Slope compensation is
ensured via the insertion of a resistor in series with the current sense
pin and is thus user−adjustable. The device packs several useful
features such as an extremely fast short circuit protection, a soft start in
current and frequency plus a dedicated circuitry to avoid latch off in
case of a line cycle dropout.
Over temperature protection (OTP) is implemented at the current
sense pin and requires the connection of a simple NTC resistance to
the auxiliary winding. Over voltage protection (OVP) is done by
sampling the auxiliary plateau and exists at the Vcc pin level.
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MARKING
DIAGRAM
TSOP−6
(SOT23−6)
SN SUFFIX
CASE 318G
STYLE 13
1
•
•
•
•
•
•
•
•
•
•
•
1
6zvAYW = Specific Device Code
z
= A or 2 (frequency)
v
= E, F, G or H
A
= Assembly Location
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
GND
1
6
DRV
FB
2
5
VCC
ZCD/Fault
3
4
CS
Features
• 65−kHz or 100−kHz Fixed−frequency Operation
• Valley Switching in Discontinuous Conduction Mode for Improved
6zvAYWG
G
Efficiency
(Top View)
Proprietary Valley Lockout for Controlled Operation in
Quasi−resonant Operation and Foldback Modes
Proprietary Quiet Skip Mode for Noiseless Operation in Light Load
ORDERING INFORMATION
Adjustable Over Power Protection
See detailed ordering, marking and shipping information on
page 3 of this data sheet.
Single 64−ms Protection Timer or Dual OCP Protection in Option
Frequency Foldback down to 25 kHz
Auto−recovery or Latched Overload Protection
• Over Temperature Protection Combined on CS Pin
True Output Short Circuit Protection with Pre−short
• Ultra−low Start−up Current Below 10 mA up to 125°C Tj
Compatibility
• Proprietary Quick Latched−state Reset Scheme
Line Cycle Dropout Recovery in Latched OCP Mode
• These are Pb−Free and RoHS−compliant Devices
5−ms Soft Start on Both Peak Current and Frequency
Typical Applications
for Lower Start−up Stress
• Ac−dc Notebook Adapters, USB Adapters, Wall−mount
Frequency Jitter in All Operating Modes
Power Supplies, Set Top Boxes, etc.
Over Voltage Protection with Precise Auxiliary Voltage
Sampling Event
© Semiconductor Components Industries, LLC, 2018
January, 2018 − Rev. 0
1
Publication Order Number:
NCP12600/D
NCP12600
Vbulk
Vout
.
.
.
OTP
opt.
NCP12600
1
6
2
5
3
4
slope
compensation
Figure 1. Typical Application Schematic
Table 1. PIN DESCRIPTION
Pin No
Pin Name
Function
Pin Description
1
GND
−
2
FB
Feedback pin
3
ZCD/
OPP/
fault
Detects core reset in QR operation.
Latches off the part in OVP. Adjusts
OPP level.
4
CS
Current sense
This pin monitors the primary peak current but also offers a means to adjust the compensation ramp level. A NTC connected to the pin offers a
simple over temperature protection.
5
Vcc
Supplies the controller
This pin is connected to an external auxiliary voltage and features an over
voltage protection circuitry.
6
DRV
Driver output
The controller ground.
Feedback input for the controller. Allows direct connection to an optocoupler.
A resistive bridge from this pin to the auxiliary winding adjusts the OPP
level and lets the controller observe the core magnetic state. A precise
OVP level can also be set via this pin.
The driver’s output to an external MOSFET gate. It is clamped to a safe
12−V gate−source level.
Options
Forming the part−number:
Y is the protection scheme:
NCP12600xyzSN65T1G – 65−kHz version with xyz picked
up in the below list
NCP12600xyzSN100T1G – 100−kHz version with xyz
picked up in the below list
The following code is adopted for the three letters x, y and z:
A = all protections are latched: OVP on demag, Vcc OVP,
OTP on CS, overload (OCP) and short circuit (SCP)
B = overload (OCP) and short circuit (SCP) are in
auto−recovery mode, all other protections (OVP on demag,
Vcc OVP, OTP on CS) are latched
C = all protections are in auto−recovery: OVP on demag, Vcc
OVP, OTP on CS, overload (OCP) and short circuit (SCP)
X implies the following choice:
A = single OCP
B = dual−level OCP level
Z implies the following options:
A = quiet skip
B = normal skip mode
600
Part
X
Y
Y
OCP trip point
OCP Fault
Quiet Skip
A – single, VCS = 0.7 V (max Ip)
A – All latched
A – Yes
B − dual, VCS = 0.5 V (overload), VCS = 0.7 V (max Ip)
B – SC/OCP autorecovery, rest is latched
C – All autorecovery
B – No
C to Z − reserved
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2
NCP12600
ORDERING INFORMATION
Controller
Marking
Freq.
(kHz)
OCP
SCP
OVP
aux
OTP
CS
OVP
Vcc
Mode
Skip
NCP12600AAASN65T1G
6AE
65
L
L
L
L
S
Q
NCP12600ABASN65T1G
6AF
65
AR
L
L
L
S
Q
NCP12600ABBSN65T1G
6AG
65
AR
L
L
L
S
N
NCP12600ACBSN65T1G
6AH
65
AR
AR
AR
AR
S
N
NCP12600AAASN100T1G
62E
100
L
L
L
L
S
Q
NCP12600ABASN100T1G
62F
100
AR
L
L
L
S
Q
NCP12600ACBSN100T1G
62G
100
AR
AR
AR
AR
S
N
AR
L
OCP
SCP
Mode
Skip
Package
Shipping
TSOP6
(Pb−free)
3000 /
Tape &
Reel
auto−recovery: the controller enters hiccup mode and tries to resume operations
latched: the controller is latched and the user needs to cycle the input voltage to restart
over current protection: the power supply is overloaded
short circuit protection: the power supply output is short circuited
single (S) or dual (D) trip point in overload
normal (N) or Quiet Skip (Q)
Jitter in
CCM
1.5 us
blanking
BO?
OVP1
UVLO
Vcc
Fault Management
Timers, UVLOs
+
ZCD
OTP
+
OVP2
−
−
VZCD
+
DCM? DMG
−
OVP1
400 mV
FB
−
Vdd
Multi−Mode Management
Fixed Frequency or
Valley Lockout Operation
VOVP1
+
reset
Fixed Fsw
or VCO
Vcc discharge
slow
clock
S
Vcc
in
Q
60mV
RFB
out
Gnd
FB
FB
Q
−
+
+
always
neg. or
0
1.5 us
blanking
Qb
R
Max
Ip
−
+
OTP
Qb
Skip
−
−
+
+
VOTP
Vilim
Clamp
clock
skip
+
LEB
CS
Rramp
slope comp.
Jitter in
DCM
Figure 2. Internal Block Diagram
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3
Drv
NCP12600
Table 2. MAXIMUM RATINGS TABLE
Symbol
VCC
VDRV(tran)
VCS, VFB, VZCD
Rating
Power Supply voltage, VCC pin, continuous voltage
DRV pin voltage, transigent voltage (Note 1)
Maximum voltage on low power pins CS and FB
Value
Unit
−0.3 to 28
V
−0.3 to VCC + 0.3
V
−0.3 to 5.5
V
VZCD(trann)
Maximum negative transient voltage on ZCD pin (Note 2)
−1
V
VZCD(tranp)
Maximum positive transient voltage on ZCD pin ( 2)
7
V
Isource,max
Maximum sourced current, pulse width < 800 ns
0.6
A
Maximum sinked current, pulse width < 800 ns
1.0
A
Maximum injected negative current into the ZCD pin (pin 1)
−2
mA
RqJ−A
Thermal Resistance Junction−to−Air
360
°C/W
TJ,max
Maximum Junction Temperature
Isink,max
IZCD
Storage Temperature Range
HBM
Human Body Model ESD Capability per JEDEC JESD22−A114F (All pins)
150
°C
−60 to +150
°C
7
kV
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The transient voltage is a voltage spike injected to DRV pin being in high state. Maximum transient duration is 100 ns.
2. See below figure for detailed specification of transient voltage
3. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.
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NCP12600
Table 3. ELECTRICAL CHARACTERISTICS
(For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, Vcc = 12 V unless otherwise noted)
Characteristics
Conditions
Symbol
Min
Typ
Max
Unit
VCC level at which driving pulses are authorized
VCC increasing
VCC(on)
16
18
20
V
VCC level at which driving pulses are stopped
VCC decreasing
VCC(min)
8.3
8.9
9.5
V
Hysteresis VCC(on) – VCC(min)
VCC(hyst)
7.7
–
VCC(reset)
SUPPLY SECTION AND VCC MANAGEMENT
Start−up hysteresis
Latched−state reset voltage
Hysteresis above Vcc(min) for fast hiccup
Hysteresis below VCC(min) before reset
8.65
VCC(hiccup)
mV
0.42
V
ICC1
–
5
10
mA
Fsw = 65 kHz, CDRV = 0 nF,
VFB = 3.2 V
Fsw = 100 kHz, CDRV = 0 nF,
VFB = 3.2 V
ICC2
–
1
Fsw = 65 kHz, CDRV = 1 nF,
VFB = 3.2 V
Fsw = 100 kHz, CDRV = 1 nF,
VFB = 3.2 V
ICC3
Internal IC consumption, skip mode – non switching
Feedback voltage is below
skip level
ICC(no−load)
300
mA
Internal IC consumption in skip mode – switching in
application, for information only
(Vcc = 12 V, driving a typical
7−A/650−V MOSFET, includes
optocoupler current)
ICC(standby)
420
mA
Internal IC consumption from OVP acknowledgment
to VCC(off) – Single−shot event
IC detects an OVP and quickly
brings VCC to VCC(off) for hiccup
ICC(OVP)
1
mA
Maximum Current Sense Voltage Limit – no OPP
VFB = VFB(max), VCS increasing
VZCD < –60 mV (Notes 4, 5)
VILIM1
0.65
0.7
0.75
V
Overload Current Sense Voltage Threshold – dual
OCP option
VFB = VFB(max), VCS increasing
VILIM2
0.46
0.5
0.53
V
tLEB1
230
280
340
ns
VCS > (VILIM+ 100 mV) to DRV
turn−off
tILIM
–
50
100
ns
VZCD = –290 mV
IOPPM
Internal IC consumption, steady state
VCC = VCC(on) – 100 mV
150
0.33
Internal IC consumption, steady state
VCC(reset,
V
0.18
Start−up supply current, controller disabled or
latched
Hysteresis VCC(min) –
VCC(reset)
V
hyst)
mA
1.1
–
1.7
mA
2.3
CURRENT SENSE COMPARATOR
Cycle by Cycle Leading Edge Blanking Duration
Cycle by Cycle Current Sense Propagation Delay
Maximum Setpoint decrease for pin 3 biased to
–290 mV (Note 6)
32.8
Voltage setpoint for pin 3 biased to −250 mV (Note 6)
IOPPvET
Blanking delay before considering VZCD for OPP
IOPPdel
600
ns
VZCD = −60 mV
IOPP0
−60
mV
VFB = 1 V
Vfreeze
200
mV
Open feedback pin
tSS
5
ms
Oscillator frequency – nominal (65 kHz version)
2.4 V < VFB < 3.8 V
fosc,nom
61
65
71
kHz
Oscillator frequency – nominal (100 kHz version)
2.4 V < VFB < 3.8 V
fosc,nom
90
100
110
kHz
VFB < 1.3 V
fosc,min
23
26
31
kHz
Dmax
76
Pin 4 voltage bias for 0% OPP
Frozen CS voltage in skip mode
Soft start, time to meet Ip,max at start up
0.46
0.51
%
0.56
V
OSCILLATOR
Oscillator frequency – minimum
Maximum duty ratio
4. OPP is not active as long as the negative voltage on the ZCD pin during ton is less than –60 mV.
5. beyond 3.8 V, the peak current is clamped to VILIM.
6. for proper linearity over negative bias voltage, we recommend keeping the level on pin 3 below –300 mV.
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5
%
NCP12600
Table 3. ELECTRICAL CHARACTERISTICS
(For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, Vcc = 12 V unless otherwise noted)
Characteristics
Conditions
Symbol
Min
Typ
Max
Unit
CCM−only operation
fjitter
±6
%
Internal offset to CS control
fswingDCM
±10
mV
–
fswing
1
kHz
Open feedback pin
tSS
5
ms
OSCILLATOR
Frequency jittering in percentage of fosc
Frequency jitter in valley−switching mode
Jitter modulation frequency in all modes
Soft−start, time to meet nominal Fsw at start up
INTERNAL SLOPE COMPENSATION
Artificial ramp level for slope compensation
Internal level at Tj = 25°C
Internal ramp resistance to CS pin
Vramp
−
4.2
−
V
Rramp
−
20.4
−
kW
FEEDBACK SECTION
FB pin is unloaded
VFB(open)
Internal Current Setpoint Division Ratio
−
Kratio
−
5.4
−
–
Pull−up resistance
−
RFB
−
40
−
kW
Equivalent resistance for the optocoupler
−
Req
Frequency foldback threshold, Fsw < 65 kHz
−
Vfold
2.3
2.4
2.5
V
End of frequency foldback threshold
−
Vfold,end
1.8
1.9
2
V
VFB going down, TJ = 25°C
Vskip(in)
0.9
1.0
1.1
V
−
Iskip
26
%
VFB is going up
Iskip,hys
60
mV
Feedback Input Open Voltage
Feedback voltage thresholds for skip mode
Skip−cycle current in percentage of ILIM
Hysteresis on skip comparator
4
V
29
kW
QUIET SKIP ONLY
nP,skip
3
−
−
−
Skip out delay
tskip
−
−
38
ms
Quiet−Skip timer
tquiet
1.0
1.25
1.5
ms
Vskip(tran)
1.8
2
2.2
V
25
45
70
mV
Minimum number of pulses in burst
Quiet−Skip escape level (transient enhancer)
VFB going up, TJ = 25°C
DEMAGNETIZATION SENSE
VZCD threshold voltage
VZCD decreasing
VZCD(TH)
VZCD hysteresis
VZCD increasing
VZCD(HYS)
Threshold voltage for output short circuit or aux.
winding short circuit detection (enter)
After tdelay_ZCD if VZCD <
VZCD(short1)
VZCD(short1)
Threshold voltage for output short circuit or aux.
winding short circuit detection (exit)
After tdelay_ZCD if VZCD >
VZCD(short2)
VZCD(short2)
VZCD decreasing from 3 V to 0 V
TDEM
−
Ttimout
4.5
5.5
6.5
ms
VCC > VCC(on) VZCD = 3 V,
DRV is low
IZCD
−
−
0.1
mA
Neg. bias present during the
on−time
VBOin
−22
−30
−38
mV
RSNK
RSRC
−
−
16
22
−
−
Propagation Delay from valley detection to DRV high
Internal delay after demagnetization detection
Low−Vin flag activation – latched OCP version only
−
0.4
mV
−
0.5
−
tdelay
Timeout after last demagnetization transition
(leakage ringing blanking)
Input leakage current
30
−
V
V
150
100
ns
ns
DRIVE OUTPUT
W
Drive resistance
DRV Sink
DRV Source
4. OPP is not active as long as the negative voltage on the ZCD pin during ton is less than –60 mV.
5. beyond 3.8 V, the peak current is clamped to VILIM.
6. for proper linearity over negative bias voltage, we recommend keeping the level on pin 3 below –300 mV.
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NCP12600
Table 3. ELECTRICAL CHARACTERISTICS
(For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, Vcc = 12 V unless otherwise noted)
Characteristics
Conditions
Symbol
Min
Typ
Max
Unit
Rise time
CDRV = 1 nF, from 10% to 90%
tr
−
40
ns
Fall time
CDRV = 1 nF, from 90% to 10%
tf
−
30
ns
DRV Low voltage
VCC = VCC(off) + 0.2 V,
CDRV = 220 pF, RDRV = 33 kW
VDRV(low)
8
−
−
V
DRV High voltage
VCC = VCC(OVP)−0.2 V, CDRV =
220 pF, RDRV = 33 kW
VDRV(high)
10
12
14
V
Source current
Peak source current VGS = 0 V
Isource
300
mA
Peak sink current VGS = 12 V
Isink
500
mA
Auto−recovery thermal shutdown
Device switching
TSHTDN
−
150
−
°C
Thermal Shutdown Hysteresis
Device switching
TSHTDN(HYS)
−
40
−
°C
Fault level detection for OVP, demagnetization pin,
toff sensing
Internal sample Vout increasing
VOVP1
2.85
3.15
3.35
V
Fault level detection on CS pin for OTP implementation – confirmation delay is TPP
Internal sample VCS increasing
VOTP
0.97
1
1.03
V
–
VOVP2
24
25.5
27
V
Sampling delay for OTP and OVP detection
(Fsw = 65 kHz)
Sampling event on ZCD and
CS pins
Tdelay_ZCD1
1.2
1.5
1.8
ms
Sampling delay for OTP and OVP detection
(Fsw = 100 kHz)
Sampling event on ZCD and
CS pins
Tdelay_ZCD2
0.8
1.1
1.3
ms
VZCD > VOVP1
Tlatch_count
−
8
−
−
Timer Delay Before Fault Acknowledgment −
Condition 1 – single OCP only
CS pin is w 0.7 V
TPP1
55
64
75
ms
Timer Delay Before Fault Acknowledgment in
Overload Condition – dual OCP only
CS pin w 0.5 V
TOCP
200
256
300
ms
Timer Delay Before Fault Acknowledgment with
dual OCP – dual OCP only
CS pin is w 0.7 V
TPP2
55
64
75
ms
Timer Delay in Clock Cycles Before Fault
Acknowledgment when in Output Short Circuit –
Condition 2
VZCD < 0.4 V
Unit is clock cycles
TSCP
DRIVE OUTPUT
Sink current
PROTECTIONS
Over Voltage Protection on the Vcc pin
Number of drive cycles before latch confirmation on
OVP1 and 2
8
4. OPP is not active as long as the negative voltage on the ZCD pin during ton is less than –60 mV.
5. beyond 3.8 V, the peak current is clamped to VILIM.
6. for proper linearity over negative bias voltage, we recommend keeping the level on pin 3 below –300 mV.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Condition 1: VFB is pushed to its maximum open−loop value. The demagnetization pin during the off−time is above 0.4 V.
Condition 2: VFB is pushed to its maximum open−loop value. The demagnetization pin during the off−time is less than 0.4 V.
8 clock cycles are counted and the part latches off or goes into auto−recovery. This mechanism only activates once the 5−ms
soft−start sequence is completed.
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NCP12600
10.0
18.8
9.8
18.6
9.6
18.4
9.4
VCC(min) (V)
19.0
18.2
18.0
17.8
9.2
9.0
8.8
17.6
8.6
17.4
8.4
17.2
17.0
−50
8.2
8.0
−50
−25
0
25
50
75
100
125
50
Figure 4.
9.0
8.9
9.6
8.8
9.4
8.7
9.2
9.0
8.8
8.2
8.2
8.0
−50
8.1
8.0
−50
50
75
100
125
125
75
100
125
75
100
125
8.4
8.4
25
100
8.5
8.3
0
75
8.6
8.6
−25
0
25
50
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 5.
Figure 6.
7.0
0.320
FSW = 65 kHz
FSW = 65 kHz
0.315
ICC NO LOAD (mA)
6.5
ICC1 (mA)
25
Figure 3.
9.8
6.0
5.5
5.0
0.310
0.305
0.300
0.295
4.5
4.0
−50
0
TEMPERATURE (°C)
10.0
−25
−25
TEMPERATURE (°C)
VCC(reset) (V)
VCC(hyst) (V)
VCC(on) (V)
TYPICAL CHARACTERISTICS
−25
0
25
50
75
100
0.290
−50
125
−25
0
25
50
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 7.
Figure 8.
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NCP12600
TYPICAL CHARACTERISTICS
2.20
1.6
1.4
2.15
ICC(AutoR) (mA)
ICC(latch) (FB = 4 V) (mA)
1.5
1.3
1.2
1.1
1.0
2.10
2.05
0.9
0.8
−50
−25
0
25
50
75
100
2.00
−50
125
25
50
TEMPERATURE (°C)
Figure 9.
Figure 10.
75
100
125
75
100
125
75
100
125
2.00
FSW = 65 kHz
1.98
1.15
FSW = 65 kHz
1.96
ICC3_65kHz (mA)
ICC2_65kHz (mA)
0
TEMPERATURE (°C)
1.20
1.10
1.05
1.00
1.94
1.92
1.90
1.88
1.86
1.84
0.95
0.90
−50
−25
−25
0
25
50
75
100
1.82
1.80
−50
125
−25
0
25
50
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11.
Figure 12.
1.14
0.320
FSW = 100 kHz
1.13
ICC2_100kHz (mA)
ICCNoLoad (mA)
0.315
0.310
0.305
0.300
1.12
1.11
1.10
0.295
0.290
−50
−25
0
25
50
75
100
125
1.09
−50
−25
0
25
50
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 13.
Figure 14.
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9
NCP12600
TYPICAL CHARACTERISTICS
2.40
0.705
0.704
0.703
2.36
VILIM (V)
ICC3_100kHz (mA)
2.38
2.34
0.701
0.700
0.699
2.32
0.698
FSW = 100 kHz
2.30
−50
0.702
−25
0
25
50
75
100
0.697
−50
125
−25
0
25
50
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 15.
Figure 16.
0.60
75
100
125
75
100
125
75
100
125
281
280
279
TLEB (ns)
VOLM(0.5) (V)
0.55
0.50
278
277
0.45
276
0.40
−50
−25
0
25
50
75
100
275
−50
125
−25
0
25
50
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 17.
Figure 18.
1.006
3.163
1.004
1.002
3.153
VOTP (V)
VOVP1 (V)
3.158
3.148
3.143
1.000
0.998
3.138
0.996
3.133
3.128
−50
−25
0
25
50
75
100
125
0.994
−50
−25
0
25
50
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 19.
Figure 20.
www.onsemi.com
10
NCP12600
TYPICAL CHARACTERISTICS
4.00
25.56
25.51
fbOpen (V)
VOVP2 (V)
3.95
25.46
3.85
125.41
25.36
−50
3.90
−25
0
25
50
75
100
3.80
−50
125
−25
0
25
50
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 21.
Figure 22.
75
100
125
75
100
125
75
100
125
3.50
18.7
3.45
3.40
18.2
Vramp (V)
Rramp (kW)
3.35
17.7
17.2
3.30
3.25
3.20
3.15
16.7
3.10
16.2
−50
3.05
3.00
−50
−25
0
25
50
75
100
125
−25
0
25
50
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 23.
Figure 24.
30.0
67.0
29.9
66.5
FOSC(max) (none) (kHz)
29.8
Req (kW)
29.7
29.6
29.5
29.4
29.3
29.2
29.1
29.0
−50
FSW = 65 kHz
66.0
65.5
65.0
64.5
−25
0
25
50
75
100
125
64.0
−50
−25
0
25
50
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 25.
Figure 26.
www.onsemi.com
11
NCP12600
TYPICAL CHARACTERISTICS
102.0
26.4
101.5
25.8
25.6
25.4
25.2
25.0
−50
101.0
100.5
100.0
99.5
FSW = 65 kHz
−25
0
FSW = 100 kHz
25
50
75
100
99.0
−50
125
0
25
50
TEMPERATURE (°C)
Figure 27.
Figure 28.
27.0
80.0
26.9
79.8
26.8
79.6
26.7
79.4
26.6
26.5
26.4
26.3
26.2
26.1
26.0
−50
−25
TEMPERATURE (°C)
DMax(65kHz) (%)
FoscMin(100kHz) (kHz)
Fosc(100kHz) (kHz)
26.0
75
100
125
75
100
125
79.2
79.0
78.8
78.6
78.4
FSW = 100 kHz
−25
0
25
50
75
100
125
78.2
78.0
−50
−25
0
25
50
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 29.
Figure 30.
80.0
79.8
79.6
DMax(100kHz) (%)
FoscMin(65kHz) (kHz)
26.2
79.4
79.2
79.0
78.8
78.6
78.4
78.2
78.0
−50
−25
0
25
50
TEMPERATURE (°C)
Figure 31.
www.onsemi.com
12
75
100
125
NCP12600
Application Information
• Low start−up current: A low start−up current is key to
The NCP12600 includes a state−of−the−art multi−mode
controller packed in a tiny 6−pin package for
fixed−frequency current mode control flyback converters
applications. Despite its limited amount of pins, the
controller includes numerous proprietary functions which
make it an ideal candidate for cost−sensitive applications.
• Fixed−Frequency Operation: Implementing peak
current mode control, the NCP12600 drives a flyback
converter at a 65−kHz or 100−kHz fixed switching
frequency and can operate in discontinuous conduction
mode (DCM) or continuous conduction mode (CCM).
• When DCM operation occurs in fixed−frequency
operation, the converter locks in a valley and a specific
mechanism paces valley jumps. When the output power
reduces, the part enters frequency foldback and jumps
into the valleys as the load further reduces. Going down
to 32 valleys (if available), the part ensures the lowest
turn−on losses and enables excellent overall efficiency.
As output power further goes down, the Voltage−
Controlled Oscillator (VCO) takes over and reduces
frequency down to 25 kHz where the current freezes to
26% of the maximum peak value. Then the part enters
normal skip cycle at lower power levels or in a no−load
situation.
• Quiet−Skip operation: classical skip cycle occurring in
light load is a known mechanism to improve the
converter’s efficiency when the load current becomes
lighter. Quiet−Skip also reduces acoustic noise by
preventing the skip mode burst period from entering the
audible range. The part is also available with a normal
skip option.
• Temporary and peak power capability: the part includes
a 2−level OCP allowing the converter to permanently
deliver a certain amount of power as long as VCS is less
than 0.5 V. When VCS exceeds 0.5 V, a 256−ms timer
is activated. If VFB further increases, the switching
frequency remains constant and the controller pushes
VCS to its maximum value, the 256−ms OCP timer is
instantaneously divided by 4 and becomes a 64−ms
timer. When it elapses, the part enters an auto−recovery
or latched mode depending on the selected option. As
such, the converter can be thermally designed for a
0.5−V VCS and authorizes temporary excursions to a
higher power level. Please note that the controller also
exists in a single OCP level (0.7 V, 64 ms duration)..
• Adjustable over power protection (OPP): Switching
power supplies are prone to output power runaway in
high−line conditions. To keep the delivered power
within control along the input voltage range, a circuit
observes the negative voltage present on the
demagnetization pin during the on−time and subtracts it
from the maximum peak current limit.
•
•
•
•
•
•
reducing the standby power in no− or light− load
situations. With a 10−mA max guaranteed up to 125°C,
the NCP12600 lets you enjoy high−valued start−up
resistors for the best standby power performance.
Over voltage protection: By precisely sampling the
auxiliary winding plateau voltage after the leakage
inductance is damped, the circuit monitors the reflected
output voltage with excellent precision. When the
monitored voltage exceeds the internal threshold more
than 8 successive clock cycles, the part definitively
latches off.
Over current protection: When the circuit senses that
the feedback loop is lost, VFB > 3.8 V, an internal
64−ms timer counts. If the fault disappears while
countdown has started, the timer resets and the power
converter keeps operating. If the timer elapses, all
pulses are immediately stopped and the part enters an
auto−recovery hiccup mode.
True short−circuit protection: By observing the peak
current setpoint and the off−time voltage on the
demagnetization pin, the circuit can detect an output
short circuit situation. When this conjunction of events
is confirmed, the SCP timer keeps counting. If this
situation is observed for more than 8 clock cycles, the
circuit immediately stops pulses and enters
auto−recovery or latched state. This circuit is active
during a start−up sequence (after SS has completed)
and in auto−recovery hiccup: if the demagnetization pin
is less than 0.4 V after the soft−start period (peak
current is maximum), then 8 cycles are counted and the
part stops operations. This is extremely efficient to
protect against board−level short circuits occurring at
high line as the RCD circuit can fail to keep the VDS
withing safe limits.
A general reset is implemented at too low an input
voltage and avoids latch off in line dropout tests with
OCP−latched versions of the NCP12600. When Vout
collapses within a line cycle dropout test, the part does
not latch (in case the latched option has been selected)
but nicely recovers when the mains is back to its
normal level.
Quick reset scheme: When latched on an OVP or an
OCP situation, the part will enter a fast low−voltage
hiccup mode slightly above the reset voltage. The reset
time by input power cycling will be greatly reduced
compared to existing solutions.
Frequency jitter: An internal clock modulates the
switching frequency and provides an efficient energy
spread to ease the converter’s EMI signature. Jitter
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13
NCP12600
•
•
clock (LFC) initiates a valley acquisition and increases or
decreases valley count during operations. When the next
low−frequency clock occurs, a new valley acquisition is run
to determine what valley number matches the upcoming
65−kHz (or 100 kHz) or VCO pulse. It is like a snapshot
where you freeze the converter operating point for the
upcoming period of time. For example, assume the 1st valley
was selected, then the new acquisition may confirm the 3rd
valley is the correct one and the part locks in valley 3. It
remains there until the next acquisition occurs or a transient
unlocks the control. That way, jumping between valleys
occurs at a controlled recurrence and not in a completely
random way, reducing the possibility to excite a mechanical
resonance on the transformer.
operates in fixed−frequency mode but also in QR and
foldback modes when the VCO is active.
Over temperature protection is implemented by forming
a resistive divider on the CS pin. The auxiliary voltage
appears during the off time and the CS level is only
considered after the 1.5−ms blanking time (1.1 ms for
the 100−kHz version). For a well−regulated output
voltage, the precision favorably compares with a
classical pull−down NTC on a dedicated pin.
Temperature shutdown: the controller includes an
internal thermal sensor which protects the circuit in
case of thermal runaway.
Overall Description
The NCP12600 builds upon previous generations of
fixed−switching frequency power suppy controllers. The
frequency is fixed in nominal power conditions but reduces
as the load is getting lighter. The major improvement lies in
the valley−switching operation: when DCM is entered
whether it is in high−power mode or in foldback, the
controller locks in the valley to ensure the best efficiency.
When variable frequency mode is activated, the part locks
in valleys and remains in this state. The peak current is free
to move at all times.
Variable Frequency Mode
When the load gets lighter, the feedback voltage starts
decreasing. When it reaches 2.4 V, the VCO takes over and
frequency reduces. When VFB reaches 1.9 V, the frequency
is clamped down to 25 kHz. Below this value, Fsw is fixed
and down to the skip cycle point, the part operates in peak
current mode control.
When the frequency reduces, the controller selects the
valley next to the VCO clock and locks in until the next
refresh signal comes from the LFC. By using a 5−bit counter,
the controller goes down to the 32nd valley if necessary.
When a transient is detected on the feedback voltage (load
re− or disconnection), the LFC disappears and the part
returns to a classical fixed−frequency operation for the best
transient response.
CCM Operation
In fixed−frequency operation, the part switches at 65 kHz
or 100 kHz in current−mode control and the feedback
permanently adjusts the current setpoint. For a feedback
voltage beyond 3.8 V, the peak current voltage setpoint is
clamped to 0.7 V. The situation with this maximum current
cannot last more than 64 ms (TPP). However, if a true short
circuit is detected in the output, the controller could
potentially place the converter in a dangerous situation if it
were pulsing while Vout is almost 0 V (heavy CCM can occur
in the primary side with a RCD clamp voltage runaway). To
avoid this stressful situation, the circuit senses the voltage on
the demagnetization pin during toff. If during toff the
demagnetization pin voltage is less than 0.4 V for more than
8 consecutive clock cycles, the controller stops all pulses
and goes into latch or auto−recovery mode depending on the
selected option. If during this mode and before the 8−cycle
timer ends, the short circuit disappears and the
demagnetization voltage goes above 0.5 V, the protection
scheme is reset.
Protections
There are several types of protection depending on
loading conditions:
1. When the load imposes a peak current setpoint
greater than 0.7 V, the 64−ms timer starts counting.
When it elapses, the converter latches off or enters
auto−recovery depending on the selected option.
2. A dual OCP version exists also for peak power
capability: when the peak current setpoint reaches
0.5 V, the 256−ms timer starts counting. If the
power further increases, VCS also does and
touches the 0.7−V limit. At this moment, the timer
is divided by 4, authorizing a 64−ms duration in
this mode. Afterwards, the controller latches off or
enters an auto−recovery cycle.
3. In this maximum power mode, the converter
observes the demagnetization voltage during toff.
If this voltage is lower than 0.4 V and if this
situation lasts for more than 8 consecutive clock
cycles, the controller immediately stops pulsing
and enters auto−recovery or latches off depending
on the selected options.
4. During start−up, the controller also observes the
demagnetization pin during the off−time. If this
voltage is less than 0.4 V once the soft−start
sequence is over (peak current is max) while Fsw is
DCM Operation
In fixed−frequency operation, it is very likely that low−
and high−line conditions lead to a different operating point
for a given Pout: CCM in low line and DCM in high line.
When the controller operates in CCM, the MOSFET is
turned on at a pace imposed by the regular clock. When
DCM is entered, the controller senses this mode and extends
the off−time to exactly match the next available valley. The
peak current is free to move while locked in the valley
whether the part operates in fixed frequency mode or in
foldback. Inside the controller, a low−frequency refresh
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14
NCP12600
7. A similar sampling occurs on the CS pin to check
if an OTP event is detected. When the pin exceeds
1 V during the off time for more than 64 ms, the
part latches off (or hiccups depending on the
selected option).
65 kHz (or 100 kHz), then the controller counts 8
clock cycles and terminates operation. Vcc goes
down to UVLO and the IC restarts (hiccup mode)
or remains latched (latched version).
5. At any moment when the 64−ms timer circuit is
counting, the controller observes a brown−out
(BO) flag raised if VZCD is less than VBOin. If a
condition arises during which the BO flag is raised
AND any of the timer is counting, all pulses stop
but the resulting counter effect (latch for instance)
is ignored and Vcc is let go down to UVLO for a
quick recovery. With this technique, when adapters
featuring a latched OCP option are tested in line
cycle dropouts, even if the converter would like to
latch off because the mains has disappeared while
it was heavily loaded, the circuit prevents this and
forces the converter to auto recover when the
mains is restored..
6. The part senses the plateau voltage on the
demagnetization pin 1.5 ms after the power switch
has been turned off (1.1 ms for the 100−kHz
version). This helps ignore the leakage ringing and
offers a clean plateau voltage to sense. When the
voltage on the demagnetization pin exceeds 3.15 V
for 8 consecutive clock cycles, the part latches off
(or hiccups depending on the selected option).
This is an easy and efficient way to protect the
converter in an OVP situation.
Start−up Sequence
As illustrated in Figure 32, peak current and the switching
frequency are gradually increased at start−up in a 5−ms
soft−start (SS) sequence. Frequency starts from 25 kHz and
hits 65 kHz (or 100 kHz) after 5 ms as feedback voltage is
pushed to its maximum value. The 64−ms timer counts as
VCS is above 0.7 V. When the 5−ms SS sequence is over, the
peak current is maximum. During this sequence (VFB is still
pushed to the max, Vout is not on target), if Vcc accidentally
touches UVLO, the part featuring the pre−short option
immediately latches off. On the contrary, if everything goes
well – the loop closes (Vout is on target) before Vcc touches
UVLO and the 64−ms timer is reset. If an UVLO event
occurs after a normal start−up sequence, it auto−recovers as
it should. This smooth start−up mode helps reduce the stress
on the output diode or in the synchronous MOSFET when
power up occurs on heavy load. As this mode is also
activated in auto−recovery protection (for the selected
option), it significantly reduces the stress on the various
power components when the converter tries resuming
operations. Figure 32 offers a typical drive waveform
captured during the power−on sequence.
vDRV (t )
Power on
25 kHz
65 kHz
5−ms SS
ton = 1.4 ms
40 ms
25 kHz
Figure 32. During the start−up sequence, both frequency and current setpoint are slowly raised for 5 ms
The NCP12600 start−up voltage is purposely made high
to permit large energy storage in a small Vcc capacitor value.
This helps operation with a small start−up current which,
together with a small Vcc capacitor, will not hamper the
start−up time. To further reduce the standby power, the
controller start−up current is purposely kept low, below
10 mA and it is guaranteed up to a 125°C junction
temperature. Start−up resistors can therefore be connected
to the bulk capacitor or directly to the mains input voltage if
desired to save a few more mW.
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15
NCP12600
D1
R3
R4
R1
R2
D2
Vcc
Input
mains
Cbulk
C1
D5
1N4148
I2
D6
BAV21
I1
X2
I3
D3
.
ICC1
D4
CVcc
C4
aux
Figure 33. The startup resistor can be connected to the input mains for further power dissipation reduction
Figure 33 shows a typical recommended configuration
where start−up resistors connect together to the mains input.
This technique offers the benefit of freely discharging the
X2 capacitor usually part of the EMI filter. The calculation
of these resistors depends on several parameters. Assuming
a 0.47−mF X2 capacitor, the safety standard recommends a
time constant t less than 1 s maximum when a resistor is
connected in parallel to provide a discharge path. This sets
the upper limit for the sum of discharge resistors connected
to the controller Vcc:
R startup t
1 t 2.1 MW
0.47 m
inputs (two half−wave connections then), half of the average
current I1 is defined by:
I1
+
2
(eq. 5)
V ac,rmsǸ2
85 1.414 −18
−V CCon
p
p
R start−up v
v
v 1.3 MW
15 m
I CV ,min
(eq. 1)
CC
We could thus connect two resistors of 1.3 MW (total
2.6 MW) across the line to a) power the IC at start up b)
ensure X2 discharge when the user unplugs the adapter.
However, 2.6 MW conflicts with (1) and we will reduce the
1.3−MW resistor to a 1−MW value, totaling 2 MW, in
agreement with (1).
Multi−mode Operation
(eq. 2)
The NCP12600 works as a classical fixed−switching
frequency controller and can operate in CCM and DCM.
When the load current is reducing, the converter eventually
enters DCM. At this moment, NCP12600 implements a
proprietary multimode engine which locks in the
drain−source valley to improve efficiency. The frequency is
now fixed but the peak current is free to move to maintain
Vout in regulation. An internal refresh clock will start a new
acquisition and valley jump occurs but at a controlled pace.
This operation differs from other controllers in which the
selected valley changes on the fly, resulting in a
spectrally−distributed perturbation. This uncontrolled
perturbation can possibly mechanically excite the
transformer and generate acoustic noise. Here, because the
refresh frequency is constant, it is less likely to excite the
transformer across a variety of frequencies and acoustic
noise is eliminated in this mode. In case a transient load
occurs, the controller naturally returns to its normal
operating mode until the feedback stabilizes again.
I CCt 1
1.5 m 10 m
w
w 1.6 mF
9
V CCon * V CCmin
Let us first select a 2.2−mF capacitor at first and
experiments in the laboratory will let us know if we were too
optimistic for t1. Testing across temperature range is
important as capacitance and ESR of this Vcc capacitor can
be affected. The Vcc capacitor being known, we can now
evaluate the charging current we need to bring the Vcc
voltage from 0 to the IC VCCon voltage, 18 V typical. This
current has to be selected to ensure start−up at the lowest
mains (85 V rms) to be less than 3 s (2.5 s for design margin)
typically for an adapter:
I charge w
V CConC V
2.5
CC
w
18
2.2 m
w 16 mA
2.5
(eq. 4)
To make sure this current is always greater than 15 mA
(half of the necessary 30−mA current), the minimum value
for Rstart−up can be extracted:
The first step starts with the calculation of the needed Vcc
capacitor which will supply the controller until the auxiliary
winding takes over. Experience shows that this time t1 can
be between 5 and 20 ms depending on the loading conditions
and the output capacitance. Considering that we need at least
an energy reservoir for a t1 time of 10 ms, the Vcc capacitor
must be larger than:
CV CC w
Vac,rmsǸ2
* V CCon
p
R startup
(eq. 3)
If we account for the 10−mA current that flows inside the
controller (I1 in Figure 33), then the total charging current
delivered by the start−up resistor must be 26 mA, rounded to
30 mA. If we connect the start−up network to both mains
www.onsemi.com
16
NCP12600
vDS (t )
vDS (t )
Jump from 3−2−3 valleys
vDS (t )
3rd to 2nd
Vin = 142 V, Iout = 0.9 A
Figure 34. The multimode engine paces the valley jump event at a controlled rate
Over Power and Over Voltage Protection
During toff , the auxiliary winding jumps to the reflected
output voltage scaled by the secondary−to−auxiliary
transformer turns ratio. Diode D1 is conducting and the
network Rupp /Rzcd sets the OVP voltage. When the power
MOSFET turns on, the auxiliary voltage jumps to a negative
voltage representative of the input voltage. That negative
voltage will be internally subtracted from the peak current
setpoint. An internal 60−mV offset prevents compensation
from taking place at low line.
The positive and negative auxiliary voltages depend on
the transformer turns ratios. We can define them as follows:
Np:Ns = Npow, the primary to power winding turns ratio
Np:Na = Naux, the primary to auxiliary winding turns ratio
During the off−time, the auxiliary winding jumps to the
following plateau voltage:
Over Power Protection (OPP) is a known means to limit
the output power excursion at high mains. Several elements
such as propagation delays and operating mode explain why
a converter operated at high line delivers more power than
at low line. NCP12600 implements a proprietary technique
that senses the bulk input voltage via a resistive network
connected to the auxiliary winding. However, as the pin used
for OPP (pin 3) also combines other functions such as
demagnetization detection and OVP, a specific network has
to be designed as shown in Figure 35.
Rupp
.
D1
BAV21
Ropp
Aux
winding
V aux + ǒV out ) V f1Ǔ
N aux
N pow
(eq. 6)
in which Vf1 is the power diode drop at nominal power. That
voltage appears on pin 3 affected by the resistive divider
Rupp /Rzcd and D1’s forward drop Vf2:
3
Rzcd
V plat + ǒV aux ) V f2Ǔ
R zcd
R zcd ) R upp
(eq. 7)
During the on−time, D1 is blocked and Ropp now appears
in series with Rupp . The voltage on pin 3 is defined as
Figure 35. Over Power Protection is provided via
the bulk voltage image present on Brown−Out pin
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17
NCP12600
V pin3 +
R zcd
N V
R zcd ) R upp ) R opp aux in
Slope Compensation
(eq. 8)
The NCP12600 includes an internal slope compensation
signal. This is the buffered oscillator clock delivered during
the on−time only. Its amplitude is around 4.2 V at the
maximum duty ratio. Slope compensation is a known means
used to eliminate sub−harmonic oscillations in CCM−
operated current−mode converters. These oscillations take
place at half the switching frequency and occur only during
CCM with a duty ratio greater than 50%. To lower the
current loop gain, one usually injects between 50 and 100%
of the inductor downslope. Figure 36 depicts how internally
the ramp is generated. Please note that the ramp signal will
be disconnected from the CS pin, during the off time.
in which Vin is the bulk dc voltage. That voltage is the
negative OPP voltage we need for our compensation. As
pin3 internally includes a 60−mV offset, the negative
voltage present on pin3 brings a final sense voltage
reduction of
V sense + 700 mV ) V pin3 ) 60 m
(eq. 9)
Assume Vpin3 = –150 mV during ton, thus the effective
sense reduction is
V sense + 700 mV * 150 m ) 60 m + 610 mV (eq. 10)
The peak current reduction is thus 12.8%. Combining the
above equations lets us calculate the values for Rupp and
Ropp based on design requirements:
ǒ
R zcd V f 2 *
R opp +
ǒ
R zcd
R upp +
N auxǒVf 1)VOVPǓ
Npow
V OVP1
NauxǒVf 1)VOVPǓ
Npow
V OVP1
Ǔ
0V
(eq. 11)
*
Ǔ
2.5 VV
4.2
ON
N auxR zcdV inHL
V opp
latch
reset
20.4 kW
20k
Rcomp
(eq. 12)
* Vf 2
+
L.E.B
CS
−
Rsense
* R zcd
In these expressions, we have:
from FB
setpoint
Rzcd is the pull−down resistor arbitrarily selected. 1.8 kW
could be a value to start with (we recommend to select a
resistance below 2 kW for the best linearity in the OPP
compensation)
VOVP is the output voltage at which you want the plateau to
reach the threshold voltage VOVP1 (3.15 V typical)
VinHL is the high−line dc voltage measured across the input
bulk capacitor
Assume the following data:
Vout = 19 V, Npow = 0.250, Naux = 0.184, Vf1 = 0.8 V, Vf2 =
0.65 V, VinHL = 375 V, Rzcd = 1.8 kW
We want an OPP reduction of 12% and an output OVP set
to 25 V. This leads to the following resistor values: Rupp =
9.2 kW and Ropp = 851 kW.
Pin3 is also used for demagnetization detection. A small
capacitance can be added in parallel with Rzcd to introduce
a delay and to exactly turn−on in the drain−source valley.
Experiments show that capacitances up to 150 pF provide
adequate results. Please make sure the negative value during
the on−time is not affected by too large a capacitance.
Pin3 protects the converter against short circuit to ground.
Should you do this during safety tests, the part simply
interprets the shortening to ground as an output short circuit
and stops pulsing quickly. Please note that an Excel®
spreadsheet is available from our product website and
automates the calculation of the above resistances.
Figure 36. inserting a resistor in series with the
current sense information brings ramp
compensation and stabilizes the converter in CCM
operation
NCP12600 oscillator ramp features a 4.2 V swing. If the
clock operates at a 65−kHz frequency, then the available
oscillator slope corresponds to:
S ramp +
V ramp,peakD max
T sw
(eq. 13)
4.2
@
0.8
+
+ 341kVńs or 341mVńms
15.4m
In our flyback design, assume a primary inductance Lp of
550 mH. The converter delivers 19 V with a Np :Ns ratio of
1:0.25. The off−time primary current slope Sp is thus given
by:
ǒVout ) Vf 1Ǔ
SP +
LP
NS
NP
(eq. 14)
+
(19 ) 0.8)
550 u
4
+ 144 kAńs
Considering a sense resistor of 330 mW, the above current
ramp turns into a voltage ramp of the following amplitude:
(eq. 15)
S sense + S PR sense + 144 k
0.33 [ 47 kVńs or 47 mVńms
If we select 50% of the downslope as the required amount of
compensation, then we shall inject a ramp whose slope is
www.onsemi.com
18
NCP12600
Feedback
23 mV/ms. Our internal compensation being of 341 mV/ms,
the divider ratio (divratio) between Rcomp and the internal
20.4−kW resistor is:
divratio +
23 m
[ 0.067
341 m
The feedback is done by bringing the FB pin down with
an optocoupler as shown in Figure 37. To maintain a low
consumption current, the resistive network on the FB pin is
higher than in other controllers. As a result, the optocoupler
pole may be located at a lower position. Popular
optocouplers like PC817 or SFH615 exhibit poles in the
3−4 kHz region. For that reason, a simple 100−pF capacitor
connected between the circuit FB and GND pins (located
close to the IC) will ensure local decoupling without
interfering with crossover selection. In the secondary side,
the figure shows a typical application for a 19.5−V output.
This is a type 2 configuration and a single 0.1−mF capacitor
will do the job typically for a fast and non−ringing transient
response.
(eq. 16)
The series compensation resistor value is thus:
(eq. 17)
R comp + R rampdivratio + 20.4 k
0.067 [ 1.4 kW
A resistor of the above value will then be inserted from the
sense resistor to the current sense pin. We recommend
adding a small capacitor of 100 pF, from the current sense
pin to the controller ground for an improved immunity to the
noise. Please make sure both components are located very
close to the controller.
Vout
Vdd
R1
40k
19.5 V
R4
1k
R6
56k
buffer
FB
1
8
GAIN
2
C1
100pF
VCO
7
9
14
VCOoutput
R5
10k
R2
135k
C2
0.1uF
10
3
R8
12k
−
6
0.7 V
5
PWMrst
11
+
R3
31k
NCP431
R7
10k
CS
Figure 37. The optocoupler brings the FB pin
down as the NCP431 injects more current into the
LED
25 kHz. This low−frequency value is reached
when VFB reaches 1.9 V. When the
voltage−controlled oscillator (VCO) operates, the
controller also locks in the valley to ensure the
best efficiency. Valley jumping is also likely to
occur here but the controller sets the pace at which
they occur. Of course, nothing prevents from
finding a stable operating point between two
hesitations, this is normal.
4. The load current is very small and the feedback
voltage is below 1.9 V. Frequency is fixed to
25 kHz and classical peak current mode control
operates. When the feedback voltage touches 1 V,
classical or Quiet skip cycle takes place for the
best standby power performance. See below for
detailed operations.
The curve in Figure 38 describes the various operating
stages as feedback varies.
The NCP12600 is a multi−mode controller meaning that
several operating modes are possible:
1. Continuous conduction mode (CCM) is available
as with any PWM controller. Usually, CCM is
entered at heavy load and low line.
2. As output power reduces, the converter leaves
CCM and enters discontinuous conduction mode
(DCM). The controller detects this mode and locks
in the next available valley. The switching
frequency is no longer fixed and is dictated by the
valley jumps. The feedback voltage can be
between its maximum value and 2.4 V in this
quasi−resonant mode. Discrete frequency jumps
occur but are controlled by NCP12600 internal
logic.
3. If the load current continues to decrease, the
feedback passes below the 2.4−V threshold and
frequency foldback begins. The frequency is
gradually reduced from 65 kHz (or 100 kHz) to
www.onsemi.com
19
NCP12600
Fsw
Foldback zone
with jitter
PWM operation
with fixed Fsw
Open-loop
PWM operation
with fixed Fsw
65 kHz
25 kHz
VFB = 3.8 V
Pout
VFB = 4 V
Vsense
0.7 V
VFB = 1.9 V VFB = 2.4 V
VFB < 1V
timer starts
Pout
Full load
Figure 38. The frequency is folded back as output power demands reduces
Dual OCP – Option
the CS pin crosses this first 0.5−V threshold, a timer of
duration t1 starts. If the power keeps increasing and pushes
the peak current to the next 0.7−V sense voltage limit, the
charging current of the timer is multiplied by 4 making the
new timer t2 equal to t1/4. For instance, a typical timer
configuration of 256 ms/64 ms lets the converter delivers
power for 256 ms when VCS hits 0.5 V and this time is
reduced to 64 ms if it directly jumps to 0.7 V during an
overload condition.
Some applications require the possibility to deliver a peak
power during a certain duration while the rest of the time, the
average power is low. The converter is thus thermally sized
to cope with a moderate average power (VCS < 0.5 V) while
allowing short−duration output power peaks when VCS
touches the 0.7−V limit. The NCP12600 can be configured
in a so−called dual−OCP mode where a second level is
inserted in the current sense circuitry. When the voltage on
Fsw
PWM operation
with fixed Fsw
Foldback zone
with jitter
Open-loop
PWM operation
with fixed Fsw
65 kHz
25 kHz
VFB = 3.8 V
Vsense
VFB = 4 V
Pout
VFB = 2.7 V
VFB = 1.9 V VFB = 2.4 V
VFB < 1V
0.7 V
64 ms timer starts
0.5 V
256 ms timer starts
Pout
Intermediate load
Full load
Figure 39. The dual−OCP option sets two timers depending on the amount of delivered current
Quiet−Skip − Option
until this timer has expired. As the output power decreases,
the switching frequency decreases. Once it hits minimum
switching frequency fOSC(min), the skip−in threshold is
reached and burst mode is entered − switching stops as soon
as the current drive pulses ends – it does not stop
immediately.
To further avoid acoustic noise, the circuit prevents the
burst frequency during skip mode from entering the audible
range by limiting it to a maximum of 800 Hz. This is
achieved via a timer tquiet that is activated during
Quiet−Skip. The start of the next burst cycle is prevented
www.onsemi.com
20
NCP12600
expires, the drive pulses will wait for the skip−exit
threshold.
This means that during no−load, there will be a minimum
of nP,skip drive pulses, and the burst−cycle period will likely
be much longer than 1250 ms. This operation helps to
improve efficiency at no−load conditions.
In order to exit burst mode, the FB voltage must rise higher
than Vskip(tran) level. If this occurs before tquiet expires, the
drive pulses will resume immediately – i.e. the controller
won’t wait for the timer to expire. Figure 40 provides an
example of how Quiet−Skip works, while Figure 41 shows
the immediate escape from Quiet−Skip if VFB crosses the
transient level Vskip(tran).
Once switching stops, FB will rise. As soon as FB crosses
the skip−exit threshold, drive pulses will resume but the
controller remains in burst mode. At this point, a 1250 ms
(typ) timer tquiet is started together with a count to nP,skip
pulses counter. This nP,skip pulses counter ensures the
minimum number of DRV signal pulses in burst. The next
time the FB voltage drops below the skip−in threshold, DRV
pulses stop at the end of the current pulse as long as nP,skip
drive pulses have been counted (if not, they do not stop until
the end of the nP,skip −th pulse). They are not allowed to start
again until the timer expires, even if the skip−exit threshold
is reached first. It is important to note that the timer will not
force the next cycle to begin – i.e. if the natural skip
frequency is such that skip−exit is reached after the timer
V FB
V skip(out)
V skip(in)
Sequence of events
1; 2; 3 starts the quiet
skip mode
V FB
V skip(out)
V skip(in)
The DRV pulses does not
start even when V FB > V skip(out)
in the quiet skip mode
2
1
DRV
time
Running just above skip
mode with fsw = f osc(min)
DRV
3
time
t quiet
n P , skip
t quiet
nP , skip
When VFB > Vskip(tran) the quiet skip
mode immediately finishes
V FB
V skip(tran)
V skip(out)
V skip(in)
DRV
time
n P , skip
n P , skip
t quiet
t quiet
n P , skip
Quiet skip mode
forces at least np,skip
pulses in skip mode
burst
DRV pulses does
not start because
VFB < V skip(in)
Figure 40. Leaving the Quiet−Skip Mode during Load Transient
V FB
Vskip(tran)
Crossing the transient
enhancement level
stops the quiet skip
immediatelly
V skip(out)
Vskip(in)
Exits skip
after quiet
timer
expires
DRV
t quiet
t quiet
Enters
skip
Enters
skip
Time
Figure 41. Quiet−skip Timing Diagram
www.onsemi.com
21
NCP12600
Over Temperature Protection
It is possible to trip a second protection via the CS pin. If
you connect a NTC resistor from the auxiliary winding
through a fast diode and a series resistance, it is possible to
latch off the part (or make it auto−recover depending on the
selected option) at the desired temperature. Figure 42 shows
the adopted principle. The auxiliary winding jumps to the
output voltage reflected to the primary side during toff and
described by (6) If the loop is well designed, i.e. with
sufficient loop gain in dc, the precision of this available
voltage can be very good. As this voltage is available during
the off−time, we can use it to build a temperature−dependent
voltage on the CS pin and compare the value to an internal
precise 1−V reference. According to Figure 42 labels, the
voltage at the CS pin during toff equals
V CS + ǒV aux * V f 2Ǔ
R ramp
R ramp ) R NTC ) R OTP
R OTP +
R rampǒV aux * V f 2Ǔ
V OTP
* R ramp * R NTC
(eq. 19)
A very popular NTC model is the TT3 series. Assume we
have selected a device exhibiting a 470−kW resistance at
25°C. When the temperature reaches 110°C, this resistance
drops to 8.8 kW typically. Statistical analysis show that a
good precision can be obtained as long as the ramp
resistance is of moderate value. Here, experiments show that
a 1−kW resistance is a good fit to the application and leads
to the following ROTP calculation:
R OTP +
1 k(14 * 0.35)
* 1 k * 8.8 k + 4.1 kW
1
(eq. 20)
The NCP12600 reference voltage VOTP is guaranteed at
±3% across the entire temperature range while all resistors
are ±1%. The auxiliary plateau is estimated to a ±5%
precision. The Vf of the series diode can be calibrated at the
trip point to refine calculations but if the auxiliary winding
is of large amplitude, its contribution to the final error
remains small.
(eq. 18)
The ramp resistor Rramp is selected depending on the
operating mode at low line while ROTP must be calculated
as
BAV21
.
ROTP
RNTC
OTP
Rramp
+
CS
Rsense
−
VOTP
DRV
Figure 42. The NTC lifts the CS pin voltage during the off−time. If the voltage exceeds 1 V, all pulses stop
200
We can estimate what the final spread will be in the
temperature trip point by assigning uniform distributions to
each of the parameters. The resulting curve shown in
Figure 43 indicates that an NTC resistance varying between
7.6 kW and 10 kW will trip the controller in OTP.
150
RNTCdisti
ƴ1Ƶ
100
50
3
7⋅ 10
3
8 ⋅ 10
RNTC = 7.6kW
3
4
9 ⋅ 10
RNTCdisti
1⋅ 10
ƴ0Ƶ
RNTC = 10kW
Figure 43. By assigning precision to the various
components, it is possible to calculate the OTP trip
point dispersion
www.onsemi.com
22
4
1.1⋅ 10
NCP12600
converter requires less slope compensation (light CCM
operation) or works exclusively in DCM.
If we now look at the corresponding temperatures the
NTC resistance varying between these two limits
correspond to, we obtain a range between 116 and 104°C.
Centered at 110°C, it gives a theoretical precision of ±5.4°C.
It is possible to improve the precision by removing the
ROTP resistor. That element is inserted because the ramp
resistance is imposed before the OTP calculation. Now
assume that you remove ROTP and calculate Rramp to match
the 1−V trip point when RNTC = 8.8 kW. In our example,
Rramp would be 680 W. Considering a 2−element divider
versus 3 as originally selected, then the dispersion would
narrow down to 8 kW − 9.6 kW, leading to a temperature trip
point of 110°C ± 4.5°C. Something worth considering if the
Latched Mode
When the part latches off in OVP or OTP (or even in an
OCP condition if the option is selected), the part
immediately stops pulsing and activates an internal 1−mA
current source. This source brings Vcc quickly to the UVLO
level +100 mV and a fast hiccup around UVLO starts. That
way, if the user cycles the input source, reset occurs at a
quicker pace. Figure 44 shows a typical waveform inherent
to this proprietary techniques.
vCC (t )
vDS (t )
1−mA source
is on
1−mA source
is off
Fast hiccup
Figure 44. when the controller latches off, the Vcc is quickly discharged
to the fast hiccup level, authorizing a fast reset
Please note that another OVP is installed on the Vcc pin
and monitors the dc value permanently biasing the pin. If
that voltage exceeds VOVP2 typically set at 25 V the part
latches off or auto−recovers depending on the selected
option.
www.onsemi.com
23
NCP12600
PACKAGE DIMENSIONS
TSOP−6
CASE 318G−02
ISSUE V
D
H
6
5
ÉÉ
E1
1
2
4
L2
GAUGE
PLANE
E
3
NOTE 5
L
M
b
C
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM
LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D
AND E1 ARE DETERMINED AT DATUM H.
5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.
SEATING
PLANE
DETAIL Z
e
A
0.05
c
A1
DETAIL Z
DIM
A
A1
b
c
D
E
E1
e
L
L2
M
MIN
0.90
0.01
0.25
0.10
2.90
2.50
1.30
0.85
0.20
0°
MILLIMETERS
NOM
MAX
1.00
1.10
0.06
0.10
0.38
0.50
0.18
0.26
3.00
3.10
2.75
3.00
1.50
1.70
0.95
1.05
0.40
0.60
0.25 BSC
10°
−
STYLE 13:
PIN 1. GATE 1
2. SOURCE 2
3. GATE 2
4. DRAIN 2
5. SOURCE 1
6. DRAIN 1
RECOMMENDED
SOLDERING FOOTPRINT*
6X
0.60
6X
3.20
0.95
0.95
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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NCP12600/D