Preliminary HY5V52(L)F(P) Series 4Banks x 2M x 32bits Synchronous DRAM Document Title 4Bank x 2M x 32bits Synchronous DRAM Revision History Revision No. History Draft Date Remark 0.1 Initial Draft Jun. 2004 Preliminary This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1 / June. 2004 1 Preliminary HY5V52(L)F(P) Series 4Banks x 2M x 32bits Synchronous DRAM DESCRIPTION The Hynix HY5V52(L)F(P) series is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. HY5V52(L)F(P) is organized as 4banks of 2,097,152x32. HY5V52(L)F(P) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a '2N' rule) FEATURES • Voltage : VDD, VDDQ 3.3V • Auto refresh and self refresh • All device pins are compatible with LVTTL interface • 4096 Refresh cycles / 64ms • 90Ball FBGA with 0.8mm of pin pitch • Programmable Burst Length and Burst Type • All inputs and outputs referenced to positive edge of system clock • Data mask function by DQM0,1,2 and 3 • Internal four banks operation - 1, 2, 4, 8 or full page for Sequential Burst - 1, 2, 4 or 8 for Interleave Burst • Programmable CAS Latency ; 2, 3 Clocks • Burst Read Single Write operation ORDERING INFORMATION Part No. Clock Frequency CAS Latency HY5V52(L)F-H 133MHz 3 HY5V52(L)F-P 100MHz 2 HY5V52(L)F-S 100MHz 3 HY5V52(L)FP-H 133MHz 3 HY5V52(L)FP-P 100MHz 2 HY5V52(L)FP-S 100MHz 3 Organization Interface 90 Ball FBGA Leaded 4Banks x 2Mbits x32 LVTTL Lead Free Note 1. HY5V52F Series : Normal power 2. HY5V52LF Series : Low Power 3. HY5V52xF Series : Leaded 90Ball FBGA 4. HY5V52xFP Series : Lead Free 90Ball FBGA This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1 / June. 2004 2 Preliminary HY5V52(L)F(P) Series 4Banks x 2M x 32bits Synchronous DRAM Ball CONFIGURATION 1 2 3 A DQ26 DQ24 B DQ28 C 7 8 9 VSS VDD DQ23 DQ21 VDDQ VSSQ VDDQ VSSQ DQ19 VSSQ DQ27 DQ25 DQ22 DQ20 VDDQ D VSSQ DQ29 DQ30 DQ17 DQ18 VDDQ E VDDQ DQ31 NC NC DQ16 VSSQ F VSS DQM3 A3 A2 DQM2 VDD G A4 A5 A6 A10 A0 A1 H A7 A8 NC NC BA1 A11 J CLK CKE A9 BA0 /CS /RAS K DQM1 NC NC /CAS /WE DQM0 L VDDQ DQS VSS VDD DQ7 VSSQ M VSSQ DQ10 DQ9 DQ6 DQ5 VDDQ N VSSQ DQ12 DQ14 DQ1 DQ3 VDDQ P DQ11 VDDQ VSSQ VDDQ VSSQ DQ4 R DQ13 DQ15 VSS VDD DQ0 DQ2 Rev. 0.1 / June. 2004 4 5 TOP View 6 3 Preliminary HY5V52(L)F(P) Series 4Banks x 2M x 32bits Synchronous DRAM Ball FUNCTION DESCRIPTIONS SYMBOL Ball NAME TYPE DESCRIPTION CLK Clock INPUT The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK. CKE Clock Enable INPUT Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh CS Chip Select INPUT Enables or disables all inputs except CLK, CKE and DQM BA0, BA1 Bank Address INPUT Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity A0 ~ A11 Address INPUT Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA8 Auto-precharge flag : A10 RAS, CAS, WE Row Address Strobe, Column Address Strobe, Write Enable INPUT RAS, CAS and WE define the operation Refer function truth table for details DQM0~3 Data Input/Output Mask I/O DQ0 ~ DQ31 Data Input/Output SUPPLY NC No Connection Rev. 0.1 / June. 2004 - Controls output buffers in read mode and masks input data in write mode Multiplexed data input / output pin No Connection 4 Preliminary HY5V52(L)F(P) Series 4Banks x 2M x 32bits Synchronous DRAM FUNCTIONAL BLOCK DIAGRAM 2Mbit x 4banks x 32 I/O Synchronous DRAM Self refresh logic & timer Internal Row Counter 2Mx32 BANK 3 CLK CKE Column Pre Decoder DQM3 DQ0 I/O Buffer & Logic Column Active DQM2 Memory Cell Array Sense AMP & I/O Gate DQM1 2Mx32 BANK 0 X-Decoder Refresh 2Mx32 BANK 1 X-Decoder X-Decoder WE DQM0 State Machine CAS 2Mx32 BANK 2 X-Decoder CS RAS Row Pre Decoder Row Active DQ31 Y-Decoder Column Add Counter Bank Select A0 A11 BA1 Address Buffers A1 Address Register Mode Register Burst Counter CAS Latency Data Out Control Pipe Line Control BA0 Rev. 0.1 / June. 2004 5 Preliminary HY5V52(L)F(P) Series 4Banks x 2M x 32bits Synchronous DRAM BASIC FUNCTIONAL DESCRIPTION Mode Register BA1 BA0 A11 A10 A9 A8 A7 0 0 0 0 OP Code 0 0 A6 A5 A4 CAS Latency A3 A2 BT A1 A0 Burst Length OP Code A9 Write Mode 0 Burst Read and Burst Write 1 Burst Read and Single Write CAS Latency Burst Type A3 Burst Type 0 Sequential 1 Interleave Burst Length A6 A5 A4 CAS Latency 0 0 0 Reserved 0 0 1 0 1 0 1 1 0 1 0 A2 A1 A0 1 0 0 0 2 0 1 3 0 Reserved 1 Burst Length A3 = 0 A3=1 0 1 1 0 1 2 2 0 1 0 4 4 0 1 1 8 8 Reserved 1 0 0 Reserved Reserved Reserved 1 1 0 Reserved 1 0 1 Reserved 1 1 1 Reserved 1 1 0 Reserved Reserved 1 1 1 Full Page Reserved Rev. 0.1 / June. 2004 6 Preliminary HY5V52(L)F(P) Series 4Banks x 2M x 32bits Synchronous DRAM ABSOLUTE MAXIMUM RATING Symbol Rating Unit Ambient Temperature Parameter TA 0 ~ 70 oC Storage Temperature TSTG -55 ~ 125 oC VIN, VOUT VDD VDDQ IOS PD -1.0 ~ 4.6 -1.0 ~ 4.6 -1.0 ~ 4.6 50 1 V V V mA W TSOLDER 260 . 10 Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Voltage on VDDQ relative to VSS Short Circuit Output Current Power Dissipation Soldering Temperature . Time oC . Sec DC OPERATING CONDITION (TA= 0 to 70oC ) Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VDD, VDDQ VIH VIL Min 3.0 2.0 -0.3 Typ 3.3 3.3 - Max 3.6 VDDQ+0.3 0.8 Unit V V V Note 1 1, 2 1, 3 Note : 1. All voltages are referenced to VSS = 0V 2. VIH(max) is acceptable 5.6V AC pulse width with <=3ns of duration. 3. VIL(min) is acceptable -2.0V AC pulse width with <=3ns of duration AC OPERATING TEST CONDITION (TA= 0 to 70 oC, VDD=3.3±0.3V, VSS=0V) Parameter AC Input High/Low Level Voltage Input Timing Measurement Reference Level Voltage Input Rise/Fall Time Output Timing Measurement Reference Level Voltage Output Load Capacitance for Access Time Measurement Rev. 0.1 / June. 2004 Symbol VIH / VIL Vtrip tR / tF Voutref CL Value 2.4/0.4 1.4 1 1.4 50 Unit V V ns V pF Note 1 7 Preliminary HY5V52(L)F(P) Series 4Banks x 2M x 32bits Synchronous DRAM CAPACITANCE (TA= 0 to 70 oC, f=1MHz, VDD=3.3V) Parameter Pin Input capacitance Data input / output capacitance Symbol Min Max Unit CLK CI1 2.0 4.0 pF A0 ~ A12, BA0, BA1, CKE, CS, RAS, CAS, WE, DQM0~3 CI2 2.0 4.0 pF DQ0 ~ DQ31 CI/O 3.5 6.5 pF Note 1. Vtt=1.4V Vtt=1.4V RT=500 Ω Output RT=50 Ω Output Z0 = 50Ω 30pF 30pF DC Output Load Circuit AC Output Load Circuit DC CHARACTERRISTICS I (TA= 0 to 70oC) Parameter Input Leakage Current Symbol Min Max Unit Note ILI -1 1 uA 1 Output Leakage Current ILO -1 1 uA 2 Output High Voltage VOH 2.4 - V IOH = -2mA Output Low Voltage VOL - 0.4 V IOL = +2mA Note : 1. VIN = 0 to 3.6V, All other balls are not tested under VIN =0V 2. DOUT is disabled, VOUT=0 to 3.6 Rev. 0.1 / June. 2004 8 Preliminary HY5V52(L)F(P) Series 4Banks x 2M x 32bits Synchronous DRAM DC CHARACTERISTICS II (TA= 0 to 70oC) Parameter Symbol Speed Test Condition H P S Uni Not t e Operating Current IDD1 Burst length=1, One bank active tRC ≥ tRC(min), IOL=0mA Precharge Standby Current in Power Down Mode IDD2P CKE ≤ VIL(max), tCK = 15ns 2 mA IDD2PS CKE ≤ VIL(max), tCK = ∞ 1 mA IDD2N CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns Input signals are changed one time during 2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V 15 IDD2NS CKE ≥ VIH(min), tCK = ∞ Input signals are stable. 15 IDD3P CKE ≤ VIL(max), tCK = 15ns 5 IDD3PS CKE ≤ VIL(max), tCK = ∞ 5 IDD3N CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns Input signals are changed one time during 2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V 30 IDD3NS CKE ≥ VIH(min), tCK = ∞ Input signals are stable. 20 Burst Mode Operating Current IDD4 tCK ≥ tCK(min), IOL=0mA All banks active Auto Refresh Current IDD5 tRC ≥ tRC(min), All banks active Self Refresh Current IDD6 CKE ≤ 0.2V Precharge Standby Current in Non Power Down Mode Active Standby Current in Power Down Mode Active Standby Current in Non Power Down Mode 120 110 mA 1 mA mA mA CL=3 150 130 CL=2 160 140 220 Normal 3 Low Power 1.5 mA 1 mA 2 mA 3 Note : 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open 2. Min. of tRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II 3. HY5V52F(P) Series : Normal, Rev. 0.1 / June. 2004 HY5V52LF(P) Series : Low Power 9 Preliminary HY5V52(L)F(P) Series 4Banks x 2M x 32bits Synchronous DRAM AC CHARACTERISTICS I (AC operating conditions unless otherwise noted) Parameter Symbol H Min P Max Min Max Min Unit Note tCK3 7.5 CAS Latency=2 tCK2 10 Clock High Pulse Width tCHW 2.5 - 3.0 - 3.0 - ns 1 Clock Low Pulse Width tCLW 2.5 - 3.0 - 3.0 - ns 1 CAS Latency=3 tAC3 - 5.4 - 6 - 6 ns CAS Latency=2 tAC2 - 6 - 6 - 6 ns Data-out Hold Time tOH 2.0 - 2.0 - 2.0 - ns Data-Input Setup Time tDS 2.0 - 2.0 - 2.0 - ns 1 Data-Input Hold Time tDH 1.0 - 1.0 - 1.0 - ns 1 Address Setup Time tAS 2.0 - 2.0 - 2.0 - ns 1 Address Hold Time tAH 1.0 - 1.0 - 1.0 - ns 1 CKE Setup Time tCKS 2.0 - 2.0 - 2.0 - ns 1 CKE Hold Time tCKH 1.0 - 1.0 - 1.0 - ns 1 Command Setup Time tCS 2.0 - 2.0 - 2.0 - ns 1 Command Hold Time tCH 1.0 - 1.0 - 1.0 - ns 1 CLK to Data Output in Low-Z Time tOLZ 1.0 - 1.0 - 1.0 - ns CLK to Data Output in High- CAS Latency=3 Z Time CAS Latency=2 tOHZ3 2.0 5.4 2.0 6.0 2.0 6.0 ns tOHZ2 2.0 6.0 2.0 6.0 2.0 6.0 ns Access Time From Clock 1000 10 1000 10 Max CAS Latency=3 System ClockCycle Time 10 S 12 1000 ns ns 2 Note : 1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter. 2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter. Rev. 0.1 / June. 2004 10 Preliminary HY5V52(L)F(P) Series 4Banks x 2M x 32bits Synchronous DRAM AC CHARACTERISTICS II (AC operating conditions unless otherwise noted) Parameter Symbol H P S Min Max Min Max Min Max Unit Note RAS Cycle Time Operation tRC 65 - 70 - 70 - ns RAS Cycle Time Auto Refresh tRRC 65 - 70 - 70 - ns RAS to CAS Delay tRCD 20 - 20 - 20 - ns RAS Active Time tRAS 45 100K 50 100K 50 100K ns RAS Precharge Time tRP 20 - 20 - 20 - ns RAS to RAS Bank Active Delay tRRD 15 - 20 - 20 - ns CAS to CAS Delay tCCD 1 - 1 - 1 - CLK Write Command to Data-In Delay tWTL 0 - 0 - 0 - CLK Data-in to Precharge Command tDPL 2 - 2 - 2 - CLK Data-In to Active Command tDAL DQM to Data-Out Hi-Z tDQZ 2 - 2 - 2 - CLK DQM to Data-In Mask tDQM 0 - 0 - 0 - CLK MRS to New Command tMRD 2 - 2 - 2 - CLK CAS Latency=3 tPROZ3 3 - 3 - 3 - CLK CAS Latency=2 tPROZ2 2 - 2 - 2 - CLK Power Down Exit Time tDPE 1 - 1 - 1 - CLK Self Refresh Exit Time tSRE 1 - 1 - 1 - CLK Refresh Time tREF - 64 - 64 - 64 ms Precharge to Data Output High-Z tDPL + tRP 1 Note : 1. A new command can be given tRC after self refresh exit. Rev. 0.1 / June. 2004 11 Preliminary HY5V52(L)F(P) Series 4Banks x 2M x 32bits Synchronous DRAM COMMAND TRUTH TABLE Command CKEn-1 CKEn CS RAS CAS WE DQM Mode Register Set H X L L L L X OP code No Operation H X H X X X L H H H X X Bank Active H X L L H H X H X L H L H X CA H X L H L L X CA H X L L H L X X Burst Stop H X L H H L X X DQM H V X Auto Refresh H H L L L H X X Burst-Read-Single-WRITE H X L L L L X A9 ball High (Other balls OP code) Entry H L L L L H X Exit L H H X X X L H H H Entry H L H X X X L H H H H X X X L H H H H X X X L V V V Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Self Refresh1 X Precharge power down Clock Suspend Exit L H Entry H L Exit L H Rev. 0.1 / June. 2004 X X ADDR A10/AP BA RA Note V L H L H V V H X L V MRS Mode X X X X X X X 12 Preliminary HY5V52(L)F(P) Series 4Banks x 2M x 32bits Synchronous DRAM PACKAGE INFORMATION 90 Ball 0.8mm pitch, 11mm x 13mm FBGA Unit [mm] 11.0 2.30 ± 0.10 6.40 BSC 0.80( Typ) A1 INDEX MARK 0.80( Typ) 0.450 ± 0.05 View 13.0 ± 0.10 11.20 BSC Bottom 6.50 ± 0.05 3.20 ± 0.05 0.340 ±0.05 5.50 ± 0.05 1.20 max Rev. 0.1 / June. 2004 13