CYM1836 128K x 32 Static RAM Module Features • High-density 4-megabit SRAM module • 32-bit standard footprint supports densities from 16K x 32 through 1M x 32 • High-speed CMOS SRAMs — Access time of 15 ns • Low active power — 2.6W (max.) at 20 ns • SMD technology • TTL-compatible inputs and outputs • Low profile — Max. height of 0.57 in. • Small PCB footprint — 0.78 sq. in. • Available in SIMM, ZIP format. SIMM suitable for vertical or angled sockets. Functional Description The CYM1836 is a high-performance 4-megabit static RAM module organized as 128K words by 32 bits. This module is Logic Block Diagram constructed from four 128K x 8 SRAMs in SOJ packages mounted on an epoxy laminate board with pins. Four chip selects (CS1, CS2, CS3, CS4) are used to independently enable the four bytes. Reading or writing can be executed on individual bytes or any combination of multiple bytes through proper use of selects. Writing to each byte is accomplished when the appropriate Chip Select (CS) and Write Enable (WE) inputs are both LOW. Data on the input/output pins (I/O) is written into the memory location specified on the address pins (A 0 through A16). Reading the device is accomplished by taking the Chip Select (CS) LOW while Write Enable (WE) remains HIGH. Under these conditions, the contents of the memory location specified on the address pins will appear on the data input/output pins (I/O). The data input/output pins stay at the high-impedance state when write enable is LOW or the appropriate chip selects are HIGH. Two pins (PD0 and PD1) are used to identify module memory density in applications where alternate versions of the JEDEC-standard modules can be interchanged. Pin Configuration ZIP/SIMM Top View PD0−OPEN PD1−OPEN A0 − A16 17 OE WE 128K x 8 SRAM 4 I/O0 − I/O7 128K x 8 SRAM 4 I/O8 − I/O15 CS1 PD0 I/O0 I/O1 I/O2 I/O3 VCC A7 A8 A9 I/O4 I/O5 I/O6 I/O7 WE A14 CS1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 CS3 A16 GND I/O16 I/O17 I/O18 I/O19 A10 A11 A12 A13 I/O20 I/O21 I/O22 I/O23 GND 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 CS2 128K x 8 SRAM 4 I/O16 − I/O23 128K x 8 SRAM 4 I/O24 − I/O31 CS3 CS4 1836–1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 GND PD1 I/O8 I/O9 I/O10 I/O11 A0 A1 A2 I/O12 I/O13 I/O14 I/O15 GND A15 CS2 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 CS4 NC OE I/O24 I/O25 I/O26 I/O27 A3 A4 A5 VCC A6 I/O28 I/O29 I/O30 I/O31 1836–2 Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 February 15, 1999 CYM1836 Selection Guide 1836–15 1836–20 1836–25 1836–30 1836–35 1836–45 Maximum Access Time (ns) 15 20 25 30 35 45 Maximum Operating Current (mA) 760 480 480 480 480 480 Maximum Standby Current (mA) 180 100 100 100 100 100 Shaded area contains preliminary information. Maximum Ratings Operating Range (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –55°C to +125°C Range Ambient Temperature VCC Commercial 0°C to +70°C 5V ± 10% Ambient Temperature with Power Applied ............................................... –10°C to +85°C Supply Voltage to Ground Potential ............... –0.5V to +7.0V DC Voltage Applied to Outputs in High Z State ............................................... –0.5V to +7.0V DC Input Voltage............................................ –0.5V to +7.0V Electrical Characteristics Over the Operating Range 1836–20, 25, 30, 35, 45 1836–15 Parameter Description Test Conditions Min. Max. VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage 2.2 VCC VIL Input LOW Voltage –0.5 0.8 IIX Input Load Current GND < VI < VCC –20 +20 IOZ Output Leakage Current GND < VO < VCC, Output Disabled –20 +20 ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, CS < VIL ISB1 Automatic CS Power-Down Current[1] VCC = Max., CS > VIH, Min. Duty Cycle = 100% ISB2 Automatic CS Power-Down Current[1] VCC = Max., CS > VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V Min. Max. 2.4 0.4 V 0.4 V 2.2 VCC V –0.5 0.8 V –20 +20 µA –20 +20 µA 760 480 mA 180 100 mA 60 28 mA Shaded area contains preliminary information. Capacitance[2] Parameter Description Capacitance[3] CIN Input COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. Unit 40/20 pF 15 pF Notes: 1. A pull-up resistor to VCC on the CS input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given. 2. Tested on a sample basis. 3. 20 pF on CS, 40 pF all others. 2 Unit CYM1836 AC Test Loads and Waveforms R1 481 Ω R1 481 Ω 5V ALL INPUT PULSES 5V OUTPUT R2 255Ω 30 pF INCLUDING JIG AND SCOPE OUTPUT 90% OUTPUT R2 255Ω 5 pF INCLUDING JIG AND SCOPE (a) Equivalent to: 3.0V < 5 ns 90% 10% < 5 ns 1836–3 (b) 1836–4 THÉ VENIN EQUIVALENT 167Ω GND 10% 1.73V 3 CYM1836 Switching Characteristics Over the Operating Range[4] 1836–15 Parameter Max. 1836–20 Min. Max. 1836–25 Min. Max. 1836–30 Min. Max. 1836–35 Min. Max. 1836– 45 Description Min. Min. Max. Unit tRC Read Cycle Time 15 tAA Address to Data Valid tOHA Output Hold from Address Change tACS CS LOW to Data Valid 15 20 25 30 35 45 ns tDOE OE LOW to Data Valid 7 8 8 10 12 15 ns tLZOE OE LOW to Low Z tHZOE OE HIGH to High Z tLZCS CS LOW to Low Z[5] tHZCS CS HIGH to High Z[5, 6] READ CYCLE 20 15 3 25 20 3 0 3 0 7 3 3 10 3 3 ns 15 3 15 ns ns 0 12 13 ns 45 3 0 11 10 45 35 3 0 10 3 35 30 3 0 8 7 30 25 ns ns 18 ns WRITE CYCLE[7] tWC Write Cycle Time 15 20 25 30 35 45 ns tSCS CS LOW to Write End 12 15 15 18 20 25 ns tAW Address Set-Up to Write End 12 15 15 18 20 25 ns tHA Address Hold from Write End 0 0 0 0 0 0 ns tSA Address Set-Up to Write Start 0 0 0 0 0 0 ns tPWE WE Pulse Width 12 15 15 18 20 25 ns tSD Data Set-Up to Write End 7 10 10 13 15 20 ns tHD Data Hold from Write End 0 0 0 0 0 0 ns tLZWE WE HIGH to Low Z 3 3 3 3 3 3 ns tHZWE WE LOW to High Z[6] 0 6 0 8 0 10 0 15 0 15 0 18 ns Shaded area contains preliminary information. Notes: 4. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 5. At any given temperature and voltage condition, tHZCS is less than tLZCS for any given device. These parameters are guaranteed by design and not 100% tested. 6. tHZCS and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage. 7. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 4 CYM1836 Switching Waveforms Read Cycle No.1[8, 9] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID 1836–5 Read Cycle No. 2[8, 10] tRC CS tACS OE tHZOE tHZCS tDOE tLZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID DATA OUT tLZCS 1836–6 Write Cycle No.1 (WE Controlled)[7] tWC ADDRESS tSCS CS tAW tHA tSA tPWE WE tSD DATA IN DATA VALID tHZWE DATA OUT tHD tLZWE HIGH IMPEDANCE DATA UNDEFINED 1836–7 Notes: 8. WE is HIGH for read cycle. 9. Device is continuously selected, CS = VIL and OE= VIL. 10. Address valid prior to or coincident with CS transition LOW. 5 CYM1836 Switching Waveforms (continued) Write Cycle No. 2 (CS Controlled)[7, 11] tWC ADDRESS tSA tSCS CS tAW tHA tPWE WE tSD DATA IN tHD DATA VALID tHZWE HIGH IMPEDANCE DATA OUT DATA UNDEFINED 1836–8 Note: 11. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. Truth Table CSN WE OE Input/Outputs Mode H X X High Z Deselect/Power-Down L H L Data Out Read L L X Data In Write L H H High Z Deselect 6 CYM1836 Ordering Information[12] Speed (ns) 15 20 25 30 35 45 Package Name Ordering Code Package Type CYM1836PM–15C PM03 64-Pin SIMM Module CYM1836PZ–15C PZ08 64-Pin ZIP Module CYM1836PY–15C PM08 64-Pin Gold SIMM Module CYM1836P8–15C PM04 72-Pin Gold SIMM Module CYM1836PM–20C PM03 64-Pin SIMM Module CYM1836PZ–20C PZ08 64-Pin ZIP Module CYM1836PY–20C PM08 64-Pin Gold SIMM Module CYM1836P8–20C PM04 72-Pin Gold SIMM Module CYM1836PM–25C PM03 64-Pin SIMM Module CYM1836PZ–25C PZ08 64-Pin ZIP Module CYM1836PY–25C PM08 64-Pin Gold SIMM Module CYM1836P8–25C PM04 72-Pin Gold SIMM Module CYM1836PM–30C PM03 64-Pin SIMM Module CYM1836PZ–30C PZ08 64-Pin ZIP Module CYM1836PY–30C PM03 64-Pin Gold SIMM Module CYM1836P8–30C PM04 72-Pin Gold SIMM Module CYM1836PM–35C PM03 64-Pin SIMM Module CYM1836PZ–35C PZ08 64-Pin ZIP Module CYM1836PY–35C PM03 64-Pin Gold SIMM Module CYM1836P8–35C PM04 72-Pin Gold SIMM Module CYM1836PM–45C PM03 64-Pin SIMM Module CYM1836PZ–45C PZ08 64-Pin ZIP Module CYM1836PY–45C PM03 64-Pin Gold SIMM Module CYM1836P8–45C PM04 72-Pin Gold SIMM Module Operating Range Commercial Commercial Commercial Commercial Commercial Commercial Shaded area contains preliminary information. Note: 12. 64-pin SIMM suitable for use in angled SIMM applications. Document #: 38–M–00050–D Package Diagrams 64-Pin SIMM Module PM03 3.855 MAX. 128KX8 .397/.403 . 200 MAX. 3.580/3.588 124/.126 DIA. 2 PLCS 128KX8 128KX8 128KX8 .595 MAX. .245/.255 .061/.063 R PIN 1 .075/.085 .249/.251 7 .135 REF. CYM1836 Package Diagrams (continued) 72-Pin Plastic SIMM Module PM04 64-Pin ZIP Module PZ08 © Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.