CDP1853, CDP1853C N-Bit 1 of 8 Decoder March 1997 Features Description • Provides Direct Control of Up to 7 Input and 7 Output Devices The CDP1853 and CDP1853C are 1 of 8 decoders designed for use in general purpose microprocessor systems. These devices, which are functionally identical, are specifically designed for use as gated N-bit decoders and interface directly with the 1800-series microprocessors without additional components. The CDP1853 has a recommended operating voltage range of 4V to 10.5V, and the CDP1853C has a recommended operating voltage range of 4V to 6.5V. • CHIP ENABLE (CE) Allows Easy Expansion for Multilevel I/O Systems Ordering Information PACKAGE TEMP. RANGE 5V 10V -40oC to +85oC CDP1853CE PDIP Burn-In SBDIP to +85oC Burn-In When CHIP ENABLE (CE) is high, the selected output will be true (high) from the trailing edge of CLOCK A (high-to-low transition) to the trailing edge of CLOCK B (high-to-low transition). All outputs will be low when the device is not selected (CE = 0) and during conditions of CLOCK A and CLOCK B as shown in Figure 2. The CDP1853 inputs N0, N1, N2, CLOCK A, and CLOCK B are connected to an 1800-series microprocessor outputs N0, N1, N2, TPA, and TPB respectively, when used to decode I/O commands as shown in Figure 5. The CHIP ENABLE (CE) input provides the capability for multiple levels of decoding as shown in Figure 6. CDP1853E E16.3 CDP1853CEX -40oC PKG. NO. - E16.3 CDP1853CD CDP1853D D16.3 CDP1853CDX - D16.3 The CDP1853 can also be used as a general 1 of 8 decoder for I/O and memory system applications as shown in Figure 4. The CDP1853 and CDP1853C are supplied in hermetic 16-lead dual-in-line ceramic (D suffix) and plastic (E suffix) packages. Pinout CDP1853 Functional Diagram 16 LEAD DIP TOP VIEW CLK A 1 N0 2 N1 3 4 N0 16 VDD 2 5 6 15 CLK B 14 N2 OUT 0 4 13 CE OUT 1 5 12 OUT 4 OUT 2 6 11 OUT 5 OUT 3 7 10 OUT 6 VSS 8 9 OUT 7 N1 N2 3 1 OF 8 DECODER 7 12 11 14 10 9 EN CE 1 TRUTH TABLE OUT 0 CE CL A CL B EN 1 0 0 Qn-1† 1 0 1 1 1 1 0 0 1 1 1 1 0 X X 0 OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 13 Qn CLOCK A (TPA) 15 CLOCK B (TPB) N2 N1 N0 EN 0 1 2 3 4 5 6 7 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 1 1 1 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 0 1 1 0 0 0 0 0 1 0 0 1 1 0 1 0 0 0 0 0 0 1 0 1 1 1 1 0 0 0 0 0 0 0 1 X X X 0 0 0 0 0 0 0 0 0 FIGURE 1. 1 = High level, 0 = Low level, X = Don’t care † Qn-1 = Enable remains in previous state. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 4-35 File Number 1189.2 CDP1853, CDP1853C Absolute Maximum Ratings Thermal Information DC Supply Voltage Range, (VDD) (All voltage values referenced to VSS terminal) CDP1853 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V CDP1853C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, any One Input . . . . . . . . . . . . . . . . . . . . . . . . .±10mA Thermal Resistance (Typical) θJA (oC/W) θJC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 85 N/A SBDIP Package . . . . . . . . . . . . . . . . . . 85 22 Operating Temperature Range (TA) Ceramic Packages (D Suffix Types) . . . . . . . . . . -55oC to +125oC Plastic Packages (E Suffix Types) . . . . . . . . . . . . . -40oC to +85oC Storage Temperature Range (TSTG) . . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering). . . . . . . . . . . . . . . . . . +265oC At distance 1/16 ± 1/32 In. (1.59 ± 0.79mm) from case for 10s max CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Static Electrical Specifications At TA = -40 to +85oC, Unless Otherwise Specified CONDITIONS LIMITS CDP1853 VO (V) VIN (V) VDD (V) MIN (NOTE1) TYP MAX MIN (NOTE1) TYP MAX UNITS - - 5 - 1 10 - 5 50 µA - - 10 - 10 100 - - - µA 0.4 0, 5 5 1.6 3.2 - 1.6 3.2 - mA 0.5 0, 10 10 2.6 5.2 - - - - mA 4.6 0, 5 5 -1.15 -2.3 - -1.15 -2.3 - mA 9.5 0, 10 10 -2.6 -5.2 - - - - mA - 0, 5 5 - 0 0.1 - 0 0.1 V - 0, 10 10 - 0 0.1 - - - V - 0, 5 5 4.9 5 - 4.9 5 - V - 0, 10 10 9.9 10 - - - - V 0.5, 4.5 - 5 - - 1.5 - - 1.5 V 1, 9 - 10 - - 3 - - - V 0.5, 4.5 - 5 3.5 - - 3.5 - - V 1, 9 - 10 7 - - - - - V Any Input 0, 5 5 - - ±1 - - ±1 µA 0, 10 10 - - ±1 - - - µA 0, 5 0, 5 5 - 50 100 - 50 100 µA 0, 10 0, 10 10 - 150 300 - - - µA CIN - - - - 5 7.5 - 5 7.5 pF COUT - - - - 10 15 - 10 15 pF PARAMETER Quiescent Device Current Output Low Drive (Sink) Current Output High Drive (Source) Current Output Voltage Low Level (Note 2) Output Voltage High Level Input Low Voltage Input High Voltage Input Leakage Current Operating Current (Note 3) Input Capacitance Output Capacitance CDP1853C IL IOL IOH VOL VOH VIL VIH IIN IDD1 NOTES: 1. Typical values are for TA = +25oC and nominal voltage. 2. IOL = IOH = 1µA 3. Operating current measured in a CDP1802 system at 2MHz with outputs floating. Spec Number 4-36 CDP1853, CDP1853C Recommended Operating Conditions At TA = Full Package Temperature Range. For maximum reliability, operating conditions should be selected so that operation is always within the following ranges: LIMITS CDP1853 PARAMETER Supply Voltage Range Recommended Input Voltage Range Dynamic Electrical Specifications CDP1853C MIN MAX MIN MAX UNITS 4 10.5 4 6.5 V VSS VDD VSS VDD V At TA = -40 to +85oC, VDD = ±5%, VIH = 0.7VDD, VIL = 0.3VDD, tR, tF = 20ns, CL = 100pF, Unless Otherwise Specified LIMITS CDP1853 PARAMETER CDP1853C VDD (V) MIN TYP MAX MIN TYP MAX UNITS 5 - 175 275 - 175 275 ns 10 - 90 150 - - - ns 5 - 225 350 - 225 350 ns 10 - 120 200 - - - ns 5 - 200 300 - 200 300 ns 10 - 100 150 - - - ns 5 - 175 275 - 175 275 ns 10 - 90 150 - - - ns 5 - 50 75 - 50 75 ns 10 - 25 50 - - - ns 5 - 50 75 - 50 75 ns 10 - 25 50 - - - ns Propagation Delay Time: CE to Output N to Output Clock A to Output Clock B to Output tEOH, tEOL tNOH, tNOL tAO tBO Minimum Pulse Widths: Clock A Clock B ns tCACA tCBCB NOTES: 1. Maximum limits of minimum characteristics are the values above which all devices function. 2. Typical values are for TA = +25oC and nominal voltages. 4-37 CDP1853, CDP1853C Timing Diagrams tEO tEO tNO CE N OUTPUT OUTPUT FIGURE 2A. CE TO OUTPUT (0-7) DELAY TIME tNO FIGURE 2B. N LINES TO OUTPUT (0-7) DELAY TIME tCACA CLOCK A tCBCB tAO tBO CLOCK B OUTPUT OUTPUT FIGURE 2C. CLOCK A TO OUTPUT (0-7) DELAY TIME FIGURE 2D. CLOCK B TO OUTPUT (0-7) DELAY TIME FIGURE 2. PROPAGATION DELAY TIME DIAGRAMS OUT 0 TPA A N0 OUT 1 TPB B N1 OUT 2 CE C N2 OUT 3 CHIP ENABLE CE OUT 4 CLOCK B OUT 5 CLOCK A OUT 6 EN (NOTE 1) VDD OUTPUT OUT 7 NOTE 1. OUTPUT ENABLED WHEN EN = HIGH INTERNAL SIGNAL SHOWN FOR REFERENCE ONLY (SEE FIGURE 1) FIGURE 3. TIMING DIAGRAM FIGURE 4. N-BIT DECODER USED AS A 1 OF 8 DECODER 4-38 CDP1853, CDP1853C TPA TPB CDP1800 SERIES N0 N1 N2 TPB MRD VDD CLOCK A CLOCK B CE N0 N1 N2 CDP1853 0 1 2-6 7 READ VIA 6F INSTRUCTION LOAD VIA 67 INSTRUCTION DATA AVAILABLE CS1 CS2 CDP1852 OUTPUT DATA PORT 7 SR MODE TPB CS1 CS2 CDP1852 INPUT PORT 7 STROBE MODE VDD 5 CDP1852 INPUT AND OUTPUT PORTS DATA CLOCK READ VIA 69 INSTRUCTION CS2 CS1 CDP1852 OUTPUT PORT 1 SR TPB MODE LOAD VIA 61 INSTRUCTION AVAILABLE CS1 CS2 CDP1852 INPUT PORT 1 STROBE MODE VDD DATA CLOCK 7 OUTPUT PORTS 7 INPUT PORTS FIGURE 5. N-BIT DECODER IN A ONE-LEVEL I/O SYSTEM NO, N1, N2 CDP1800 SERIES TPA TPB TPA CDP1853 I DECODED “61” INSTRUCTION NOTE: SYSTEM SHOWN WILL SELECT UP TO 56 INPUT AND 48 OUTPUT PORTS. WITH ADDITIONAL DECODING THE TOTAL NUMBER OF INPUT AND OUTPUT PORTS CAN BE DATA BUS FURTHER EXPANDED. MRD BUS CL CSI CS2 CDP1852 INTERCONNECTED AS IN FIGURE 4 NO, N1, N2 CLOCK A CLOCK B CE CDP1853 “62-6F” INST I/O 7 INPUT 6 OUTPUT PORTS NO, N1, N2 CLOCK A CLOCK B CE CDP1853 “62-6F” INST I/O 7 INPUT 6 OUTPUT PORTS CLOCK A CLOCK B CE CDP1853 “62-6F” INST I/O 7 INPUT 6 OUTPUT PORTS SECTIONS 3-7 NO, N1, N2 FIGURE 6. TWO-LEVEL I/O USING CDP1853 AND CDP1852 4-39 CDP1853, CDP1853C All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 4-40 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029