Ordering number : ENA0646 Monolithic Linear IC LA73033M I2C bus control (excluding standby control and RGB through control) Overview This LA73033M is DVD recorder video signal input SW & output driver. Functions [SW side] • Composite signal five-input SW and S signal three-input SW • Keyed clamp • Component signal or RGB signal 1 input • 0dB/ 6dB amplifier • AGC amplifier (composite and Y signal only) • LPF for removal of 13.5MHz clock • Composite output/ Y output changeover switch • Compatible with standby (two types) • C.SYNC & V.SYNC output [Driver side] • Six-channel input & six-channel output of composite signal & S signal & component or RGB signal • Clamp (keyed clamp for Cb and Cr) • 6dB/ 9dB amplifier amplifier • LPF for removal of 27MHz/ 54MHz clock • Output mute (three types) • 75Ω driver (two drives possible) • Through changeover of RGB signal from the SW side • Y/ C-MIX • DC output for S1/ S2 • SCART-RGB/ YC changeover SW Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 71807 TI PC B8-7592, No.0646-1/24 LA73033M Specifications Maximum Ratings at Ta = 25°C Parameter Symbol Maximum supply voltage Conditions Ratings VCC max Allowable power dissipation Unit 7.0 Ta ≤ 75°C * Mounted on a board Pd max 1200 V mW Operating temperature Topg -20 to +75 °C Storage temperature Tstg -40 to +150 °C * Mounted on a board : 114.3×76.1×1.6mm3, glass epoxy board. Recommended Operating Conditions at Ta = 25°C Parameter Symbol Recommended supply voltage VCC Operating supply voltage range VCC opg Input pin voltage application range Conditions Ratings Unit 5.0 VCC opg +0.3 ≤ 7V VIN V 4.75 to 5.25 V -0.3 to VCC opg +0.3 V Package Dimensions unit : mm (typ) 3255 17.2 0.8 14.0 60 41 40 80 21 14.0 17.2 61 1 0.65 0.25 20 0.15 (2.7) 0.1 3.0max (0.83) SANYO : QFP80(14X14) No.A0646-2/24 Gain at 6dB RGB output clmap voltage voltage Component output pedestal Y output clamp voltage voltage Chroma output center voltage Composite output clamp VIN79 VIN11 VIN9 VIN1 VIN73 G23H G27H G29H G25H G25H G27H RC29 VIN13 VIN7 VIN1 VIN73 RC25 G23H VIN11 VIN9 PC25 RC23 VIN9 PC23 VIN77 VIN75 VIN79 VIN7 VIN5 VIN3 VIN19 VIN21 VIN13 VIN15 VIN17 Point VIN1 VIN11 C27 C25 C23 ICC13 Current drain 1 at RGB standby ICC11 ICC12 Current drain at standby Symbol Current drain 1 Parameter SG8 SG5 SG8 SG8 SG5 SG6 SG5 SG8 SG5 SG8 SG8 SG6 SG6 SG5 SG1 SG2 SG3 Signal Freq Input signal Mag T27 VCC1 VCC1 VCC1 Point Out T25 T23 T27 T27 T27 T27 700mVp-p T29 1Vp-p 700mVp-p T25 700mVp-p T23 1Vp-p 714mVp-p T25 1Vp-p 700mVp-p T29 1Vp-p 700mVp-p T25 700mVp-p T23 1Vp-p 1Vp-p 1Vp-p 1Vp-p 714mVp-p T25 1Vp-p Electrical Characteristics at Ta = 25°C, VCC = 5.0V Measure GAIN for input of each output Measure the output pedestal clamp voltage Measure the output pedestal clamp voltage voltage) Measure the output clamp voltage (sink chip voltage) Measure the output DC voltage (center voltage) Measure the output clamp voltage (sink chip control Current flowing through VCC1 at EXT-RGB control Current flowing through VCC1 at standby Current flowing through VCC1 at no signal Test Condition 5.5 1.15 2.4 0.7 2.2 0.7 11 9 58 min 6 1.25 2.5 0.8 2.4 0.8 14 11 73 typ Spec 6.5 1.35 2.6 0.9 2.7 0.9 17 13 88 max dB V V V V V mA mA mA unit 330 330 330 330 330 330 330 330 330 R1 0 0 0 0 0 0 0 3 3 0 V18 0 0 0 0 0 0 0 3 0 0 3.5 3.5 3.5 3.5 3.5 3.5 3.5 3.5 V38 V30, V35 Control voltage SW1 00000000 00000000 10101010 11001010 00000000 00000000 00000000 00000000 00000000 00000000 Continued on next page. 00101100 01001000 01000100 01001010 00100100 00000000 10000100 00000100 00000000 01100100 00000000 00000000 10000100 01000100 00000000 01100100 00000000 00000000 01000100 00000000 10001010 00000000 00000000 SW2 01101010 01001010 01000010 2 I C bus data (MSB-LSB) LA73033M No.A0646-3/24 VIN11 VIN9 VIN1 VIN73 F27 F23 F27 VIN1 VIN73 F27L1 F23L1 F27L1 (with LPF) 1Vp-p 1Vp-p 1Vp-p T27 T27 T27 T29 T27 1Vp-p T27 1Vp-p T27 1Vp-p T27 1Vp-p T27 1Vp-p T27 700mVp-p T25 T27 5MHz 5MHz 5MHz 5MHz SG9 SG9 SG1 SG9 VIN11 VIN9 VIN1 VIN73 F23L2 F27L2 F29L2 F25L2 700mVp-p T23 5MHz SG1 T27 VIN79 1Vp-p T27 700mVp-p T29 1Vp-p 1Vp-p 714mVp-p T25 F27L2 5MHz 5MHz (with LPF) SG2 F25L2 4.5MHz 700mVp-p T29 4.5MHz 4.5MHz 700mVp-p T25 4.5MHz 700mVp-p T23 4.5MHz 4.5MHz 714mVp-p T25 4.5MHz 10MHz 700mVp-p T29 10MHz 10MHz 700mVp-p T25 10MHz 700mVp-p T23 10MHz F23L2 SG3 2Vp-p 1.4Vp-p T25 10MHz 714mVp-p T25 10MHz 1.4Vp-p 1.4Vp-p f characterics of gain SG9 SG1 SG9 SG9 SG1 SG2 SG3 SG9 SG1 SG9 SG9 SG1 SG2 SG3 SG5 SG5 SG8 SG5 SG8 5MHz change rate of F29L1 VIN13 VIN7 VIN11 VIN9 F25L1 f characterics of gain F25L1 VIN79 F23L1 4.5MHz change rate of F29 VIN13 VIN7 VIN79 F25 f characteristics of gain F25 VIN13 VIN7 F23 VA27M VA23M G29H VIN13 VIN79 VIN1 VIN73 G27H G25H T23 VIN11 VIN9 G23H SG8 T27 SG5 VIN79 G27L 2Vp-p 1.428Vp-p T25 SG6 G25L calculates the change rate for gain at 100kHz. Measure gain for input of each output and calculates the change rate for gain at 100kHz. Measure gain for input of each output and calculates the change rate for gain at 100kHz. Measure gain for input of each output and changeable. Measure V30 and V35 where the output gain -1 -0.5 -0.5 2 min -0.5 T27 Measure GAIN for input of each output Point Mag Test Condition 2Vp-p SG5 Freq Signal Point Out VIN13 VIN7 Input signal G23L Symbol 10MHz change rate for AGC-AMP control voltage Gain at 0dB Parameter Continued from preceding page. -0.3 -0.2 -0.1 3.5 0 typ Spec 0.5 0.5 0.5 5 0.5 max dB dB dB V dB unit R1 1k 1k 330 330 330 0 0 0 0 0 V18 0 0 0 0 0 3.5 3.5 3.5 VA27M VA23M 3.5 V38 V30, V35 Control voltage SW1 SW2 00000000 Continued on next page. 00000000 00111100 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 10000000 10000000 00000000 00000000 00000000 00000000 01011000 01010100 01011010 00111100 01011000 01010100 01011010 00101100 01001000 01000100 01001010 01001000 01001010 00100000 01000000 01000000 01000010 2 I C bus data (MSB-LSB) LA73033M No.A0646-4/24 VIN11 VIN9 VIN1 VIN73 F27L3 VIN11 VIN9 VIN1 VIN73 H27 H23 H27 T27 T27 T27 T27 700mVp-p T23 700mVp-p T25 T27 5MHz 5MHz 5MHz 5MHz SG9 SG9 SG1 SG9 VIN11 VIN9 VIN1 VIN73 H23 H27 V36H V36L V37H V37L C.SYNC output H voltage C.SYNC output L voltage C.SYNC2 output H voltage C.SYNC2 output L voltage H29 H25 5MHz SG1 VIN79 VIN13 VIN79 1Vp-p SG5 1Vp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p SG5 SG5 T27 T37 T37 T36 T36 700mVp-p T29 1Vp-p 1Vp-p SG5 SG5 VIN13 VIN79 SG5 VIN79 SG5 VIN79 VIN13 SG5 VIN13 T27 714mVp-p T25 H27 5MHz 1Vp-p 700mVp-p T29 1Vp-p 700mVp-p T25 700mVp-p T23 1Vp-p (with LPF) SG2 5MHz 1Vp-p 714mVp-p T25 H25 5MHz 5MHz 5MHz 5MHz 5MHz 5MHz 5MHz H23 SG3 1Vp-p 13.5MHz 700mVp-p T29 13.5MHz 13.5MHz 700mVp-p T25 13.5MHz 700mVp-p T23 (secondary distortion) SG9 SG1 SG9 SG9 SG1 SG2 SG3 SG9 SG1 SG9 SG9 Output drive capacity 1 H29 VIN13 VIN7 VIN79 H25 (secondary distortion) H25 VIN13 VIN7 H23 Output drive capacity 1 F29L3 F25L3 F23L3 T27 1Vp-p SG1 13.5MHz 13.5MHz 714mVp-p T25 SG2 F27L3 VIN79 F25L3 (with LPF) T27 SG3 f characteristics of gain Point Mag 1Vp-p Freq 13.5MHz Signal Out Point Input signal VIN13 VIN7 F23L3 Symbol 13.5 MHz change rate of Parameter Continued from preceding page. Connect 10kΩ between this output and VCC. Connect 10kΩ between this output and VCC. Connect 10kΩ between this output and VCC. Connect 10kΩ between this output and VCC. distortion of output. connection and measure the secondary Connect the load of 1kΩ to the output via C distortion of output. connection and measure the secondary Connect the load of 330Ω to the output via C calculates the change rate for gain at 100kHz. Measure gain for input of each output and Test Condition 0 4.75 0 4.75 min 0.3 5 0.3 5 -45 -45 -41 typ Spec 0.6 5.25 0.6 5.25 -35 -35 -30 max V V V V dB dB dB unit 330 330 1k R1 0 0 0 0 0 0 0 V18 0 0 0 0 0 0 0 3.5 3.5 3.5 3.5 3.5 3.5 3.5 V38 V30, V35 Control voltage SW1 SW2 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Continued on next page. 01001000 01001010 01001000 01001010 01001000 01001010 01001000 00000000 00000000 00111100 01001010 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 01011000 01010100 01011010 00101100 01001000 01000100 01001010 00111100 01011000 01010100 01011010 2 I C bus data (MSB-LSB) LA73033M No.A0646-5/24 W36 W36V C.SYNC output pulse width C.SYNC threshold level SG5 SG5 VIN79 SG5 VIN13 SG5 VIN79 Signal VIN13 Point Freq Input signal 1Vp-p 1Vp-p 1Vp-p 1Vp-p Mag VIN13 VIN79 VIN13 VIN79 VIN13 VIN79 ADP23 VIN79 VIN77 CT27 SN23 SN27 (with LPF) SN27 VIN13 VIN79 VIN13 VIN79 VIN7 VIN5 CT25 SN23 VIN13 VIN15 CT23 ADP27 DP27 DP23 ADG27 DG27 ADG23 Point VIN13 VIN79 DG23 Symbol Video S/ N ratio Video S/ N ratio Crosstalk DP DG Parameter Design guarantee items Freq Mag SG5 SG5 SG5 SG5 1Vp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p 714mVp-p SG5 4MHz SG2 714mVp-p SG5 4MHz SG2 1Vp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p SG5 3.58MHz 3.58MHz 3.58MHz 3.58MHz 3.58MHz 3.58MHz 3.58MHz 3.58MHz SG5 SG7 SG7 SG7 SG7 SG7 SG7 SG7 SG7 Signal Input signal (Note) The C. SYNC2 threshold level is 12 IRE at 6dB and 12.8 IRE at 0dB . Symbol Parameter Continued from preceding page. T27 T27 T27 T27 T27 T25 T27 T27 T27 T27 T27 T27 T27 T27 T27 Point Out T36 T36 Point Out bands is expressed in dB. S/ N in the HPF100kHz and LPF 10MHz bands is expressed in dB. S/ N in the HPF100kHz and LPF 10MHz of selected signal output. selected signal output is specified by the value non-selected input signal is carried on the The magnitude of crosstalk in which the When AGC amplifier is used relative to that on the black level Difference of the phase on the white level When AGC amplifier is used relative to that on the black level. Ratio of the amplitude on the white level Test Condition input SYNC is reduced. pulse width becomes 1.3-folds or more as the The value of input SYNC at which the output Output pulse width Test Condition -1 -1 -2 -2 min 7.5 3.2 min -65 -70 -60 -60 -60 1.2 1 1 1 typ Spec 11.5 4.2 typ Spec -60 -65 -55 -55 -55 2 1.5 2 2 max 15.5 5.2 max dB dB dB dB dB deg deg % % unit IRE μs unit 1k 330 330 330 330 1k 1k R1 R1 0 0 0 0 0 0 0 0 0 3.5 3.5 V38 V30, V35 0 0 0 0 0 0 0 3.5 3.5 3.5 3.5 3.5 VA27M VA23M 3.5 VA27M VA23M 3.5 V38 V30, V35 Control voltage V18 0 0 V18 Control voltage SW1 SW1 01011000 01011010 01001000 01001010 01001000 01000100 01001010 01011000 01011010 01011000 01011010 01011000 01011010 01011000 01011010 2 00000000 00000000 00000000 00000000 SW2 00000000 00000000 00000000 00000000 00000000 00000000 00000000 10000000 10000000 00000000 00000000 10000000 10000000 00000000 00000000 SW2 I C bus data (MSB-LSB) 01001000 01001010 01001000 01001010 2 I C bus data (MSB-LSB) LA73033M No.A0646-6/24 T56 T68 T65 T63 1Vp-p 709mVp-p 507mVp-p 709mVp-p SG6 SG3 SG2 SG1 VIN45 VIN51 VIN53 VIN39 VIN41 VIN43 VIN45 VIN51 VIN53 G60L G56L G68H G63H G60H G56H VIN43 VIN45 VIN51 VIN53 G65L G63L G60L G56L (composite/ S) Output gain ratio SG6 SG3 SG2 SG1 VIN53 G56H Δ68/65 VIN39 Δ68/63 VIN41 Δ65/63 VIN43 G58H SG1 SG6 SG5 VIN43 VIN45 VIN51 SG2 G63H G65H in two-drive mode SG3 SG6 SG6 SG5 SG1 SG2 SG3 SG6 SG6 SG5 SG6 G60H VIN39 VIN41 G68H Gain at 9dB for one drive G58L VIN39 VIN41 G68L in two-drive mode G58H G65H G58L 709mVp-p 507mVp-p 709mVp-p 709mVp-p 709mVp-p 709mVp-p 709mVp-p 507mVp-p 709mVp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p 714mVp-p 1Vp-p 709mVp-p 709mVp-p 709mVp-p 1Vp-p T63 T65 T68 T56 T58 T60 T63 T65 T68 T56 T58 T60 T63 T65 T68 T56 T58 T60 T58 T60 T63 1Vp-p SG1 VIN43 G63L 1Vp-p T65 SG5 T68 1Vp-p VCC2 VCC2 Point 714mVp-p Mag SG2 Freq SG3 Signal VIN39 VIN41 G65L Gain at 6dB for one drive Gain at 9dB for two drives Gain at 6dB for two drives Point Out G68L ICC23 Current drain at RGB standby 2 ICC21 Symbol Current drain 2 Parameter Input signal Calculate the gain ratio of two outputs. Measure gain of each output relative to input Measure gain of each output relative to input Measure gain of each output relative to input Measure gain of each output relative to input control Current flowing through VCC2 at EXT-RGB Current flowing through VCC2 at no signal Test Condition Electrical characteristics at Ta=25°C, unless otherwise specified VCC = 5.0V -5 8.55 5.6 8.55 5.6 18 64 min 0 9.1 6.1 8.9 5.9 22 80 typ Spec 5 9.45 6.4 9.45 6.4 26 96 max % dB dB dB dB mA mA unit 0 0 0 0 0 3 0 V18 0 0 0 0 0 3 0 V38 voltage Control ON ON OFF ON ON ON ON S63 ON OFF ON ON ON ON ON S56 S68, S65, S60, S58, SW DV2 11110000 11110000 00110000 11110000 00110000 00110000 Continued on next page. 00000000 00000000 00000000 00000000 00000000 00000000 DV1 (MSB-LSB) 2 I C bus data LA73033M No.A0646-7/24 F65H f characteristics of GAIN VIN39 VIN41 VIN53 VIN45 VIN51 G58E F58E F56E G60E G58E f characteristics of GAIN at RGB through Gain at RGB standby One drive G56E F60E 10MHz change rate for G56E G60E drive VIN9 VIN11 VIN73 VIN9 VIN11 VIN73 VIN9 VIN11 VIN73 SG8 SG8 SG8 SG9 SG9 SG9 SG8 SG8 SG8 SG4 SG1 SG4 SG4 F56H2 VIN53 Gain at RGB through One characteristics of GAIN 27MHz SG4 SG4 F56L2 27MHz SG4 700mVp-p 700mVp-p 700mVp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p 700mVp-p 700mVp-p 700mVp-p 10MHz 700mVp-p 10MHz 700mVp-p 10MHz 700mVp-p 54MHz 54MHz 54MHz 14MHz 14MHz 14MHz 27MHz SG1 27MHz SG1 F60H2 VIN45 F58H2 VIN51 VIN53 F58L2 characteristics of GAIN 54MHz change rate for f VIN45 VIN51 F60L2 14MHz change rate for f 1Vp-p 1Vp-p 1Vp-p T56 T58 T60 T56 T58 T60 T56 T58 T60 T56 T58 T60 T56 T58 T60 T56 T58 T60 T63 T65 T68 T56 T58 input. Measure gain of each output relative to 100kHz. and calculate the change rate for gain at Measure gain of each output relative to input input. Two-drive mode. Measure gain of each output relative to 100kHz. and calculate the change rate for gain at Measure gain of each output relative to input 100kHz. and calculate the change rate for gain at Measure gain of each output relative to input 100kHz. T60 T63 1Vp-p 1Vp-p 27MHz 714mVp-p 27MHz 7MHz 7MHz 7MHz 7MHz SG1 SG2 SG3 SG4 SG4 SG1 SG1 and calculate the change rate for gain at VIN43 Measure gain of each output relative to input T65 7MHz 714mVp-p SG2 F63H VIN43 F60H1 V 45 IN F58H1 V 51 IN F56H1 V 53 IN F68H 27MHz change rate of F56L1 F58L1 F60L1 F63L F65L f characteristics of GAIN T56 T68 Calculate the gain ratio of two outputs. Test Condition 1Vp-p T58 T60 Point Out 709mVp-p 709mVp-p 7MHz SG6 709mVp-p Mag SG3 SG6 Δ58/56 VIN53 Freq VIN39 VIN41 SG5 Δ60/58 VIN45 Δ60/56 VIN51 F68L Signal Input signal Point Symbol 7MHz change rate for (component) Output gain ratio Parameter Continued from preceding page. 5.6 -0.5 5.6 -2.3 -2 -5 min 5.9 -0.1 6.1 -37 -1.1 -33 -0.8 0 typ Spec 6.4 0.5 6.4 -30 0.1 -25 0.4 5 max dB dB dB dB dB dB dB % unit 3 0 0 0 0 0 0 V18 3 3 3 0 0 0 0 V38 voltage Control ON ON ON ON ON ON ON S63 OFF OFF OFF ON ON ON ON S56 S68, S65, S60, S58, SW DV2 00100000 00100000 00110000 00110000 00110000 00110000 11110000 Continued on next page. 10000000 10000000 00001000 00001000 00000000 00000000 00000000 DV1 (MSB-LSB) 2 I C bus data LA73033M No.A0646-8/24 V43 DC for 4 : 3 Mag 1Vp-p GD56-2 VIN53 VIN39 VIN43 VIN45 DG68 DG60 (progressive) DG DGMIX VIN41 VIN43 DG63 GD60-2 VIN45 GD58-2 VIN51 1Vp-p 1Vp-p 1Vp-p SG2 3.58MHz 286mVp-p Y only 1Vp-p SG7 component SG7 3.58MHz SG7 3.58MHz 1Vp-p 14MHz 714mVp-p 14MHz 714mVp-p 14MHz 7MHz 714mVp-p SG7 3.58MHz SG4 SG4 SG1 SG4 GD56-1 VIN53 group delay at 14MHz 7MHz 714mVp-p 1Vp-p 7MHz 1Vp-p SG4 7MHz 7MHz 714mVp-p 7MHz SG1 SG2 SG3 Freq GD60-1 VIN45 GD58-1 VIN51 GD63 (interlace) VIN39 VIN41 Signal SG1 GD65 group delay at 7MHz f characteristics of Point VIN43 GD68 f characteristcs of Symbol Design guarantee items VLB T68 T60 T63 T68 T56 T58 T60 T56 T58 T60 T63 T65 T68 Point Out T66 T66 T66 T56 V56MD VSQ T60 T58 V58MD DC for LB Parameter Point V60MD Input signal Mag T63 Freq V63MD Signal Out T65 Point Input signal V65MD Symbol DC for SQ MUTE voltage Parameter Continued from preceding page. Test Condition level of each output signal. relative to that of SIN wave on the black amplitude of SIN wave on the white level Calculate the ratio in percentage of the 100kHz of each output Difference in group delay of 14MHz from to 100kHz of each output Difference in group delay of 7MHz relative 5.25V Measure the pin voltage with VCC = 4.75 to Measure the pin voltage. Test Condition -15 -20 min 0 2.05 4.1 2.1 min 1 5 10 typ Spec 0 2.2 4.4 2.5 typ Spec 2 15 20 max 0.35 2.35 4.7 2.9 max % ns ns unit V V V V unit 0 0 0 0 V38 0 0 0 V18 0 0 0 V38 voltage Control 0 0 0 0 V18 voltage Control SW ON ON ON ON S56 ON ON ON S63 ON ON ON S56 S68, S65, S60, S58, ON ON ON ON S63 S68, S65, S60, S58, SW 00110000 00110000 00110000 00110000 00110000 00110000 00110000 00110000 00110000 DV2 Continued on next page. 01000000 00000000 00001000 00000000 DV1 (MSB-LSB) 2 DV2 00110000 I C bus data 00000000 00010000 00100000 00000100 00000001 00000010 DV1 (MSB-LSB) 2 I C bus data LA73033M No.A0646-9/24 Video S/ N ratio Crosstalk DP Parameter Continued from preceding page. VIN45 VIN43 CT63 SG5 SG5 VIN45 SN60 SNMIX VIN43 SG5 SG4 SG4 SG1 SG1 SG2 SG3 SG5 SN63 Mag 1Vp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p 1Vp-p 4MHz 714mVp-p 4MHz 714mVp-p 4MHz 4MHz 4MHz 714mVp-p 4MHz SG2 3.58MHz 286mVp-p Y only SG7 1Vp-p component SG7 3.58MHz SG7 3.58MHz VIN39 VIN43 VIN53 Freq SG7 3.58MHz Signal SN68 CT56 CT58 CT60 VIN45 VIN51 VIN39 VIN41 CT65 CT68 DPMIX VIN41 VIN43 DP63 DP60 Point VIN39 VIN43 DP68 Symbol Input signal T68 T60 T63 T68 T56 T58 T60 T63 T65 T68 T68 T60 T63 T68 Point Out express it in dB. noise meter (LPF 10MHz, HPF 100kHz) and Measure the S/ N ratio of output signal with a outputs. relative to the 4MHz amplitude of other of non-input route and calculate its ratio Measure the 4MHz component of the otput white level. signal relative to that of SIN wave on the wave on the black level of each output Measure the difference in phase of the SIN Test Condition -1 min -73 -79 -60 0.5 typ Spec -71 -77 -55 1 max dB dB dB deg unit 0 0 0 0 V18 0 0 0 0 V38 voltage Control ON ON ON ON S63 ON ON ON ON S56 S68, S65, S60, S58, SW 01000000 00000000 00000000 01000000 00000000 DV1 00110000 00110000 00110000 00110000 00110000 DV2 (MSB-LSB) 2 I C bus data LA73033M No.A0646-10/24 LA73033M 60 GND (CN2) 53 64 + 10kΩ 65 66 67 + 68 N.C 47 N.C 46 45 44 C.IN Y.IN Y2.IN/R.IN N.C 48 GND (CS1) 42 41 43 pedestal CLAMP 39 75Ω driver LPF1 LPF2 6dB/9dB AMP pedestal CLAMP CLAMP 75Ω driver LPF1 LPF2 6dB/9dB AMP pedestal CLAMP CLAMP 75Ω driver LPF1 LPF2 6dB/9dB AMP 75Ω driver LPF1 6dB/9dB AMP 75Ω driver LPF1 75Ω driver LPF1 6dB AMP 6dB AMP 69 CV.IN 38 EXT-RGB_SW 37 36 35 Y/C MIX 34 6dB/9dB AMP 33 CTL LOGIC SERIAL DECORDER 0dB/6dB AMP SYNC SEP LPF N.C 71 CLP PULSE GEN synctip CLAMP V.SEP 31 30 pedestal CLAMP 72 29 73 28 LPF LPF LPF 74 75 AGCAMP 0dB/3dB Y4.IN 0dB/6dB AMP N.C 76 SYNC SEP SYNC SEP 27 SYNC LPF SYNC LPF 26 0dB/6dB AMP AGCAMP 0dB/3dB 0dB/6dB AMP SYNC SELECT SYNC SELECT 25 77 24 Y3.IN pedestal pedestal CLAMP CLAMP synctip synctip synctip synctip synctip CLAMP CLAMP CLAMP CLAMP CLAMP CLAMP CLAMP synctip synctip synctip synctip CLAMP CLAMP CLAMP CLAMP N.C 78 AGCCTL2 VCC (IC) CLAMP 32 pedestal CLAMP CLAMP CSYNC.OUT CLAMP 6dB/9dB AMP 6dB AMP CSYNC2.OUT CLAMP S1/S2 PC_OUT N.C 70 B.IN VCC (Y) 50 N.C 49 VCC (CS1) REG2 40 + C.OUT VCC (B) Cr.IN/G.IN Cb.IN/B.IN Cb.OUT/B.OUT 55 GND (CN1) 52 51 SYNC SEP + 63 GND (CN3) GND (CS4) 58 N.C 54 VCC (CN1) 62 Y1.OUT CV.OUT/Y.OUT 59 GND + (CN3) 57 56 VCC (CN2) 61 VCC (CN2) GND (CS2) GND + (CN4) Cr.OUT/G.OUT + Y2.OUT/R OUT/C.OUT Block Diagram and Test Circuits 23 79 22 Y2.IN N.C 80 SCLK SDATA GND (IC) AGCCTL1 B_OUT GND (B) Y.OUT/CV.OUT GND (Y) C.OUT/Cr.OUT/R.OUT GND (C) CV.OUT/Cb.OUT/G.OUT GND (CV) 21 REG1 VCC (CV) 13 14 GND (SY) 15 16 17 18 19 CV6.IN 20 + CV5.IN 12 STAND.BY VCC (SY) 11 N.C 10 CV4.IN VCC (C) 9 CV3.IN 8 CV2.IN 7 C2.IN C3.IN C4.IN 6 Cb.IN/G.IN 5 Cr.IN/R.IN 4 N.C 3 N.C 2 N.C Y.IN/CV.IN 1 No.A0646-11/24 LA73033M Pin Functions Pin No. 13 Pin name CV2.IN 15 CV3.IN 17 CV4.IN 19 21 1 79 I/0 I Impe dance DC voltage Pin Explanation Clamp 1.5V at 0dB Recommended clamp capacitor = Form 2.1V at 6dB 0.1μF. 1.5V at AGC For the selected pin, keyed clamp 1.5V at no selection is applied to the input so that the 1.5V at no signal clamp voltage of the output signal CS-REC : 1.5V becomes constant when the CV5.IN CV6.IN signal is provided. Diode clamp is Y1.IN applied to the input when there is / CV.IN no signal. When no pin is Input/Output form VCC VCC VCC CLAMP PULSE 200Ω IN CLAMP PULSE 0.5μA 100kΩ clamp is applied to the input 77 Y3.IN regardless of whether or not the 75 Y4.IN signal is provided. 7 C2.IN I 10kΩ 2.9V VCC 19kΩ selected and at CS-REC, diode Y2.IN VCC 50μF Recommended capacitor = 0.1μF. VCC DC is overlapped over the signal VCC VCC through external C connection regardless of whether there is a 5 signal or the pin is selected or C3.IN AMP-GAIN in the mode other than 10kΩ IN CS-REC. 200Ω 3 11 C4.IN Cb.IN 50μF I G.IN 9 73 Clamp For component Recommended clamp capacitor = Form 3.2V at 0dB 0.1μF. For the selected signal, 3.0V at 6dB keyed clamp is applied to the For RGB input so that the clamp voltage of Cr.IN 2.2V at 0dB output signal becomes constant R.IN 2.5V at 6dB when there is a signal to pin 1. For RGB through Diode clamp is applied to the input 2.3V when there is no signal at pin 1 or 1.2V at no selection when the pin is not selected. For 1.2V at no signal to RGB through, feedback clamp is pin 1 applied from the output to the B.IN VCC VCC VCC 100μF VCC VCC 19kΩ CLAMP PULSE 200Ω IN 50μF CLAMP 100kΩ PULSE 0.5μA input. 23 25 CV.OUT 0.8V for CV/ Y The signal that has been selected Cb.OUT 2.5V for component and keyed clamped (excluding G.OUT 1.25V for RGB chroma) is amplified and output For chroma output from the emitter follower. C.OUT 2.2V at 0dB The constant current of emitter Cr.OUT 2.4V at 6dB follower is 2.5mA when the built-in R.OUT O 4.5Ω LPF is selected and 7.5mA when it is not selected. 27 VCC VCC 40Ω OUT Y.OUT CV.OUT 29 B.OUT Continued on next page. No.A0646-12/24 LA73033M Continued from preceding page. Pin No. 18 Pin name STAND I/0 I Impe dance 17GΩ -BY-SW DC voltage Pin Explanation Hi : 3.3V Normal mode when pins 18 and Lo : 0V 38 are “L.” RGB through mode Input/Output form VCC when pin 18 is “L” and pin 38 is “H.” RGB standby mode when 100μF pins 18 and 38 are “H.” CS-REC mode when pin 18 is “H” and pin 38 38 is “L.” EXT -RGB IN -SW 8kΩ 50kΩ 20 SW-REG O 880Ω -FILT With pin 18 = L, Output pin for regulator voltage in Pin 20 : 2.5V IC. S/ N improvement measures Pin 40 : 2.0V recommended by inserting a 1With pin 18 = H, capacitor of about 470μF between Pin 20 : 0V this pin and GND. The amplifier Pin 40 : 0V reference voltage on the SW side VCC 10pF is based on the regulator voltage 40 DV-REG of pin 20 and that on the driver -FILT side is based on the regulator OUT voltage of pin 40. 10kΩ 12kΩ 30 AGCCTL1 I 128MΩ (CV) Hi : 5V Pin to control gain of composite Lo : 2V and Y signals when AGC-AMP is Center : 3.3V used. To suppress crosstalk, it is VCC 10kΩ VCC VCC recommended to insert a noise suppressing capacitor near the pin between the pin and GND. 35 IN 500Ω AGCCTL2 (Y) 20μF 36 C.SYNC OUT I 480Ω Hi : 5V Composite sink output pin Lo : 0.3V Lo (sink) at SYNC Pin 36 can be used for detection OUT of no-signal because LPF is VCC 10kΩ applied. Pin 37 is for detection of the weak electric field. Pin 37 can be changed to V.SYNC-OUT. 37 300Ω EXT.RES. C.SYNC OUT2 Continued on next page. No.A0646-13/24 LA73033M Continued from preceding page. Pin No. Pin name I/0 Impe DC voltage dance VCC for pin 73 input VCC (Y) insert a capacitor between each VCC for input of pins 1, 79, 77, and 75 8 VCC (C) VCC and GND. Keep VCC always ON. VCC for input of pins 9, 7, 5, and 3 10 VCC (SY) 12 VCC (CV) 14 GND VCC (B) 5V Description of Input/Output form VCC on the input SW. To avoid crosstalk, it is recommended to 72 P Pin Explanation each pin 74 VCC for input of pins 11, 13, 15, 17, 19, and 21 VCC for SYNC-SEP, clamp pulse P 0V (SY) 22 Description of GND on the input SW side each pin GND GND for pin 73 input GND for input of pins 1, 79, 77, and 75 (CV) 24 GND (C) GND for input of pins 9, 7, 5, and 3 26 GND (Y) GND for pins 11, 13, 15, 17, 19, and 21 28 GND (B) 76 NC 78 NC 80 NC 2 NC 4 NC 6 NC 16 NC 32 SDATA GND for SYNC-SEP, clamp pulse 0V NC pins on the input SW side. It is recommended to connect this to GND on the substrate to avoid interference between input signals. I 734MΩ Hi : 5V Pin to enter the serial data and its Lo : V clock for IIC bus. For the input VCC waveform, refer to the SDA & SCL standard. 25μA 33 SCLK IN 500Ω 39 CV.IN I Clamp 2.2V at 6dB Recommended capacitor = 0.1μF. Form 2.3V at 9dB For the signal with input, feedback 1.85V at no signal clamp is applied to the input so that the clamp voltage becomes constant. For signal VCC without input, diode clamp is applied to the input. Pins 43 Y1.IN VCC VCC VCC 19kΩ 39 and 45 drop to 0 to 1V when not selected. IN 200Ω 100μF 45 Y2.IN 100kΩ R.IN Continued on next page. No.A0646-14/24 LA73033M Continued from preceding page. Pin No. 41 Pin name C.IN I/0 I Impe DC voltage dance 10kΩ 2.7V Pin Explanation Input/Output form Recommended capacitor = 0.1μF. VCC DC is overlapped over the signal VCC VCC VCC with external C connected, regardless of the signal or no-signal and AMP-GAIN. 10kΩ IN 200Ω 150μF 51 Cr.IN I G.IN 53 Clamp For component Recommended capacitor = 0.1μF. Form 2.8V at 6dB In the component mode, keyed 2.7V at 9dB clamp is applied to the input so For RGB that the pedestal of output signal 2.2V at 6dB becomes constant when there is a 2.3 at 9dB signal at pin 45. In the RGB mode, 1.85V at no signal feedback clamp is applied to the Cb.IN VCC VCC VCC 100μF VCC VCC 19kΩ CLAMP PULSE 200Ω IN input so that the output signal B.IN clamp voltage becomes constant. Diode clamp is applied to the input 100kΩ CLAMP PULSE when there is no signal. 68 CV.OUT O 4Ω Y1.OUT 65 63 C.OUT 1.3V for CV/ Y/ RGB Recommended coupling 2.5V for component capacitor = 470μF (0.1μF for For chroma output chroma). The signal that has 2.4V at 0dB passed AMP & LPF is output from 2.6V at 6dB the 75Ω driver. Two drives VCC VCC 30Ω possible. It is recommended to Y1.OUT provide this capacitor as near as OUT possible to the pin to avoid 60 Y2.OUT interference. 30Ω R.OUT C.OUT 58 Cr.OUT G.OUT 56 Cb.OUT B.OUT 66 C_DC O OUT 11Ω Hi : 4.4V Circuit to output the DC voltage of Mid : 2.2V S1 and S2 standards. When Lo : 0V using this pin, insert a resistor VCC 500Ω 1kΩ (driving with about 10 kΩ per drive) between the output chroma signal after coupling and this pin, VCC VCC 500Ω so that the DC voltage of S1 and OUT 100kΩ S2 standard can be overlapped. 100μF VCC on the output driver side. It is recommended to insert a VCC for input of pins 32 and 33 VCC (CS1) capacitor between each VCC and VCC for input of pins 39, 41, and 43 50 VCC (CN1) VCC normally ON. 55 VCC (CN2) VCC for output of pins 60, 58, and 56 62 VCC (CS2) VCC for output of pins 68, 65, and 63 34 44 VCC (IC) P 5V Description of 300μF 500Ω each pin GND to avoid crosstalk. Keep VCC for input of pins 45, 51, and 53 Continued on next page. No.A0646-15/24 LA73033M Continued from preceding page. Pin No. 31 Pin name GND I/0 P Impe DC voltage dance 0V GND on the output driver side Input/Output form GND for input of pins 32 and 33 each pin (IC) 42 Description of Pin Explanation GND GND for input of pins 39, 41, and 43 (CS1) 52 GND GND for input of 45, 51, and 53 (CN1) 57 GND GND for output of pin 56 (CN3) 59 GND GND for output of pin 58 (CN4) 61 GND GND for output of pins 60 (CN2) 64 GND GND for output of pins 63 (CS3) 67 GND GND for output of pin 65 (CS2) 69 GND GND for output of pin 68 (CS4) 46 NC 47 NC 48 NC 49 NC 54 NC 70 NC 71 NC 0V NC pins on the output driver side. It is recommended to connect this pin to GND on the substrate to avoid interference with the input SW side. No.A0646-16/24 LA73033M Device address Gr address bit7 (MSB) bit6 bit5 bit4 bit3 bit2 bit1 SW1 00000001 INSEL3 INSEL2 INSEL1 LPF SWGAIN1 SWGAIN2 YOUT SEL bit0 (LSB) *Res SW2 00000010 AGC V.SYNC *Res *Res CLPOFF1 CLPIUP TEST2 TEST1 DR1 00000011 SCART YC MIX CDC2 CDC1 PROG GB MUTE YC MUTE CP MUTE DR2 00000100 CV/ S GAIN CP GAIN CV/ S DRIVE CP DRIVE SCART YC *Res *Res CLPOFF2 * Res means a reserved bit. Initial state SW block INSEL3 SW block input selection/mode INSEL2 changeover INSEL1 INSEL3 INSEL2 INSEL1 Input selection Mode 0 0 0 IN1 Component 0 0 1 IN1 RGB 0 1 0 IN2 Composite/ S 0 1 1 IN3 Composite/ S 1 0 0 IN4 Composite/ S 1 0 1 IN5 Composite/ S 1 1 0 IN6 Composite/ S 1 1 1 LPF SWGAIN1 Prohibition SW block LPF 1 : LPF on 0 : LPF off SW block amplifier gain changeover 1 (for composite/ Y 1 : +6dB (AGC used+3dB) 0 : 0dB 1 : +6dB (AGC used+3dB) 0 : 0dB signal) SWGAIN2 SW block amplifier gain changeover 2 (C/ component/ RGB signal) YOUT SEL AGC V.SYNC SW block YOUT output selection 1 : Composite 0:Y SW block AGC ON/OFF 1 : ON 0 : OFF SYNC output changeover 1 : V-SYNC output 0 : C- SYNC output (for detection of weak Test mode (SW block input clamp OFF) 1 : Clamp OFF 0 : Clamp ON Increase in SW block clamp current 1 : Increase in the clamp 0 : Clamp current normal field) CLPOFF1 CLPIUP current TEST2 C-SYNC output (TEST mode) 00 : C-SYNC (Normal) 01 : Clamp pulse 10 : Prohibition 11 : Macro vision gate Driver block component mode changeover 1 : SCART (RGB) 0 : Y/ Cb/ Cr Driver block composite output selection 1 : Y/ C MIX 0 : Composite (Y/ C MIX OFF) Driver block C_DC output voltage 00 : Low (0V) 4 : 3mode 01 : Middle (2.2V) letter box 10 : High (5V) squeeze 11 : Prohibition TEST1 Driver block SCART YC MIX CDC2 CDC1 Driver block LPF changeover 1 : Progressive 0 : Interlace GB MUTE PROG Driver block G/B MUTE 1 : MUTE ON 0 : MUTE OFF YC MUTE Driver block YC MUTE 1 : MUTE ON 0 : MUTE OFF CP MUTE CV/ S GAIN CP GAIN CV/ S DRIVE Driver block component MUTE 1 : MUTE ON 0 : MUTE OFF Driver block composite/ S amplifier gain 1 : +9dB 0 : +6dB Driver block component amplifier gain 1 : +9dB 0 : +6dB 0 : One-system drive Driver block composite/ S output drive capacity 1 : Two-system drive CP DRIVE Driver block component output drive capacity 1 : Two-system drive 0 : One-system drive SCART YC Driver block SCART YC mode changeover 1 : YC 0 : RGB CLPOFF2 Test mode (driver block input clamp OFF) 1 : Clamp OFF 0 : Clamp ON *Initial setting at power ON Gr address data SW1 00000001 01100010 SW2 00000010 00000000 DR1 00000011 01000000 DR2 00000100 00110000 No.A0646-17/24 LA73033M Control pin function table (1) *For the serial control pin, enter 3.5 to 5V for H and 0 to 1.5V for L. *For the parallel control pin, enter 2.6 to 5V for H and 0 to 0.7V for L. *For all control pins, do not apply the voltage higher than the one applied to VCC or lower than the one applied to GND. *No control pin must be used in the OPEN state. *Values in the table are standard values. For SPEC, refer to the electrical characteristics. [Selection of the SW side input signal] Control Gr address Gr address Pin 18 Pin 38 00000001 00000010 Standby RGB through Pin 23 CV (rear 1) 010***1* ****0*00 L H/ L 13 (CV) , 7 (C) S (rear 1) 010***0* ****0*00 L H/ L 7 (C) , 79 (Y) CV (rear 2) 011***1* ****0*00 L H/ L 15 (CV) , 5 (C) S (rear 2) 011***0* ****0*00 L H/ L 5 (C) , 77 (Y) CV (front) 100***1* ****0*00 L H/ L 17 (CV) , 3 (C) S (front) 100***0* ****0*00 L H/ L 3 (C) , 75 (Y) CV (tuner) CV (tuner) component RGB CS-REC Signal to be output Input pin to be selected 101***1* ****0*00 L H/ L 19 (CV) 101***0* ****0*00 L H/ L None 110***1* ****0*00 L H/ L 21 (CV) 110***0* ****0*00 L H/ L None 000***** ****0*00 L L 1 1(Cb) , 9 (Cr) , 1 (Y) Pin 25 Pin 27 Pin 29 (CV) C CV DC - C Y DC (CV) C CV DC DC - C Y (CV) C CV DC - C Y DC (CV) DC CV DC - DC DC DC (CV) DC CV DC - DC DC DC Cb Cr Y DC 000***** ****0*00 L H 1 (Y) - - Y - 001***** ****0*00 L L 11 (G) , 9 (R) , 1 (CV) , 73 (B) G R CV B 001***** ****0*00 L H 1 (CV) - - CV - ******** ******** H L Pin 15 input→15 (CV) - - - - ******** ******** H L Pins 15+77 input→77 (Y) - - - - ******** ******** H L Pin 77 input→77 (Y) - - - - (Note 1) (CV) : Though a signal is output, its use is not recommended. (Note 2) DC : The DC voltage differing depending on the AMP-GAIN setting is output. (Note 3) - : Either the signal is not output or should not be used because the DC voltage is abnormal if output. [Selection of the input signal for C.SYNC OUT] Signal to be output Gr address Gr address Pin 18 Pin 38 00000001 00000010 Standby RGB through CV (rear 1) 010***1* *0**0*00 L H/ L 13 (CV) C.SYNC C.SYNC2 S (rear 1) 010***0* *0**0*00 L H/ L 79 (Y) C.SYNC C.SYNC2 Control Input pin to be selected C.SYNC C.SYNC2 CV (rear 2) 011***1* *0**0*00 L H/ L 15 (CV) C.SYNC C.SYNC2 S (rear 2) 011***0* *0**0*00 L H/ L 77 (Y) C.SYNC C.SYNC2 CV (front) 100***1* *0**0*00 L H/ L 17 (CV) C.SYNC C.SYNC2 S (front) 100***0* *0**0*00 L H/ L 75 (Y) C.SYNC C.SYNC2 101***1* *0**0*00 L H/ L 19 (CV) C.SYNC C.SYNC2 101***0* *0**0*00 L H/ L None × × 110***1* *0**0*00 L H/ L 21 (CV) C.SYNC C.SYNC2 110***0* *0**0*00 L H/ L None × × component 000***** *0**0*00 L H/ L 1 (Y) C.SYNC C.SYNC2 RGB 001***** *0**0*00 L H/ L 1 (CV) C.SYNC C.SYNC2 V.SYNC ******** *1**0*00 L H/ L Same as above C.SYNC V.SYNC ******** *0**0*01 L H/ L Same as above Clamp pulse C.SYNC2 Same as above CV (tuner) CV (tuner) Monitor CS-REC RGB standby ******** *0**0*11 L H/L Macro gate pulse C.SYNC2 ******** ******** H L Pin 15 input→15 (CV) C.SYNC × ******** ******** H L Pins 15 + 77 input→77 (Y) C.SYNC × ******** ******** H L Pin 77 input→77 (Y) C.SYNC × ******** ******** H H 1 (CV) C.SYNC × No.A0646-18/24 LA73033M Control pin function table (2) [SW side AMP-GAIN selection] Control CV/ S component RGB AMP-GAIN Gr address Gr address Pin 18 Pin 38 00000001 00000010 Standby RGB through Pin 23 Pin 25 Pin 27 Pin 29 ****00** 0***0*00 L H/ L (Fixed at 0dB) Fixed at 0dB Fixed at 0dB DC ****10** 0***0*00 L H/ L (Fixed at 6dB) Fixed at 0dB Fixed at 6dB DC ****01** 0***0*00 L H/ L (Fixed at 0dB) Fixed at 6dB Fixed at 0dB DC ****11** 0***0*00 L H/ L (Fixed at 6dB) Fixed at 6dB Fixed at 6dB DC ****00** 1***0*00 L H/ L (AGC0dB) Fixed at 0dB AGC0dB DC ****10** 1***0*00 L H/ L (AGC3dB) Fixed at 0dB AGC3dB DC ****01** 1***0*00 L H/ L (AGC0dB) Fixed at 6dB AGC0dB DC ****11** 1***0*00 L H/ L (AGC3dB) Fixed at 6dB AGC3dB DC 000*00** 0***0*00 L H/ L Fixed at 0dB Fixed at 0dB Fixed at 0dB DC 000*10** 0***0*00 L H/ L Fixed at 0dB Fixed at 0dB Fixed at 6dB DC 000*01** 0***0*00 L H/ L Fixed at 6dB Fixed at 6dB Fixed at 0dB DC 000*11** 0***0*00 L H/ L Fixed at 6dB Fixed at 6dB Fixed at 6dB DC 000*00** 1***0*00 L H/ L Fixed at 0dB Fixed at 0dB AGC0dB DC 000*10** 1***0*00 L H/ L Fixed at 0dB Fixed at 0dB AGC3dB DC 000*01** 1***0*00 L H/ L Fixed at 6dB Fixed at 6dB AGC0dB DC 000*11** 1***0*00 L H/ L Fixed at 6dB Fixed at 6dB AGC3dB DC 001*00** 0***0*00 L H/ L Fixed at 0dB Fixed at 0dB Fixed at 0dB Fixed at 0dB 001*10** 0***0*00 L H/ L Fixed at 0dB Fixed at 0dB Fixed at 6dB Fixed at 0dB 001*01** 0***0*00 L H/ L Fixed at 6dB Fixed at 6dB Fixed at 0dB Fixed at 6dB 001*11** 0***0*00 L H/ L Fixed at 6dB Fixed at 6dB Fixed at 6dB Fixed at 6dB 001*00** 1***0*00 L H/ L Fixed at 0dB Fixed at 0dB AGC0dB Fixed at 0dB 001*10** 1***0*00 L H/ L Fixed at 0dB Fixed at 0dB AGC3dB Fixed at 0dB 001*01** 1***0*00 L H/ L Fixed at 6dB Fixed at 6dB AGC0dB Fixed at 6dB 001*11** 1***0*00 L H/ L Fixed at 6dB Fixed at 6dB AGC3dB Fixed at 6dB (Note 1) Though a signal is output, its use is not recommended. (Note 2) At the Gr address = 0000 0001 of CV/S, *** ∼ does not contain 00* ∼ . [SW side LPF selection] Gr address Gr address Pin 18 Pin 38 LPF route of each output Load corresponding to each output 00000001 00000010 Standby RGB through Pins 23, 25, 27, 29 Pins 23, 25, 27, 29 LPF-ON ***1**** ****0*00 L H/ L Pass 1kΩ LPF-OFF ***0**** ****0*00 L H/ L Through 330Ω Control No.A0646-19/24 LA73033M Control pin function table (3) [Driver side input signal selection] Control Gr Gr address address 00000011 00000100 00***000 CV/ S component Y/ C-MIX component CV/ S RGB YC/ MIX RGB SCART Y/ C SCART Y/ C-MIX ****0**0 Pin 18 Standby L Pin 38 Signal to be output Input pin to be selected RGB Pin 68 Pin 65 Pin 63 Pin 60 Pin 58 Pin 56 through L 39 (CV) 41 (C) 43 (Y1) 45 (Y2) 51 (Cr) 53 (Cb) 00***010 ****0**0 L L 39 (CV) 00***001 ****0**0 L L 39 (CV) 41 (C) 43 (Y1) 45 (Y2) 51 (Cr) 53 (Cb) 01***000 ****0**0 L L 41 (C) 43 (Y1) 45 (Y2) 51 (Cr) 53 (Cb) 01***010 ****0**0 L L 01***001 ****0**0 L L 39 (CV) 41 (C) 43 (Y1) 41 (C) 43 (Y1) 45 (Y2) 51 (Cr) 53 (Cb) 10***000 ****0**0 L L 39 (CV) 41 (C) 43 (Y1) 45 (R) 51 (G) 53 (B) 51 (G) 53 (B) 10***010 ****0**0 L L 39 (CV) 10***001 ****0**0 L L 39 (CV) 41 (C) 43 (Y1) 45 (R) 11***000 ****0**0 L L 41 (C) 43 (Y1) 45 (R) 51 (G) 53 (B) 41 (C) 43 (Y1) 45 (R) 51 (G) 53 (B) 11***010 ****0**0 L L 11***001 ****0**0 L L 39 (CV) 41 (C) 43 (Y1) 10***000 ****1**0 L L 41 (C) 43 (Y1) 51 (G) 51 (G) 10***010 ****1**0 L L 41 (C) 43 (Y1) 10***100 ****1**0 L L 41 (C) 43 (Y1) CV C Y1 Y2 Cr Cb CV DC DC Y2 Cr Cb CV C Y1 DC DC DC CV C Y1 Y2 Cr Cb CV DC DC Y2 Cr Cb CV C Y1 DC DC DC CV C Y1 R G B CV DC DC R G B CV C Y1 DC DC DC CV C Y1 R G B CV DC DC R G B CV C Y1 DC DC DC 53 (B) Y1 C Y1 C G R 53 (B) Y1 DC DC C G R Y1 C Y1 C DC DC 11***000 ****1**0 L L 41 (C) 43 (Y1) 51 (G) 53 (B) CV C Y1 C G R 11***010 ****1**0 L L 41 (C) 43 (Y1) 51 (G) 53 (B) CV DC DC C G R DC 11***100 ****1**0 L L 41 (C) 43 (Y1) CV C Y1 C DC CV/ S *0****0* ****0**0 L H 39 (CV) 41 (C) 43 (Y1) 9 (R) 11 (G) 73 (B) CV C Y1 R G B RGB through *0****1* ****0**0 L H 39 (CV) 9 (R) 11 (G) 73 (B) CV DC DC R G B SCART Y/ C *0****0* ****1**0 L H 41 (C) 43 (Y1) 9 (R) 11 (G) 73 (B) Y1 C Y1 R G B RGB through *0****1* ****1**0 L H 43 (Y1) 9 (R) 11 (G) 73 (B) Y1 DC DC R G B Y/ C-MIX *1****0* *******0 L H 41 (C) 43 (Y1) 9 (R) 11 (G) 73 (B) CV C Y1 R G B RGB through *1****1* *******0 L H 41 (C) 43 (Y1) 9 (R) 11 (G) 73 (B) CV DC DC R G B RGB standby ******** ******** H H 9 (R) 11 (G) 73 (B) - - - R G B CS-REC ******** ******** H L - - - - - - (Note 1) Y1 is a Y signal for S and Y2 is a Y signal for component. (Note 2) The mute voltage described in the table of electrical characteristics is output. (Note 3) -: Either the signal is not output or should not be used because the DC voltage is abnormal if output. No.A0646-20/24 LA73033M Control pin function table (4) [Driver side AMP-GAIN selection] Gr address Gr address Pin 18 00000011 00000100 Standby *****000 00****00 L *****000 10****00 *****000 01****00 *****000 DAC signal RGB through RGB standby ******** Control DAC signal Pin 38 AMP-GAIN RGB Pin 68 Pin 65 Pin 63 Pin 60 Pin 58 Pin 56 L 6dB 6dB 6dB 6dB 6dB 6dB L L 9dB 9dB 9dB 6dB 6dB 6dB L L 6dB 6dB 6dB 9dB 9dB 9dB 11****00 L L 9dB 9dB 9dB 9dB 9dB 9dB *****000 0*****00 L H 6dB 6dB 6dB 6dB 6dB 6dB *****000 1*****00 L H 9dB 9dB 9dB 6dB 6dB 6dB ******** H H - - - 6dB 6dB 6dB through (Note 1) At SCART-YC, the gain control of chroma output is different between pin 65 and pin 60. (Note 2) -: Either the signal is not output or should not be used because the DC voltage is abnormal if output. [Driver side LPF selection] Gr address Gr address Pin 18 0000001 00000100 Standby Interlace ***1**** ******00 Progressive ***0**** RGB through RGB standby Control Pin 38 LPF cut-off frequency (MHz) RGB through Pin 68 Pin 65 Pin 63 Pin 60 Pin 58 Pin 56 L L 9 9 9 9 9 9 ******00 L L 9 9 9 18 18 18 ******** ******00 L H 9 9 9 Through Through Through ******** ******** H H - - - Through Through Through [Selection of the number of channels that can be driven by 75Ω driver ] Control DAC signal Gr address Gr address Pin 18 0000001 00000100 Standby *****000 **00***0 L *****000 **10***0 *****000 **01***0 *****000 Pin 38 Number of channels that can be driven of each output RGB Pin 68 Pin 65 Pin 63 Pin 60 Pin 58 Pin 56 L 1 1 1 1 1 1 L L 2 2 2 1 1 1 L L 1 1 1 2 2 2 **11***0 L L 2 2 2 2 2 2 through ******0* **00***0 L H 1 1 1 1 1 1 DAC signal ******0* **10***0 L H 2 2 2 1 1 1 RGB through ******0* **01***0 L H 1 1 1 2 2 2 ******0* **11***0 L H 2 2 2 2 2 2 ******** ******** H H - - - 1 1 1 RGB standby [Selection of S1 and S2 overlapping DC] Control Gr address Gr address Pin 18 0000001 00000100 Standby **00**** *******0 L Pin 38 Pin 66 RGB Application Output voltage (V) H/ L For 4 : 3 0 through For S1 and S2 **01**** *******0 L H/ L For letter box 2.2 control **10**** *******0 L H/ L For squeeze 4.4 **11**** *******0 L H/ L Prohibited - No.A0646-21/24 LA73033M Test Input Signal SIN WAVE P-P 140IRE SG.1 1H 40IRE SIN WAVE P-P 100IRE SG.2 1H SIN WAVE P-P 140IRE SG.3 1H P-P 40IRE SIN WAVE SG.4 100IRE 50IRE 1H P-P 140IRE SG.5 1H P-P 100IRE SG.6 1H SIN WAVE P-P 140IRE 40IRE SG.7 1H 40IRE P-P 100IRE SG.8 1H P-P 100IRE SG.9 1H No.A0646-22/24 LA73033M Sample Application 75Ω T53 + T51 T45 T43 T41 + VIN39 0.1μF 75Ω + VIN41 0.1μF 75Ω + VIN43 VIN45 + T39 + VCC2 75Ω S58 75Ω 470μF T60A T60 75Ω T65 CV_IN 39 SYNC_L 36 66 C_DC AGCCTL2 35 67 GNDCS2 68 CVOUT SCL 33 69 GNDCS4 SDA 32 70 NC GNDC 24 80 NC CV6_IN 21 T79 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 NC 1 V30 T27 T25 T23 + 100μF 330Ω + 100μF 330Ω + 100μF 330Ω + 100μF 330Ω + + T20 470μF 75Ω 0.1μF V1 8 + + 75Ω 0.1μF + T21 T19 VIN21 T17 75Ω 0.1μF + VIN17 T15 75Ω 0.1μF + VIN15 T13 75Ω 0.1μF VIN13 + 75Ω 0.1μF T11 VIN11 + 75Ω 0.1μF T9 VIN9 + 75Ω 0.1μF T7 VIN7 + 75Ω 0.1μF T5 VIN5 + 75Ω 0.1μF VIN3 T3 VIN19 T1 75Ω 0.1μF VIN1 CV3_IN + 75Ω 0.1μF CV5_IN GNDCV 22 STDBYH CVOUT 23 79 Y2_IN CV4_IN 78 NC VCCSY T77 COUT 25 77 Y3_IN C1_IN VIN79 76 NC VCCC + 75Ω 0.1μF GNDY 26 C2_IN T75 YOUT 27 75 Y4_IN C3_IN VIN77 VCC1 74 VCCY NC + + 75Ω 0.1μF GNDB 28 C4_IN T73 73 B1_IN NC VIN75 BOUT 29 Y1_IN + 75Ω 0.1μF T29 AGCCTL1 30 72 VCCB NC VIN73 SERIA L DATA GNDIC 31 LA73033M 71 NC + + V35 VCCIC 34 GNDSY 75Ω S68 75Ω 470μF 65 COUTD T37 10kΩ +5V + T36 10kΩ +5V + V38 SYNC2L 37 CV2_IN 75Ω S65 75Ω 470μF 0.1μF T68A T66 T68 4.7kΩ 75Ω 75Ω + 64 GNDCS3 VCCCV + + 470μF EXTRGBH 38 CV1_IN 75Ω C_IN GNDCS1 Y1_IN Y2_IN VCCCS1 NC NC NC NC CR_IN VCCCN1 GNDCN1 NC CB_IN CBOUT CROUT 62 VCCCS2 63 YOUT1 75Ω T40 REGDV 40 REGSW 75Ω S63 75Ω 470μF T65A 61 GNDCN2 VCCCN2 + GNDCN3 75Ω YOUT2 75Ω 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 T63 GNDCN4 75Ω + 75Ω S60 75Ω 470μF T63A + 0.1μF 75Ω T58 75Ω + 0.1μF 75Ω 75Ω S56 75Ω 470μF T58A VIN51 + 0.1μF 75Ω 0.1μF 75Ω T56 75Ω VIN53 T56A 75Ω No.A0646-23/24 LA73033M SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of July, 2007. Specifications and information herein are subject to change without notice. PS No.A0646-24/24