Micro Linear ML6673CQ Fast ethernet/fddi tp-pmd transceiver Datasheet

December 1998
ML6673
Fast Ethernet/FDDI TP-PMD Transceiver
GENERAL DESCRIPTION
FEATURES
The ML6673 is a complete monolithic transceiver for 125
Mbaud MLT-3 encoded data transmission over Category 5
unshielded twisted pair and shielded twisted pair cables.
The ML6673 integrates the baseline restoration function
defined in the TP-PMD standard. The adaptive equalizer in
the ML6673 will accurately compensate for line losses
exceeding the IEEE 802.3u limit of 100m of UTP.
■
Compliant with IEEE 802.3u Fast Ethernet (100BASE-TX)
standard
■
Compliant with ANSI X3T12 FDDI over copper
(TP-PMD) standard
Integrated baseline wander correction circuit
Transmitter converts NRZI ECL signals to MLT-3 current
driven outputs
Transmitter can be externally turned off
(high impedence) for true quiet line
The ML6673 receive section consists of an equalizing filter
with a feedback loop for controlling effective line
compensation. The feedback loop contains a filter and
detection block for determining the proper control signal.
The ML6673 also contains data comparators with
precisely controlled slicing thresholds and an MLT-3 to
NRZI translator.
The ML6673 transmit section accepts ECL 100K
compatible NRZ inputs and converts them to differential
current mode MLT-3 signals. Transmit amplitude is
controlled by a single external resistor.
■
■
■
■
■
■
Receiver includes adaptive equalizer and MLT-3 to
NRZI decoder
Operates over 100 meters of STP or category 5 UTP
Twisted Pair Cable set by the IEEE 802.3u standards
32-pin PLCC and TQFP
BLOCK DIAGRAM
LPBK
TXOFF
TVCCA
RTSET
TVCCD
RTSET1
RTSET2
TXIN+
TPOUT+
NRZI
TO MLT-3
TXIN–
TPOUT–
BASELINE
WANDER
CORRECTION
LINK
STATUS
SD+
SD–
ADAPTIVE
CONTROL
RXOUT+
MUX
RXOUT–
RRSET1
TGNDA TGNDD
TPIN+
ADAPTIVE
EQUALIZER
MLT-3
TO NRZI
GND
TPIN–
RRSET2
RRSET
RVCCA RVCCD CMREF
1
ML6673
PIN CONFIGURATION
ML6673
32-Pin TQFP (H32-7)
RGND
N/C
N/C
TVCCA
TGNDA
32 31 30
N/C
CMREF
1
N/C
N/C
2
RRSET2
N/C
3
TPIN–
RVCCA
4
TPIN+
RXOUT–
ML6673
32-Pin PCC (Q32)
32
31
30
29
28
27
26
25
RVCCD
6
28
RRSET2
TPIN–
2
23
TPOUT+
SD–
7
27
N/C
TPIN+
3
22
RTSET2
SD+
8
26
N/C
CMREF
4
21
RTSET1
N/C
9
25
RGND
N/C
5
20
TVCCD
TGNDD
10
24
N/C
N/C
6
19
TXIN–
LPBK
11
23
N/C
RVCCA
7
18
TXIN+
TXOFF
12
22
TVCCA
RXOUT–
8
17
N/C
N/C
21
13
TGNDA
TPOUT–
RTSET2
TPOUT+
RTSET1
TVCCD
TXIN–
TXIN+
14 15 16 17 18 19 20
9
10
11
12
13
14
15
16
TXOFF
TPOUT–
LPBK
24
TGNDD
1
N/C
RRSET1
SD+
RRSET1
SD–
29
RVCCD
5
RXOUT+
RXOUT+
PIN DESCRIPTION
NAME
FUNCTION
NAME
FUNCTION
TXIN+, TXIN–
These differential ECL100K compatible
inputs receive NRZI data from the PHY
for transmission.
Outputs from the NRZI-MLT3 state
machine drive these differential current
outputs. The transmitter filter/transformer
module connects the media to these pins.
This TTL input enables transmitterreceiver loopback internally when
asserted low. When LPBK is asserted,
signal detect is asserted.
This TTL input forces the NRZI-MLT3
state machine to a high impedence state
when asserted low and shuts off transmit
bias current.
An external 1% resistor connected
between these pins controls the
transmitter output current amplitude.
IOUT = 64 x 1.25V/RTSET
Separate analog and digital transmitter
power supply pins help to isolate
sensitive circuitry from noise generating
digital functions. Both supplies are
nominally +5 volts.
TGNDA,
TGNDD
Analog and digital transmitter grounds
provide separate return paths for clean
and noisy signals.
These differential ECL100K compatible
outputs indicate the presence of a data
signal with an amplitude exceeding a
preset threshold.
MLT-3 encoded data from the receiver
filter/transformer module enters the
receiver through these pins.
Differential ECL100K compatible outputs
provide NRZI encoded data to the PHY.
Internal time constants controlling the
equalizer’s transfer function are set by an
external resistor connected across these
pins.
This pin provides a DC common mode
reference point for the receiver inputs.
Analog and digital supply pins are
separated to isolate clean and noisy
circuit functions. Both supplies are
nominally +5 volts.
Receiver ground.
TPOUT+,
TPOUT–
LPBK
TXOFF
RTSET1,
RTSET2
TVCCA,
TVCCD
2
SD+, SD–
TPIN+, TPIN–
RXOUT+,
RXOUT–
RRSET1,
RRSET2
CMREF
RVCCA,
RVCCD
RGND
ML6673
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond
which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and
functional device operation is not implied.
Lead Temperature (Soldering, 10 sec) ..................... 260°C
Thermal Resistance (θJA)
PLCC ............................................................... 60°C/W
TQFP ............................................................... 80°C/W
VCC Supply Voltage Range ................... GND –0.3V to 6V
Input Voltage Range
Digital Inputs ........................ GND –0.3V to VCC +0.3V
Output Current
TPOUT±, SD±, RXOUT± ................................... 50mA
All other outputs ................................................. 10mA
Junction Temperature ............................................. 150°C
Storage Temperature ................................ –65°C to 150°C
OPERATING CONDITIONS
VCC Supply Voltage ............................................ 5V ± 5%
TA, Ambient Temperature .............................. 0°C to 70°C
RTSET ............................................................... 2kΩ ±1%
RRSET .......................................................... 9.53kΩ ±1%
Receive Transformer Insertion Loss ..................... < –0.5dB
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, TA = TMIN to TMAX, VCC = 5V ±5%, RTSET = 2kΩ. (Note 1)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
195
mA
mA
mA
mA
mA
0.8
V
DC Characteristics
Supply Current
RVCCD
RVCCA
TVCCD
TVCCA
RVCCD + RVCCA + TVCCD + TVCCA
74
65
24
6
TTL Inputs (TXOFF, LPBK)
VIL Input Low Voltage
VIH Input High Voltage
2.0
V
Differential Inputs (TPIN±, TXIN±)
TPIN+, TPIN–
Common Mode Input Voltage
2.2
TPIN+, TPIN–
Differential Input Voltage
TPIN+, TPIN–
Differential Input Resistance
VCC
V
1.5
V
Ω
10.0K
TPIN+, TPIN–
Common Mode Input Current
+10
µA
TXIN+, TXIN–
Input Voltage HIGH (VIH)
VCC–1.165
VCC–0.88
V
TXIN+, TXIN–
Input Voltage LOW (VIL)
VCC–1.810
VCC–1.475
V
TXIN+, TXIN–
Input Current LOW (IIL)
0.5
TXIN+, TXIN–
Input Current HIGH (IIH)
µA
50
µA
Differential Outputs (SD±, RXOUT±, TPOUT±)
SD+, SD–, RXOUT+, RXOUT–
Output Voltage HIGH (VOH)
Note 3
VCC–1.025
VCC–0.88
V
SD+, SD–, RXOUT+, RXOUT–
Output Voltage LOW (VOL)
Note 3
VCC–1.81
VCC–1.62
V
3
ML6673
ELECTRICAL CHARACTERISTICS (Continued)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Differential Outputs (SD±, RXOUT±, TPOUT±) (Continued)
TPOUT+, TPOUT–
Output Current HIGH
VOUT = VCC ± 0.5, Note 2
38.0
42.0
mA
TPOUT+, TPOUT–
Output Current LOW
VOUT = VCC ± 0.5, Note 2
0
0.5
mA
0.5
mA
–5.0
5.0
%
–2.0
+2.0
%
TPOUT+, TPOUT–
Output Current Offset
TPOUT+, TPOUT–VOUT = VCC
Output Amplitude Error
Note 2
TPOUT+, TPOUT–VOUT = VCC ±1.1V
Output Voltage Compliance
AC Characteristics
TPOUT+, TPOUT–
Rise/Fall Time
2.0
ns
TPOUT+, TPOUT–
Output Jitter
0.8
ns
RXOUT+, RXOUT–
Rise/Fall Time
2.0
ns
RXOUT+, RXOUT–
Output Jitter
2.0
ns
Note 1.
Note 2.
Note 3.
4
Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
Output current amplitude is determined by IOUT = 64 x 1.25V/RTSET.
Output voltage levels are specified when terminated by 50Ω to VCC – 2V or equivalent load.
ML6673
FUNCTIONAL DESCRIPTION
The ML6673 MLT-3 transceiver is a physical media
dependent transceiver that allows the transmission and
reception of 125 Mbaud data over shielded twisted pair
cable or category 5 unshielded twisted pair cable. It
provides a standard Physical Media Dependent (PMD)
interface compatible with many FDDI chip sets.
The transmit section accepts NRZI data, converting it to a
three level MLT-3 code and sending the information on a
two pin current driven transmitter. The transmitted output
passes through an external low pass filter and transformer
before entering the connectors to the STP or UTP cable.
The output amplitude of the transmitted signal is
programmable through the external RTSET resistor.
IOUT = 64 × 1.25V
RTSET
For 100BASE-TX UTP application, the transmit amplitude
is 2VP-P differential achieved by setting RTSET = 2kΩ (1%).
The receive section accepts MLT-3 coded data after
passing through an isolation transformer and band
limiting filter. Before the data can be converted from MLT3 back to NRZI, the adaptive equalizer is used to
compensate for the amplitude and phase distortion
incurred from the cable. The adaptive control section
determines the signal amplitude (and therefore the cable
length) and adjusts the equalizer accordingly.
The receiver also includes the Baseline Wander correction
circuitry. The circuit will compensate and track the DC
baseline wander caused by DC imbalance of the received
data. It will tolerate the test pattern as specified in the
ANSI X3T12 TP-PMD specification. A parallel 10pF
capacitor can be connected between TPIN+ and TPIN–
to improve Bit Error Rate.
The adaptive control block governs both the equalization
level as well as the signal detection status. Signal detect is
asserted when the equalizer control loop settles or when
loop back is asserted. When the input signal is small, the
equalization will be at its maximum.
After the signal has been equalized, it passes into the MLT-3
to NRZI converter where it is converted back to NRZI
and fed through the loopback multiplexer onto the
RXOUT± pins.
Figure 1 shows a timing diagram of NRZI data and the
equivalent MLT-3 data. The MLT-3 data shows the output
current IOUT for one side of the transmitter, either TPOUT+
or TPOUT–. The other transmit output pin will be the
complement. Whenever there is a change in level in
NRZI, MLT-3 will change levels too. The maximum
fundamental frequency of MLT-3 is half of the maximum
fundamental of NRZI.
Figure 2 shows a typical gain vs frequency plot of the
adaptive equalizer for 0, 25, 50, 75 and 100 meter
category 5 cable lengths.
ML6671 COMPATIBILITY
The ML6673 implements the Baseline Wander correction
circuit, in addition to providing the functionality of the
existing ML6671 device. The ML6673 is plug-compatible
with the ML6671 with the following note:
• In the ML6673 design, the following passive
components may be eliminated
— RSET resistor
— RTH resistor
— CAP1 capacitor
— CAP2 capacitor
CURRENT (mA)
MLT-3 DATA
20
IOUT
15
IOUT/2
10
0
8 16 24 32 40 48 56 64 72 80 88 96 104
(nsec)
NRZI DATA
5
1
0
0
Figure 1. MLT-3 Encoding
1 x 106
1 x 107
1 x 108
1 x 109
Figure 2. Equalization Range
5
Note 1.
Note 2.
Note 3.
Note 4.
6
Split 100K ECL terminations are 82ý and 130ý to VCC and GND respectively.
Recommended power supply bypass capacitors are 0.1µF with optional 10µF tantalum in parallel.
Transformer turns ratio is 1:1.
LPBK and TXOFF inputs are active LOW.
FROM PHY
TO PHY
TO PHY
NOTE 1
FROM PHY
+5.0V
0.1µF
ML6673 TP-PMD
TRANSCEIVER
LPBK TXOFF TGNDD TGNDA RGND
RXOUT–
RXOUT+
SD–
SD+
TXIN–
TXIN+
+5.0V
TVCCA RVCCA
0.1µF
+5.0V
TVCCD
0.1µF
RVCCD
0.1µF
+5.0V
TPIN–
CMREF
TPIN+
TPOUT–
TPOUT+
RTSET2
9.53K 1%
RRSET1 RRSET2
RTSET1
2.0K 1%
50
50
0.1µF
50
10pF
50
TO MIC
TRANSFORMER
FROM MIC
FILTER
MODULE
CT
TRANSFORMER
FILTER
MODULE
0.1µF
XFMRS INC. XF3506SIP
BEL FUSE 0558-5999-00
VALOR PT4172
PULSE PE-68508
FOR THE TRANSFORMER
FILTER MODULE, USE:
+5.0V
ML6673
Application Example of ML6673 Configured for 2.0VP-P Transmit Amplitude on C5 UTP.
ML6673
PHYSICAL DIMENSIONS inches (millimeters)
Package: H32-7
32-Pin (7 x 7 x 1mm) TQFP
0.354 BSC
(9.00 BSC)
0.276 BSC
(7.00 BSC)
0º - 8º
0.003 - 0.008
(0.09 - 0.20)
25
1
PIN 1 ID
0.276 BSC
(7.00 BSC)
0.354 BSC
(9.00 BSC)
0.018 - 0.030
(0.45 - 0.75)
17
8
0.032 BSC
(0.08 BSC)
SEATING PLANE
0.048 MAX
(1.20 MAX)
0.012 - 0.018
(0.29 - 0.45)
0.037 - 0.041
(0.95 - 1.05)
Package: Q32
32-Pin PLCC
0.485 - 0.495
(12.32 - 12.57)
0.098 - 0.112
(2.49 - 2.85)
0.450 - 0.456
(11.43 - 11.58)
1
PIN 1 ID
0.042 - 0.048
(1.07 - 1.22)
9
25
0.490 - 0.530
(12.45 - 13.46)
0.550 - 0.556 0.585 - 0.595
(13.97 - 14.12) (14.86 - 15.11)
17
0.019 - 0.021
(0.48 - 0.51)
0.050 BSC
(1.27 BSC)
0.026 - 0.032
(0.66 - 0.81)
0.165 - 0.180
(4.06 - 4.57)
0.025 - 0.045
(0.63 - 1.14)
(RADIUS)
0.148 - 0.156
(3.76 - 3.96)
0.013 - 0.021
(0.33 - 0.53)
0.390 - 0.430
(9.90 - 10.92)
SEATING PLANE
7
ML6673
ORDERING INFORMATION
PART NUMBER
ML6673CQ
ML6673CH
TEMPERATURE RANGE
0°C to 70°C
0°C to 70°C
PACKAGE
32-Pin PLCC (Q32)
32-Pin TQFP (H32-7)
© Micro Linear 1997
Micro Linear is a registered trademark of Micro Linear Corporation
Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940;
5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending.
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design.
Micro Linear does not assume any liability arising out of the application or use of any product described herein,
neither does it convey any license under its patent right nor the rights of others. The circuits contained in this
data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to
whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility
or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel
before deciding on a particular application.
8
2092 Concourse Drive
San Jose, CA 95131
Tel: 408/433-5200
Fax: 408/432-0295
DS6673-01
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