Mitel MT91L61 Iso2-cmos 3 volt multi-featured codec (mfc) Datasheet

ISO2-CMOS MT91L60/61
3 Volt Multi-Featured Codec (MFC)
Advance Information
DS5224
Features
•
•
•
•
•
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•
•
•
•
•
Single 2.7-3.6 volt supply operation
MT91L61 version features a delayed framing
pulse in SSI and ST-BUS modes to facilitate
cascaded devices
Programmable µ-Law/A-Law Codec and Filters
Programmable ITU-T (G.711)/sign-magnitude
coding
Programmable transmit, receive and side-tone
gains
Fully differential interface to handset
transducers - including 300 ohm receiver driver
Flexible digital interface including ST-BUS/SSI
Serial microport
Low power operation
ITU-T G.714 compliant
Multiple power down modes
Applications
•
•
•
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ISSUE 3
August 1999
Ordering Information
MT91L61AE
MT91L60AE
MT91L61AS
MT91L60AS
MT91L61AN
MT91L60AN
24 Pin Plastic DIP (600 mil)
24 Pin Plastic DIP (600 mil)
24 Pin SOIC
20 Pin SOIC
24 Pin SSOP
20 Pin SSOP
-40°C to +85°C
Description
The
MT91L60/61
3V
Multi-featured
Codec
incorporates a built-in Filter/Codec, gain control and
programmable sidetone path as well as on-chip
anti-alias filters, reference voltage and bias source.
The device supports both ITU-T and sign- magnitude
A-Law and µ-Law requirements. The MT91L60/61 is
a true 3V device employing a fully differential
architecture to ensure wide dynamic range.
Complete telephony interfaces are provided for
connection to handset transducers. Internal register
access is provided through a serial microport
compatible
with
various
industry
standard
micro-controllers.
Battery operated equipment
Digital telephone sets
Cellular radio sets
Local area communications stations
Pair Gain Systems
Line cards
The MT91L60/61 is fabricated in Mitel's ISO2-CMOS
technology ensuring low power consumption and
high reliability.
VSSD
VDD
VSSA
FILTER/CODEC GAIN
MENCODER
7dB
DECODER
-7dB
VBias
VRef
M+
Transducer
Interface
HSPKR +
HSPKR -
Din
Dout
STB/F0i
CLOCKin
Timing
Flexible
Digital
Interface
ST-BUS
C&D
Channels
STBd/FOod
Serial Microport
(MT91L61only)
PWRST
IC
CS
DATA1
DATA2
A/µ/IRQ
SCLK
Figure 1 - Functional Block Diagram
1
MT91L60/61
Advance Information
MT91L60AE
MT91L60AS/AN
VBias
VRef
PWRST
IC
A/µ/IRQ
VSSD
CS
SCLK
DATA1
DATA2
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
M+
MVSSA
HSPKR +
HSPKR VDD
CLOCKin
STB/F0i
Din
Dout
20 PIN SOIC/SSOP
VBias
VRef
NC
PWRST
IC
A/µ/IRQ
VSSD
CS
NC
SCLK
DATA1
DATA2
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
MT91L61AE/AS/AN
M+
MVSSA
NC
HSPKR +
HSPKR VDD
CLOCKin
NC
STB/F0i
Din
Dout
VBias
VRef
NC
PWRST
IC
A/µ/IRQ
VSSD
CS
NC
SCLK
DATA1
DATA2
24 PIN PDIP
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
M+
MVSSA
NC
HSPKR +
HSPKR VDD
CLOCKin
STBd/FOod
STB/F0i
Din
Dout
24 PIN PDIP/SOIC/SSOP
Figure 2 - Pin Connections
Pin Description
Pin #
20 Pin
24 Pin
2
Name
Description
1
1
VBias
Bias Voltage (Output). (VDD/2) volts is available at this pin for biasing external
amplifiers. Connect 0.1 µF capacitor to VSSA.
2
2
VRef
Reference Voltage for Codec (Output). Used internally. Nominally [Vdd/2 - 1.1]
volts. Connect 0.1 µF capacitor to VSSA.
3
4
4
5
5
6
6
7
VSSD
7
8
CS
Chip Select (Input). This input signal is used to select the device for microport
data transfers. Active low. CMOS level compatible.
8
10
SCLK
Serial Port Synchronous Clock (Input). Data clock for microport. CMOS level
compatible.
9
11
DATA 1 Bidirectional Serial Data. Port for microprocessor serial data transfer. In Motorola/
National mode of operation, this pin becomes the data transmit pin only and data
receive is performed on the DATA 2 pin. Input CMOS level compatible.
10
12
DATA 2 Serial Data Receive. In Motorola/National mode of operation, this pin is used for
data receive. In Intel mode, serial data transmit and receive are performed on the
DATA 1 pin and DATA 2 is disconnected. Input CMOS level compatible.
11
13
Dout
Data Output. A high impedance three-state digital output for 8 bit wide channel
data being sent to the Layer 1 transceiver. Data is shifted out via this pin concurrent
with the rising edge of the bit clock during the timeslot defined by STB, or according
to standard ST-BUS timing.
12
14
Din
Data Input. A digital input for 8 bit wide channel data received from the Layer 1
transceiver. Data is sampled on the falling edge of the bit clock during the timeslot
defined by STB, or according to standard ST-BUS timing. Input level is CMOS
compatible.
PWRST Power-up Reset (Input). CMOS compatible input with Schmitt Trigger (active low).
IC
Internal Connection. Tie externally to VSSD for normal operation.
A/µ/IRQ A/µ - When internal control bit DEn = 0 this CMOS level compatible input pin governs
the companding law used by the filter/Codec; µ-Law when tied to VSSD and A-Law
when tied to VDD. Logically OR’ed with A/µ register bit.
IRQ - When internal control bit DEn = 1 this pin becomes an open-drain interrupt
output signalling valid access to the D-Channel registers in ST-BUS mode.
Digital Ground. Nominally 0 volts.
MT91L60/61
Advance Information
Pin Description (continued)
Pin #
20 Pin
24 Pin
13
15
16
Name
Description
STB/F0i Data Strobe/Frame Pulse (Input). For SSI mode this input determines the 8 bit
timeslot used by the device for both transmit and receive data. This active high
signal has a repetition rate of 8 kHz. Standard frame pulse definitions apply in
ST-BUS mode. CMOS level compatible input.
STBd/
F0od
(MT91L61
only)
Delayed Frame Pulse Output. In SSI mode, an 8 bit wide strobe is output after the
first strobe goes low. In ST-BUS mode, a frame pulse is output after 4 channel
timeslots.
14
17
CLOCKin Clock (Input). The clock provided to this input pin is used for the internal device
functions. For SSI mode connect the bit clock to this pin when it is 512 kHz or
greater. Connect a 4096 kHz clock to this input when the available bit clock is 128
kHz or 256 kHz. For ST-BUS mode connect C4i to this pin. CMOS level compatible.
15
18
16
19
HSPKR- Inverting Handset Speaker (Output). Output to the handset speaker (balanced).
17
20
HSPKR+ Non-Inverting Handset Speaker (Output). Output to the handset speaker
(balanced).
18
22
VSSA
19
23
M-
Inverting Microphone (Input). Inverting input to microphone amplifier from the
handset microphone.
20
24
M+
Non-Inverting Microphone (Input). Non-inverting input to microphone amplifier
from the handset microphone.
3,9,
16,21
NC
No Connect. (24 Packages only). Pin 16 is NC for MT91L60.
VDD
Positive Power Supply (Input). Nominally 3 volts.
Analog Ground (Input). Nominally 0 volts.
Overview
Functional Description
The 3V Multi-featured Codec (MFC) features
complete
Analog/Digital
and
Digital/Analog
conversion of audio signals (Filter/Codec) and an
analog interface to a standard handset transmitter
and receiver (Transducer Interface). The receiver
amplifier is capable of driving a 300 ohm load.
Filter/Codec
Each of the programmable parameters within the
functional blocks is accessed through a serial
microcontroller port compatible with Intel MCS-51®,
Motorola SPI® and National Semiconductor
Microwire®
specifications.
These
parameters
include: gain control, power down, mute, B-Channel
select (ST-BUS mode), C&D channel control/access,
law control, digital interface programming and
loopback. Optionally the device may be used in a
controllerless mode utilizing the power-on default
settings.
The Filter/Codec block implements conversion of the
analog 0-3.3 kHz speech signals to/from the digital
domain compatible with 64 kb/s PCM B-Channels.
Selection of companding curves and digital code
assignment are programmable. These are ITU-T
G.711 A-law or µ-Law, with true-sign/Alternate Digit
Inversion or true-sign/Inverted Magnitude coding,
respectively. Optionally, sign-magnitude coding may
also be selected for proprietary applications.
The Filter/Codec block also implements transmit and
receive audio path gains in the analog domain. A
programmable gain, voice side-tone path is also
included to provide proportional transmit speech
feedback to the handset receiver. This side tone path
feature is disabled by default. Figure 3 depicts the
nominal half-channel and side-tone gains for the
MT91L60/61.
3
MT91L60/61
In the event of PWRST, the MT91L60/61 defaults
such that the side-tone path is off, all programmable
gains are set to 0dB and ITU-T µ-Law is selected.
Further, the digital port is set to SSI mode operation
at 2048 kb/s and the FDI and driver sections are
powered up. (See Microport section.)
The internal architecture is fully differential to provide
the best possible noise rejection as well as to allow a
wide dynamic range from a single 3 volt supply
design. This fully differential architecture is
continued into the Transducer Interface section to
provide full chip realization of these capabilities for
the handset functions.
A reference voltage (VRef), for the conversion
requirements of the Codec section, and a bias
voltage (VBias), for biasing the internal analog
sections, are both generated on-chip. VBias is also
brought to an external pin so that it may be used for
biasing external gain setting amplifiers. A 0.1µF
capacitor must be connected from VBias to analog
ground at all times. Although VRef may only be used
internally, a 0.1µF capacitor must be connected from
VRef to ground. The analog ground reference point
for these two capacitors must be physically the same
point. To facilitate this the VRef and VBias pins are
situated on adjacent pins.
Preliminary Information
Register 1 (address 00h). Transmit filter gain is
adjustable from 0dB to +7dB and receive filter gain
from 0dB to -7dB, both in 1dB increments.
Side-tone filter gain is controlled by the STG0-STG2
control bits located in Gain Control Register 2
(address 01h). Side-tone gain is adjustable from
-9.96dB to +9.96dB in 3.32dB increments.
Companding law selection for the Filter/Codec is
provided by the A/µ companding control bit while
the coding scheme is controlled by the Smag/ITU-T
control bit. The A/µ control bit is logically OR’ed with
the A/µ pin providing access in both controller and
controllerless modes. Both A/µ and Smag/ITU-T
reside in Control Register 2 (address 04h). Table 1
illustrates these choices.
ITU-T (G.711)
Code
Sign/
Magnitude
µ-Law
A-Law
+ Full Scale
1111 1111
1000 0000
1010 1010
+ Zero
1000 0000
1111 1111
1101 0101
-Zero
(quiet code)
0000 0000
0111 1111
0101 0101
- Full Scale
0111 1111
0000 0000
0010 1010
Table 1
Transducer Interfaces
The transmit filter is designed to meet ITU-T G.714
specifications. The nominal gain for this filter is 0dB
(gain control = 0dB). Gain control allows the output
signal to be increased up to 7dB. An anti-aliasing
filter is included. This is a second order lowpass
implementation with a corner frequency at 25 kHz.
The receive filter is designed to meet ITU-T G.714
specifications. The nominal gain for this filter is 0dB
(gain control = 0dB). Gain control allows the output
signal to be attenuated up to 7dB. Filter response is
peaked to compensate for the sinx/x attenuation
caused by the 8 kHz sampling rate.
Side-tone is derived from the input of the Tx filter and
is not subject to the gain control of the Tx filter
section. Side-tone is summed into the receive
handset transducer driver path after the Rx filter gain
control section so that Rx gain adjustment will not
affect side-tone levels. The side-tone path may be
enabled/disabled with the gain control bits located in
Gain Control Register 2 (address 01h).
Standard handset transducer interfaces are provided
by the MT91L60/61. These are:
• The handset microphone inputs (transmitter),
pins M+/M-. The nominal transmit path gain may
be adjusted to either 6.0 dB or 15.3 dB. Control of
this gain is provided by the TxINC control bit
(Gain Control register 1, address 00h).
• The handset speaker outputs (receiver), pins
HSPKR+/HSPKR-. This internally compensated
fully differential output driver is capable of driving
the load shown in Figure 3. The nominal receive
path gain may be adjusted to either 0 dB, -6 dB or
-12 dB. Control of this gain is provided by the
RxINC control bit (Gain Control register 1,
address 00h). This gain adjustment is in addition
to the programmable gain provided by the receive
filter.
Microport
Transmit and receive filter gains are controlled by the
TxFG0-TxFG2 and RxFG0-RxFG2 control bits,
respectively. These are located in Gain Control
The serial microport, compatible with Intel MCS-51
(mode 0), Motorola SPI (CPOL=0,CPHA=0) and
Intel® and MCS-51® are registered trademarks of Intel Corporation
Motorola® and SPI® are registered trademarks of Motorola Corporation
National® and Microwire® are trademarks of National Semiconductor Corporation
4
MT91L60/61
Advance Information
National Semiconductor Microwire specifications
provides access to all MT91L60/61 internal read and
write registers. This microport consists of a transmit/
receive data pin (DATA1), a receive data pin
(DATA2), a chip select pin (CS) and a synchronous
data clock pin (SCLK). For D-channel contention
control, in ST-BUS mode, this interface provides an
open-drain interrupt output (IRQ).
The microport dynamically senses the state of the
serial clock (SCLK) each time chip select becomes
active. The device then automatically adjusts its
internal timing and pin configuration to conform to
Intel or Motorola/National requirements. If SCLK is
high during chip select activation then Intel mode 0
timing is assumed. The DATA1 pin is defined as a
bi-directional (transmit/receive) serial port and
DATA2 is internally disconnected. If SCLK is low
during chip select activation then Motorola/National
timing is assumed. Motorola processor mode
CPOL=0, CPHA=0 must be used. DATA1 is defined
as the data transmit pin while DATA2 becomes the
data receive pin. Although the dual port Motorola
controller configuration usually supports full-duplex
communication, only half-duplex communication is
possible in the MT91L60/61. The micro must discard
non-valid data which it clocks in during a valid write
transfer to the MT91L60/61. During a valid read
transfer from the MT91L60/61 data simultaneously
clocked out by the micro is ignored by the MT91L60/
61.
All data transfers through the microport are two-byte
transfers requiring the transmission of a Command/
Address byte followed by the data byte written or
read from the addressed register. CS must remain
asserted for the duration of this two-byte transfer. As
shown in Figures 5 and 6 the falling edge of CS
indicates to the MT91L60/61 that a microport
transfer is about to begin. The first 8 clock cycles of
SCLK after the falling edge of CS are always used to
receive the Command/Address byte from the
microcontroller.
The
Command/Address
byte
contains information detailing whether the second
byte transfer will be a read or a write operation and
at what address. The next 8 clock cycles are used to
transfer the data byte between the MT91L60/61 and
the microcontroller. At the end of the two-byte
transfer CS is brought high again to terminate the
session. The rising edge of CS will tri-state the
output driver of DATA1 which will remain tri-stated as
long as CS is high.
Intel processors utilize least significant bit first
transmission while Motorola/National processors
employ most significant bit first transmission. The
MT91L60/61
microport
automatically
accommodates these two schemes for normal data
bytes. However, to ensure decoding of the R/W and
Filter/Codec and Transducer Interface
Serial Port
Default Bypass
Decoder
-6.0 dB or
0 dB
Receiver
Driver
-6 dB
Side-tone
-9.96 to
+9. 96 dB
(3.32 dB steps)
HSPKR +
75Ω
HSPKR -
Handset
Receiver
(150Ω)
75Ω
Default Side-tone off
PCM
Din
Receive
Filter Gain
0 to -7 dB
(1 dB steps)
-11 dB
PCM
Dout
Encoder
Transmit Filter
Gain
Gain
to +7 dB
0(10todB
+7
dB
steps)
Transmit Gain
-0.37 dB or 8.93 dB
Transmit
Gain
6.37 dB
Internal To Device
M+
M-
Transmitter
Microphone
External To Device
Figure 3 - Audio Gain Partitioning
5
MT91L60/61
address information, the Command/Address byte is
defined differently for Intel operation than it is for
Motorola/National operation. Refer to the relative
timing diagrams of Figures 5 and 6.
Receive data is sampled on the rising edge of SCLK
while transmit data is made available concurrent with
the falling edge of SCLK.
Flexible Digital Interface
A serial link is required to transport data between the
MT91L60/61 and an external digital transmission
device. The MT91L60/61 utilizes the ST-BUS
architecture defined by Mitel Semiconductor but also
supports a strobed data interface found on many
standard Codec devices. This interface is commonly
referred to as Simple Serial Interface (SSI). The
combination of ST-BUS and SSI provides a Flexible
Digital Interface (FDI) capable of supporting all Mitel
basic rate transmission devices as well as many
other 2B+D transceivers.
The required mode of operation is selected via the
CSL2-0 control bits (Control Register 2, address
04h). Pin definitions alter dependent upon the
operational mode selected, as described in the
following subsections as well as in the Pin
Description tables.
Quiet Code
The FDI can be made to send quiet code to the
decoder and receive filter path by setting the RxMute
bit high. Likewise, the FDI will send quiet code in the
transmit path when the TxMute bit is high. Both of
these control bits reside in Control Register 1 at
address 03h. When either of these bits are low their
respective paths function normally. The -Zero entry
of Table 1 is used for the quiet code definition.
ST-BUS Mode
The ST-BUS consists of output (DSTo) and input
(DSTi) serial data streams, in FDI these are named
Dout and Din respectively, a synchronous clock input
signal CLOCKin (C4i), and a framing pulse input
(F0i). These signals are direct connections to the
corresponding pins of Mitel basic rate devices. The
CSL2, CSL1 and CSL0 bits are set to 1 for ST-BUS
operation.
The data streams operate at 2048 kb/s and are Time
Division Multiplexed into 32 identical channels of 64
kb/s bandwidth. A frame pulse (a 244 nSec low going
pulse) is used to separate the continuous serial data
streams into the 32 channel TDM frames. Each
frame has a 125 µSecond period translating into an 8
kHz frame rate. A valid frame begins when F0i is
6
Preliminary Information
logic low coincident with a falling edge of C4i. Refer
to Figure 11 for detailed ST-BUS timing. C4i has a
frequency (4096 kHz) which is twice the data rate.
This clock is used to sample the data at the 3/4
bit-cell position on DSTi and to make data available
on DSTo at the start of the bit-cell. C4i is also used to
clock the MT91L60/61 internal functions (i.e., Filter/
Codec, Digital gain and tone generation) and to
provide the channel timing requirements.
The MT91L60/61 uses only the first four channels of
the 32 channel frame. These channels are always
defined, beginning with Channel 0 after the frame
pulse, as shown in Figure 6 (ST-BUS channel
assignments). The MT91L60/61 provides a delayed
frame pulse (F0od), 4 channels after the input frame
pulse.
The first two (D & C) Channels are enabled for use
by the DEN and CEN bits respectively, (Control
Register 2, address 04h). ISDN basic rate service
(2B+D) defines a 16 kb/s signalling (D) Channel. The
MT91L60/61 supports transparent access to this
signalling channel. ST-BUS basic rate transmission
devices, which may not employ a microport, provide
access to their internal control/status registers
through the ST-BUS Control (C) Channel. The
MT91L60/61 supports microport access to this
C-Channel.
DEN - D-Channel
In ST-BUS mode access to the D-Channel (transmit
and receive) data is provided through an 8-bit read/
write register (address 06h). D-Channel data is
accumulated in, or transmitted from this register at
the rate of 2 bits/frame for 16 kb/s operation (1 bit/
frame for 8 kb/s operation). Since the ST-BUS is
asynchronous, with respect to the microport, valid
access to this register is controlled through the use
of an interrupt (IRQ) output. D-Channel access is
enabled via the (DEn) bit.
DEN:
When 1, ST-BUS D-channel data (1 or 2 bits/frame
depending on the state of the D8 bit) is shifted into/
out of the D-channel (READ/WRITE) register.
When 0, the receive D-channel data (READ) is still
shifted into the proper register while the DSTo
D-channel timeslot and IRQ outputs are tri-stated
(default).
D8:
When 1, D-Channel data is shifted at the rate of 1 bit/
frame (8 kb/s).
MT91L60/61
Advance Information
When 0, D-Channel data is shifted at the rate of 2
bits/frame (16 kb/s default).
16 kb/s D-Channel operation is the default mode
which allows the microprocessor access to a full byte
of D-Channel information every fourth ST-BUS
COMMAND/ADDRESS ➄
➀
frame. By arbitrarily assigning ST-BUS frame n as
the
reference
frame,
during
which
the
microprocessor D-Channel read and write operations
are performed, then:
DATA INPUT/OUTPUT
➃ COMMAND/ADDRESS:
➀
DATA 1
RECEIVE D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
DATA 1
TRANSMIT
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
SCLK ②
➃
CS
➂
➂
➀ Delays due to internal processor timing which are transparent.
② The MT91L60/L61:latches received data on the rising edge of SCLK.
-outputs transmit data on the falling edge of SCLK.
➂ The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The
subsequent byte is always data until terminated via CS returning high.
➃ A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.
D7
➄ The COMMAND/ADDRESS byte contains: 1 bit - Read/Write
3 bits - Addressing Data
X
X
A2
A1
X
X
4 bits - Unused
D0
A0
R/W
Figure 4 - Serial Port Relative Timing for Intel Mode 0
COMMAND/ADDRESS ➄
➀
DATA INPUT/OUTPUT
➃ COMMAND/ADDRESS:
➀
DATA 2
RECEIVE D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
DATA 1
TRANSMIT
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SCLK ②
➃
CS
➂
➂
➀ Delays due to internal processor timing which are transparent .
② The MT91L60/L61: latches received data on the rising edge of SCLK.
-outputs transmit data on the falling edge of SCLK.
➂ The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The
subsequent byte is always data until terminated via CS returning high.
➃ A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.
D7
➄ The COMMAND/ADDRESS byte contains: 1 bit - Read/Write
3 bits - Addressing Data
A2
4 bits - Unused
X
X
R/W
X
A1
D0
A0
X
Figure 5 - Serial Port Relative Timing for Motorola Mode 00/National Microwire
7
MT91L60/61
Advance Information
125 µs
F0i
DSTi,
DSTo
CHANNEL 0
D-channel
FOod
LSB first
for DChannel
CHANNEL 1
C-channel
CHANNEL 2
B1-channel
CHANNEL 3
B2-channel
MSB first for C, B1- & B2Channels
Figure 6 - ST-BUS
(a) A microport read of address 04 hex will result in a
byte of data being extracted which is composed of
four di-bits (designated by roman numerals I,II,III,IV).
These di-bits are composed of the two D-Channel
bits received during each of frames n, n-1, n-2 and
n-3. Referring to Fig. 7a: di-bit I is mapped from
frame n-3, di-bit II is mapped from frame n-2, di-bit III
is mapped from frame n-1 and di-bit IV is mapped
from frame n.
The D-Channel read register is not preset to any
particular value on power-up (PWRST) or software
reset (RST).
(b) A microport write to Address 04 hex will result in
a byte of data being loaded which is composed of
four di-bits (designated by roman numerals I, II, III,
IV). These di-bits are destined for the two D-Channel
bits transmitted during each of frames n+1, n+2, n+3,
n+4. Referring to Fig. 7a: di-bit I is mapped to frame
n+1, di-bit II is mapped to frame n+2, di bit III is
mapped to frame n+3 and di bit IV is mapped to
frame n+4.
If no new data is written to address 04 hex , the
current D-channel register contents will be
continuously re-transmitted. The D-Channel write
register is preset to all ones on power-up (PWRST)
or software reset (RST).
An interrupt output is provided (IRQ) to synchronize
microprocessor access to the D-Channel register
during valid ST-BUS periods only. IRQ will occur
every fourth (eighth in 8 kb/s mode) ST-BUS frame
at the beginning of the third (second in 8 kb/s mode)
ST-BUS bit cell period. The interrupt will be removed
following a microprocessor Read or Write of Address
04 hex or upon encountering the following frames F0i
input, whichever occurs first. To ensure D-Channel
data integrity, microport read/write access to
Address 04 hex must occur before the following
frame pulse. See Figure 7b for timing.
8
CHANNELS 4-31
Not Used
Channel Assignment
8 kb/s operation expands the interrupt to every eight
frames and processes data one-bit-per-frame.
D-Channel register data is mapped according to
Figure 7c.
CEn - C-Channel
Channel 1 conveys the control/status information for
the Layer 1 transceiver. C-Channel data is
transferred MSB first on the ST-BUS by the
MT91L60/61. The full 64 kb/s bandwidth is available
and is assigned according to which transceiver is
being used. Consult the data sheet for the selected
transceiver for its C-Channel bit definitions and order
of bit transfer.
When CEN is high, data written to the C-Channel
register (address 05h) is transmitted, most
significant bit first, on DSTo. On power-up reset
(PWRST) or software reset (Rst, address 03h) all
C-Channel bits default to logic high.
Receive
C-Channel data (DSTi) is always routed to the read
register regardless of this control bit's logic state.
When low, data transmission is halted and this
timeslot is tri-stated on DSTo.
B1-Channel and B2-Channel
Channels 2 and 3 are the B1 and B2 channels,
respectively. B-channel PCM associated with the
Filter/Codec and transducer audio paths is selected
on an independent basis for the transmit and receive
paths. TxBSel and RxBSel (Control Register 1,
address 03h) are used for this purpose.
If no valid transmit path has been selected then the
timeslot output on DSTo is tri-stated (see PDFDI and
PDDR control bits, Control Register 1 address 03h).
MT91L60/61
Advance Information
IRQ
Microport Read/Write Access
FP
n-3
n-2
n-1
n
n+1
n+2
n+3
n+4*
DSTo/
DSTi
Di-bit Group
Receive
D0
D-Channel
I
II
D1 D2
D3
No preset value
D4
III
IV
D5 D6
D7
Di-bit Group
Transmit D0
D-Channel
I
D1 D2
II
D3
D4
III
D5 D6
IV
D7
Power-up reset to 1111 1111
* note that frame n+4 is equivalent to frame n of the next cycle.
Figure 7a - D-Channel 16 kb/s Operation
FP
C4i
C2
DSTo/
DSTi
D0
tir =500 nsec max
Rpullup= 10 k
D1
tif =500 nsec max
IRQ
8 kb/s operation
16 kb/s operation
Reset coincident with
Read/Write of Address 04 Hex
or next FP, whichever occurs first
Microport Read/Write Access
Figure 7b - IRQ Timing Diagram
IRQ
Microport Read/Write Access
FP
n-7
n-6
n-5
n-4
n-3
n-2
n-1
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
D-Channel
Di-bit Group
Receive
D-Channel
I
D0
II
D1
III
D2
IV
D3
No preset value
V
D4
VI
D5
VII
D6
VIII
D7
Di-bit Group
Transmit
D-Channel
I
D0
II
D1
III
D2
IV
D3
V
D4
VI
D5
VII
D6
VIII
D7
Power-up reset to 1111 1111
Figure 7c - D-Channel 8 kb/s Operation
9
MT91L60/61
SSI Mode
The SSI BUS consists of input and output serial data
streams named Din and Dout respectively, a Clock
input signal (CLOCKin), and a framing strobe input
(STB). The frame strobe must be synchronous with,
and eight cycles of, the bit clock. A 4.096 MHz
master clock is also required for SSI operation if the
bit clock is less than 512 kHz. The timing
requirements for SSI are shown in Figures 12 & 13.
In SSI mode the MT91L60/61 supports only
B-Channel operation. The internal C and D Channel
registers used in ST-BUS mode are not functional for
SSI operation. The control bits TxBSel and RxBSel,
as described in the ST-BUS section, are ignored
since the B-Channel timeslot is defined by the input
STB strobe. Hence, in SSI mode transmit and
receive B-Channel data are always in the channel
defined by the STB input.
The data strobe input STB determines the 8-bit
timeslot used by the device for both transmit and
receive data. This is an active high signal with an 8
kHz repetition rate.
The MT91L61 provides a
delayed strobe pulse which occurs after the initial
strobe goes low and is held high for the duration of 8
pcm bits.
SSI operation is separated into two categories based
upon the data rate of the available bit clock. If the bit
clock is 512 kHz or greater then it is used directly by
the internal MT91L60/61 functions allowing
synchronous operation. If the available bit clock is
128 kHz or 256 kHz, then a 4096 kHz master clock is
required to derive clocks for the internal MT91L60/61
functions.
Applications where Bit Clock (BCL) is below 512 kHz
are designated as asynchronous. The MT91L60/61
will re-align its internal clocks to allow operation
when the external master and bit clocks are
asynchronous. Control bits CSL2, CSL1 and CSL0 in
Control Register 2 (address 04h) are used to
program the bit rates.
For synchronous operation data is sampled, from
Din, on the falling edge of BCL during the time slot
defined by the STB input. Data is made available, on
Dout, on the rising edge of BCL during the time slot
defined by the STB input. Dout is tri-stated at all
times when STB is not true. If STB is valid and
PDDR is set, then quiet code will be transmitted on
Dout during the valid strobe period. There is no
frame delay through the FDI circuit for synchronous
operation.
10
Preliminary Information
For asynchronous operation Dout and Din are as
defined for synchronous operation except that the
allowed output jitter on Dout is larger. This is due to
the resynchronization circuitry activity and will not
affect operation since the bit cell period at 128 kb/s
and 256 kb/s is relatively large. There is a one frame
delay through the FDI circuit for asynchronous
operation. Refer to the specifications of Figures 12
& 13 for both synchronous and asynchronous SSI
timing.
PWRST/Software Reset (Rst)
While the MT91L60/61 is held in PWRST no device
control or functionality is possible. While in software
reset (Rst=1, address 03h) only the microport is
functional. Software reset can only be removed by
writing the Rst bit low or by performing a hardware
PWRST. While the Rst bit is high, the other bits in
Control Register 1 are held low and cannot be
reprogrammed. Therefore to modify Control Register
1 the Rst bit must first be written low, followed by a
2nd write operation which writes the desired data.
This avoids a race condition between clearing the
reset bit and the writing of the other bits in Control
Register 1.
After a Power-up reset (PWRST) or software reset
(Rst) all control bits assume their "Power Reset
Value" default states; µ-Law coding, 0 dB Rx and
6dB Tx gains and the device powered up in SSI
mode 2048 kb/s operation with Dout tri-stated while
there is no strobe active on STB. If a valid strobe is
supplied to STB, then Dout will be active, during the
defined channel.
To attain complete power-down from a normal
operating condition, write PDFDI = 1 and PDDR = 1
(Control Register 1, address 03h) or set the PWRST
pin low.
MT91L60/61
Advance Information
Applications
Figure 8 shows an application in a wireless phone
set. Figure 9 shows an MT9161B’s delayed frame
pulse driving a second MT9161B. This configuration
would be used where multiple CODEC’s were using
a data bus (an example being Mitel’s ST-BUS).
00
RxINC
RxFG2
RxFG1
RxFG0
TxINC
TxFG2
TxFG1
TxFG0
Gain Control
Register 1
01
-
-
-
-
-
STG2
STG1
STG0
Gain Control
Register 2
02
-
-
-
-
-
-
-
DrGain
Path Control
03
PDFDI
PDDR
RST
-
TxMute
RxMute
TxBsel
04
CEN
DEN
D8
A/µ
Smag/
ITU-T
CSL2
CSL1
CSL0
Control Register 2
05
C7
C6
C5
C4
C3
C2
C1
C0
C-Channel
Register
06
D7
D6
D5
D4
D3
D2
D1
D0
D-Channel
Register
07
-
-
-
-
PCM/
ANALOG
loopen
-
-
Loop Back
RxBsel Control Register 1
Table 2: 3V Multi-featured Codec Register Map
Note: Bits marked "-" are reserved bits and should be written with logic "0"
11
MT91L60/61
Advance Information
330Ω
+3V
+
+
330Ω
M+
-
10 µF
0.1 µF 100K
511Ω
+
Electret
Microphone
10 µF
R
T Av = 1 + 2R
T
VBias
0.1 µF
VBias
+3V
+
M+
-
0.1 µF
1K
+
T
+
Electret
Microphone
R
VBias
R
100K
Single-ended Amplifier
-
511Ω
M-
+
Differential Amplifier
0.1 µF
VBias
(
)
Typical External Gain
AV= 5-10
M+
M-
0.1 µF
0.1 µF
100K
+3V
A/µ/IRQ
3V
INTEL
MCS-51
or
MOTOROLA
SPI
MicroController
CS
SCLK
DATA1
DATA2
DATA2 Motorola
Mode only
1
2
3
4
5
6
7
8
9
10
MT91L60
20
19
18
17
16
15
14
13
12
11
75Ω
+3V
150Ω
75Ω
Din
Wireless
Dout
Phone
Baseband
Processer
Figure 8 - Wireless Phone Set
12
Frame Pulse
Clock
M-
MT91L60/61
Advance Information
VBias
0.1 µF
(
)
Typical External Gain
AV= 5-10
M+
M-
0.1 µF
0.1 µF
1
100K
+3V
3V
INTEL
MCS-51
or
MOTOROLA
SPI
MicroController
24
23
2
3
4
A/µ/IRQ
5
6
CS
7
8
9
SCLK
DATA1
DATA2
DATA2 Motorola
Mode only
MT91L61
10
11
12
22
21
20
19
18
17
16
15
75Ω
+3V
150Ω
75Ω
14
13
Din
Dout
Timing
from
Frame Pulse
PC Bus
Clock
0.1 µF
VBias
MM+
0.1 µF
1
24
23
2
3
4
+3V
A/µ/IRQ
CS
SCLK
DATA1
DATA2
DATA2 Motorola
Mode only
5
6
7
8
9
10
11
12
MT91L61
22
21
20
19
18
17
16
15
75Ω
+3V
75Ω
150Ω
14
13
Figure 9 - Delayed Frame Pulse of First MT91L61 Signalling Second MT91L61
13
MT91L60/61
Advance Information
Register Summary
Gain Control Register 1
ADDRESS = 00h WRITE/READ VERIFY
Power Reset Value
1000 0000
RxINC RxFG2 RxFG1 RxFG0 TxINC TxFG2 TxFG1 TxFG0
7
6
5
4
3
2
1
0
Receive Gain
Setting (dB)
RxFG2
RxFG1
RxFG0
Transmit Gain
Setting (dB)
TxFG2
TxFG1
TxFG0
(default) 0
-1
-2
-3
-4
-5
-6
-7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
(default) 0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
RxFGn = Receive Filter Gain bit n
TxFGn = Transmit Filter Gain bit n
RxINC: When high, the receive path nominal gain is set to 0 dB. When low, this gain is -6.0 dB.
TxINC: When high, the transmit path nominal gain is set to 15.3 dB. When low, this gain is 6.0 dB.
Gain Control Register 2
ADDRESS = 01h WRITE/READ VERIFY
-
-
-
-
-
STG2
STG1
STG0
7
6
5
4
3
2
1
0
Side-tone Gain
Setting (dB)
STG2
STG1
STG0
(default) OFF
-9.96
-6.64
-3.32
0
3.32
6.64
9.96
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
STGn = Side-tone Gain bit n
Note: Bits marked "-" are reserved bits and should be written with logic "0"
14
Power Reset Value
XXXX X000
MT91L60/61
Advance Information
Path Control
ADDRESS = 02h WRITE/READ VERIFY
7
DrGain
-
-
-
-
-
-
DrGain
6
5
4
3
2
1
0
When high, the receive path is summed with the side tone path and is attenuated by 6dB.
When low, the receive path conatins no side tone (default).
Control Register 1
ADDRESS = 03h WRITE/READ VERIFY
PDFDI PDDR
7
PDFDI
PDDR
Rst
TxMute
RxMute
TxBsel
RxBsel
Power Reset Value
XX00 0000
6
Rst
_
5
4
TxMute RxMute TxBsel RxBsel
3
2
1
Power Reset Value
0000 0000
0
When high, the FDI PLA and the Filter/Codec are powered down (default). When low, the FDI is active.
When high, the ear driver and Filter/Codec are powered down (default). In addition, in ST-BUS mode, the selected
output channel is tri-stated. In SSI mode the PCM output code will be -zero code during the valid strobe period. The
output will be tri-stated outside of the valid strobe and for the whole frame if no strobe is supplied. When low, the driver
and Filter/Codec are active if PDFDI is low.
When high, a software reset occurs performing the same function as the hardware reset (PWRST) except that the Rst
bit remains high and device remains powered up. A software reset can be removed only by writing this bit low or by
means of a hardware reset (PWRST). This bit is useful for quickly programming the Registers to the default Power
Reset Values. When this bit is low, the reset condition is removed allowing the registers to be modified
When high the transmit PCM stream is interrupted and replaced with quiet code; thus forcing the output code into a
mute state (only the output code is muted, the transmit microphone and transmit Filter/Codec are still functional). When
low the full transmit path functions normally (default).
When high the received PCM stream is interrupted and replaced with quiet code; thus forcing the receive path into a
mute state. When low the full receive path functions normally (default).
When high, the transmit B2 channel is functional in ST-BUS mode. When low, the transmit B1 channel is functional in
ST-BUS mode. Not used in SSI mode.
When high, the receive B2 channel is functional in ST-BUS mode. When low, the receive B1 channel is functional in
Note: Bits marked "-" are reserved bits and should be written with logic "0"
15
MT91L60/61
Advance Information
Control Register 2
CEn
ADDRESS = 04h WRITE/READ VERIFY
DEn
D8
A/µ
6
5
4
7
CEn
Smag/
ITU-T
3
CSL2 CSL1
2
1
Power Reset Value
0000 0010
CSL0
0
When high, data written into the C-Channel register (address 05h) is transmitted during channel 1 on DSTo. When
low, the channel 1 timeslot is tri-stated on DSTo. Channel 1 data received on DSTi is read via the C-Channel
register (address 05h) regardless of the state of CEn. This control bit has significance only for ST-BUS operation
and is ignored for SSI operation.
When high, data written into the D-Channel Register (address 06h) is transmitted (2 bits/frame) during channel 0
on DSTo. The remaining six bits of the D-Channel carry no information. When low, the channel 0 timeslot is
completely tri-stated on DSTo. Channel 0 data received on DSTi is read via the D-Channel register regardless of
the state of DEN. This control bit has significance only for ST-BUS mode and is ignored for SSI operation.
When high, D-channel operates at 8kb/s. When low, D-channel operates at 16kb/s (default).
When high, A-Law encoding/decoding is selected for the MT91L60/61. When low, µ-Law encoding/decoding is
selected.
When high, sign-magnitude code assignment is selected for the Codec input/output. When low, ITU-T code
assignment is selected for the Codec input/output; true sign, inverted magnitude (µ-Law) or true sign, alternate
digit inversion (A-Law).
DEn
D8
A/µ
Smag/ITU-T
CSL2
CSL1
CSL0
Bit Clock rate (kHz)
CLOCKin (kHz)
Mode
1
1
1
N/A
4096
ST-BUS
1
0
0
128
4096
SSI
1
0
1
256
4096
SSI
0
0
0
512
512
SSI
0
0
1
1536
1536
SSI
0
1
0
2048
2048
SSI (default)
0
1
1
4096
4096
SSI
Note: Bits marked "-" are reserved bits and should be written with logic "0"
16
MT91L60/61
Advance Information
C-Channel Register
ADDRESS = 05h WRITE/READ
C7
C6
C5
C4
C3
C2
C1
C0
7
6
5
4
3
2
1
0
Power Reset Value
1111 1111- write
XXXX XXXX - read
Micro-port access to the ST-BUS C-Channel information read and write
D-Channel Register
D7-D0
ADDRESS = 06h WRITE/READ
D7
D6
7
6
D5
D4
5
4
D3
D2
D1
D0
3
2
1
0
Power Reset Value
1111 1111- write
XXXX XXXX - read
Data written to this register will be transmitted every frame, in channel 0, if the DEn control bit is set (address 04h).
Received D-Channel data is valid, regardless of the state of DEn. These bits are valid for ST-BUS mode only and are
accessible only when IRQ indicates valid access.
ADDRESS = 07h WRITE/READ VERIFY
Loopback Register
-
-
-
-
7
6
5
4
PCM/
ANALOG
3
loopen
-
-
2
1
0
Power Reset Value
XXXX 0000
PCM/ANALOG This control bit functions only when loopen is set high. It is ignored when loopen is low.
For loopback operation when this bit is high, the device is configured for digital-to-digital loopback operation. Data on
Din is looped back to Dout without conversion to the analog domain. However, the receive D/A path (from Din to
HSPKR ±) still functions. When low, the device is configured for analog-to-analog operation. An analog input signal at
M± is looped back to the SPKR± outputs through the A/D and D/A circuits as well as through the normal transmit A/D
path (from M± to Dout).
loopen
When high, loopback operation is enabled and the loopback type is governed by the state of the PCM/ANALOG bit.
When low, loopbacks are disabled, the device operates normally and the PCM/ANALOG bit is ignored.
HSPKR +/-
Dout
M +/-
Dout
Analog Loopback
PCM/ANALOG = 0
HSPKR +/-
Din
Digital Loopback
PCM/ANALOG = 1 loopen = 1
loopen = 1
Figure 10 - Loopback Signal Flow
Note: Bits marked "-" are reserved bits and should be written with logic "0"
17
MT91L60/61
Advance Information
Absolute Maximum Ratings†
Parameter
Symbol
Min
Max
Units
VDD - VSS
- 0.3
5
V
VI/VO
VSS - 0.3
VDD + 0.3
V
± 20
mA
+ 150
°C
750
mW
1
Supply Voltage
2
Voltage on any I/O pin
3
Current on any I/O pin (transducers excluded)
II/IO
4
Storage Temperature
TS
5
Power Dissipation (package)
PD
- 65
† Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions Characteristics
Voltages are with respect to VSS unless otherwise stated
Sym
Min
Typ
Max
Units
3
3.6
V
1
Supply Voltage
VDD
2.7
2
CMOS Input Voltage (high)
VIHC
0.9*VDD
VDD
V
3
CMOS Input Voltage (low)
VILC
VSS
0.1*VDD
V
4
Operating Temperature
TA
- 40
+ 85
°C
Test Conditions
Power Characteristics
Characteristics
Sym
Min
Typ
Max
Units
1
Static Supply Current (clock
disabled, all functions off, PDFDI/
PDDR=1, PWRST=0)
IDDC1
2
20
µA
Outputs unloaded, Input
signals static, not loaded
2
Dynamic Supply Current:
Total all functions enabled
IDDFT
6
10
mA
See Note 1.
Note 1: Power delivered to the load is in addition to the bias current requirements.
18
Test Conditions
MT91L60/61
Advance Information
DC Electrical Characteristics† - Voltages are with respect to ground (VSS)
Typ‡
unless otherwise stated.
Characteristics
Sym
Min
Max
Units
Test Conditions
1
Input HIGH Voltage CMOS inputs
VIHC
0.7*Vdd
2
Input LOW Voltage CMOS inputs
VILC
3
VBias Voltage Output
VBias
VDD/2
V
Max. Load = 20kΩ
4
VRef Voltage Output
VRef
VDD/2-1.1
V
No Load
5
Input Leakage Current
IIZ
0.1
µA
VIN=VDD to VSS
6
Positive Going Threshold
Voltage (PWRST only)
Negative Going Threshold
Voltage (PWRST only)
Hysteresis
VT+
V
Vdd = 3V
7
Output HIGH Current
IOH
1.0
mA
VOH = 0.9*VDD
See Note 1
8
Output LOW Current
IOL
2.5
mA
VOL = 0.1*VDD
See Note 1
9
Output Leakage Current
IOZ
0.01
µA
VOUT = VDD and VSS
10
Output Capacitance
Co
15
pF
11
Input Capacitance
Ci
10
pF
V
0.3*Vdd
10
2.2
VT-
0.7
V
V
0.65
V
10
† DC Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.
* Note 1 - Magnitude measurement, ignore signs.
Clockin Tolerance Characteristics† (ST-BUS Mode)
Characteristics
1
C4i Frequency
Min
Typ‡
Max
Units
4095.6
4096
4096.4
kHz
Test Conditions
(i.e., 100 ppm)
† AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.
19
MT91L60/61
Advance Information
AC Characteristics† for A/D (Transmit) Path - 0dBm0 = ALo3.17 - 3.17dB = 1.027Vrms for µ-Law and 0dBm0 = ALo3.14
- 3.14dB =1.067Vrms for A-Law, at the Codec. (VRef = 0.4V and VBias=1.5 volts.)
Characteristics
1
Analog input equivalent to
overload decision
2
Absolute half-channel gain
M ± to Dout
Sym
Min
ALi3.17
ALi3.14
GAX1
GAX2
Tolerance at all other transmit
filter settings
(1 to 7dB)
Typ‡
Max
4.246
4.4
Units
Vp-p
Vp-p
Test Conditions
µ-Law
A-Law
Both at Codec
Transmit filter gain=0dB
setting.
TxINC = 0*
TxINC = 1*
@1020 Hz
5.4
14.7
6.0
15.3
6.6
15.9
dB
dB
-0.2
±0.1
+0.2
dB
0.3
0.6
1.6
dB
dB
dB
3 to -40 dBm0
-40 to -50 dBm0
-50 to -55 dBm0
dB
dB
dB
0 to -30 dBm0
-40 dBm0
-45 dBm0
3
Gain tracking vs. input level
ITU-T G.714 Method 2
GTX
-0.3
-0.6
-1.6
4
Signal to total Distortion vs. input
level.
ITU-T G.714 Method 2
DQX
35
29
24
5
Transmit Idle Channel Noise
NCX
NPX
6
Gain relative to gain at 1020Hz
<50Hz
60Hz
200Hz
300 - 3000 Hz
3000-3300 Hz
3300 Hz
3400 Hz
4000 Hz
4600 Hz
>4600 Hz
GRX
7
Absolute Delay
DAX
360
µs
at frequency of minimum
delay
8
Group Delay relative to DAX
DDX
750
380
130
750
µs
µs
µs
µs
500-600 Hz
600 - 1000 Hz
1000 - 2600 Hz
2600 - 2800 Hz
9
Power Supply Rejection
dB
±100mV peak signal on
VDD
µ-law
f=1020 Hz
13
-70.5
-45
-0.25
-0.9
-0.9
-1.2
PSSR
30
-0.2
-0.6
-23
-41
50
16
-69
dBrnC0
dBm0p
-25
-30
0.0
0.25
0.25
0.25
0.25
-12.5
-25
-25
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
µ-Law
A-Law
† AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.
* Note: TxINC, refer to Control Register 1, address 00h.
20
MT91L60/61
Advance Information
AC Characteristics† for D/A (Receive) Path - 0dBm0 = ALo3.17 - 3.17dB = 1.027Vrms for µ-Law and 0dBm0 = ALo3.14
- 3.14dB =1.067Vrms for A-Law, at the Codec.
(VRef = 0.4V and VBias=1.5 volts.)
Characteristics
Sym
1
Analog output at the Codec full
scale
ALo3.17
ALo3.14
2
Absolute half-channel gain.
Din to HSPKR±
GAR1
GAR2
GAR3
GAR4
Tolerance at all other receive
filter settings
(-1 to -7dB)
Min
Typ‡
Max
4.183
4.331
Units
Vp-p
Vp-p
Test Conditions
µ-Law
A-Law
-0.6
-6.6
-6.6
-12.6
0
-6
-6
-12
0.6
-5.4
-5.4
-11.4
dB
dB
dB
dB
DrGain=0, RxINC =1*
DrGain=0, RxINC =0*
DrGain=1, RxINC =1*
DrGain=1, RxINC =0*
@ 1020 Hz
-0.2
±0.1
+0.2
dB
0.3
0.6
1.6
dB
dB
dB
3 to -40 dBm0
-40 to -50 dBm0
-50 to -55 dBm0
dB
dB
dB
0 to -30 dBm0
-40 dBm0
-45 dBm0
3
Gain tracking vs. input level
ITU-T G.714 Method 2
GTR
-0.3
-0.6
-1.6
4
Signal to total distortion vs.
input level.
ITU-T G.714 Method 2
GQR
35
29
24
5
Receive Idle Channel Noise
NCR
NPR
6
Gain relative to gain at 1020Hz
200 Hz
300 - 3000 Hz
3000 - 3300 Hz
3300 Hz
3400 Hz
4000 Hz
4600 Hz
>4600 Hz
GRR
7
Absolute Delay
DAR
240
µs
at frequency of min. delay
8
Group Delay relative to DAR
DDR
750
380
130
750
µs
µs
µs
µs
500-600 Hz
600 - 1000 Hz
1000 - 2600 Hz
2600 - 2800 Hz
9
Crosstalk
CTRT
CTTR
-90
-90
dB
dB
ITU-T
G.714.16
D/A to A/D
A/D to D/A
11.5
-80
-0.25
-0.90
-0.9
-0.9
-0.1
-0.5
-23
-41
14
-77
dBrnC0
dBm0p
0.25
0.25
0.25
0.25
0.25
-12.5
-25
-25
dB
dB
dB
dB
dB
dB
dB
dB
-74
-80
µ-Law
A-Law
† AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.
* Note: RxINC, refer to Control Register 1, address 00h.
21
MT91L60/61
Advance Information
AC Electrical Characteristics† for Side-tone Path
Characteristics
1
Absolute path gain
gain adjust = 0dB
2
Tolerance of other side-tone
settings (-9.96 to 9.96 dB)
relative to output at 0dB setting
Sym
Min
Typ‡
Max
Units
GAS1
GAS2
-17.1
-11.1
-16.5
-10.5
-15.9
-9.9
dB
dB
-0.5
+/-0.2
+0.5
dB
Test Conditions
RxINC = 0*
RxINC = 1*
M± inputs to HSPKR± outputs
1000 Hz at STG2=1
† AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.
* Note: RxINC, refer to Control Register 1, address 00h.
Electrical Characteristics† for Analog Outputs
Characteristics
Sym
Min
Typ‡
260
300
ohms
Max
Units
Test Conditions
1
EarpIece load impedance
EZL
across HSPKR±
2
Allowable earpiece capacitive
load
ECL
300
pF
each pin:
3
Earpiece harmonic distortion
ED
0.5
%
300 ohms load across
HSPKR± (tol-15%),
VO≤693mVRMS, RxINC=1*,
Rx gain=0dB
HSPKR+,
HSPKR-
† Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.
* Note: RxINC, refer to Control Register 1, address 00h.
Electrical Characteristics† for Analog Inputs
Characteristics
1
Sym
Min
Typ‡
Max
Units
Test Conditions
Maximum input voltage without
overloading Codec
across M+/M-
VIOLH
2.128
0.756
Vp-p
Vp-p
TxINC = 0, A/µ = 0*
TxINC = 1, A/µ = 1*
Tx filter gain=0dB setting
2 Input Impedance
ZI
50
kΩ
M+/M† Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.
* Note: TxINC, refer to Control Register 1, address 00h.
22
to VSSA
MT91L60/61
Advance Information
AC Electrical Characteristics† - ST-BUS Timing (See Figure 11)
Characteristics
Sym
Min
Typ‡
Max
Units
1
C4i Clock Period
tC4P
244
ns
2
C4i Clock High period
tC4H
122
ns
3
C4i Clock Low period
tC4L
122
ns
4
C4i Clock Transition Time
tT
20
ns
5
F0i Frame Pulse Setup Time
tF0iS
50
ns
6
F0i Frame Pulse Hold Time
tF0iH
50
ns
7
Delayed Frame Pulse delay
after C4i rising
tF0odS
55
ns
8
Delayed Frame Pulse hold
time from C4i rising
tF0odH
50
ns
9
DSTo Delay
tDSToD
125
ns
10
DSTi Setup Time
tDSTiS
20
Test Conditions
CL = 30pF, 1kΩ load.*
ns
11 DSTi Hold Time
tDSTiH
50
ns
† Timing is over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.
* Note: All conditions → data-data, data-HiZ, HiZ-data.
tT
C4i
tT
1 bit cell
tC4P
tC4H
tC4L
70%
30%
tDSToD
DSTo
70%
30%
tDSTiS
DSTi
70%
30%
tT
F0i
tDSTiH
tF0iS
tF0iH
tT
70%
30%
tF0odS
F0od
tF0odH
70%
30%
64 Clock Periods
NOTE: Levels refer to %VDD
Figure 11 - ST-BUS Timing Diagram
23
MT91L60/61
Advance Information
AC Electrical Characteristics† - SSI BUS Synchronous Timing (see Figure 12)
Characteristics
Sym
Min
Typ‡
Max
Units
Test Conditions
1953
ns
BCL=4096 kHz to 512 kHz
122
ns
BCL=4096 kHz
1
BCL Clock Period
tBCL
244
2
BCL Pulse Width High
tBCLH
115
3
BCL Pulse Width Low
tBCLL
122
ns
BCL=4096 kHz
4
BCL Rise/Fall Time
tR/tF
ns
Note 1
5
Strobe Pulse Width
tENW
20
8 x tBCL
ns
Note 1
6
Delayed Strobe Pulse Width
tENWD
8 x tBCL
ns
Note 1
7
Strobe setup time before BCL falling
tSSS
70
tBCL-80
ns
8
Strobe hold time after BCL falling
tSSH
80
tBCL-80
ns
9
Delayed Strobe Pulse delay after BCL
rising
tDSTBR
55
ns
Note 1
10 Delayed Strobe Pulse hold time after
BCL rising
tDSTBF
55
ns
Note 1
11 Dout High Impedance to Active Low
from Strobe rising
tDOZL
55
ns
CL=50 pF, RL=1K
12 Dout High Impedance to Active High
from Strobe rising
tDOZH
55
ns
CL=50 pF, RL=1K
13 Dout Active Low to High Impedance
from Strobe falling
tDOLZ
90
ns
CL=50 pF, RL=1K
14 Dout Active High to High Impedance
from Strobe falling
tDOHZ
90
ns
CL=50 pF, RL=1K
15 Dout Delay (high and low) from BCL
rising
tDD
80
ns
CL=50 pF, RL=1K
16 Din Setup time before BCL falling
tDIS
10
ns
17 Din Hold Time from BCL falling
tDIH
50
ns
† Timing is over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
Note 1: Not production tested, guaranteed by design.
24
MT91L60/61
Advance Information
tBCL
tBCLH
tR
tF
CLOCKin 70%
(BCL)
30%
tBCLL
tDIS
Din
tDIH
70%
30%
tDD
tDOZL
Dout
70%
30%
tDOZH
STB
tDOLZ
tDOHZ
tSSH
tENW
tSSS
70%
30%
tDSTBR
tDSTBF
70%
STBd
30%
tENWD
NOTE: Levels refer to % VDD (CMOS I/O)
Figure 12 - SSI Synchronous Timing Diagram
AC Electrical Characteristics† - SSI BUS Asynchronous Timing (note 1) (see Figure 13)
Characteristics
1 Bit Cell Period
2 Frame Jitter
Sym
Min
TDATA
Typ‡
Max
7812
3906
Units
ns
ns
Test Conditions
BCL=128 kHz
BCL=256 kHz
Tj
600
ns
3 Bit 1 Dout Delay from STB
going high
tdda1
Tj+600
ns
CL=50 pF, RL=1K
4 Bit 2 Dout Delay from STB
going high
tdda2
600+
TDATA-Tj
600+
TDATA
600 +
TDATA+Tj
ns
CL=50 pF, RL=1K
5 Bit n Dout Delay from STB
going high
tddan
600 +
(n-1) x
TDATA-Tj
600 +
(n-1) x
TDATA
600 +
(n-1) x
TDATA+Tj
ns
CL=50 pF, RL=1K
n=3 to 8
TDATA1
TDATA-Tj
TDATA+Tj
ns
7 Din Bit n Data Setup time from
STB rising
tSU
TDATA\2
+500ns-Tj
+(n-1) x
TDATA
ns
8 Din Data Hold time from STB
rising
tho
TDATA\2
+500ns+Tj
+(n-1) x
TDATA
ns
6 Bit 1 Data Boundary
n=1-8
† Timing is over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
NOTE 1: Not production tested, guaranteed by design.
25
MT91L60/61
Advance Information
Tj
STB
70%
30%
tdda2
tdha1
tdda1
Dout
70%
Bit 1
30%
Bit 2
Bit 3
TDATA
TDATA1
tho
tsu
Din
70%
D2
D1
30%
TDATA/2
TDATA
D3
TDATA
NOTE: Levels refer to % VDD (CMOS I/O)
Figure 13 - SSI Asynchronous Timing Diagram
AC Electrical Characteristics† - Microport Timing (see Figure 14)
Characteristics
Sym
Min
Typ‡
Max
Units
1
Input data setup
tIDS
100
ns
2
Input data hold
tIDH
30
ns
3
Output data delay
tODD
4
Serial clock period
tCYC
500
1000
ns
5
SCLK pulse width high
tCH
250
500
ns
6
SCLK pulse width low
tCL
250
500
ns
7
CS setup-Intel
tCSSI
200
ns
8
CS setup-Motorola
tCSSM
100
ns
9
CS hold
tCSH
100
ns
10
CS to output high impedance
tOHZ
120
120
ns
ns
Test Conditions
CL = 50pF, RL = 1K *
CL = 50pF, RL = 1K
† Timing is over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* Note: All conditions → data-data, data-HiZ, HiZ-data.
26
MT91L60/61
Advance Information
2.0V
DATA INPUT
0.8V
tIDS
HiZ
0.8V
tIDH
10%
Intel
Mode = 0
tODD
tCYC
tCH
90%
2.0V
DATA OUTPUT
2.0V
SCLK
0.8V
tCSSI
tOHZ
tCL
2.0V
CS
0.8V
tCSSM
tCSH
tCH
2.0V
SCLK
Motorola
Mode = 00
0.8V
tCL
tCYC
tODD
tIDH
DATA OUTPUT
2.0V
0.8V
90%
HiZ
10%
tIDS
2.0V
DATA INPUT
0.8V
NOTE: % refers to % VDD
Figure 14 - Microport Timing
27
Package Outlines
Pin 1
E
A
C
L
H
e
Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
4) Ref. JEDEC Standard M0-150/M0118 for 48 Pin
5) A & B Maximum dimensions include allowable mold flash
D
A2
A1
B
20-Pin
24-Pin
28-Pin
48-Pin
Dim
Min
A
A1
0.002
(0.05)
B
0.0087
(0.22)
C
Max
Min
Max
0.079
(2)
-
0.079
(2)
0.002
(0.05)
0.013
(0.33)
0.0087
(0.22)
0.008
(0.21)
Min
Max
Min
Max
0.079
(2)
0.095
(2.41)
0.110
(2.79)
0.008
(0.2)
0.016
(0.406)
0.008
(0.2)
0.0135
(0.342)
0.002
(0.05)
0.013
(0.33)
0.0087
(0.22)
0.008
(0.21)
0.013
(0.33)
0.008
(0.21)
0.010
(0.25)
D
0.27
(6.9)
0.295
(7.5)
0.31
(7.9)
0.33
(8.5)
0.39
(9.9)
0.42
(10.5)
0.62
(15.75)
0.63
(16.00)
E
0.2
(5.0)
0.22
(5.6)
0.2
(5.0)
0.22
(5.6)
0.2
(5.0)
0.22
(5.6)
0.291
(7.39)
0.299
(7.59)
e
0.025 BSC
(0.635 BSC)
0.025 BSC
(0.635 BSC)
0.025 BSC
(0.635 BSC)
0.025 BSC
(0.635 BSC)
A2
0.065
(1.65)
0.073
(1.85)
0.065
(1.65)
0.073
(1.85)
0.065
(1.65)
0.073
(1.85)
0.089
(2.26)
0.099
(2.52)
H
0.29
(7.4)
0.32
(8.2)
0.29
(7.4)
0.32
(8.2)
0.29
(7.4)
0.32
(8.2)
0.395
(10.03)
0.42
(10.67)
L
0.022
(0.55)
0.037
(0.95)
0.022
(0.55)
0.037
(0.95)
0.022
(0.55)
0.037
(0.95)
0.02
(0.51)
0.04
(1.02)
Small Shrink Outline Package (SSOP) - N Suffix
General-11
Package Outlines
Pin 1
E
A
C
L
H
e
D
L
4 mils (lead coplanarity)
Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
4) A & B Maximum dimensions include allowable mold flash
A1
B
DIM
16-Pin
18-Pin
20-Pin
24-Pin
28-Pin
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
A
0.093
(2.35)
0.104
(2.65)
0.093
(2.35)
0.104
(2.65)
0.093
(2.35)
0.104
(2.65)
0.093
(2.35)
0.104
(2.65)
0.093
(2.35)
0.104
(2.65)
A1
0.004
(0.10)
0.012
(0.30)
0.004
(0.10)
0.012
(0.30)
0.004
(0.10)
0.012
(0.30)
0.004
(0.10)
0.012
(0.30)
0.004
(0.10)
0.012
(0.30)
B
0.013
(0.33)
0.020
(0.51)
0.013
(0.33)
0.030
(0.51)
0.013
(0.33)
0.020
(0.51)
0.013
(0.33)
0.020
(0.51)
0.013
(0.33)
0.020
(0.51)
C
0.009
(0.231)
0.013
(0.318)
0.009
(0.231)
0.013
(0.318)
0.009
(0.231)
0.013
(0.318)
0.009
(0.231)
0.013
(0.318)
0.009
(0.231)
0.013
(0.318)
D
0.398
(10.1)
0.413
(10.5)
0.447
(11.35)
0.4625
(11.75)
0.496
(12.60)
0.512
(13.00)
0.5985
(15.2)
0.614
(15.6)
0.697
(17.7)
0.7125
(18.1)
E
0.291
(7.40)
0.299
(7.40)
0.291
(7.40)
0.299
(7.40)
0.291
(7.40)
0.299
(7.40)
0.291
(7.40)
0.299
(7.40)
0.291
(7.40)
0.299
(7.40)
e
0.050 BSC
(1.27 BSC)
0.050 BSC
(1.27 BSC)
0.050 BSC
(1.27 BSC)
0.050 BSC
(1.27 BSC)
0.050 BSC
(1.27 BSC)
H
0.394
(10.00)
0.419
(10.65)
0.394
(10.00)
0.419
(10.65)
0.394
(10.00)
0.419
(10.65)
0.394
(10.00)
0.419
(10.65)
0.394
(10.00)
0.419
(10.65)
L
0.016
(0.40)
0.050
(1.27)
0.016
(0.40)
0.050
(1.27)
0.016
(0.40)
0.050
(1.27)
0.016
(0.40)
0.050
(1.27)
0.016
(0.40)
0.050
(1.27)
Lead SOIC Package - S Suffix
NOTES: 1. Controlling dimensions in parenthesis ( ) are in millimeters.
2. Converted inch dimensions are not necessarily exact.
General-7
Package Outlines
3
2
1
E1
E
n-2 n-1 n
D
A2
A
L
C
eA
b2
e
eC
eB
b
Notes:
D1
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
Plastic Dual-In-Line Packages (PDIP) - E Suffix
DIM
8-Pin
16-Pin
18-Pin
20-Pin
Plastic
Plastic
Plastic
Plastic
Min
A
Max
Min
0.210 (5.33)
Max
Min
0.210 (5.33)
Max
Min
0.210 (5.33)
Max
0.210 (5.33)
A2
0.115 (2.92)
0.195 (4.95)
0.115 (2.92)
0.195 (4.95)
0.115 (2.92)
0.195 (4.95)
0.115 (2.92)
0.195 (4.95)
b
0.014 (0.356)
0.022 (0.558)
0.014 (0.356)
0.022 (0.558)
0.014 (0.356)
0.022 (0.558)
0.014 (0.356)
0.022 (0.558)
b2
0.045 (1.14)
0.070 (1.77)
0.045 (1.14)
0.070 (1.77)
0.045 (1.14)
0.070 (1.77)
0.045 (1.14)
0.070 (1.77)
C
0.008
(0.203)
0.014 (0.356)
0.008 (0.203)
0.014(0.356)
0.008 (0.203)
0.014 (0.356)
0.008 (0.203)
0.014 (0.356)
D
0.355 (9.02)
0.400 (10.16)
0.780 (19.81)
0.800 (20.32)
0.880 (22.35)
0.920 (23.37)
0.980 (24.89)
1.060 (26.9)
D1
0.005 (0.13)
E
0.300 (7.62)
0.325 (8.26)
0.300 (7.62)
0.325 (8.26)
0.300 (7.62)
0.325 (8.26)
0.300 (7.62)
0.325 (8.26)
E1
0.240 (6.10)
0.280 (7.11)
0.240 (6.10)
0.280 (7.11)
0.240 (6.10)
0.280 (7.11)
0.240 (6.10)
0.280 (7.11)
0.005 (0.13)
0.005 (0.13)
0.005 (0.13)
e
0.100 BSC (2.54)
0.100 BSC (2.54)
0.100 BSC (2.54)
0.100 BSC (2.54)
eA
0.300 BSC (7.62)
0.300 BSC (7.62)
0.300 BSC (7.62)
0.300 BSC (7.62)
L
0.115 (2.92)
eB
eC
0.150 (3.81)
0.115 (2.92)
0.430 (10.92)
0
0.060 (1.52)
0.150 (3.81)
0.430 (10.92)
0
0.060 (1.52)
NOTE: Controlling dimensions in parenthesis ( ) are in millimeters.
General-8
0.115 (2.92)
0.150 (3.81)
0.115 (2.92)
0.430 (10.92)
0
0.060 (1.52)
0.150 (3.81)
0.430 (10.92)
0
0.060 (1.52)
Package Outlines
3
2
1
E1
E
n-2 n-1 n
D
α
A2
A
L
C
eA
b2
e
eB
b
Notes:
D1
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
Plastic Dual-In-Line Packages (PDIP) - E Suffix
DIM
22-Pin
24-Pin
28-Pin
40-Pin
Plastic
Plastic
Plastic
Plastic
Min
A
Max
Min
0.210 (5.33)
Max
Min
0.250 (6.35)
Max
Min
0.250 (6.35)
Max
0.250 (6.35)
A2
0.125 (3.18)
0.195 (4.95)
0.125 (3.18)
0.195 (4.95)
0.125 (3.18)
0.195 (4.95)
0.125 (3.18)
0.195 (4.95)
b
0.014 (0.356)
0.022 (0.558)
0.014 (0.356)
0.022 (0.558)
0.014 (0.356)
0.022 (0.558)
0.014 (0.356)
0.022 (0.558)
b2
0.045 (1.15)
0.070 (1.77)
0.030 (0.77)
0.070 (1.77)
0.030 (0.77)
0.070 (1.77)
0.030 (0.77)
0.070 (1.77)
C
0.008 (0.204)
0.015 (0.381)
0.008 (0.204)
0.015 (0.381)
0.008 (0.204)
0.015 (0.381)
0.008 (0.204)
0.015 (0.381)
D
1.050 (26.67)
1.120 (28.44)
1.150 (29.3)
1.290 (32.7)
1.380 (35.1)
1.565 (39.7)
1.980 (50.3)
2.095 (53.2)
D1
0.005 (0.13)
E
0.390 (9.91)
0.005 (0.13)
0.430 (10.92)
E
E1
0.330 (8.39)
0.380 (9.65)
E1
0.005 (0.13)
0.600 (15.24)
0.670 (17.02)
0.290 (7.37)
.330 (8.38)
0.485 (12.32)
0.580 (14.73)
0.246 (6.25)
0.254 (6.45)
0.005 (0.13)
0.600 (15.24)
0.670 (17.02)
0.600 (15.24)
0.670 (17.02)
0.485 (12.32)
0.580 (14.73)
0.485 (12.32)
0.580 (14.73)
e
0.100 BSC (2.54)
0.100 BSC (2.54)
0.100 BSC (2.54)
0.100 BSC (2.54)
eA
0.400 BSC (10.16)
0.600 BSC (15.24)
0.600 BSC (15.24)
0.600 BSC (15.24)
eA
0.300 BSC (7.62)
eB
L
α
0.430 (10.92)
0.115 (2.93)
0.160 (4.06)
0.115 (2.93)
0.200 (5.08)
15°
Shaded areas for 300 Mil Body Width 24 PDIP only
15°
0.115 (2.93)
0.200 (5.08)
15°
0.115 (2.93)
0.200 (5.08)
15°
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