TI AM1707BZKBA4 Am1705 arm microprocessor Datasheet

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AM1705 ARM Microprocessor
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1 AM1705 ARM Microprocessor
1.1
Features
• Highlights
– 375/456-MHz ARM926EJ-S™ RISC Core
– ARM9 Memory Architecture
– Programmable Real-Time Unit Subsystem
– Enhanced Direct-Memory-Access Controller
3 (EDMA3)
– Two External Memory Interfaces
– Three Configurable 16550 type UART
Modules
– Two Serial Peripheral Interfaces (SPI)
– Multimedia Card (MMC)/Secure Digital (SD)
Card Interface with Secure Data I/O (SDIO)
– Two Master/Slave Inter-Integrated Circuit
– USB 2.0 OTG Port With Integrated PHY
– Two Multichannel Audio Serial Ports
– 10/100 Mb/s Ethernet MAC (EMAC)
– One 64-Bit General-Purpose Timer
– One 64-bit General-Purpose/Watchdog Timer
– Three Enhanced Pulse Width Modulators
– Three 32-Bit Enhanced Capture Modules
• Applications
– Industrial Automation
– Home Automation
– Test and Measurement
– Portable Data Terminals
– Educational Consoles
– Power Protection Systems
• 375/456-MHz ARM926EJ-S™ RISC Core
– 32-Bit and 16-Bit (Thumb®) Instructions
– Single Cycle MAC
– ARM® Jazelle® Technology
– EmbeddedICE-RT™ for Real-Time Debug
• ARM9 Memory Architecture
– 16K-Byte Instruction Cache
– 16K-Byte Data Cache
– 8K-Byte RAM (Vector Table)
– 64K-Byte ROM
• Enhanced Direct-Memory-Access Controller 3
(EDMA3):
– 2 Transfer Controllers
•
•
•
•
•
•
•
•
•
– 32 Independent DMA Channels
– 8 Quick DMA Channels
– Programmable Transfer Burst Size
128K-Byte RAM Memory
3.3V LVCMOS IOs (except for USB interface)
Two External Memory Interfaces:
– EMIFA
• NOR (8-/16-Bit-Wide Data)
• NAND (8-/16-Bit-Wide Data)
– EMIFB
• 16-Bit SDRAM With 256MB Address
Space
Three Configurable 16550 type UART Modules:
– UART0 With Modem Control Signals
– 16-byte FIFO
– 16x or 13x Oversampling Option
Two Serial Peripheral Interfaces (SPI) Each
With One Chip-Select
Programmable Real-Time Unit Subsystem
(PRUSS)
– Two Independent Programmable Realtime
Unit (PRU) Cores
• 32-Bit Load/Store RISC architecture
• 4K Byte instruction RAM per core
• 512 Bytes data RAM per core
• PRU Subsystem (PRUSS) can be disabled
via software to save power
– Standard power management mechanism
• Clock gating
• Entire subsystem under a single PSC
clock gating domain
– Dedicated interrupt controller
– Dedicated switched central resource
Multimedia Card (MMC)/Secure Digital (SD)
Card Interface with Secure Data I/O (SDIO)
Two Master/Slave Inter-Integrated Circuit (I2C
Bus™)
USB 2.0 OTG Port With Integrated PHY (USB0)
– USB 2.0 High-/Full-Speed Client
– USB 2.0 High-/Full-/Low-Speed Host
– End Point 0 (Control)
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ARM926EJ-S, EmbeddedICE-RT, ETM9, CoreSight are trademarks of ARM Limited.
ARM, Jazelle are registered trademarks of ARM Limited.
ADVANCE INFORMATION concerns new products in the sampling
or preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.
Copyright © 2010, Texas Instruments Incorporated
ADVANCE INFORMATION
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•
•
•
•
ADVANCE INFORMATION
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– End Points 1,2,3,4 (Control, Bulk, Interrupt or
ISOC) Rx and Tx
Two Multichannel Audio Serial Ports:
– Transmit/Receive Clocks up to 50 MHz
– Six Clock Zones and 28 Serial Data Pins
– Supports TDM, I2S, and Similar Formats
– FIFO buffers for Transmit and Receive
10/100 Mb/s Ethernet MAC (EMAC):
– IEEE 802.3 Compliant (3.3-V I/O Only)
– RMII Media Independent Interface
– Management Data I/O (MDIO) Module
One 64-Bit General-Purpose Timer
(Configurable as Two 32-Bit Timers)
One 64-bit General-Purpose/Watchdog Timer
(Configurable as Two 32-bit General-Purpose
Timers)
Three Enhanced Pulse Width Modulators
(eHRPWM):
– Dedicated 16-Bit Time-Base Counter With
Period And Frequency Control
•
•
•
•
•
– 6 Single Edge, 6 Dual Edge Symmetric or 3
Dual Edge Asymmetric Outputs
– Dead-Band Generation
– PWM Chopping by High-Frequency Carrier
– Trip Zone Input
Three 32-Bit Enhanced Capture Modules
(eCAP):
– Configurable as 3 Capture Inputs or 3
Auxiliary Pulse Width Modulator (APWM)
outputs
– Single Shot Capture of up to Four Event
Time-Stamps
Two 32-Bit Enhanced Quadrature Encoder
Pulse Modules (eQEP)
176-pin PowerPADTM Plastic Quad Flat Pack
[PTP suffix], 0.5-mm Pin Pitch
Commercial, Industrial, or Extended
Temperature
Community Resources
– TI E2E Community
– TI Embedded Processors Wiki
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Trademarks
ADVANCE INFORMATION
All trademarks are the property of their respective owners.
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Description
The device is a low-power ARM microprocessor based on an ARM926EJ-S™.
The device enables OEMs and ODMs to quickly bring to market devices featuring robust operating
systems support, rich user interfaces, and high processing performance life through the maximum
flexibility of a fully integrated mixed processor solution.
The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and
processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and
memory system can operate continuously.
The ARM core has a coprocessor 15 (CP15), protection module, and Data and program Memory
Management Units (MMUs) with table look-aside buffers. It has separate 16K-byte instruction and
16K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT). The ARM core
also has a 8KB RAM (Vector Table) and 64KB ROM.
ADVANCE INFORMATION
The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output
(MDIO) module; two inter-integrated circuit (I2C) Bus interfaces; 3 multichannel audio serial port (McASP)
with serializers and FIFO buffers; 2 64-bit general-purpose timers each configurable (one configurable as
watchdog); up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable
interrupt/event generation modes, multiplexed with other peripherals; 3 UART interfaces (one with RTS
and CTS); 3 enhanced high-resolution pulse width modulator (eHRPWM) peripherals; 3 32-bit enhanced
capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width
modulator (APWM) outputs; 2 32-bit enhanced quadrature pulse (eQEP) peripherals; and 2 external
memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower
memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM.
The Ethernet Media Access Controller (EMAC) provides an efficient interface between the device and the
network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps
in either half- or full-duplex mode. Additionally an Management Data Input/Output (MDIO) interface is
available for PHY configuration.
TheI2C, SPI, and USB2.0 ports allow the device to easily control peripheral devices and/or communicate
with host processors.
The rich peripheral set provides the ability to control external peripheral devices and communicate with
external processors. For details on each of the peripherals, see the related sections later in this document
and the associated peripheral reference guides.
The device has a complete set of development tools for the ARM. These include C compilers and a
Windows™ debugger interface for visibility into source code execution.
4
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Functional Block Diagram
JTAG Interface
ARM Subsystem
System Control
Input
Clock(s)
ARM926EJ-S CPU
With MMU
PLL/Clock
Generator
w/OSC
4 KB ETB
GeneralPurpose
Timer
GeneralPurpose
Timer
(Watchdog)
Power/Sleep
Controller
16 KB
16 KB
I-Cache D-Cache
8 KB RAM
(Vector Table)
Pin
Multiplexing
64 KB ROM
Switched Central Resource (SCR)
Peripherals
Audio Ports
EDMA3
McASP
w/FIFO
(2)
I2C
(2)
SPI
(2)
eCAP
(3)
UART
(3)
GPIO
eQEP
(2)
USB2.0
OTG Ctlr
PHY
(10/100)
EMAC
(RMII)
MDIO
Shared Memory
PRU
Subsystem
Connectivity
Control Timers
eHRPWM
(3)
Customizable Interface
Serial Interfaces
128 KB
RAM
ADVANCE INFORMATION
DMA
External Memory Interfaces
MMC/SD
(8b)
EMIFA
NAND/ Flash
(8b)
EMIFB
SDRAM Only
(16b/32b)
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1
2
3
4
ADVANCE INFORMATION
5
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........................ 1
1.1
Features .............................................. 1
1.2
Trademarks .......................................... 3
1.3
Description ........................................... 4
1.4
Functional Block Diagram ............................ 5
Revision History ......................................... 7
Device Overview ........................................ 8
3.1
Device Characteristics ............................... 8
3.2
Device Compatibility ................................. 9
3.3
ARM Subsystem ..................................... 9
3.4
Memory Map Summary ............................. 12
3.5
Pin Assignments .................................... 15
3.6
Terminal Functions ................................. 16
Device Configuration ................................. 29
4.1
Boot Modes ......................................... 29
4.2
SYSCFG Module ................................... 29
4.3
Pullup/Pulldown Resistors .......................... 31
Device Operating Conditions ....................... 32
AM1705 ARM Microprocessor
Clock PLLs
6.8
Interrupts ............................................ 46
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
6.17
6
6.1
6.2
Parameter Information .............................. 35
Recommended Clock and Control Signal Transition
Behavior ............................................ 36
6.3
Power Supplies
6.4
6.5
6.6
6
.....................................
Unused USB0 (USB2.0) Pin Configurations .......
Reset ...............................................
Crystal Oscillator or External Clock Input ..........
37
7
8
58
65
71
74
77
82
Multichannel Audio Serial Ports (McASP0,
McASP1) ............................................ 84
.....
Enhanced Capture (eCAP) Peripheral ............ 111
Enhanced Quadrature Encoder (eQEP) Peripheral
..................................................... 114
Enhanced High-Resolution Pulse-Width Modulator
(eHRPWM) ........................................ 116
6.24
Peripheral Information and Electrical
Specifications .......................................... 35
50
53
Serial Peripheral Interface Ports (SPI0, SPI1)
6.22
6.23
Recommended Operating Conditions .............. 33
Electrical Characteristics Over Recommended
Ranges of Supply Voltage and Operating Junction
Temperature (Unless Otherwise Noted) ............ 34
General-Purpose Input/Output (GPIO)
EDMA
6.19
6.20
5.1
5.2
5.3
.............
...............................................
External Memory Interface A (EMIFA) .............
External Memory Interface B (EMIFB) .............
Memory Protection Units ...........................
MMC / SD / SDIO (MMCSD) .......................
Ethernet Media Access Controller (EMAC) .........
Management Data Input/Output (MDIO) ...........
43
6.18
6.21
Absolute Maximum Ratings Over Operating
Junction Temperature Range
(Unless Otherwise Noted) ................................. 32
.........................................
6.7
93
Timers ............................................. 120
Inter-Integrated Circuit Serial Ports (I2C0, I2C1)
..................................................... 122
Universal Asynchronous Receiver/Transmitter
(UART) ............................................ 127
........................
6.25
USB0 OTG (USB2.0 OTG)
6.26
6.27
Power and Sleep Controller (PSC) ................ 137
Programmable Real-Time Unit Subsystem (PRUSS)
..................................................... 140
...................................
................................
Device and Documentation Support .............
7.1
Device Support ....................................
7.2
Documentation Support ...........................
129
6.28
Emulation Logic
143
6.29
IEEE 1149.1 JTAG
149
151
151
151
37
Mechanical Packaging and Orderable
Information ............................................ 152
37
8.1
Device and Development-Support Tool
Nomenclature ..................................... 152
8.2
Mechanical Drawings
41
Contents
.............................
152
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2 Revision History
This data manual revision history highlights the changes made to the SPRS657 device-specific data
manual to make it an SPRS657A revision.
Table 2-1. Revision History
ADDITIONS/MODIFICATIONS/DELETIONS
Removed references to USB0_VDDA12 from Section 5.1.
ADVANCE INFORMATION
Updated Device and Development-Support Tool Nomenclature - Section 8.1.
Revision History
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3 Device Overview
3.1
Device Characteristics
provides an overview of the device . The table shows significant features of the device, including the
capacity of on-chip RAM, peripherals, and the package type with pin count.
Table 3-1. Characteristics of the device
HARDWARE FEATURES
16-bit , upto 512Mb SDRAM
EMIFA
Asynchronous (8/16-bit bus width) RAM, Flash, NOR, NAND
Flash Card Interface
ADVANCE INFORMATION
Not all peripherals pins
are available at the
same time (for more
detail, see the Device
Configurations section).
On-Chip Memory
MMC and SD cards supported.
EDMA3
32 independent channels, 8 QDMA channels, 2 Transfer controllers
Timers
2 64-Bit General Purpose (configurable as 2 separate 32-bit timers, 1 configurable as
Watch Dog)
UART
3 (one with RTS and CTS flow control)
SPI
2 (Each with one hardware chip select)
I2C
2 (both Master/Slave)
Multichannel Audio
Serial Port [McASP]
Peripherals
AM1705
EMIFB
2(each with transmit/receive, FIFO buffer, 16/12/4 serializers)
10/100 Ethernet MAC
with Management Data
I/O
eHRPWM
eCAP
eQEP
1 (RMII Interface)
6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs
3 32-bit capture inputs or 3 32-bit auxiliary PWM outputs
2 32-bit QEP channels with 4 inputs/channel
USB 2.0 (USB0)
High-Speed OTG Controller with on-chip OTG PHY
General-Purpose
Input/Output Port
8 banks of 16-bit
PRU Subsystem
(PRUSS)
2 Programmable PRU Cores
Size (Bytes)
168KB RAM, 1088KB ROM
Organization
ARM
16KB I-Cache
16KB D-Cache
8KB RAM (Vector Table)
64KB ROM
ADDITIONAL MEMORY
128KB RAM
JTAG BSDL_ID
DEVIDR0 register
CPU Frequency
MHz
Voltage
Core (V)
0x8B7D F02F (Silicon Revision 1.1)
0x9B7D F02F (Silicon Revision 2.0)
ARM926 375 MHz (1.2V) or 456 MHz (1.3V)
1.2 V nominal for 375 MHz version
1.3 V nominal for 456 MHz version
I/O (V)
Package
Product Status (1)
(1)
8
3.3 V
24 mm x 24 mm, 176-Pin, 0.5 mm pitch, TQFP (PTP)
Product Preview (PP),
Advance Information
(AI),
or Production Data
(PD)
AI
ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and
other specifications are subject to change without notice.
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Device Compatibility
The ARM926EJ-S RISC CPU is compatible with other ARM9 CPUs from ARM Holdings plc.
3.3
ARM Subsystem
3.3.1
ARM926EJ-S RISC CPU
The ARM Subsystem integrates the ARM926EJ-S processor. The ARM926EJ-S processor is a member of
ARM9 family of general-purpose microprocessors. This processor is targeted at multi-tasking applications
where full memory management, high performance, low die size, and low power are all important. The
ARM926EJ-S processor supports the 32-bit ARM and 16 bit THUMB instruction sets, enabling the user to
trade off between high performance and high code density. Specifically, the ARM926EJ-S processor
supports the ARMv5TEJ instruction set, which includes features for efficient execution of Java byte codes,
providing Java performance similar to Just in Time (JIT) Java interpreter, but without associated code
overhead.
The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both
hardware and software debug. The ARM926EJ-S processor has a Harvard architecture and provides a
complete high performance subsystem, including:
• ARM926EJ -S integer core
• CP15 system control coprocessor
• Memory Management Unit (MMU)
• Separate instruction and data caches
• Write buffer
• Separate instruction and data (internal RAM) interfaces
• Separate instruction and data AHB bus interfaces
• Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)
For more complete details on the ARM9, refer to the ARM926EJ-S Technical Reference Manual, available
at http://www.arm.com
3.3.2
CP15
The ARM926EJ-S system control coprocessor (CP15) is used to configure and control instruction and
data caches, Memory Management Unit (MMU), and other ARM subsystem functions. The CP15 registers
are programmed using the MRC and MCR ARM instructions, when the ARM in a privileged mode such as
supervisor or system mode.
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The ARM Subsystem includes the following features:
• ARM926EJ-S RISC processor
• ARMv5TEJ (32/16-bit) instruction set
• Little endian
• System Control Co-Processor 15 (CP15)
• MMU
• 16KB Instruction cache
• 16KB Data cache
• Write Buffer
• Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)
• ARM Interrupt controller
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MMU
ADVANCE INFORMATION
A single set of two level page tables stored in main memory is used to control the address translation,
permission checks and memory region attributes for both data and instruction accesses. The MMU uses a
single unified Translation Lookaside Buffer (TLB) to cache the information held in the page tables. The
MMU features are:
• Standard ARM architecture v4 and v5 MMU mapping sizes, domains and access protection scheme.
• Mapping sizes are:
– 1MB (sections)
– 64KB (large pages)
– 4KB (small pages)
– 1KB (tiny pages)
• Access permissions for large pages and small pages can be specified separately for each quarter of
the page (subpage permissions)
• Hardware page table walks
• Invalidate entire TLB, using CP15 register 8
• Invalidate TLB entry, selected by MVA, using CP15 register 8
• Lockdown of TLB entries, using CP15 register 10
3.3.4
Caches and Write Buffer
The size of the Instruction cache is 16KB, Data cache is 16KB. Additionally, the caches have the following
features:
• Virtual index, virtual tag, and addressed using the Modified Virtual Address (MVA)
• Four-way set associative, with a cache line length of eight words per line (32-bytes per line) and with
two dirty bits in the Dcache
• Dcache supports write-through and write-back (or copy back) cache operation, selected by memory
region using the C and B bits in the MMU translation tables
• Critical-word first cache refilling
• Cache lockdown registers enable control over which cache ways are used for allocation on a line fill,
providing a mechanism for both lockdown, and controlling cache corruption
• Dcache stores the Physical Address TAG (PA TAG) corresponding to each Dcache entry in the TAG
RAM for use during the cache line write-backs, in addition to the Virtual Address TAG stored in the
TAG RAM. This means that the MMU is not involved in Dcache write-back operations, removing the
possibility of TLB misses related to the write-back address.
• Cache maintenance operations provide efficient invalidation of, the entire Dcache or Icache, regions of
the Dcache or Icache, and regions of virtual memory.
The write buffer is used for all writes to a noncachable bufferable region, write-through region and write
misses to a write-back region. A separate buffer is incorporated in the Dcache for holding write-back for
cache line evictions or cleaning of dirty cache lines. The main write buffer has 16-word data buffer and a
four-address buffer. The Dcache write-back has eight data word entries and a single address entry.
3.3.5
Advanced High-Performance Bus (AHB)
The ARM Subsystem uses the AHB port of the ARM926EJ-S to connect the ARM to the Config bus and
the external memories. Arbiters are employed to arbitrate access to the separate D-AHB and I-AHB by the
Config Bus and the external memories bus.
3.3.6
Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
To support real-time trace, the ARM926EJ-S processor provides an interface to enable connection of an
Embedded Trace Macrocell (ETM). The ARM926EJ-S Subsystem in the device also includes the
Embedded Trace Buffer (ETB). The ETM consists of two parts:
10
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Trace Port provides real-time trace capability for the ARM9.
Triggering facilities provide trigger resources, which include address and data comparators, counter,
and sequencers.
The device trace port is not pinned out and is instead only connected to the Embedded Trace Buffer. The
ETB has a 4KB buffer memory. ETB enabled debug tools are required to read/interpret the captured trace
data.
This device uses ETM9™ version r2p2 and ETB version r0p1. Documentation on the ETM and ETB is
available from ARM Ltd. Reference the ' CoreSight™ ETM9™ Technical Reference Manual, revision r0p1'
and the 'ETM9 Technical Reference Manual, revision r2p2'.
3.3.7
ARM Memory Mapping
By default the ARM has access to most on and off chip memory areas, EMIFA, EMIFB, and the additional
128K byte on chip SRAM. Likewise almost all of the on chip peripherals are accessible to the ARM by
default.
ADVANCE INFORMATION
See for a detailed top level device memory map that includes the ARM memory space.
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Memory Map Summary
Table 3-2. AM1705 Top Level Memory Map
ADVANCE INFORMATION
Start Address
End Address
Size
0x0000 0000
0x0000 0FFF
4K
0x0000 1000
0x01BB FFFF
0x01BC 0000
0x01BC 0FFF
0x01BC 1000
0x01BC 1800
0x01BC 1900
0x01BF FFFF
0x01C0 0000
0x01C0 7FFF
32K
EDMA3 CC
0x01C0 8000
0x01C0 83FF
1024
EDMA3 TC0
0x01C0 8400
0x01C0 87FF
1024
EDMA3 TC1
0x01C0 8800
0x01C0 FFFF
0x01C1 0000
0x01C1 0FFF
4K
PSC 0
0x01C1 1000
0x01C1 1FFF
4K
PLL Controller
0x01C1 2000
0x01C1 3FFF
0x01C1 4000
0x01C1 4FFF
4K
SYSCFG
0x01C1 5000
0x01C1 FFFF
0x01C2 0000
0x01C2 0FFF
4K
Timer64P 0
0x01C2 1000
0x01C2 1FFF
4K
Timer64P 1
0x01C2 2000
0x01C2 2FFF
4K
I2C 0
0x01C2 3000
0x01C2 3FFF
0x01C2 4000
0x01C3 FFFF
0x01C4 0000
0x01C4 0FFF
4K
MMC/SD 0
0x01C4 1000
0x01C4 1FFF
4K
SPI 0
0x01C4 2000
0x01C4 2FFF
4K
UART 0
0x01C4 3000
0x01CF FFFF
0x01D0 0000
0x01D0 0FFF
4K
McASP 0 Control
0x01D0 1000
0x01D0 1FFF
4K
McASP 0 AFIFO Ctrl
0x01D0 2000
0x01D0 2FFF
4K
McASP 0 Data
0x01D0 3000
0x01D0 3FFF
0x01D0 4000
0x01D0 4FFF
4K
McASP 1 Control
0x01D0 5000
0x01D0 5FFF
4K
McASP 1 AFIFO Ctrl
0x01D0 6000
0x01D0 6FFF
4K
McASP 1 Data
0x01D0 7000
0x01D0 7FFF
-
0x01D0 8000
0x01D0 8FFF
-
0x01D0 9000
0x01D0 9FFF
-
0x01D0 A000
0x01D0 AFFF
-
0x01D0 B000
0x01D0 BFFF
0x01D0 C000
0x01D0 CFFF
4K
UART 1
0x01D0 D000
0x01D0 DFFF
4K
UART 2
0x01D0 E000
0x01DF FFFF
0x01E0 0000
0x01E0 FFFF
64K
USB0
0x01E1 0000
0x01E1 0FFF
-
0x01E1 1000
0x01E1 1FFF
-
12
ARM Mem Map
EDMA Mem
Map
-
PRUSS Mem
Map
Master Peripheral
Mem Map
PRUSS Local
Address
Space
-
4K
ARM ETB
memory
-
0x01BC 17FF
2K
ARM ETB reg
-
0x01BC 18FF
256
ARM Ice
Crusher
-
-
-
-
-
-
Device Overview
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SPRS657A – FEBRUARY 2010 – REVISED APRIL 2010
Table 3-2. AM1705 Top Level Memory Map (continued)
Start Address
End Address
Size
0x01E1 2000
0x01E1 2FFF
4K
0x01E1 3000
0x01E1 3FFF
0x01E1 4000
0x01E1 4FFF
4K
Memory Protection Unit 1 (MPU 1)
0x01E1 5000
0x01E1 5FFF
4K
Memory Protection Unit 2 (MPU 2)
0x01E1 6000
0x01E1 FFFF
0x01E2 0000
0x01E2 1FFF
8K
EMAC Control Module RAM
0x01E2 2000
0x01E2 2FFF
4K
EMAC Control Module Registers
0x01E2 3000
0x01E2 3FFF
4K
EMAC Control Registers
0x01E2 4000
0x01E2 4FFF
4K
EMAC MDIO port
0x01E2 5000
0x01E2 5FFF
0x01E2 6000
0x01E2 6FFF
4K
GPIO
0x01E2 7000
0x01E2 7FFF
4K
PSC 1
0x01E2 8000
0x01E2 8FFF
4K
I2C 1
0x01E2 9000
0x01EF FFFF
0x01F0 0000
0x01F0 0FFF
4K
eHRPWM 0
0x01F0 1000
0x01F0 1FFF
4K
HRPWM 0
0x01F0 2000
0x01F0 2FFF
4K
eHRPWM 1
0x01F0 3000
0x01F0 3FFF
4K
HRPWM 1
0x01F0 4000
0x01F0 4FFF
4K
eHRPWM 2
0x01F0 5000
0x01F0 5FFF
4K
HRPWM 2
0x01F0 6000
0x01F0 6FFF
4K
ECAP 0
0x01F0 7000
0x01F0 7FFF
4K
ECAP 1
0x01F0 8000
0x01F0 8FFF
4K
ECAP 2
0x01F0 9000
0x01F0 9FFF
4K
EQEP 0
0x01F0 A000
0x01F0 AFFF
4K
EQEP 1
0x01F0 B000
0x3FFF FFFF
-
0x4000 0000
0x47FF FFFF
-
0x4800 0000
0x5FFF FFFF
0x6000 0000
0x61FF FFFF
32M
EMIFA async data (CS2)
0x6200 0000
0x63FF FFFF
32M
EMIFA async data (CS3)
0x6400 0000
0x65FF FFFF
32M
EMIFA async data (CS4)
0x6600 0000
0x67FF FFFF
32M
EMIFA async data (CS5)
0x6800 0000
0x6800 7FFF
32K
EMIFA Control Regs
0x6800 8000
0x7FFF FFFF
0x8000 0000
0x8001 FFFF
128K
On-chip RAM
0x8002 0000
0xAFFF FFFF
0xB000 0000
0xB000 7FFF
32K
EMIFB Control Regs
256M
EMIFB SDRAM Data
0xB000 8000
0xBFFF FFFF
0xC000 0000
0xCFFF FFFF
0xD000 0000
0xFFFC FFFF
0xFFFD 0000
0xFFFD FFFF
ARM Mem Map
EDMA Mem
Map
PRUSS Mem
Map
Master Peripheral
Mem Map
SPI 1
-
-
-
ADVANCE INFORMATION
-
-
-
64K
ARM local
ROM
0xFFFE 0000
0xFFFE DFFF
0xFFFE E000
0xFFFE FFFF
8K
ARM Interrupt
Controller
0xFFFF 0000
0xFFFF 1FFF
8K
ARM local
RAM
-
ARM local
RAM (PRU 0
Only)
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SPRS657A – FEBRUARY 2010 – REVISED APRIL 2010
www.ti.com
Table 3-2. AM1705 Top Level Memory Map (continued)
Start Address
End Address
0xFFFF 2000
0xFFFF FFFF
Size
ARM Mem Map
EDMA Mem
Map
PRUSS Mem
Map
Master Peripheral
Mem Map
-
ADVANCE INFORMATION
14
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
AMUTE1/EPWMTZ/GP4[14]
AFSR0/GP3[12]
ACLKR0/ECAP1/APWM1/GP2[15]
AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11]
DVDD
AFSX0/GP2[13]/BOOT[10]
ACLKX0/ECAP0/APWM0/GP2[12]
AHCLKX0/USB_REFCLKIN/GP2[11]
AXR0[11]/GP3[11]
UART1_TXD/AXR0[10]/GP3[10]
UART1_RXD/AXR0[9]/GP3[9]
AXR0[8]/MDIO_D/GP3[8]
AXR0[7]/MDIO_CLK/GP3[7]
DVDD
AXR0[6]/RMII_RXER/ACLKR2/GP3[6]
AXR0[5]/RMII_RXD[1]/GP3[5]
AXR0[4]/RMII_RXD[0]/AXR2[1]/GP3[4]
AXR0[3]/RMII_CRS_DV/GP3[3]
CVDD
AXR0[2]/RMII_TXEN/GP3[2]
AXR0[1]/RMII_TXD[1]/GP3[1]
AXR0[0]/RMII_TXD[0]/GP3[0]
EMB_RAS
DVDD
EMB_CS[0]
EMB_BA[0]/GP7[1]
EMB_BA[1]/GP7[0]
EMB_A[10]/GP7[12]
CVDD
EMB_A[0]/GP7[2]
EMB_A[1]/GP7[3]
EMB_A[2]/GP7[4]
EMB_A[3]/GP7[5]
DVDD
EMB_A[4]/GP7[6]
EMB_A[5]/GP7[7]
EMB_A[6]/GP7[8]
EMB_A[7]/GP7[9]
EMB_A[8]/GP7[10]
CVDD
EMB_A[9]/GP7[11]
EMB_A[11]/GP7[13]
DVDD
EMB_A[12]/GP3[13]
www.ti.com
3.5.1
RSV2
USB0_VDDA12
USB0_VDDA18
NC
USB0_DP
USB0_DM
NC
USB0_VDDA33
PLL0_VDDA
PLL0_VSSA
OSCIN
OSCVSS
OSCOUT
RESET
CVDD
RSV4
RSV3
TRST
DVDD
TMS
TDI
CVDD
TCK
TDO
GP7[14]
DVDD
RVDD
AHCLKX1/EPWM0B/GP3[14]
CVDD
ACLKX1/EPWM0A/GP3[15]
AFSX1/EPWMSYNCI/EPWMSYNC0/GP4[10]
DVDD
ACLKR1/ECAP2/APWM2/GP4[12]
AFSR1/GP4[13]
CVDD
AXR1[8]/EPWM1A/GP4[8]
AXR1[7]/EPWM1B/GP4[7]
AXR1[6]/EPWM2A/GP4[6]
AXR1[5]/EPWM2B/GP4[5]
DVDD
AXR1[4]/EQEP1B/GP4[4]
AXR1[3]/EQEP1A/GP4[3]
AXR1[2]/GP4[2]
AXR1[1]/GP4[1]
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
VSS
(177)
Thermal Pad
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88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
EMB_SDCKE
DVDD
EMB_CLK
EMB_WE_DQM[1]/GP5[14]
EMB_D[8]/GP6[8]
EMB_D[9]/GP6[9]
EMB_D[10]/GP6[10]
DVDD
EMB_D[11]/GP6[11]
EMB_D[12]/GP6[12]
EMB_D[13]/GP6[13]
CVDD
EMB_D[14]/GP6[14]
DVDD
EMB_D[15]/GP6[15]
EMB_D[0]/GP6[0]
EMB_D[1]/GP6[1]
DVDD
EMB_D[2]/GP6[2]
CVDD
EMB_D[3]/GP6[3]
RVDD
EMB_D[4]/GP6[4]
DVDD
EMB_D[5]/GP6[5]
EMB_D[6]/GP6[6]
EMB_D[7]/GP6[7]
CVDD
EMB_WE_DQM[0]/GP5[15]
EMB_WE
DVDD
EMB_CAS
CVDD
EMA_WE/AXR0[12]/GP2[3]/BOOT[14]
EMA_D[7]/MMCSD_DAT[7]/GP0[7]/BOOT[13]
DVDD
EMA_D[6]/MMCSD_DAT[6]/GP0[6]
EMA_D[5]/MMCSD_DAT[5]/GP0[5]
CVDD
EMA_D[4]/MMCSD_DAT[4]/GP0[4]
EMA_D[3]/MMCSD_DAT[3]/GP0[3]
DVDD
EMA_D[2]/MMCSD_DAT[2]/GP0[2]
EMA_D[1]/MMCSD_DAT[1]/GP0[1]
Device Overview
ADVANCE INFORMATION
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
3.5
CVDD
SPI0_CLK/EQEP1I/GP5[2]/BOOT[2]
SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3]
SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5]
SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6]
DVDD
SPI1_CLK/EQEP1S/GP5[7]/BOOT[7]
SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0]
SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1]
EMA_WAIT[0]/GP2[10]
CVDD
EMA_CS[3]/GP2[6]
EMA_OE/AXR0[13]/GP2[7]
EMA_CS[2]/GP2[5]/BOOT[15]
DVDD
EMA_BA[0]/GP1[14]
EMA_BA[1]/GP1[13]
EMA_A[10]/GP1[10]
CVDD
EMA_A[0]/GP1[0]
EMA_A[1]/MMCSD_CLK/GP1[1]
EMA_A[2]/MMCSD_CMD/GP1[2]
EMA_A[3]/GP1[3]
DVDD
EMA_A[4]/GP1[4]
EMA_A[5]/GP1[5]
EMA_A[6]/GP1[6]
EMA_A[7]/GP1[7]
CVDD
EMA_A[8]/GP1[8]
EMA_A[9]/GP1[9]
EMA_A[11]/GP1[11]
EMA_A[12]/GP1[12]
DVDD
EMA_D[0]/MMCSD_DAT[0]/GP0[0]/BOOT[12]
AXR1[0]/GP4[0]
UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8]
UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9]
AXR1[10]/GP5[10]
DVDD
AXR1[11]/GP5[11]
SPI1_ENA/UART2_RXD/GP5[12]
SPI1_SCS[0]/UART2_TXD/GP5[13]
SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4]
AM1705
SPRS657A – FEBRUARY 2010 – REVISED APRIL 2010
Pin Assignments
Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in
the smallest possible package. Pin multiplexing is controlled using a combination of hardware
configuration at device reset and software programmable register settings.
Pin Map (Bottom View)
Figure 3-1. Pin Map (PTP)
15
AM1705
SPRS657A – FEBRUARY 2010 – REVISED APRIL 2010
3.6
www.ti.com
Terminal Functions
to identify the external signal names, the associated pin/ball numbers along with the mechanical package
designator, the pin type (I, O, IO, OZ, or PWR), whether the pin/ball has any internal pullup/pulldown
resistors, whether the pin/ball is configurable as an IO in GPIO mode, and a functional pin description.
3.6.1
Device Reset and JTAG
Table 3-3. Reset and JTAG Terminal Functions
SIGNAL NAME
PIN NO
PTP
TYPE (1)
PULL (2)
DESCRIPTION
RESET
RESET
146
I
Device reset input
JTAG
TMS
152
ADVANCE INFORMATION
I
IPU
JTAG test mode select
TDI
TDO
153
I
IPU
JTAG test data input
156
O
IPD
JTAG test data output
TCK
155
I
IPU
JTAG test clock
TRST
150
I
IPD
JTAG test reset
-
I/O
IPU
Emulation Signal
EMU[0]/GP7[15]
(1)
(2)
I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for
that particular peripheral.
IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
3.6.2
High-Frequency Oscillator and PLL
Table 3-4. High-Frequency Oscillator and PLL Terminal Functions
SIGNAL NAME
PIN NO
PTP
TYPE (1)
PULL (2)
DESCRIPTION
1.2-V OSCILLATOR
OSCIN
143
I
Oscillator input
OSCOUT
145
O
Oscillator output
OSCVSS
144
GND
PLL0_VDDA
141
PWR
PLL analog VDD (1.2-V filtered supply)
PLL0_VSSA
142
GND
PLL analog VSS (for filter)
Oscillator ground (for filter only)
1.2-V PLL
(1)
(2)
16
I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for
that particular peripheral.
IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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3.6.3
SPRS657A – FEBRUARY 2010 – REVISED APRIL 2010
External Memory Interface A (ASYNC)
Table 3-5. External Memory Interface A (EMIFA) Terminal Functions
SIGNAL NAME
PIN
NO
TYPE (1)
PULL (2)
MUXED
MMC/SD, GPIO,
BOOT
DESCRIPTION
PTP
EMA_D[7]/MMCSD_DAT[7]/GP0[7]/BOOT[13]
54
I/O
IPU
EMA_D[6]/MMCSD_DAT[6]/GP0[6]
52
I/O
IPU
EMA_D[5]/MMCSD_DAT[5]/GP0[5]
51
I/O
IPU
EMA_D[4]/MMCSD_DAT[4]/GP0[4]
49
I/O
IPU
EMA_D[3]/MMCSD_DAT[3]/GP0[3]
48
I/O
IPU
EMA_D[2]/MMCSD_DAT[2]/GP0[2]
46
I/O
IPU
EMA_D[1]/MMCSD_DAT[1]/GP0[1]
45
I/O
IPU
EMA_D[0]/MMCSD_DAT[0]/GP0[0]/BOOT[12]
44
I/O
IPU
EMA_A[12]/GP1[12]
42
O
IPU
EMA_A[11]/ GP1[11]
41
O
IPU
EMA_A[10]/GP1[10]
27
O
IPU
EMA_A[9]/GP1[9]
40
O
IPU
EMA_A[8]/GP1[8]
39
O
IPU
EMA_A[7]/GP1[7]
37
O
IPD
EMA_A[6]/GP1[6]
36
O
IPD
EMA_A[5]/GP1[5]
35
O
IPD
EMA_A[4]/GP1[4]
34
O
IPD
EMA_A[3]/GP1[3]
32
O
IPD
EMA_A[2]/MMCSD_CMD/GP1[2]
31
O
IPU
EMA_A[1]/MMCSD_CLK/GP1[1]
30
O
IPU
EMA_A[0]/GP1[0]
29
O
IPD
EMA_BA[1]/GP1[13]
26
O
IPU
EMA_BA[0]/GP1[14]
25
O
IPU
GPIO
EMA_CS[3] /GP2[6]
21
O
IPU
GPIO
EMA_CS[2]/GP2[5]/BOOT[15]
23
O
IPU
GPIO, BOOT
EMIFA Async Chip
Select
EMA_OE /AXR0[13]/GP2[7]
22
O
IPU
McASP0, GPIO
EMIFA output enable.
EMA_WAIT[0]/ GP2[10]
19
I
IPU
GPIO
EMIFA wait
input/interrupt.
(1)
(2)
MMC/SD, GPIO
EMIFA data bus
GPIO
MMCSD, GPIO
ADVANCE INFORMATION
MMC/SD, GPIO,
BOOT
EMIFA address bus
EMIFA address bus.
GPIO
EMIFA bank address
I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
Device Overview
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SPRS657A – FEBRUARY 2010 – REVISED APRIL 2010
3.6.4
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External Memory Interface B (only SDRAM )
Table 3-6. External Memory Interface B (EMIFB) Terminal Functions
SIGNAL NAME
PIN NO
PTP
TYPE (1)
PULL (2)
MUXED
DESCRIPTION
ADVANCE INFORMATION
EMB_D[15]/GP6[15]
74
I/O
IPD
EMB_D[14]/GP6[14]
76
I/O
IPD
EMB_D[13]/GP6[13]
78
I/O
IPD
EMB_D[12]/GP6[12]
79
I/O
IPD
EMB_D[11]/GP6[11]
80
I/O
IPD
EMB_D[10]/GP6[10]
82
I/O
IPD
EMB_D[9]/GP6[9]
83
I/O
IPD
EMB_D[8]/GP6[8]
84
I/O
IPD
EMB_D[7]/GP6[7]
62
I/O
IPD
EMB_D[6]/GP6[6]
63
I/O
IPD
EMB_D[5]/GP6[5]
64
I/O
IPD
EMB_D[4]/GP6[4]
66
I/O
IPD
EMB_D[3]/GP6[3]
68
I/O
IPD
EMB_D[2]/GP6[2]
70
I/O
IPD
EMB_D[1]/GP6[1]
72
I/O
IPD
EMB_D[0]/GP6[0]
73
I/O
IPD
EMB_A[12]/GP3[13]
89
O
IPD
EMB_A[11]/GP7[13]
91
O
IPD
EMB_A[10]/GP7[12]
105
O
IPD
EMB_A[9]/GP7[11]
92
O
IPD
EMB_A[8]/GP7[10]
94
O
IPD
EMB_A[7]/GP7[9]
95
O
IPD
EMB_A[6]/GP7[8]
96
O
IPD
EMB_A[5]/GP7[7]
97
O
IPD
EMB_A[4]/GP7[6]
98
O
IPD
EMB_A[3]/GP7[5]
100
O
IPD
EMB_A[2]/GP7[4]
101
O
IPD
EMB_A[1]/GP7[3]
102
O
IPD
EMB_A[0]/GP7[2]
103
O
IPD
EMB_BA[1]/GP7[0]
106
O
IPU
EMB_BA[0]/GP7[1]
107
O
IPU
EMB_CLK
86
O
IPU
EMIF SDRAM clock.
EMB_SDCKE
88
I/O
IPU
EMIFB SDRAM clock enable.
EMB_WE
59
O
IPU
EMIFB write enable
EMB_RAS
110
O
IPU
EMIFB SDRAM row address
strobe.
EMB_CAS
57
O
IPU
EMIFB column address strobe.
EMB_CS[0]
108
O
IPU
EMIFB SDRAM chip select 0.
EMB_WE_DQM[1] /GP5[14]
85
O
IPU
EMB_WE_DQM[0] /GP5[15]
60
O
IPU
(1)
(2)
18
GPIO
EMIFB SDRAM data bus.
GPIO
EMIFB SDRAM row/column
address bus.
EMIFB SDRAM row/column
address.
GPIO
EMIFB SDRAM bank address.
GPIO
EMIFB write enable/data mask
for EMB_D.
I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
Device Overview
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3.6.5
SPRS657A – FEBRUARY 2010 – REVISED APRIL 2010
Serial Peripheral Interface Modules (SPI0, SPI1)
Table 3-7. Serial Peripheral Interface (SPI) Terminal Functions
PIN NO
SIGNAL NAME
PTP
TYPE (1)
PULL (2)
MUXED
DESCRIPTION
SPI0
SPI0_SCS[0] /UART0_RTS/EQEP0B/GP5[4]/BOOT[4]
9
I/O
IPU
UART0, EQEP0B,
GPIO, BOOT
SPI0 chip select.
SPI0_ENA /UART0_CTS/EQEP0A/GP5[3]/BOOT[3]
12
I/O
IPU
UART0, EQEP0A,
GPIO, BOOT
SPI0 enable.
SPI0_CLK/EQEP1I/GP5[2]/BOOT[2]
11
I/O
IPD
eQEP1, GPIO, BOOT SPI0 clock.
SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1]
18
I/O
IPD
eQEP0, GPIO, BOOT
SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0]
17
I/O
IPD
SPI0 data
slave-in-masterout.
SPI0 data
slave-out-masterin.
SPI1_SCS[0] /UART2_TXD/GP5[13]
8
I/O
IPU
SPI1_ENA /UART2_RXD/GP5[12]
7
I/O
IPU
SPI1_CLK/EQEP1S/GP5[7]/BOOT[7]
16
I/O
IPD
SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6]
14
I/O
IPU
SPI1 chip select.
UART2, GPIO
SPI1 enable.
eQEP1, GPIO, BOOT SPI1 clock.
I2C1, GPIO, BOOT
SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5]
(1)
(2)
13
I/O
IPU
SPI1 data
slave-in-masterout.
SPI1 data
slave-out-masterin.
I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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Enhanced Capture/Auxiliary PWM Modules (eCAP0, eCAP1, eCAP2)
The eCAP Module pins function as either input captures or auxiliary PWM 32-bit outputs, depending upon
how the eCAP module is programmed.
Table 3-8. Enhanced Capture Module (eCAP) Terminal Functions
SIGNAL NAME
PIN NO
TYPE (1)
PTP
PULL (2)
MUXED
DESCRIPTION
eCAP0
ACLKX0/ECAP0/APWM0/GP2[12]
126
I/O
IPD
McASP0, GPIO
enhanced capture 0
input or auxiliary
PWM 0 output.
I/O
IPD
McASP0, GPIO
enhanced capture 1
input or auxiliary
PWM 1 output.
I/O
IPD
McASP1, GPIO
enhanced capture 2
input or auxiliary
PWM 2 output.
eCAP1
ACLKR0/ECAP1/APWM1/GP2[15]
130
eCAP2
ACLKR1/ECAP2/APWM2/GP4[12]
ADVANCE INFORMATION
(1)
(2)
165
I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
3.6.7
Enhanced Pulse Width Modulators (eHRPWM0, eHRPWM1, eHRPWM2)
Table 3-9. Enhanced Pulse Width Modulator (eHRPWM) Terminal Functions
SIGNAL NAME
PIN NO
PTP
TYPE (1)
PULL (2)
MUXED
DESCRIPTION
eHRPWM0
ACLKX1/EPWM0A/GP3[15]
162
I/O
IPD
McASP1, GPIO
eHRPWM0 A output
(with
high-resolution).
eHRPWM0 B
output.
AHCLKX1/EPWM0B/GP3[14]
160
I/O
IPD
AMUTE1/EPWMTZ/GP4[14]
132
I/O
IPD
McASP1,
eHRPWM1, GPIO,
eHRPWM2
eHRPWM0 trip zone
input.
IPD
McASP1,
eHRPWM0, GPIO
Sync input to
eHRPWM0 module
or sync output to
external PWM.
AFSX1/EPWMSYNCI/EPWMSYNCO/GP4[10]
163
I/O
eHRPWM1
AXR1[8]/EPWM1A/GP4[8]
168
I/O
IPD
AXR1[7]/EPWM1B/GP4[7]
169
I/O
IPD
AMUTE1/EPWMTZ/GP4[14]
132
I/O
IPD
McASP1, GPIO
(1)
(2)
20
McASP1,
eHRPWM0, GPIO,
eHRPWM2
eHRPWM1 A (with
high-resolution).
eHRPWM1 B
output.
eHRPWM1 trip zone
input.
I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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Table 3-9. Enhanced Pulse Width Modulator (eHRPWM) Terminal Functions (continued)
PIN NO
SIGNAL NAME
PTP
TYPE (1)
PULL (2)
MUXED
DESCRIPTION
eHRPWM2
AXR1[6]/EPWM2A/GP4[6]
170
I/O
IPD
AXR1[5]/EPWM2B/GP4[5]
171
I/O
IPD
AMUTE1/EPWMTZ/GP4[14]
132
I/O
IPD
eHRPWM2 A (with
high-resolution).
McASP1, GPIO
3.6.8
eHRPWM2 B
output.
McASP1,
eHRPWM0, GPIO,
eHRPWM2
eHRPWM2 trip zone
input.
Enhanced Quadrature Encoder Pulse Module (eQEP)
Table 3-10. Enhanced Quadrature Encoder Pulse Module (eQEP) Terminal Functions
PTP
TYPE (1)
PULL (2)
MUXED
DESCRIPTION
eQEP0
SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3]
12
I
IPU
SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4]
9
I
IPU
SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0]
17
I
IPD
SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1]
18
I
IPD
I
IPD
eQEP0A quadrature
input.
SPIO, UART0,
GPIO, BOOT
eQEP0B quadrature
input.
SPI0, GPIO, BOOT
eQEP0 index.
eQEP0 strobe.
eQEP1
AXR1[3]/EQEP1A/GP4[3]
174
eQEP1A quadrature
input.
McASP1, GPIO
eQEP1B quadrature
input.
AXR1[4]/EQEP1B/GP4[4]
173
I
IPD
SPI0_CLK/EQEP1I/GP5[2]/BOOT[2]
11
I
IPD
SPI0, GPIO, BOOT
eQEP1 index.
SPI1_CLK/EQEP1S/GP5[7]/BOOT[7]
16
I
IPD
SPI1, GPIO, BOOT
eQEP1 strobe.
(1)
(2)
I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
3.6.9
Boot
Table 3-11. Boot Terminal Functions (1)
SIGNAL NAME
EMA_CS[2]/GP2[5]/BOOT[15]
PIN NO
PTP
23
TYPE (2)
PULL (3)
I
IPU
EMIFA, GPIO
BOOT[15].
EMIFA, McASP0,
GPIO
BOOT[14].
EMA_WE/AXR0[12]/GP2[3]/BOOT[14]
55
I
IPU
EMA_D[7]/MMCSD_DAT[7]/GP0[7]/BOOT[13]
54
I
IPU
EMA_D[0]/MMCSD_DAT[0]/GP0[0]/BOOT[12]
44
I
IPU
(1)
(2)
(3)
MUXED
DESCRIPTION
EMIFA, MMC/SD,
GPIO
BOOT[13].
BOOT[12].
Boot decoding will be defined in the ROM datasheet.
I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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SIGNAL NAME
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Table 3-11. Boot Terminal Functions
PIN NO
SIGNAL NAME
PTP
(1)
(continued)
TYPE (2)
PULL (3)
MUXED
DESCRIPTION
AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11]
129
I
IPD
McASP0, EMAC,
GPIO
BOOT[11].
AFSX0/GP2[13]/BOOT[10]
127
I
IPD
McASP0, GPIO
BOOT[10].
UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9]
3
I
IPU
UART0, I2C0, Timer0,
BOOT[9].
GPIO
UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8]
2
I
IPU
UART0, I2C0, Timer0,
BOOT[8].
GPIO
SPI1_CLK/EQEP1S/GP5[7]/BOOT[7]
16
I
IPD
SPI1, eQEP1, GPIO
SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6]
14
I
IPU
SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5]
13
I
IPU
SPI1, I2C1, GPIO
BOOT[7].
BOOT[6].
BOOT[5].
ADVANCE INFORMATION
SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4]
9
I
IPU
SPI0, UART0,
eQEP0, GPIO
SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3]
12
I
IPU
SPI0, UART0,
eQEP0, GPIO
BOOT[3].
SPI0_CLK/EQEP1I/GP5[2]/BOOT[2]
11
I
IPD
SPIO, eQEP1, GPIO
BOOT[2].
SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1]
18
I
IPD
SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0]
17
I
IPD
SPI0, eQEP0, GPIO
BOOT[4].
BOOT[1].
BOOT[0].
3.6.10 Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2)
Table 3-12. Universal Asynchronous Receiver/Transmitter (UART) Terminal Functions
PIN NO
SIGNAL NAME
PTP
TYPE (1)
PULL (2)
MUXED
DESCRIPTION
UART0
UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8]
2
I
IPU
I2C0, BOOT,
Timer0, GPIO,
UART0 receive
data.
UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9]
3
O
IPU
I2C0, Timer0,
GPIO, BOOT
UART0 transmit
data.
SPI0_SCS[0]/ UART0_RTS /EQEP0B/GP5[4]/BOOT[4]
9
O
IPU
SPI0_ENA/ UART0_CTS /EQEP0A/GP5[3]/BOOT[3]
12
I
IPU
UART0
clear-to-send input
122
I
IPD
UART1 receive
data.
123
O
IPD
UART1 transmit
data.
UART2 receive
data.
SPIO, eQEP0,
GPIO, BOOT
UART0
ready-to-send
output
UART1
UART1_RXD/AXR0[9]/GP3[9]
(3)
McASP0, GPIO
UART1_TXD/AXR0[10]/GP3[10] (3)
UART2
SPI1_ENA/UART2_RXD/GP5[12]
7
I
IPU
SPI1_SCS[0]/UART2_TXD/GP5[13]
8
O
IPU
SPI1, GPIO
(1)
(2)
(3)
22
UART2 transmit
data.
I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
As these signals are internally pulled down while the device is in reset, it is necessary to externally pull them high with resistors if
UART1 boot mode is used.
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3.6.11 Inter-Integrated Circuit Modules(I2C0, I2C1)
Table 3-13. Inter-Integrated Circuit (I2C) Terminal Functions
PIN NO
SIGNAL NAME
PTP
TYPE (1)
PULL (2)
MUXED
DESCRIPTION
I2C0
UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8]
2
I/O
IPU
UART0, Timer0,
GPIO, BOOT
I2C0 serial data.
UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9]
3
I/O
IPU
UART0, Timer0,
GPIO, BOOT
I2C0 serial clock.
SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6]
14
I/O
IPU
SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5]
13
I/O
IPU
I2C1
(2)
I2C1 serial Data.
I2C1 serial clock.
I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
3.6.12 Timers
Table 3-14. Timers Terminal Functions
PIN NO
SIGNAL NAME
PTP
TYPE (1)
PULL (2)
MUXED
DESCRIPTION
TIMER0
UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8]
2
I
IPU
UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9]
3
O
IPU
UART0, I2C0,
GPIO, BOOT
Timer0 lower
input.
Timer0 lower
output
TIMER1 (Watchdog )
No external pins. The Timer1 peripheral pins are not pinned out as external pins.
(1)
(2)
I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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3.6.13 Multichannel Audio Serial Ports (McASP0, McASP1)
Table 3-15. Multichannel Audio Serial Ports (McASPs) Terminal Functions
SIGNAL NAME
PIN NO
PTP
TYPE (1)
PULL (2)
MUXED
DESCRIPTION
McASP0
ADVANCE INFORMATION
EMA_OE/AXR0[13]/GP2[7]
22
I/O
IPU
EMIFA, GPIO
EMA_WE/AXR0[12]/GP2[3]/BOOT[14]
55
I/O
IPU
EMIFA, GPIO,
BOOT
AXR0[11]/ AXR2[0]/GP3[11]
124
I/O
IPD
McASP2,
GPIO
UART1_TXD/AXR0[10]/GP3[10]
123
I/O
IPD
GPIO
UART1_RXD/AXR0[9]/GP3[9]
122
I/O
IPD
GPIO
AXR0[8]/MDIO_D/GP3[8]
121
I/O
IPU
AXR0[7]/MDIO_CLK/GP3[7]
120
I/O
IPD
AXR0[6]/RMII_RXER/GP3[6]
118
I/O
IPD
AXR0[5]/RMII_RXD[1]/GP3[5]
117
I/O
IPD
AXR0[4]/RMII_RXD[0]/GP3[4]
116
I/O
IPD
AXR0[3]/RMII_CRS_DV/GP3[3]
115
I/O
IPD
AXR0[2]/RMII_TXEN/GP3[2]
113
I/O
IPD
AXR0[1]/RMII_TXD[1]/GP3[1]
112
I/O
IPD
AXR0[0]/RMII_TXD[0]/GP3[0]
111
I/O
IPD
AHCLKX0/AHCLKX2/USB_REFCLKIN/GP2[11]
125
I/O
IPD
USB, GPIO
McASP0
transmit master
clock.
ACLKX0/ECAP0/APWM0/GP2[12]
126
I/O
IPD
eCAP0, GPIO
McASP0
transmit bit
clock.
AFSX0/GP2[13]/BOOT[10]
127
I/O
IPD
GPIO, BOOT
McASP0
transmit frame
sync.
AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11]
129
I/O
IPD
EMAC, GPIO,
BOOT
McASP0 receive
master clock.
ACLKR0/ECAP1/APWM1/GP2[15]
130
I/O
IPD
eCAP1, GPIO
McASP0 receive
bit clock.
AFSR0/GP3[12]
131
I/O
IPD
GPIO
McASP0 receive
frame sync.
(1)
(2)
24
MDIO, GPIO
McASP0 serial
data.
EMAC, GPIO
I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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Table 3-15. Multichannel Audio Serial Ports (McASPs) Terminal Functions (continued)
PIN NO
SIGNAL NAME
PTP
TYPE (1)
PULL (2)
MUXED
DESCRIPTION
McASP1
AXR1[11]/GP5[11]
7
I/O
IPU
AXR1[10]/GP5[10]
4
I/O
IPU
AXR1[8]/EPWM1A/GP4[8]
168
I/O
IPD
eHRPWM1 A,
GPIO
AXR1[7]/EPWM1B/GP4[7]
169
I/O
IPD
eHRPWM1 B,
GPIO
AXR1[6]/EPWM2A/GP4[6]
170
I/O
IPD
eHRPWM2 A,
GPIO
AXR1[5]/EPWM2B/GP4[5]
171
I/O
IPD
eHRPWM2 B,
GPIO
AXR1[4]/EQEP1B/GP4[4]
173
I/O
IPD
AXR1[3]/EQEP1A/GP4[3]
174
I/O
IPD
AXR1[2]/GP4[2]
175
I/O
IPD
AXR1[1]/GP4[1]
176
I/O
IPD
AXR1[0]/GP4[0]
1
I/O
IPD
AHCLKX1/EPWM0B/GP3[14]
160
I/O
IPD
eHRPWM0,
GPIO
McASP1
transmit master
clock.
ACLKX1/EPWM0A/GP3[15]
162
I/O
IPD
eHRPWM0,
GPIO
McASP1
transmit bit
clock.
AFSX1/EPWMSYNCI/EPWMSYNCO/GP4[10]
163
I/O
IPD
eHRPWM0,
GPIO
McASP1
transmit frame
sync.
ACLKR1/ECAP2/APWM2/GP4[12]
165
I/O
IPD
eCAP2, GPIO
McASP1 receive
bit clock.
AFSR1/GP4[13]
166
I/O
IPD
GPIO
McASP1 receive
frame sync.
IPD
eHRPWM0,
eHRPWM1,
GPIO,
eHRPWM2
McASP1 mute
output.
132
O
McASP1 serial
data.
eQEP, GPIO
GPIO
3.6.14 Universal Serial Bus Modules (USB0)
Table 3-16. Universal Serial Bus (USB) Terminal Functions
SIGNAL NAME
PIN NO
PTP
TYPE (1)
PULL (2)
DESCRIPTION
USB0 2.0 OTG (USB0)
USB0_DM
138
USB0_DP
USB0_VDDA33
USB0_VDDA18
USB0_VDDA12
(3)
AHCLKX0/AHCLKX2/USB_REFCLKIN/GP2[11]
(1)
(2)
(3)
A
USB0 PHY data minus
137
A
USB0 PHY data plus
140
PWR
USB0 PHY 3.3-V supply
135
PWR
USB0 PHY 1.8-V supply input
134
PWR
125
I
USB0 PHY 1.2-V LDO output for bypass cap
IPD
USB_REFCLKIN. Optional clock input.
I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
Core power supply LDO output for USB PHY. This pin must be connected via a 0.22 uF capacitor to VSS.
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25
ADVANCE INFORMATION
AMUTE1/EPWMTZ/GP4[14]
GPIO
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3.6.15 Ethernet Media Access Controller (EMAC)
Table 3-17. Ethernet Media Access Controller (EMAC) Terminal Functions
SIGNAL NAME
PIN NO
TYPE (1)
PTP
PULL (2)
MUXED
DESCRIPTION
RMII
ADVANCE INFORMATION
AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11]
129
I/O
IPD
AXR0[6]/RMII_RXER/GP3[6]
118
I
IPD
AXR0[5]/RMII_RXD[1]/GP3[5]
117
I
IPD
AXR0[4]/RMII_RXD[0]/GP3[4]
116
I
IPD
AXR0[3]/RMII_CRS_DV/GP3[3]
115
I
IPD
AXR0[2]/RMII_TXEN/GP3[2]
113
O
IPD
AXR0[1]/RMII_TXD[1]/GP3[1]
112
O
IPD
AXR0[0]/RMII_TXD[0]/GP3[0]
111
O
IPD
AXR0[8]/MDIO_D/GP3[8]
121
I/O
IPU
AXR0[7]/MDIO_CLK/GP3[7]
120
O
IPD
McASP0, GPIO, BOOT
EMAC 50-MHz
clock input or
output.
EMAC RMII
receiver error.
EMAC RMII
receive data.
McASP0, GPIO
EMAC RMII carrier
sense data valid.
EMAC RMII
transmit enable.
EMAC RMII trasmit
data.
MDIO
(1)
(2)
McASP0, GPIO
MDIO data clock.
I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
3.6.16 Multimedia Card/Secure Digital (MMC/SD)
Table 3-18. Multimedia Card/Secure Digital (MMC/SD) Terminal Functions
SIGNAL NAME
PIN
NO
TYPE (1)
PULL (2)
MUXED
DESCRIPTION
PTP
EMA_A[1]/MMCSD_CLK/GP1[1]
30
O
IPU
EMA_A[2]/MMCSD_CMD/GP1[2]
31
I/O
IPU
EMA_D[7]/MMCSD_DAT[7]/GP0[7]/BOOT[13]
54
I/O
IPU
EMA_D[6]/MMCSD_DAT[6]/GP0[6]
52
I/O
IPU
EMA_D[5]/MMCSD_DAT[5]/GP0[5]
51
I/O
IPU
EMA_D[4]/MMCSD_DAT[4]/GP0[4]
49
I/O
IPU
EMA_D[3]/MMCSD_DAT[3]/GP0[3]
48
I/O
IPU
EMA_D[2]/MMCSD_DAT[2]/GP0[2]
46
I/O
IPU
EMA_D[1]/MMCSD_DAT[1]/GP0[1]
45
I/O
IPU
EMA_D[0]/MMCSD_DAT[0]/GP0[0]/BOOT[12]
44
I/O
IPU
(1)
(2)
26
EMIFA, GPIO
MMCSD_CLK.
MMCSD_CMD.
EMIFA, GPIO, BOOT
EMIFA, GPIO
MMC/SD data.
EMIFA, GPIO, BOOT
I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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3.6.17 General-Purpose IO Only Terminal Functions
Table 3-19. General-Purpose IO Only Terminal Functions
SIGNAL NAME
GP7[14]
(1)
(1)
PIN NO
PTP
157
TYPE
PULL
DESCRIPTION
I/O
IPD
General-Purpose IO signal.
GP7[14] is initially configured as a reserved function after reset and will not be in a predictable state. This signal will only be stable after
the GPIO configuration for this pin has been completed. Users should carefully consider the system implications of this pin being in an
unknown state after reset.
3.6.18 Reserved and No Connect
Table 3-20. Reserved and No Connect Terminal Functions
PIN NO
PTP
TYPE (1)
DESCRIPTION
RSV2
133
PWR
Reserved. For proper device operation, this pin must be tied directly to
CVDD.
RSV3
149
PWR
Reserved. For proper device operation, this pin must be tied directly to
CVDD.
RSV4
148
I
Reserved. This pin may be tied high or low.
NC
136
-
No Connect (leave unconnected)
NC
139
-
No Connect (leave unconnected)
(1)
ADVANCE INFORMATION
SIGNAL NAME
PWR = Supply voltage.
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3.6.19 Supply and Ground
Table 3-21. Supply and Ground Terminal Functions
SIGNAL NAME
PIN NO
TYPE (1)
PTP
DESCRIPTION
CVDD (Core supply)
10, 20, 28, 38,
50, 56, 61, 69,
77, 93, 104,
114, 147, 154,
161, 167
PWR
1.2-V core supply voltage pins
RVDD (Internal RAM supply)
67, 159
PWR
1.2V internal ram supply voltage pins
DVDD (I/O supply)
5, 15, 24, 33,
43, 47, 53, 58,
65, 71, 75, 81,
87, 90, 99,
109, 119, 128,
151, 158, 164,
172
PWR
3.3-V I/O supply voltage pins.
VSS (Ground)
177
GND
Ground pins.
ADVANCE INFORMATION
(1)
28
PWR = Supply voltage, GND - Ground.
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4 Device Configuration
4.1
Boot Modes
This device supports a variety of boot modes through an internal ROM bootloader. This device does not
support dedicated hardware boot modes; therefore, all boot modes utilize the internal ROM. The input
states of the BOOT pins are sampled and latched into the BOOTCFG register, which is part of the system
configuration (SYSCFG) module, when device reset is deasserted. Boot mode selection is determined by
the values of the BOOT pins
4.2
ADVANCE INFORMATION
The following boot modes are supported:
• NAND Flash boot
– 8-bit NAND
• NOR Flash boot
– NOR Direct boot (8-bit or 16-bit)
– NOR Legacy boot (8-bit or 16-bit)
– NOR AIS boot (8-bit or 16-bit)
• I2C0 / I2C1 Boot
– EEPROM (Master Mode)
– External Host (Slave Mode)
• SPI0 / SPI1 Boot
– Serial Flash (Master Mode)
– SERIAL EEPROM (Master Mode)
– External Host (Slave Mode)
• UART0 / UART1 / UART2 Boot
– External Host
SYSCFG Module
The following system level features of the chip are controlled by the SYSCFG peripheral:
• Readable Device, Die, and Chip Revision ID
• Control of Pin Multiplexing
• Priority of bus accesses different bus masters in the system
• Capture at power on reset the chip BOOT[15:0] pin values and make them available to software
• Special case settings for peripherals:
– Locking of PLL controller settings
– Default burst sizes for EDMA3 TC0 and TC1
– Selection of the source for the eCAP module input capture (including on chip sources)
– McASP AMUTEIN selection and clearing of AMUTE status for the three McASP peripherals
– Control of the reference clock source and other side-band signals for both of the integrated USB
PHYs
– Clock source selection for EMIFA and EMIFB
• Selects the source of emulation suspend signal of peripherals supporting this function.
Since the SYSCFG peripheral controls global operation of the device, its registers are protected against
erroneous accesses by several mechanisms:
• A special key sequence must be written to KICK0, KICK1 registers before any other registers are
writeable.
• Additionally, many registers are accessible only by a host (ARM) when it is operating in its privileged
mode. (ex. from the kernel, but not from user space code).
Device Configuration
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Table 4-1. System Configuration (SYSCFG) Module Register Access
BYTE ADDRESS
ACRONYM
0x01C1 4000
REVID
Revision Identification Register
—
0x01C14008
DIEIDR0
Device Identification Register 0
—
0x01C1 400C
DIEIDR1
Device Identification Register 1
—
0x01C1 4010
DIEIDR2
Device Identification Register 2
—
0x01C1 4014
DIEIDR3
Device Identification Register 3
—
0x01C1 4018
DEVIDR0
Device Identification Register 0
0x01C1 4020
BOOTCFG
0x01C1 4038
ADVANCE INFORMATION
30
REGISTER DESCRIPTION
ACCESS
—
Boot Configuration Register
Privileged mode
KICK0R
Kick 0 Register
Privileged mode
0x01C1 403C
KICK1R
Kick 1 Register
Privileged mode
0x01C1 4040
HOST0CFG
Host 0 Configuration Register
0x01C1 4044
HOST1CFG
Host 1 Configuration Register
0x01C1 40E0
IRAWSTAT
Interrupt Raw Status/Set Register
Privileged mode
0x01C1 40E4
IENSTAT
Interrupt Enable Status/Clear Register
Privileged mode
0x01C1 40E8
IENSET
Interrupt Enable Register
Privileged mode
0x01C1 40EC
IENCLR
Interrupt Enable Clear Register
Privileged mode
End of Interrupt Register
Privileged mode
Fault Address Register
Privileged mode
—
—
0x01C1 40F0
EOI
0x01C1 40F4
FLTADDRR
0x01C1 40F8
FLTSTAT
Fault Status Register
0x01C1 4110
MSTPRI0
Master Priority 0 Register
Privileged mode
0x01C1 4114
MSTPRI1
Master Priority 1 Register
Privileged mode
0x01C1 4118
MSTPRI2
Master Priority 2 Register
Privileged mode
0x01C1 4120
PINMUX0
Pin Multiplexing Control 0 Register
Privileged mode
0x01C1 4124
PINMUX1
Pin Multiplexing Control 1 Register
Privileged mode
0x01C1 4128
PINMUX2
Pin Multiplexing Control 2 Register
Privileged mode
0x01C1 412C
PINMUX3
Pin Multiplexing Control 3 Register
Privileged mode
0x01C1 4130
PINMUX4
Pin Multiplexing Control 4 Register
Privileged mode
0x01C1 4134
PINMUX5
Pin Multiplexing Control 5 Register
Privileged mode
0x01C1 4138
PINMUX6
Pin Multiplexing Control 6 Register
Privileged mode
0x01C1 413C
PINMUX7
Pin Multiplexing Control 7 Register
Privileged mode
0x01C1 4140
PINMUX8
Pin Multiplexing Control 8 Register
Privileged mode
0x01C1 4144
PINMUX9
Pin Multiplexing Control 9 Register
Privileged mode
0x01C1 4148
PINMUX10
Pin Multiplexing Control 10 Register
Privileged mode
0x01C1 414C
PINMUX11
Pin Multiplexing Control 11 Register
Privileged mode
0x01C1 4150
PINMUX12
Pin Multiplexing Control 12 Register
Privileged mode
0x01C1 4154
PINMUX13
Pin Multiplexing Control 13 Register
Privileged mode
—
0x01C1 4158
PINMUX14
Pin Multiplexing Control 14 Register
Privileged mode
0x01C1 415C
PINMUX15
Pin Multiplexing Control 15 Register
Privileged mode
0x01C1 4160
PINMUX16
Pin Multiplexing Control 16 Register
Privileged mode
0x01C1 4164
PINMUX17
Pin Multiplexing Control 17 Register
Privileged mode
0x01C1 4168
PINMUX18
Pin Multiplexing Control 18 Register
Privileged mode
0x01C1 416C
PINMUX19
Pin Multiplexing Control 19 Register
Privileged mode
0x01C1 4170
SUSPSRC
Suspend Source Register
Privileged mode
0x01C1 4174
-
Reserved
0x01C1 4178
-
Reserved
0x01C1 417C
CFGCHIP0
Chip Configuration 0 Register
Privileged mode
0x01C1 4180
CFGCHIP1
Chip Configuration 1 Register
Privileged mode
0x01C1 4184
CFGCHIP2
Chip Configuration 2 Register
Privileged mode
Device Configuration
—
—
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Table 4-1. System Configuration (SYSCFG) Module Register Access (continued)
BYTE ADDRESS
ACRONYM
0x01C1 4188
CFGCHIP3
Chip Configuration 3 Register
Privileged mode
0x01C1 418C
CFGCHIP4
Chip Configuration 4 Register
Privileged mode
4.3
REGISTER DESCRIPTION
ACCESS
Pullup/Pulldown Resistors
Proper board design should ensure that input pins to the device always be at a valid logic level and not
floating. This may be achieved via pullup/pulldown resistors. The device features internal pullup (IPU) and
internal pulldown (IPD) resistors on most pins to eliminate the need, unless otherwise noted, for external
pullup/pulldown resistors.
For the boot and configuration pins, if they are both routed out and 3-stated (not driven), it is strongly
recommended that an external pullup/pulldown resistor be implemented. Although, internal
pullup/pulldown resistors exist on these pins and they may match the desired configuration value,
providing external connectivity can help ensure that valid logic levels are latched on these device boot and
configuration pins. In addition, applying external pullup/pulldown resistors on the boot and configuration
pins adds convenience to the user in debugging and flexibility in switching operating modes.
Tips for choosing an external pullup/pulldown resistor:
• Consider the total amount of current that may pass through the pullup or pulldown resistor. Make sure
to include the leakage currents of all the devices connected to the net, as well as any internal pullup or
pulldown resistors.
• Decide a target value for the net. For a pulldown resistor, this should be below the lowest VIL level of
all inputs connected to the net. For a pullup resistor, this should be above the highest VIH level of all
inputs on the net. A reasonable choice would be to target the VOL or VOH levels for the logic family of
the limiting device; which, by definition, have margin to the VIL and VIH levels.
• Select a pullup/pulldown resistor with the largest possible value; but, which can still ensure that the net
will reach the target pulled value when maximum current from all devices on the net is flowing through
the resistor. The current to be considered includes leakage current plus, any other internal and
external pullup/pulldown resistors on the net.
• For bidirectional nets, there is an additional consideration which sets a lower limit on the resistance
value of the external resistor. Verify that the resistance is small enough that the weakest output buffer
can drive the net to the opposite logic level (including margin).
• Remember to include tolerances when selecting the resistor value.
• For pullup resistors, also remember to include tolerances on the IO supply rail.
• For most systems, a 1-kΩ resistor can be used to oppose the IPU/IPD while meeting the above
criteria. Users should confirm this resistor value is correct for their specific application.
• For most systems, a 20-kΩ resistor can be used to compliment the IPU/IPD on the boot and
configuration pins while meeting the above criteria. Users should confirm this resistor value is correct
for their specific application.
• For more detailed information on input current (II), and the low-/high-level input voltages (VIL and VIH)
for the device, see Section 5.2, Recommended Operating Conditions.
• For the internal pullup/pulldown resistors for all device pins, see the peripheral/system-specific terminal
functions table.
Device Configuration
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An external pullup/pulldown resistor needs to be used in the following situations:
• Boot and Configuration Pins: If the pin is both routed out and 3-stated (not driven), an external
pullup/pulldown resistor is strongly recommended, even if the IPU/IPD matches the desired value/state.
• Other Input Pins: If the IPU/IPD does not match the desired value/state, use an external
pullup/pulldown resistor to pull the signal to the opposite rail.
AM1705
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5 Device Operating Conditions
5.1 Absolute Maximum Ratings Over Operating Junction Temperature Range
(Unless Otherwise Noted) (1)
Core
(CVDD, RVDD, PLL0_VDDA )
Supply voltage ranges
I/O, 1.8V
(USB0_VDDA18)
ADVANCE INFORMATION
Output voltage ranges
-0.5 V to 2 V
(2)
I/O, 3.3V
(DVDD, USB0_VDDA33)
Input voltage ranges
-0.5 V to 1.4 V
(2)
-0.5 V to 3.8V
(2)
VI I/O, 1.2V
(OSCIN)
-0.3 V to CVDD + 0.3V
VI I/O, 3.3V
(Steady State)
-0.3V to DVDD + 0.3V
VI I/O, 3.3V
(Transient)
DVDD + 20%
up to 20% of Signal
Period
VI I/O, USB 5V Tolerant Pins:
(USB0_DM, USB0_DP)
5.25V (3)
VI I/O, USB0 VBUS
5.50V (3)
VO I/O, 3.3V
(Steady State)
-0.5 V to DVDD + 0.3V
VO I/O, 3.3V
(Transient Overshoot/Undershoot)
20% of DVDD for up to
20% of the signal period
Clamp Current
Input or Output Voltages 0.3V above or below their respective power
rails. Limit clamp current that flows through the I/O's internal diode
protection cells.
Storage temperature range, Tstg
(default)
Operating Junction Temperature ranges,
TJ
(1)
(2)
(3)
32
±20mA
-55°C to 150°C
Commercial (default)
0°C to 90°C
Industrial (D version)
-40°C to 90°C
Extended (A version)
-40°C to 105°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to VSS, PLL0_VSSA, OSCVSS
Up to a max of 24 hours.
Device Operating Conditions
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Recommended Operating Conditions
MIN
NOM
MAX
UNIT
375 MHz version
1.14
1.2
1.32
V
456 MHz version
1.25
1.3
1.35
V
CVDD
Supply voltage, Core
(CVDD, PLL0_VDDA )
RVDD
Supply Voltage, Internal RAM
1.14
1.2
1.32
V
Supply voltage, I/O, 1.8V
(USB0_VDDA18, USB1_VDDA18)
1.71
1.8
1.89
V
Supply voltage, I/O, 3.3V
(DVDD, USB0_VDDA33)
3.15
3.3
3.45
V
0
0
0
V
DVDD
Supply ground
(VSS, PLL0_VSSA, OSCVSS (1))
VSS
High-level input voltage, I/O, 3.3V
VIH
(2)
VIL
(2)
2
High-level input voltage, OSCIN
V
0.7*CVDD
Low-level input voltage, I/O, 3.3V
0.8
Low-level input voltage, OSCIN
VHYS
Input Hysteresis
USB
USB0_VBUS
tt
Transition time, 10%-90%, All Inputs (unless otherwise specified in
the electrical data sections)
FSYSCLK6
(1)
(2)
(3)
ARM Operating Frequency (SYSCLK6)
V
0.3*CVDD
160
4.75
5
mV
5.25
0.25P
V
(3)
ns
Commercial (default)
0
375 (1.2V)
456 (1.3V)
MHz
Industrial (D suffix)
0
375 (1.2V)
456(1.3V)
MHz
Extended (A suffix)
0
375(1.2V)
MHz
When an external crystal is used, oscillator (OSC_VSS) ground must be kept separate from other grounds and connected directly to the
crystal load capacitor ground. These pins are shorted to VSS on the device itself and should not be connected to VSS on the circuit
board. If a crystal is not used and the clock input is driven directly, then the oscillator VSS may be connected to board ground.
These I/O specifications do not apply to USB I/Os. USB0 I/Os adhere to USB2.0 specification.
P = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve noise immunity on input
signals.
Device Operating Conditions
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5.2
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5.3
Electrical Characteristics Over Recommended Ranges of Supply Voltage and
Operating Junction Temperature (Unless Otherwise Noted)
PARAMETER
VOH
Low/full speed:
USB0_DM and USB0_DP
High speed:
USB_DM and USB_DP
High-level output voltage (3.3V I/O)
VOL
(1)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2.8
USB0_VDDA33
V
360
440
mV
DVDD= 3.15V, IOH = -4 mA
2.4
V
DVDD= 3.15V, IOH = 100 mA
2.95
V
Low/full speed:
USB_DM and USB_DP
0.0
0.3
V
High speed:
USB_DM and USB_DP
-10
10
mV
DVDD= 3.15V, IOL = 4mA
0.4
V
DVDD= 3.15V, IOL = -100 mA
0.2
V
VI = VSS to DVDD without opposing
internal resistor
±35
mA
Low-level output voltage (3.3V I/O)
II
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Input current
ADVANCE INFORMATION
VI = VSS to DVDD with opposing
internal pullup resistor (2)
30
-200
mA
VI = VSS to DVDD with opposing
internal pulldown resistor (2)
-50
300
mA
±40
mA
VI = VSS to USB1_VDDA33 USB1_DM and USB1_DP
IOH
High-level output current
All peripherals
-4
mA
IOL
Low-level output current
All peripherals
4
mA
I/O Off-state output current
VO = VDD or VSS; Internal pull disabled
±35
mA
LVCMOS signals
3
pF
LVCMOS signals
3
pF
IOZ
CI
CO
(1)
(2)
(3)
34
(3)
Input capacitance
Output capacitance
II applies to input-only pins and bi-directional pins. For input-only pins, II indicates the input leakage current. For bi-directional pins, II
indicates the input leakage current and off-state (Hi-Z) output leakage current.
Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.
IOZ applies to output-only pins, indicating off-state (Hi-Z) output leakage current.
Device Operating Conditions
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6 Peripheral Information and Electrical Specifications
Parameter Information
6.1.1
Parameter Information Device-Specific Information
Tester Pin Electronics
42 Ω
3.5 nH
Transmission Line
Z0 = 50 Ω
(see note)
4.0 pF
A.
1.85 pF
Data Sheet Timing Reference Point
Output
Under
Test
Device Pin
(see note)
The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to
produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to
add or subtract the transmission line delay (2 ns or longer) from the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the
device pin and the input signals are driven between 0V and the appropriate IO supply rail for the signal.
Figure 6-1. Test Load Circuit for AC Timing Measurements
The load capacitance value stated is only for characterization and measurement of AC timing signals. This
load capacitance value does not indicate the maximum load the device is capable of driving.
6.1.1.1
Signal Transition Levels
All input and output timing parameters are referenced to Vref for both "0" and "1" logic levels. For 3.3 V I/O,
Vref = 1.65 V. For 1.8 V I/O, Vref = 0.9 V.
Vref
Figure 6-2. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks,
VOLMAX and VOH MIN for output clocks.
Vref = VIH MIN (or VOH MIN)
Vref = VIL MAX (or VOL MAX)
Figure 6-3. Rise and Fall Transition Time Voltage Reference Levels
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Peripheral Information and Electrical Specifications
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6.1
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6.2
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Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner.
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6.3
6.3.1
SPRS657A – FEBRUARY 2010 – REVISED APRIL 2010
Power Supplies
Power-on Sequence
The device should be powered-on in the following order:
• 2a) CVDD core logic supply
• 2b) Other 1.2V logic supplies (RVDD, PLL0_VDDA). Groups 2a) and 2b) may be powered up together
or 2a) first followed by 2b).
• 3) All 1.8V IO supplies (USB0_VDDA18).
• 4) All digital IO and analog 3.3V PHY supplies (DVDD, USB0_VDDA33). USB0_VDDA33 is not
required if USB0 is not used and may be left unconnected.
There is no specific required voltage ramp rate for any of the supplies.
RESET must be maintained active until all power supplies have reached their nominal values.
6.3.2
Power-off Sequence
The power supplies can be powered-off in any order as long as the 3.3V supplies do not remain powered
with the other supplies unpowered.
6.4
Unused USB0 (USB2.0) Pin Configurations
Table 6-1. Unused USB0 Pin Configurations
6.5
6.5.1
SIGNAL NAME
Configuration
(When USB0 is not used)
USB0_DM
No connect
USB0_DP
No connect
USB0_VDDA33
No connect
USB0_VDDA18
No connect
USB0_VBUS
No connect
USB0_VDDA12
No connect
AHCLKX0/AHCLKX2/USB_REFCLKIN/
GP2[11]
No connect or use as alternate function
Reset
Power-On Reset (POR)
A power-on reset (POR) is required to place the device in a known good state after power-up. Power-On
Reset is initiated by bringing RESET and TRST low at the same time. POR sets all of the device internal
logic to its default state. All pins are 3-stated .
While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for
the device to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG
port interface and device's emulation logic in the reset state.
TRST only needs to be released when it is necessary to use a JTAG controller to debug the device or
exercise the device's boundary scan functionality. Note: TRST is synchronous and must be clocked by
TCK; otherwise, the boundary scan logic may not respond as expected after TRST is asserted.
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Note: Future devices may support higher performance at a higher core logic voltage (CVDD). If future
migration is desired, the current design should provide separate supplies for 2a) and 2b). If not, then 2a)
and 2b) may be provided by a single supply.
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RESET must be released only in order for boundary-scan JTAG to read the variant field of IDCODE
correctly. Other boundary-scan instructions work correctly independent of current state of RESET. For
maximum reliability, the device includes an internal pulldown on the TRST pin to ensure that TRST will
always be asserted upon power up and the device's internal emulation logic will always be properly
initialized.
JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG
controllers may not drive TRST high but expect the use of a pullup resistor on TRST. When using this type
of JTAG controller, assert TRST to intialize the device after powerup and externally drive TRST high
before attempting any emulation or boundary scan operations.
RTCK is maintained active through a POR.
A
•
•
•
summary of the effects of Power-On Reset is given below:
All internal logic (including emulation logic and the PLL logic) is reset to its default state
Internal memory is not maintained through a POR
All device pins go to a high-impedance state
CAUTION: A watchdog reset triggers a POR.
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6.5.2
SPRS657A – FEBRUARY 2010 – REVISED APRIL 2010
Warm Reset
A warm reset provides a limited reset to the device. Warm Reset is initiated by bringing only RESET low
(TRST is maintained high through a warm reset). Warm reset sets certain portions of the device to their
default state while leaving others unaltered. All pins are 3-stated .
During emulation, the emulator will maintain TRST high and hence only warm reset (not POR) is available
during emulation debug and development.
RTCK is maintained active through a warm reset.
summary of the effects of Warm Reset is given below:
All internal logic (except for the emulation logic and the PLL logic) is reset to its default state
Internal memory is maintained through a warm reset
All device pins go to a high-impedance state
ADVANCE INFORMATION
A
•
•
•
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6.5.3
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Reset Electrical Data Timings
Table 6-2 assumes testing over the recommended operating conditions.
Table 6-2. Reset Timing Requirements (,
No.
(1)
)
PARAMETER
MIN
MAX
UNIT
1
tw(RSTL)
Pulse width, RESET/TRST low
100
ns
2
tsu(BPV-RSTH)
Setup time, boot pins valid before RESET/TRST high
20
ns
3
th(RSTH-BPV)
Hold time, boot pins valid after RESET/TRST high
20
ns
(1)
For power-on reset (POR), the reset timings in this table refer to RESET and TRST together. For warm reset, the reset timings in this
table refer to RESET only (TRST is held high).
Power
Supplies
Ramping
Power Supplies Stable
Clock Source Stable
OSCIN
ADVANCE INFORMATION
1
RESET
TRST
3
2
Boot Pins
Config
Figure 6-4. Power-On Reset (RESET and TRST active) Timing
Power Supplies Stable
OSCIN
TRST
1
RESET
3
2
Boot Pins
Driven or Hi-Z
Config
Figure 6-5. Warm Reset (RESET active, TRST high) Timing
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6.6
SPRS657A – FEBRUARY 2010 – REVISED APRIL 2010
Crystal Oscillator or External Clock Input
The device includes two choices to provide an external clock input, which is fed to the on-chip PLL to
generate high-frequency system clocks. These options are illustrated in Figure 6-6 and Figure 6-7. For
input clock frequencies between 12 and 20 MHz, a crystal with 80 ohm max ESR is recommended. For
input clock frequencies between 20 and 30 MHz, a crystal with 60 ohm max ESR is recommended.
Typical C1, C2 values are 10-20 pF.
• Figure 6-6 illustrates the option that uses on-chip 1.2V oscillator with external crystal circuit.
• Figure 6-7 illustrates the option that uses an external 1.2V clock input.
C2
OSCIN
Clock Input
to PLL
X1
OSCOUT
ADVANCE INFORMATION
C1
OSCVSS
Figure 6-6. On-Chip 1.2V Oscillator
Table 6-3. Oscillator Timing Requirements
PARAMETER
fosc
Oscillator frequency range (OSCIN/OSCOUT)
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MIN
MAX
UNIT
12
30
MHz
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OSCIN
NC
Clock
Input
to PLL
OSCOUT
OSCVSS
Figure 6-7. External 1.2V Clock Source
Table 6-4. OSCIN Timing Requirements
ADVANCE INFORMATION
No.
PARAMETER
fOSCIN
OSCIN frequency range (OSCIN)
tc(OSCIN)
Cycle time, external clock driven on OSCIN
MIN
MAX
UNIT
12
50
MHz
20
ns
tw(OSCINH) Pulse width high, external clock on OSCIN
0.4 tc(OSCIN)
ns
tw(OSCINL) Pulse width low, external clock on OSCIN
0.4 tc(OSCIN)
tt(OSCIN)
Transition time, OSCIN
tj(OSCIN)
Period jitter, OSCIN
(1)
42
ns
0.25P
(1)
0.02P
ns
ns
P = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve noise immunity on input
signals.
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6.7
SPRS657A – FEBRUARY 2010 – REVISED APRIL 2010
Clock PLLs
The device has one PLL controller that provides clock to different parts of the system. PLL0 provides
clocks (though various dividers) to most of the components of the device.
The PLL controller provides the following:
• Glitch-Free Transitions (on changing clock settings)
• Domain Clocks Alignment
• Clock Gating
• PLL power down
The various clock outputs given by the controller are as follows:
• Domain Clocks: SYSCLK [1:n]
• Auxiliary Clock from reference clock source: AUXCLK
Various other controls supported are as follows:
• PLL Multiplier Control: PLLM
• Software programmable PLL Bypass: PLLEN
6.7.1
PLL Device-Specific Information
The PLL requires some external filtering components to reduce power supply noise as shown in
Figure 6-8.
1.14V - 1.32V
PLL0_VDDA
50R
0.1
µF
VSS
50R
0.01
µF
PLL0_VSSA
Ferrite Bead: Murata BLM31PG500SN1L or Equivalent
Figure 6-8. PLL External Filtering Components
The input to the PLL is either from the on-chip oscillator (OSCIN pin) or from an external clock on the
CLKIN pin. The PLL outputs seven clocks that have programmable divider options. Figure 6-9 illustrates
the PLL Topology.
The PLL is disabled by default after a device reset. It must be configured by software according to the
allowable operating conditions listed in Table 6-5 before enabling the processor to run from the PLL by
setting PLLEN = 1.
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Various dividers that can be used are as follows:
• Post-PLL Divider: POSTDIV
• SYSCLK Divider: D1, ¼, Dn
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CLKMODE
OSCIN
PLLEN
Square
Wave
1
Crystal
0
Pre-Div
PLL
Post-Div
PLLM
1
PLLDIV1 (/1)
SYSCLK1
0
PLLDIV2 (/2)
SYSCLK2
PLLDIV3 (/3)
SYSCLK3
PLLDIV4 (/4)
SYSCLK4
PLLDIV5 (/3)
SYSCLK5
PLLDIV7 (/6)
SYSCLK7
AUXCLK
EMIFA
Internal
Clock
Source
0
ADVANCE INFORMATION
DIV4.5
1
CFGCHIP3[EMA_CLKSRC]
DIV4.5
EMIFB
Internal
Clock
Source
1
0
CFGCHIP3[EMB_CLKSRC]
Figure 6-9. PLL Topology
Table 6-5. Allowed PLL Operating Conditions
No.
PARAMETER
Default
Value
MIN
MAX
UNIT
1
PLLRST: Assertion time during
initialization
N/A
1000
N/A
ns
2
Lock time: The time that the application
has to wait for the PLL to acquire locks
before setting PLLEN, after changing
PREDIV, PLLM, or OSCIN
N/A
3
PREDIV
/1
4
PLL input frequency
( PLLREF)
2000 N
m
where N = Pre-Divider Ratio
Max PLL Lock Time =
N/A
OSCIN
cycles
M = PLL Multiplier
(1)
5
(1)
/32
ns
12
50
MHz
x20
x4
x32
6
PLL output frequency. ( PLLOUT )
N/A
400
600 (2)
MHz
7
POSTDIV
/1
/2 (2)
/32
ns
(1)
(2)
44
PLL multiplier values (PLLM)
/1
The multiplier values must be chosen such that the PLL output frequency (at PLLOUT) is between 400 and 600 MHz, but the frequency
going into the SYSCLK dividers (after the post divider) cannot exceed 300 MHz. The Post Divider and SYSCLK divider values must be
chosen such that the CPU clocks do not exceed 300 MHz.
PLL post divider / 2 must be used. The /4.5 clock path can be used to generate an EMIF clock from the undivided (i.e. 600 MHz) PLL
output clock.
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6.7.2
SPRS657A – FEBRUARY 2010 – REVISED APRIL 2010
Device Clock Generation
PLL0 is controlled by PLL Controller 0. The PLLC0 manages the clock ratios, alignment, and gating for the
system clocks to the chip. The PLLC is responsible for controlling all modes of the PLL through software,
in terms of pre-division of the clock inputs, multiply factor within the PLL, and post-division for each of the
chip-level clocks from the PLL output. The PLLC also controls reset propagation through the chip, clock
alignment, and test points.
6.7.3
PLL Controller 0 Registers
Table 6-6. PLL Controller 0 Registers
BYTE
ADDRESS
ACRONYM
0x01C1 1000
REVID
0x01C1 10E4
RSTYPE
Reset Type Status Register
0x01C1 1100
PLLCTL
PLL Control Register
0x01C1 1104
-
REGISTER DESCRIPTION
Revision Identification Register
Reserved
PLLM
0x01C1 1114
PREDIV
PLL Multiplier Control Register
PLL Pre-Divider Control Register
0x01C1 1118
PLLDIV1
PLL Controller Divider 1 Register
0x01C1 111C
PLLDIV2
PLL Controller Divider 2 Register
0x01C1 1120
PLLDIV3
PLL Controller Divider 3 Register
0x01C1 1124
-
0x01C1 1128
POSTDIV
PLL Post-Divider Control Register
ADVANCE INFORMATION
0x01C1 1110
Reserved
0x01C1 1138
PLLCMD
PLL Controller Command Register
0x01C1 113C
PLLSTAT
PLL Controller Status Register
0x01C1 1140
ALNCTL
PLL Controller Clock Align Control Register
0x01C1 1144
DCHANGE
0x01C1 1148
CKEN
0x01C1 114C
CKSTAT
Clock Status Register
0x01C1 1150
SYSTAT
SYSCLK Status Register
0x01C1 1160
PLLDIV4
PLL Controller Divider 4 Register
0x01C1 1164
PLLDIV5
PLL Controller Divider 5 Register
0x01C1 1168
PLLDIV6
PLL Controller Divider 6 Register
0x01C1 116C
PLLDIV7
PLL Controller Divider 7 Register
PLLDIV Ratio Change Status Register
Clock Enable Control Register
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6.8
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Interrupts
6.8.1
ARM CPU Interrupts
The ARM9 CPU core supports 2 direct interrupts: FIQ and IRQ. The ARM Interrupt Controller extends the
number of interrupts to 100, and provides features like programmable masking, priority, hardware nesting
support, and interrupt vector generation.
6.8.1.1
ARM Interrupt Controller (AINTC) Interrupt Signal Hierarchy
ADVANCE INFORMATION
The ARM Interrupt controller organizes interrupts into the following hierarchy:
• Peripheral Interrupt Requests
– Individual Interrupt Sources from Peripherals
• 100 System Interrupts
– One or more Peripheral Interrupt Requests are combined (fixed configuration) to generate a
System Interrupt.
– After prioritization, the AINTC will provide an interrupt vector based unique to each System Interrupt
• 32 Interrupt Channels
– Each System Interrupt is mapped to one of the 32 Interrupt Channels
– Channel Number determines the first level of prioritization, Channel 0 is highest priority and 31
lowest.
– If more than one system interrupt is mapped to a channel, priority within the channel is determined
by system interrupt number (0 highest priority)
• Host Interrupts (FIQ and IRQ)
– Interrupt Channels 0 and 1 generate the ARM FIQ interrupt
– Interrupt Channels 2 through 31 Generate the ARM IRQ interrupt
• Debug Interrupts
– Two Debug Interrupts are supported and can be used to trigger events in the debug subsystem
– Sources can be selected from any of the System Interrupts or Host Interrupts
6.8.1.2
AINTC Hardware Vector Generation
The AINTC also generates an interrupt vector in hardware for both IRQ and FIQ host interrupts. This may
be used to accelerate interrupt dispatch. A unique vector is generated for each of the 100 system
interrupts. The vector is computed in hardware as:
VECTOR = BASE + (SYSTEM INTERRUPT NUMBER × SIZE)
Where BASE and SIZE are programmable. The computed vector is a 32-bit address which may
dispatched to using a single instruction of type LDR PC, [PC, #-<offset_12>] at the FIQ and IRQ vector
locations (0xFFFF0018 and 0xFFFF001C respectively).
6.8.1.3
AINTC Hardware Interrupt Nesting Support
Interrupt nesting occurs when an interrupt service routine re-enables interrupts, to allow the CPU to
interrupt the ISR if a higher priority event occurs. The AINTC provides hardware support to facilitate
interrupt nesting. It supports both global and per host interrupt (FIQ and IRQ in this case) automatic
nesting. If enabled, the AINTC will automatically update an internal nesting register that temporarily masks
interrupts at and below the priority of the current interrupt channel. Then if the ISR re-enables interrupts;
only higher priority channels will be able to interrupt it. The nesting level is restored by the ISR by writing
to the nesting level register on completion. Support for nesting can be enabled/disabled by software, with
the option of automatic nesting on a global or per host interrupt basis; or manual nesting.
6.8.1.4
AINTC System Interrupt Assignments on the device
System Interrupt assignments for the device are listed in Table 6-7
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Table 6-7. AINTC System Interrupt Assignments
Interrupt Name
Source
0
COMMTX
ARM
1
COMMRX
ARM
2
NINT
ARM
3
PRU_EVTOUT0
PRUSS Interrupt
4
PRU_EVTOUT1
PRUSS Interrupt
5
PRU_EVTOUT2
PRUSS Interrupt
6
PRU_EVTOUT3
PRUSS Interrupt
7
PRU_EVTOUT4
PRUSS Interrupt
8
PRU_EVTOUT5
PRUSS Interrupt
9
PRU_EVTOUT6
PRUSS Interrupt
10
PRU_EVTOUT7
PRUSS Interrupt
11
EDMA3_CC0_CCINT
EDMA CC Region 0
12
EDMA3_CC0_CCERRINT
EDMA CC
13
EDMA3_TC0_TCERRINT
EDMA TC0
14
EMIFA_INT
EMIFA
15
IIC0_INT
I2C0
16
MMCSD_INT0
MMCSD
17
MMCSD_INT1
MMCSD
18
PSC0_ALLINT
PSC0
19
-
Reserved
20
SPI0_INT
SPI0
21
T64P0_TINT12
Timer64P0 Interrupt 12
22
T64P0_TINT34
Timer64P0 Interrupt 34
23
T64P1_TINT12
Timer64P1 Interrupt 12
24
T64P1_TINT34
Timer64P1 Interrupt 34
25
UART0_INT
UART0
26
-
Reserved
27
PROTERR
SYSCFG Protection Shared Interrupt
28 - 31
-
Reserved
32
EDMA3_TC1_TCERRINT
EDMA TC1
33
EMAC_C0RXTHRESH
EMAC - Core 0 Receive Threshold Interrupt
34
EMAC_C0RX
EMAC - Core 0 Receive Interrupt
35
EMAC_C0TX
EMAC - Core 0 Transmit Interrupt
36
EMAC_C0MISC
EMAC - Core 0 Miscellaneous Interrupt
37
EMAC_C1RXTHRESH
EMAC - Core 1 Receive Threshold Interrupt
38
EMAC_C1RX
EMAC - Core 1 Receive Interrupt
39
EMAC_C1TX
EMAC - Core 1 Transmit Interrupt
40
EMAC_C1MISC
EMAC - Core 1 Miscellaneous Interrupt
41
EMIF_MEMERR
EMIFB
42
GPIO_B0INT
GPIO Bank 0 Interrupt
43
GPIO_B1INT
GPIO Bank 1 Interrupt
44
GPIO_B2INT
GPIO Bank 2 Interrupt
45
GPIO_B3INT
GPIO Bank 3 Interrupt
46
GPIO_B4INT
GPIO Bank 4 Interrupt
47
GPIO_B5INT
GPIO Bank 5 Interrupt
48
GPIO_B6INT
GPIO Bank 6 Interrupt
49
GPIO_B7INT
GPIO Bank 7 Interrupt
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System Interrupt
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Table 6-7. AINTC System Interrupt Assignments (continued)
System Interrupt
Source
ADVANCE INFORMATION
50
-
Reserved
51
IIC1_INT
I2C1
52
-
Reserved
53
UART_INT1
UART1
54
MCASP_INT
McASP0, 1, 2 Combined RX / TX Interrupts
55
PSC1_ALLINT
PSC1
56
SPI1_INT
SPI1
-
Reserved
58
USB0_INT
USB0 Interrupt
59
-
Reserved
60
-
Reserved
61
UART2_INT
UART2
62
-
Reserved
63
EHRPWM0
HiResTimer / PWM0 Interrupt
64
EHRPWM0TZ
HiResTimer / PWM0 Trip Zone Interrupt
65
EHRPWM1
HiResTimer / PWM1 Interrupt
66
EHRPWM1TZ
HiResTimer / PWM1 Trip Zone Interrupt
67
EHRPWM2
HiResTimer / PWM2 Interrupt
68
EHRPWM2TZ
HiResTimer / PWM2 Trip Zone Interrupt
69
ECAP0
ECAP0
70
ECAP1
ECAP1
71
ECAP2
ECAP2
72
EQEP0
EQEP0
73
EQEP1
EQEP1
74
T64P0_CMPINT0
Timer64P0 - Compare 0
75
T64P0_CMPINT1
Timer64P0 - Compare 1
76
T64P0_CMPINT2
Timer64P0 - Compare 2
77
T64P0_CMPINT3
Timer64P0 - Compare 3
78
T64P0_CMPINT4
Timer64P0 - Compare 4
79
T64P0_CMPINT5
Timer64P0 - Compare 5
80
T64P0_CMPINT6
Timer64P0 - Compare 6
81
T64P0_CMPINT7
Timer64P0 - Compare 7
82
T64P1_CMPINT0
Timer64P1 - Compare 0
83
T64P1_CMPINT1
Timer64P1 - Compare 1
84
T64P1_CMPINT2
Timer64P1 - Compare 2
85
T64P1_CMPINT3
Timer64P1 - Compare 3
86
T64P1_CMPINT4
Timer64P1 - Compare 4
87
T64P1_CMPINT5
Timer64P1 - Compare 5
88
T64P1_CMPINT6
Timer64P1 - Compare 6
89
T64P1_CMPINT7
Timer64P1 - Compare 7
90
ARMCLKSTOPREQ
PSC0
-
Reserved
91 - 100
48
Interrupt Name
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6.8.1.5
SPRS657A – FEBRUARY 2010 – REVISED APRIL 2010
AINTC Memory Map
Table 6-8. AINTC Memory Map
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
0xFFFE E000
REV
Revision Register
0xFFFE E004
CR
Control Register
0xFFFE E008 - 0xFFFE E00F
-
Reserved
0xFFFE E010
GER
0xFFFE E014 - 0xFFFE E01B
-
Global Enable Register
0xFFFE E01C
GNLR
Global Nesting Level Register
0xFFFE E020
SISR
System Interrupt Status Indexed Set Register
0xFFFE E024
SICR
System Interrupt Status Indexed Clear Register
0xFFFE E028
EISR
System Interrupt Enable Indexed Set Register
0xFFFE E02C
EICR
System Interrupt Enable Indexed Clear Register
Reserved
-
0xFFFE E034
HIEISR
Reserved
Host Interrupt Enable Indexed Set Register
0xFFFE E038
HIEICR
Host Interrupt Enable Indexed Clear Register
0xFFFE E03C - 0xFFFE E04F
-
0xFFFE E050
VBR
Vector Base Register
0xFFFE E054
VSR
Vector Size Register
0xFFFE E058
VNR
Vector Null Register
Reserved
0xFFFE E05C - 0xFFFE E07F
-
0xFFFE E080
GPIR
Global Prioritized Index Register
0xFFFE E084
GPVR
Global Prioritized Vector Register
0xFFFE E088 - 0xFFFE E1FF
-
0xFFFE E200 - 0xFFFE E20B
SRSR[1] - SRSR[3]
0xFFFE E20C- 0xFFFE E27F
-
0xFFFE E280 - 0xFFFE E28B
SECR[1] - SECR[3]
0xFFFE E28C - 0xFFFE E2FF
-
0xFFFE E300 - 0xFFFE E30B
ESR[1] - ESR[3]
0xFFFE E30C - 0xFFFE E37F
-
Reserved
Reserved
System Interrupt Status Raw / Set Registers
Reserved
System Interrupt Status Enabled / Clear Registers
Reserved
System Interrupt Enable Set Registers
Reserved
0xFFFE E380 - 0xFFFE E38B
ECR[1] - ECR[3]
0xFFFE E38C - 0xFFFE E3FF
-
0xFFFE E400 - 0xFFFE E458
CMR[0] - CMR[22]
0xFFFE E459 - 0xFFFE E7FF
-
Reserved
0xFFFE E800 - 0xFFFE E81F
-
Reserved
0xFFFE E820 - 0xFFFE E8FF
-
Reserved
System Interrupt Enable Clear Registers
Reserved
Channel Map Registers (Byte Wide Registers)
0xFFFE E900 - 0xFFFE E904
HIPIR[1] - HIPIR[2]
0xFFFE E908 - 0xFFFE EEFF
-
Reserved
0xFFFE EF00 - 0xFFFE EF04
-
Reserved
0xFFFE EF08 - 0xFFFE F0FF
-
Reserved
0xFFFE F100 - 0xFFFE F104
HINLR[1] - HINLR[2]
0xFFFE F108 - 0xFFFE F4FF
-
0xFFFE F500
HIER[0]
0xFFFE F504 - 0xFFFE F5FF
-
0xFFFE F600
HIPVR[1] - HIPVR[2]
0xFFFE F608 - 0xFFFE FFFF
-
Copyright © 2010, Texas Instruments Incorporated
ADVANCE INFORMATION
0xFFFE E030
Host Interrupt Prioritized Index Registers
Host Interrupt Nesting Level Registers
Reserved
Host Interrupt Enable Register
Reserved
Host Interrupt Prioritized Vector Registers
Reserved
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6.9
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General-Purpose Input/Output (GPIO)
The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs.
When configured as an output, a write to an internal register can control the state driven on the output pin.
When configured as an input, the state of the input is detectable by reading the state of an internal
register. In addition, the GPIO peripheral can produce CPU interrupts and EDMA events in different
interrupt/event generation modes. The GPIO peripheral provides generic connections to external devices.
The GPIO pins are grouped into banks of 16 pins per bank (i.e., bank 0 consists of GPIO [0:15]).
ADVANCE INFORMATION
The device GPIO peripheral supports the following:
• External Interrupt and DMA request Capability
– Every GPIO pin may be configured to generate an interrupt request on detection of rising and/or
falling edges on the pin.
– The interrupt requests within each bank are combined (logical or) to create eight unique bank level
interrupt requests.
– The bank level interrupt service routine may poll the INTSTATx register for its bank to determine
which pin(s) have triggered the interrupt.
– GPIO Banks 0, 1, 2, 3, 4, 5, 6, and 7 Interrupts assigned to ARM INTC Interrupt Requests 42, 43,
44, 45, 46, 47, 48, and 49 respectively
– Additionally, GPIO Banks 0, 1, 2, 3, 4, and 5 Interrupts assigned to EDMA events 6, 7, 22, 23, 28,
and 29 respectively.
• Set/clear functionality: Firmware writes 1 to corresponding bit position(s) to set or to clear GPIO
signal(s). This allows multiple firmware processes to toggle GPIO output signals without critical section
protection (disable interrupts, program GPIO, re-enable interrupts, to prevent context switching to
anther process during GPIO programming).
• Separate Input/Output registers
• Output register in addition to set/clear so that, if preferred by firmware, some GPIO output signals can
be toggled by direct write to the output register(s).
• Output register, when read, reflects output drive status. This, in addition to the input register reflecting
pin status and open-drain I/O cell, allows wired logic be implemented.
The memory map for the GPIO registers is shown in Table 6-9.
50
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6.9.1
SPRS657A – FEBRUARY 2010 – REVISED APRIL 2010
GPIO Register Description(s)
Table 6-9. GPIO Registers
BYTE ADDRESS
ACRONYM
0x01E2 6000
REV
REGISTER DESCRIPTION
0x01E2 6004
RESERVED
0x01E2 6008
BINTEN
0x01E2 6010
DIR01
0x01E2 6014
OUT_DATA01
GPIO Banks 0 and 1 Output Data Register
Peripheral Revision Register
Reserved
GPIO Interrupt Per-Bank Enable Register
GPIO BANKS 0 AND 1
0x01E2 6018
SET_DATA01
GPIO Banks 0 and 1 Set Data Register
0x01E2 601C
CLR_DATA01
GPIO Banks 0 and 1 Clear Data Register
0x01E2 6020
IN_DATA01
GPIO Banks 0 and 1 Input Data Register
0x01E2 6024
SET_RIS_TRIG01
GPIO Banks 0 and 1 Set Rising Edge Interrupt Register
0x01E2 6028
CLR_RIS_TRIG01
GPIO Banks 0 and 1 Clear Rising Edge Interrupt Register
0x01E2 602C
SET_FAL_TRIG01
GPIO Banks 0 and 1 Set Falling Edge Interrupt Register
0x01E2 6030
CLR_FAL_TRIG01
GPIO Banks 0 and 1 Clear Falling Edge Interrupt Register
0x01E2 6034
INTSTAT01
ADVANCE INFORMATION
GPIO Banks 0 and 1 Direction Register
GPIO Banks 0 and 1 Interrupt Status Register
GPIO BANKS 2 AND 3
0x01E2 6038
DIR23
GPIO Banks 2 and 3 Direction Register
0x01E2 603C
OUT_DATA23
GPIO Banks 2 and 3 Output Data Register
0x01E2 6040
SET_DATA23
GPIO Banks 2 and 3 Set Data Register
0x01E2 6044
CLR_DATA23
GPIO Banks 2 and 3 Clear Data Register
GPIO Banks 2 and 3 Input Data Register
0x01E2 6048
IN_DATA23
0x01E2 604C
SET_RIS_TRIG23
GPIO Banks 2 and 3 Set Rising Edge Interrupt Register
0x01E2 6050
CLR_RIS_TRIG23
GPIO Banks 2 and 3 Clear Rising Edge Interrupt Register
0x01E2 6054
SET_FAL_TRIG23
GPIO Banks 2 and 3 Set Falling Edge Interrupt Register
0x01E2 6058
CLR_FAL_TRIG23
GPIO Banks 2 and 3 Clear Falling Edge Interrupt Register
0x01E2 605C
INTSTAT23
GPIO Banks 2 and 3 Interrupt Status Register
GPIO BANKS 4 AND 5
0x01E2 6060
DIR45
0x01E2 6064
OUT_DATA45
GPIO Banks 4 and 5 Direction Register
GPIO Banks 4 and 5 Output Data Register
0x01E2 6068
SET_DATA45
GPIO Banks 4 and 5 Set Data Register
0x01E2 606C
CLR_DATA45
GPIO Banks 4 and 5 Clear Data Register
0x01E2 6070
IN_DATA45
GPIO Banks 4 and 5 Input Data Register
0x01E2 6074
SET_RIS_TRIG45
GPIO Banks 4 and 5 Set Rising Edge Interrupt Register
0x01E2 6078
CLR_RIS_TRIG45
GPIO Banks 4 and 5 Clear Rising Edge Interrupt Register
0x01E2 607C
SET_FAL_TRIG45
GPIO Banks 4 and 5 Set Falling Edge Interrupt Register
0x01E2 6080
CLR_FAL_TRIG45
GPIO Banks 4 and 5 Clear Falling Edge Interrupt Register
0x01E2 6084
INTSTAT45
0x01E2 6088
DIR67
0x01E2 608C
OUT_DATA67
GPIO Banks 6 and 7 Output Data Register
0x01E2 6090
SET_DATA67
GPIO Banks 6 and 7 Set Data Register
0x01E2 6094
CLR_DATA67
GPIO Banks 6 and 7 Clear Data Register
0x01E2 6098
IN_DATA67
GPIO Banks 6 and 7 Input Data Register
0x01E2 609C
SET_RIS_TRIG67
GPIO Banks 6 and 7 Set Rising Edge Interrupt Register
0x01E2 60A0
CLR_RIS_TRIG67
GPIO Banks 6 and 7 Clear Rising Edge Interrupt Register
0x01E2 60A4
SET_FAL_TRIG67
GPIO Banks 6 and 7 Set Falling Edge Interrupt Register
GPIO Banks 4 and 5 Interrupt Status Register
GPIO BANKS 6 AND 7
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GPIO Banks 6 and 7 Direction Register
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Table 6-9. GPIO Registers (continued)
6.9.2
BYTE ADDRESS
ACRONYM
0x01E2 60A8
CLR_FAL_TRIG67
0x01E2 60AC
INTSTAT67
REGISTER DESCRIPTION
GPIO Banks 6 and 7 Clear Falling Edge Interrupt Register
GPIO Banks 6 and 7 Interrupt Status Register
GPIO Peripheral Input/Output Electrical Data/Timing
Table 6-10. Timing Requirements for GPIO Inputs (1) (see Figure 6-10)
No.
PARAMETER
1
tw(GPIH)
2
(1)
tw(GPIL)
MIN
2C (1)
Pulse duration, GPn[m] as input high
Pulse duration, GPn[m] as input low
2C
MAX
UNIT
(2)
ns
(1) (2)
ns
The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have the device
recognize the GPIx changes through software polling of the GPIO register, the GPIx duration must be extended to allow the device
enough time to access the GPIO register through the internal bus.
C=SYSCLK4 period in ns.
(2)
ADVANCE INFORMATION
Table 6-11. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs
(see Figure 6-10)
No.
PARAMETER
3
tw(GPOH)
4
(1)
MIN
2C (1)
Pulse duration, GPn[m] as output high
tw(GPOL)
Pulse duration, GPn[m] as output low
2C
MAX
UNIT
(2)
ns
(1) (2)
ns
This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the
GPIO is dependent upon internal bus activity.
C=SYSCLK4 period in ns.
(2)
2
1
GPn[m] as input
4
3
GPn[m] as output
Figure 6-10. GPIO Port Timing
6.9.3
GPIO Peripheral External Interrupts Electrical Data/Timing
Table 6-12. Timing Requirements for External Interrupts (1) (see Figure 6-11)
No.
(1)
(2)
PARAMETER
MIN
MAX
1
tw(ILOW)
Width of the external interrupt pulse low
2C (1)
2
tw(IHIGH)
Width of the external interrupt pulse high
2C
UNIT
(2)
ns
(1) (2)
ns
The pulse width given is sufficient to generate an interrupt or an EDMA event. However, if a user wants to have device recognize the
GPIO changes through software polling of the GPIO register, the GPIO duration must be extended to allow the device enough time to
access the GPIO register through the internal bus.
C=SYSCLK4 period in ns.
2
1
GPn[m] as input
Figure 6-11. GPIO External Interrupt Timing
52
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6.10 EDMA
Table 6-13 is the list of EDMA3 Channel Contoller Registers and Table 6-14 is the list of EDMA3 Transfer
Controller registers.
Table 6-13. EDMA3 Channel Controller (EDMA3CC) Registers
BYTE ADDRESS
ACRONYM
0x01C0 0000
PID
REGISTER DESCRIPTION
0x01C0 0004
CCCFG
0x01C0 0200
QCHMAP0
QDMA Channel 0 Mapping Register
0x01C0 0204
QCHMAP1
QDMA Channel 1 Mapping Register
0x01C0 0208
QCHMAP2
QDMA Channel 2 Mapping Register
0x01C0 020C
QCHMAP3
QDMA Channel 3 Mapping Register
0x01C0 0210
QCHMAP4
QDMA Channel 4 Mapping Register
0x01C0 0214
QCHMAP5
QDMA Channel 5 Mapping Register
0x01C0 0218
QCHMAP6
QDMA Channel 6 Mapping Register
0x01C0 021C
QCHMAP7
QDMA Channel 7 Mapping Register
0x01C0 0240
DMAQNUM0
DMA Channel Queue Number Register 0
0x01C0 0244
DMAQNUM1
DMA Channel Queue Number Register 1
0x01C0 0248
DMAQNUM2
DMA Channel Queue Number Register 2
0x01C0 024C
DMAQNUM3
DMA Channel Queue Number Register 3
0x01C0 0260
QDMAQNUM
QDMA Channel Queue Number Register
0x01C0 0284
QUEPRI
0x01C0 0300
EMR
Peripheral Identification Register
EDMA3CC Configuration Register
ADVANCE INFORMATION
GLOBAL REGISTERS
Queue Priority Register (1)
Event Missed Register
0x01C0 0308
EMCR
Event Missed Clear Register
0x01C0 0310
QEMR
QDMA Event Missed Register
0x01C0 0314
QEMCR
QDMA Event Missed Clear Register
EDMA3CC Error Register
0x01C0 0318
CCERR
0x01C0 031C
CCERRCLR
0x01C0 0320
EEVAL
Error Evaluate Register
0x01C0 0340
DRAE0
DMA Region Access Enable Register for Region 0
0x01C0 0348
DRAE1
DMA Region Access Enable Register for Region 1
0x01C0 0350
DRAE2
DMA Region Access Enable Register for Region 2
0x01C0 0358
DRAE3
DMA Region Access Enable Register for Region 3
0x01C0 0380
QRAE0
QDMA Region Access Enable Register for Region 0
0x01C0 0384
QRAE1
QDMA Region Access Enable Register for Region 1
0x01C0 0388
QRAE2
QDMA Region Access Enable Register for Region 2
QDMA Region Access Enable Register for Region 3
EDMA3CC Error Clear Register
0x01C0 038C
QRAE3
0x01C0 0400 - 0x01C0 043C
Q0E0-Q0E15
Event Queue Entry Registers Q0E0-Q0E15
0x01C0 0440 - 0x01C0 047C
Q1E0-Q1E15
Event Queue Entry Registers Q1E0-Q1E15
0x01C0 0600
QSTAT0
Queue 0 Status Register
0x01C0 0604
QSTAT1
Queue 1 Status Register
0x01C0 0620
QWMTHRA
0x01C0 0640
CCSTAT
0x01C0 1000
ER
0x01C0 1008
ECR
Queue Watermark Threshold A Register
EDMA3CC Status Register
GLOBAL CHANNEL REGISTERS
(1)
Event Register
Event Clear Register
On previous architectures, the EDMA3TC priority was controlled by the queue priority register (QUEPRI) in the EDMA3CC
memory-map. However for this device, the priority control for the transfer controllers is controlled by the chip-level registers in the
System Configuration Module. You should use the chip-level registers and not QUEPRI to configure the TC priority.
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Table 6-13. EDMA3 Channel Controller (EDMA3CC) Registers (continued)
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
0x01C0 1010
ESR
Event Set Register
0x01C0 1018
CER
Chained Event Register
0x01C0 1020
EER
Event Enable Register
0x01C0 1028
EECR
Event Enable Clear Register
0x01C0 1030
EESR
Event Enable Set Register
0x01C0 1038
SER
Secondary Event Register
0x01C0 1040
SECR
0x01C0 1050
IER
0x01C0 1058
IECR
Interrupt Enable Clear Register
0x01C0 1060
IESR
Interrupt Enable Set Register
Secondary Event Clear Register
Interrupt Enable Register
0x01C0 1068
IPR
Interrupt Pending Register
0x01C0 1070
ICR
Interrupt Clear Register
0x01C0 1078
IEVAL
Interrupt Evaluate Register
ADVANCE INFORMATION
0x01C0 1080
QER
0x01C0 1084
QEER
QDMA Event Register
0x01C0 1088
QEECR
QDMA Event Enable Clear Register
0x01C0 108C
QEESR
QDMA Event Enable Set Register
0x01C0 1090
QSER
QDMA Secondary Event Register
0x01C0 1094
QSECR
QDMA Event Enable Register
QDMA Secondary Event Clear Register
SHADOW REGION 0 CHANNEL REGISTERS
0x01C0 2000
ER
0x01C0 2008
ECR
Event Register
Event Clear Register
0x01C0 2010
ESR
Event Set Register
0x01C0 2018
CER
Chained Event Register
0x01C0 2020
EER
Event Enable Register
0x01C0 2028
EECR
Event Enable Clear Register
0x01C0 2030
EESR
Event Enable Set Register
0x01C0 2038
SER
Secondary Event Register
0x01C0 2040
SECR
0x01C0 2050
IER
0x01C0 2058
IECR
Interrupt Enable Clear Register
0x01C0 2060
IESR
Interrupt Enable Set Register
0x01C0 2068
IPR
Interrupt Pending Register
0x01C0 2070
ICR
Interrupt Clear Register
0x01C0 2078
IEVAL
0x01C0 2080
QER
Secondary Event Clear Register
Interrupt Enable Register
Interrupt Evaluate Register
QDMA Event Register
0x01C0 2084
QEER
0x01C0 2088
QEECR
QDMA Event Enable Register
QDMA Event Enable Clear Register
0x01C0 208C
QEESR
QDMA Event Enable Set Register
0x01C0 2090
QSER
QDMA Secondary Event Register
0x01C0 2094
QSECR
QDMA Secondary Event Clear Register
SHADOW REGION 1 CHANNEL REGISTERS
54
0x01C0 2200
ER
Event Register
0x01C0 2208
ECR
Event Clear Register
0x01C0 2210
ESR
Event Set Register
0x01C0 2218
CER
Chained Event Register
0x01C0 2220
EER
Event Enable Register
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Table 6-13. EDMA3 Channel Controller (EDMA3CC) Registers (continued)
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
0x01C0 2228
EECR
Event Enable Clear Register
0x01C0 2230
EESR
Event Enable Set Register
0x01C0 2238
SER
Secondary Event Register
0x01C0 2240
SECR
0x01C0 2250
IER
0x01C0 2258
IECR
Interrupt Enable Clear Register
0x01C0 2260
IESR
Interrupt Enable Set Register
0x01C0 2268
IPR
Interrupt Pending Register
0x01C0 2270
ICR
Interrupt Clear Register
0x01C0 2278
IEVAL
Secondary Event Clear Register
Interrupt Enable Register
Interrupt Evaluate Register
0x01C0 2280
QER
0x01C0 2284
QEER
QDMA Event Register
0x01C0 2288
QEECR
QDMA Event Enable Clear Register
0x01C0 228C
QEESR
QDMA Event Enable Set Register
0x01C0 2290
QSER
QDMA Secondary Event Register
0x01C0 2294
QSECR
0x01C0 4000 - 0x01C0 4FFF
—
ADVANCE INFORMATION
QDMA Event Enable Register
QDMA Secondary Event Clear Register
Parameter RAM (PaRAM)
Table 6-14. EDMA3 Transfer Controller (EDMA3TC) Registers
TRANSFER
CONTROLLER 0
BYTE ADDRESS
TRANSFER
CONTROLLER 1
BYTE ADDRESS
ACRONYM
0x01C0 8000
0x01C0 8400
PID
Peripheral Identification Register
0x01C0 8004
0x01C0 8404
TCCFG
EDMA3TC Configuration Register
0x01C0 8100
0x01C0 8500
TCSTAT
EDMA3TC Channel Status Register
0x01C0 8120
0x01C0 8520
ERRSTAT
Error Status Register
0x01C0 8124
0x01C0 8524
ERREN
Error Enable Register
REGISTER DESCRIPTION
0x01C0 8128
0x01C0 8528
ERRCLR
Error Clear Register
0x01C0 812C
0x01C0 852C
ERRDET
Error Details Register
0x01C0 8130
0x01C0 8530
ERRCMD
Error Interrupt Command Register
0x01C0 8140
0x01C0 8540
RDRATE
Read Command Rate Register
0x01C0 8240
0x01C0 8640
SAOPT
Source Active Options Register
0x01C0 8244
0x01C0 8644
SASRC
Source Active Source Address Register
0x01C0 8248
0x01C0 8648
SACNT
Source Active Count Register
0x01C0 824C
0x01C0 864C
SADST
Source Active Destination Address Register
0x01C0 8250
0x01C0 8650
SABIDX
Source Active B-Index Register
0x01C0 8254
0x01C0 8654
SAMPPRXY
Source Active Memory Protection Proxy Register
Source Active Count Reload Register
0x01C0 8258
0x01C0 8658
SACNTRLD
0x01C0 825C
0x01C0 865C
SASRCBREF
Source Active Source Address B-Reference Register
0x01C0 8260
0x01C0 8660
SADSTBREF
Source Active Destination Address B-Reference Register
0x01C0 8280
0x01C0 8680
DFCNTRLD
0x01C0 8284
0x01C0 8684
DFSRCBREF
Destination FIFO Set Source Address B-Reference Register
0x01C0 8288
0x01C0 8688
DFDSTBREF
Destination FIFO Set Destination Address B-Reference Register
0x01C0 8300
0x01C0 8700
DFOPT0
Destination FIFO Options Register 0
0x01C0 8304
0x01C0 8704
DFSRC0
Destination FIFO Source Address Register 0
0x01C0 8308
0x01C0 8708
DFCNT0
Destination FIFO Count Register 0
0x01C0 830C
0x01C0 870C
DFDST0
Destination FIFO Destination Address Register 0
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Destination FIFO Set Count Reload Register
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Table 6-14. EDMA3 Transfer Controller (EDMA3TC) Registers (continued)
ADVANCE INFORMATION
TRANSFER
CONTROLLER 0
BYTE ADDRESS
TRANSFER
CONTROLLER 1
BYTE ADDRESS
ACRONYM
0x01C0 8310
0x01C0 8710
DFBIDX0
0x01C0 8314
0x01C0 8714
DFMPPRXY0
0x01C0 8340
0x01C0 8740
DFOPT1
Destination FIFO Options Register 1
0x01C0 8344
0x01C0 8744
DFSRC1
Destination FIFO Source Address Register 1
0x01C0 8348
0x01C0 8748
DFCNT1
Destination FIFO Count Register 1
0x01C0 834C
0x01C0 874C
DFDST1
Destination FIFO Destination Address Register 1
0x01C0 8350
0x01C0 8750
DFBIDX1
Destination FIFO B-Index Register 1
0x01C0 8354
0x01C0 8754
DFMPPRXY1
0x01C0 8380
0x01C0 8780
DFOPT2
Destination FIFO Options Register 2
0x01C0 8384
0x01C0 8784
DFSRC2
Destination FIFO Source Address Register 2
0x01C0 8388
0x01C0 8788
DFCNT2
Destination FIFO Count Register 2
0x01C0 838C
0x01C0 878C
DFDST2
Destination FIFO Destination Address Register 2
0x01C0 8390
0x01C0 8790
DFBIDX2
Destination FIFO B-Index Register 2
0x01C0 8394
0x01C0 8794
DFMPPRXY2
0x01C0 83C0
0x01C0 87C0
DFOPT3
Destination FIFO Options Register 3
0x01C0 83C4
0x01C0 87C4
DFSRC3
Destination FIFO Source Address Register 3
0x01C0 83C8
0x01C0 87C8
DFCNT3
Destination FIFO Count Register 3
0x01C0 83CC
0x01C0 87CC
DFDST3
Destination FIFO Destination Address Register 3
0x01C0 83D0
0x01C0 87D0
DFBIDX3
Destination FIFO B-Index Register 3
0x01C0 83D4
0x01C0 87D4
DFMPPRXY3
REGISTER DESCRIPTION
Destination FIFO B-Index Register 0
Destination FIFO Memory Protection Proxy Register 0
Destination FIFO Memory Protection Proxy Register 1
Destination FIFO Memory Protection Proxy Register 2
Destination FIFO Memory Protection Proxy Register 3
Table 6-15 shows an abbreviation of the set of registers which make up the parameter set for each of 128
EDMA events. Each of the parameter register sets consist of 8 32-bit word entries. Table 6-16 shows the
parameter set entry registers with relative memory address locations within each of the parameter sets.
Table 6-15. EDMA Parameter Set RAM
BYTE ADDRESS
DESCRIPTION
0x01C0 4000 - 0x01C0 401F
Parameters Set 0 (8 32-bit words)
0x01C0 4020 - 0x01C0 403F
Parameters Set 1 (8 32-bit words)
0x01C0 4040 - 0x01C0 405F
Parameters Set 2 (8 32-bit words)
0x01C0 4060 - 0x01C0 407F
Parameters Set 3 (8 32-bit words)
0x01C0 4080 - 0x01C0 409F
Parameters Set 4 (8 32-bit words)
0x01C0 40A0 - 0x01C0 40BF
Parameters Set 5 (8 32-bit words)
...
...
0x01C0 4FC0 - 0x01C0 4FDF
Parameters Set 126 (8 32-bit words)
0x01C0 4FE0 - 0x01C0 4FFF
Parameters Set 127 (8 32-bit words)
Table 6-16. Parameter Set Entries
HEX OFFSET ADDRESS
WITHIN THE PARAMETER SET
56
ACRONYM
PARAMETER ENTRY
0x0000
OPT
Option
0x0004
SRC
Source Address
0x0008
A_B_CNT
0x000C
DST
0x0010
SRC_DST_BIDX
Source B Index, Destination B Index
0x0014
LINK_BCNTRLD
Link Address, B Count Reload
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Destination Address
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Table 6-16. Parameter Set Entries (continued)
HEX OFFSET ADDRESS
WITHIN THE PARAMETER SET
ACRONYM
0x0018
SRC_DST_CIDX
0x001C
CCNT
PARAMETER ENTRY
Source C Index, Destination C Index
C Count
Table 6-17. EDMA Events
Event Name / Source
Event
0
McASP0 Receive
16
MMCSD Receive
1
McASP0 Transmit
17
MMCSD Transmit
2
McASP1 Receive
18
SPI1 Receive
3
McASP1 Transmit
19
SPI1 Transmit
4
Reserved
20
PRU_EVTOUT6
5
Reserved
21
PRU_EVTOUT7
6
GPIO Bank 0 Interrupt
22
GPIO Bank 2 Interrupt
7
GPIO Bank 1 Interrupt
23
GPIO Bank 3 Interrupt
8
UART0 Receive
24
I2C0 Receive
9
UART0 Transmit
25
I2C0 Transmit
10
Timer64P0 Event Out 12
26
I2C1 Receive
11
Timer64P0 Event Out 34
27
I2C1 Transmit
12
UART1 Receive
28
GPIO Bank 4 Interrupt
13
UART1 Transmit
29
GPIO Bank 5 Interrupt
14
SPI0 Receive
30
UART2 Receive
15
SPI0 Transmit
31
UART2 Transmit
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6.11 External Memory Interface A (EMIFA)
EMIFA is one of two external memory interfaces supported on the device . It supports asynchronous
memory types, such as NAND and NOR flash and Asynchronous SRAM.
6.11.1 EMIFA Asynchronous Memory Support
EMIFA supports asynchronous:
• SRAM memories
• NAND Flash memories
• NOR Flash memories
The device supports up to 13 address lines and an external wait/interrupt input. Up to 2 asynchronous
chip selects are supported by EMIFA (EMA_CS[3:2]) .
ADVANCE INFORMATION
Each chip select has the following individually programmable attributes:
• Data Bus Width
• Read cycle timings: setup, hold, strobe
• Write cycle timings: setup, hold, strobe
• Bus turn around time
• Extended Wait Option With Programmable Timeout
• Select Strobe Option
• NAND flash controller supports 1-bit and 4-bit ECC calculation on blocks of 512 bytes.
58
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6.11.2 External Memory Interface A (EMIFA) Registers
Table 6-18 is a list of the EMIF registers.
Table 6-18. External Memory Interface (EMIFA) Registers
ACRONYM
0x6800 0000
MIDR
Module ID Register
REGISTER DESCRIPTION
0x6800 0004
AWCC
Asynchronous Wait Cycle Configuration Register
0x6800 0008
-
Reserved
0x6800 000C
-
Reserved
0x6800 0010
CE2CFG
Asynchronous 1 Configuration Register
0x6800 0014
CE3CFG
Asynchronous 2 Configuration Register
0x6800 0018
CE4CFG
Asynchronous 3 Configuration Register
0x6800 001C
CE5CFG
Asynchronous 4 Configuration Register
0x6800 0020
-
Reserved
0x6800 003C
-
Reserved
0x6800 0040
INTRAW
EMIFA Interrupt Raw Register
0x6800 0044
INTMSK
EMIFA Interrupt Mask Register
0x6800 0048
INTMSKSET
EMIFA Interrupt Mask Set Register
0x6800 004C
INTMSKCLR
EMIFA Interrupt Mask Clear Register
0x6800 0060
NANDFCR
NAND Flash Control Register
0x6800 0064
NANDFSR
NAND Flash Status Register
0x6800 0070
NANDF1ECC
NAND Flash 1 ECC Register (CS2 Space)
0x6800 0074
NANDF2ECC
NAND Flash 2 ECC Register (CS3 Space)
0x6800 0078
NANDF3ECC
NAND Flash 3 ECC Register (CS4 Space)
0x6800 007C
NANDF4ECC
NAND Flash 4 ECC Register (CS5 Space)
0x6800 00BC
NAND4BITECCLOAD
0x6800 00C0
NAND4BITECC1
NAND Flash 4-Bit ECC Register 1
0x6800 00C4
NAND4BITECC2
NAND Flash 4-Bit ECC Register 2
0x6800 00C8
NAND4BITECC3
NAND Flash 4-Bit ECC Register 3
0x6800 00CC
NAND4BITECC4
NAND Flash 4-Bit ECC Register 4
0x6800 00D0
NANDERRADD1
NAND Flash 4-Bit ECC Error Address Register 1
0x6800 00D4
NANDERRADD2
NAND Flash 4-Bit ECC Error Address Register 2
0x6800 00D8
NANDERRVAL1
NAND Flash 4-Bit ECC Error Value Register 1
0x6800 00DC
NANDERRVAL2
NAND Flash 4-Bit ECC Error Value Register 2
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BYTE ADDRESS
NAND Flash 4-Bit ECC Load Register
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6.11.3 EMIFA Electrical Data/Timing
The following assume testing over recommended operating conditions.
Table 6-19. EMIFA Asynchronous Memory Timing Requirements (1)
No.
PARAMETER
MIN
NOM
MAX
UNIT
READS and WRITES
E
tc(CLK)
Cycle time, EMIFA module clock
10
ns
tw(EM_WAIT)
Pulse duration, EM_WAIT assertion and
deassertion
2E
ns
12
tsu(EMDV-EMOEH)
Setup time, EM_D[15:0] valid before EM_OE
high
3
ns
13
th(EMOEH-EMDIV)
Hold time, EM_D[15:0] valid after EM_OE high
0
ns
tsu (EMOEL-EMWAIT)
Setup Time, EM_WAIT asserted before end of
Strobe Phase (2)
4E+3
ns
tsu (EMWEL-EMWAIT)
Setup Time, EM_WAIT asserted before end of
Strobe Phase (2)
4E+3
ns
2
READS
14
WRITES
28
ADVANCE INFORMATION
(1)
E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL output clock divided by 4.5. As an example, when
SYSCLK3 is selected and set to 100MHz, E=10ns.
Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAIT must be asserted to add extended
wait states. Figure 6-14 and Figure 6-15 describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.
(2)
Table 6-20. EMIFA Asynchronous Memory Switching Characteristics (1)
No.
PARAMETER
MIN
NOM
(2) (3)
MAX
UNIT
READS and WRITES
1
td(TURNAROUND)
Turn around time
(TA)*E - 3
(TA)*E
(TA)*E + 3
ns
EMIF read cycle time (EW = 0)
(RS+RST+RH)*E
-3
(RS+RST+RH)*E
(RS+RST+RH)*E
+3
ns
EMIF read cycle time (EW = 1)
(RS+RST+RH+(E
WC*16))*E - 3
(RS+RST+RH+(EW
C*16))*E
(RS+RST+RH+(
EWC*16))*E + 3
ns
Output setup time, EMA_CE[5:2] low to
EMA_OE low (SS = 0)
(RS)*E-3
(RS)*E
(RS)*E+3
ns
Output setup time, EMA_CE[5:2] low to
EMA_OE low (SS = 1)
-3
0
+3
ns
Output hold time, EMA_OE high to
EMA_CE[5:2] high (SS = 0)
(RH)*E - 3
(RH)*E
(RH)*E + 3
ns
Output hold time, EMA_OE high to
EMA_CE[5:2] high (SS = 1)
-3
0
+3
ns
READS
3
4
5
(1)
(2)
(3)
60
tc(EMRCYCLE)
tsu(EMCEL-EMOEL)
th(EMOEH-EMCEH)
6
tsu(EMBAV-EMOEL)
Output setup time, EMA_BA[1:0] valid to
EMA_OE low
(RS)*E-3
(RS)*E
(RS)*E+3
ns
7
th(EMOEH-EMBAIV)
Output hold time, EMA_OE high to
EMA_BA[1:0] invalid
(RH)*E-3
(RH)*E
(RH)*E+3
ns
8
tsu(EMBAV-EMOEL)
Output setup time, EMA_A[13:0] valid to
EMA_OE low
(RS)*E-3
(RS)*E
(RS)*E+3
ns
TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold,
MEWC = Maximum external wait cycles. These parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle
Configuration Registers. These support the following range of values: TA[4-1], RS[16-1], RST[64-1], RH[8-1], WS[16-1], WST[64-1],
WH[8-1], and MEW[1-256].
E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL output clock divided by 4.5. As an example, when
SYSCLK3 is selected and set to 100MHz, E=10ns.
EWC = external wait cycles determined by EMA_WAIT input signal. EWC supports the following range of values EWC[256-1]. Note that
the maximum wait time before timeout is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register.
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Table 6-20. EMIFA Asynchronous Memory Switching Characteristics
No.
PARAMETER
9
th(EMOEH-EMAIV)
10
tw(EMOEL)
11
td(EMWAITHEMOEH)
MIN
(1) (2) (3)
NOM
(continued)
MAX
UNIT
Output hold time, EMA_OE high to
EMA_A[13:0] invalid
(RH)*E-3
(RH)*E
(RH)*E+3
ns
EMA_OE active low width (EW = 0)
(RST)*E-3
(RST)*E
(RST)*E+3
ns
EMA_OE active low width (EW = 1)
(RST+(EWC*16))*
E-3
(RST+(EWC*16))*E
(RST+(EWC*16)
)*E+3
ns
3E-3
4E
4E+3
ns
EMIF write cycle time (EW = 0)
(WS+WST+WH)*
E-3
(WS+WST+WH)*E
(WS+WST+WH)*
E+3
ns
EMIF write cycle time (EW = 1)
(WS+WST+WH+(
EWC*16))*E - 3
(WS+WST+WH+(E (WS+WST+WH+
WC*16))*E (EWC*16))*E + 3
ns
Delay time from EMA_WAIT deasserted to
EMA_OE high
15
16
17
18
tc(EMWCYCLE)
tsu(EMCEL-EMWEL)
th(EMWEH-EMCEH)
tsu(EMDQMVEMWEL)
19
th(EMWEHEMDQMIV)
20
tsu(EMBAVEMWEL)
Output setup time, EMA_CE[5:2] low to
EMA_WE low (SS = 0)
(WS)*E - 3
(WS)*E
(WS)*E + 3
ns
Output setup time, EMA_CE[5:2] low to
EMA_WE low (SS = 1)
-3
0
+3
ns
Output hold time, EMA_WE high to
EMA_CE[5:2] high (SS = 0)
(WH)*E-3
(WH)*E
(WH)*E+3
ns
Output hold time, EMA_WE high to
EMA_CE[5:2] high (SS = 1)
-3
0
+3
ns
Output setup time, EMA_BA[1:0] valid to
EMA_WE low
(WS)*E-3
(WS)*E
(WS)*E+3
ns
Output hold time, EMA_WE high to
EMA_BA[1:0] invalid
(WH)*E-3
(WH)*E
(WH)*E+3
ns
Output setup time, EMA_BA[1:0] valid to
EMA_WE low
(WS)*E-3
(WS)*E
(WS)*E+3
ns
21
th(EMWEH-EMBAIV)
Output hold time, EMA_WE high to
EMA_BA[1:0] invalid
(WH)*E-3
(WH)*E
(WH)*E+3
ns
22
tsu(EMAV-EMWEL)
Output setup time, EMA_A[13:0] valid to
EMA_WE low
(WS)*E-3
(WS)*E
(WS)*E+3
ns
23
th(EMWEH-EMAIV)
Output hold time, EMA_WE high to
EMA_A[13:0] invalid
(WH)*E-3
(WH)*E
(WH)*E+3
ns
EMA_WE active low width (EW = 0)
(WST)*E-3
(WST)*E
(WST)*E+3
ns
24
tw(EMWEL)
EMA_WE active low width (EW = 1)
(WST+(EWC*16))
*E-3
(WST+(EWC*16)
(WST+(EWC*16))*E
)*E+3
ns
25
td(EMWAITHEMWEH)
Delay time from EMA_WAIT deasserted to
EMA_WE high
3E-3
4E
4E+3
ns
26
tsu(EMDV-EMWEL)
Output setup time, EMA_D[15:0] valid to
EMA_WE low
(WS)*E-3
(WS)*E
(WS)*E+3
ns
27
th(EMWEH-EMDIV)
Output hold time, EMA_WE high to
EMA_D[15:0] invalid
(WH)*E-3
(WH)*E
(WH)*E+3
ns
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3
1
EMA_CS[5:2]
EMA_BA[1:0]
EMA_A[12:0]
EMA_WE_DQM[1:0]
4
8
5
9
6
29
7
30
10
ADVANCE INFORMATION
EMA_OE
13
12
EMA_D[15:0]
EMA_WE
Figure 6-12. Asynchronous Memory Read Timing for EMIFA
62
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15
1
EMA_CS[5:2]
EMA_BA[1:0]
EMA_A[12:0]
EMA_WE_DQM[1:0]
16
17
18
19
20
21
22
23
24
31
32
26
ADVANCE INFORMATION
EMA_WE
27
EMA_D[15:0]
EMA_OE
Figure 6-13. Asynchronous Memory Write Timing for EMIFA
EMA_CS[5:2]
SETUP
STROBE
Extended Due to EMA_WAIT
STROBE HOLD
EMA_BA[1:0]
EMA_A[12:0]
EMA_D[15:0]
14
11
EMA_OE
2
EMA_WAIT
Asserted
2
Deasserted
Figure 6-14. EMA_WAIT Read Timing Requirements
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ADVANCE INFORMATION
Figure 6-15. EMA_WAIT Write Timing Requirements
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6.12 External Memory Interface B (EMIFB)
The following EMIFB Functional Block Diagram illustrates a high-level view of the EMIFB and its
connections within the device. Multiple requesters have access to EMIFB through a switched central
resource (indicated as crossbar in the figure). The EMIFB implements a split transaction internal bus,
allowing concurrence between reads and writes from the various requesters.
EMIFB
Registers
CPU
Crossbar
Master
Peripherals
SDRAM
Interface
ADVANCE INFORMATION
EDMA
EMB_CS
EMB_CAS
Cmd/Write
EMB_RAS
FIFO
EMB_WE
EMB_CLK
EMB_SDCKE
Read
EMB_BA[1:0]
FIFO
EMB_A[x:0]
EMB_D[x:0]
EMB_WE_DQM[x:0]
Figure 6-16. EMIFB Functional Block Diagram
EMIFB supports a 3.3V LVCMOS Interface.
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6.12.1 Interfacing to SDRAM
The EMIFB supports a glueless interface to SDRAM devices with the following characteristics:
• Pre-charge bit is A[10]
• Supports 8, 9, 10 or 11 column address bits
• Supports up to 13 row address bits
• Supports 1, 2 or 4 internal banks
Table 6-21 shows the supported SDRAM configurations for EMIFB.
Table 6-21. EMIFB Supported SDRAM Configurations (1)
SDRAM
Memory
Data Bus
Width
(bits)
ADVANCE INFORMATION
16
(1)
Number of
Memories
EMIFB Data
Bus Size
Rows
Columns
Banks
Total Memory
(Mbits)
Total Memory
(Mbytes)
Memory
Density
(Mbits)
2
32
13
8
1
64
8
32
2
32
13
8
2
128
16
64
2
32
13
8
4
256
32
128
2
32
13
9
1
128
16
64
2
32
13
9
2
256
32
128
2
32
13
9
4
512
64
256
2
32
13
10
1
256
32
128
2
32
13
10
2
512
64
256
2
32
13
10
4
1024
128
512
2
32
13
11
1
512
64
256
2
32
13
11
2
1024
128
512
2
32
13
11
4
2048
256
1024
The shaded cells indicate configurations that are possible on the EMIFB interface but as of this writing SDRAM memories capable of
supporting these densities are not available in the market.
Figure 6-17 shows an interface between the EMIFB and a 2M × 16 × 4 bank SDRAM device. Figure 6-18
shows an interface between the EMIFB and two 4M × 16 × 4 bank SDRAM devices. Refer to Table 6-22,
as an example that shows additional list of commonly-supported SDRAM devices and the required
connections for the address pins. Note that in Table 6-22, page size/column size (not indicated in the
table) is varied to get the required addressability range.
EMIFB
EMB_CS
EMB_CAS
EMB_RAS
EMB_WE
EMB_CLK
EMB_SDCKE
EMB_BA[1:0]
EMB_A[11:0]
EMB_WE_DQM[0]
EMB_WE_DQM[1]
EMB_D[15:0]
SDRAM
2M x 16 x 4
Bank
CE
CAS
RAS
WE
CLK
CKE
BA[1:0]
A[11:0]
LDQM
UDQM
DQ[15:0]
Figure 6-17. EMIFB to 2M × 16 × 4 bank SDRAM Interface
66
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SDRAM
4M x 16 x 4
Bank
EMIFB
EMB_CS
EMB_CAS
EMB_RAS
EMB_WE
EMB_CLK
EMB_SDCKE
EMB_BA[1:0]
EMB_A[12:0]
EMB_WE_DQM[0]
EMB_WE_DQM[1]
EMB_D[15:0]
EMB_WE_DQM[2]
EMB_WE_DQM[3]
EMB_D[31:16]
CE
CAS
RAS
WE
CLK
CKE
BA[1:0]
A[12:0]
LDQM
UDQM
DQ[15:0]
SDRAM
4M x 16 x 4
Bank
ADVANCE INFORMATION
CE
CAS
RAS
WE
CLK
CKE
BA[1:0]
A[12:0]
LDQM
UDQM
DQ[15:0]
Figure 6-18. EMIFB to Dual 4M × 16 × 4 bank SDRAM Interface
Table 6-22. Example of 16-bit EMIFB Address Pin Connections
SDRAM Size
Width
Banks
64M bits
×16
4
Address Pins
SDRAM
A[11:0]
EMIFB
EMB_A[11:0]
128M bits
×16
4
SDRAM
A[11:0]
EMIFB
EMB_A[11:0]
256M bits
×16
4
SDRAM
A[12:0]
EMIFB
EMB_A[12:0]
512M bits
×16
4
SDRAM
A[12:0]
EMIFB
EMB_A[12:0]
Table 6-23 is a list of the EMIFB registers.
Table 6-23. EMIFB Controller Registers
BYTE ADDRESS
ACRONYM
0xB000 0000
MIDR
0xB000 0008
SDCFG
SDRAM Configuration Register
0xB000 000C
SDRFC
SDRAM Refresh Control Register
0xB000 0010
SDTIM1
SDRAM Timing Register 1
0xB000 0014
SDTIM2
SDRAM Timing Register 2
0xB000 001C
SDCFG2
SDRAM Configuration 2 Register
0xB000 0020
BPRIO
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REGISTER DESCRIPTION
Module ID Register
Peripheral Bus Burst Priority Register
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Table 6-23. EMIFB Controller Registers (continued)
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
0xB000 0040
PC1
Performance Counter 1 Register
0xB000 0044
PC2
Performance Counter 2 Register
0xB000 0048
PCC
Performance Counter Configuration Register
0xB000 004C
PCMRS
0xB000 0050
PCT
Performance Counter Time Register
0xB000 00C0
IRR
Interrupt Raw Register
0xB000 00C4
IMR
Interrupt Mask Register
0xB000 00C8
IMSR
Interrupt Mask Set Register
0xB000 00CC
IMCR
Interrupt Mask Clear Register
Performance Counter Master Region Select Register
ADVANCE INFORMATION
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6.12.2 EMIFB Electrical Data/Timing
Table 6-24. EMIFB SDRAM Interface Timing Requirements
No.
PARAMETER
MIN
MAX
UNIT
19
tsu(DV-CLKH)
Input setup time, read data valid on EMB_D[31:0] before EMB_CLK rising
0.8
ns
20
th(CLKH-DIV)
Input hold time, read data valid on EMB_D[31:0] after EMB_CLK rising
1.5
ns
Table 6-25. EMIFB SDRAM Interface Switching Characteristics
PARAMETER
MIN
1
tc(CLK)
Cycle time, EMIF clock EMB_CLK
7.5
ns
2
tw(CLK)
Pulse width, EMIF clock EMB_CLK high or low
3
ns
3
td(CLKH-CSV)
Delay time, EMB_CLK rising to EMB_CS[0] valid
4
toh(CLKH-CSIV)
Output hold time, EMB_CLK rising to EMB_CS[0] invalid
5
td(CLKH-DQMV)
Delay time, EMB_CLK rising to EMB_WE_DQM[3:0] valid
6
toh(CLKH-DQMIV)
Output hold time, EMB_CLK rising to EMB_WE_DQM[3:0] invalid
7
td(CLKH-AV)
Delay time, EMB_CLK rising to EMB_A[12:0] and EMB_BA[1:0] valid
8
toh(CLKH-AIV)
Output hold time, EMB_CLK rising to EMB_A[12:0] and EMB_BA[1:0] invalid
9
td(CLKH-DV)
Delay time, EMB_CLK rising to EMB_D[31:0] valid
10
toh(CLKH-DIV)
Output hold time, EMB_CLK rising to EMB_D[31:0] invalid
11
td(CLKH-RASV)
Delay time, EMB_CLK rising to EMB_RAS valid
12
toh(CLKH-RASIV)
Output hold time, EMB_CLK rising to EMB_RAS invalid
13
td(CLKH-CASV)
Delay time, EMB_CLK rising to EMB_CAS valid
14
toh(CLKH-CASIV)
Output hold time, EMB_CLK rising to EMB_CAS invalid
15
td(CLKH-WEV)
Delay time, EMB_CLK rising to EMB_WE valid
16
toh(CLKH-WEIV)
Output hold time, EMB_CLK rising to EMB_WE invalid
17
tdis(CLKH-DHZ)
Delay time, EMB_CLK rising to EMB_D[31:0] 3-stated
18
tena(CLKH-DLZ)
Output hold time, EMB_CLK rising to EMB_D[31:0] driving
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MAX
5.1
0.9
UNIT
ns
ns
5.1
0.9
ns
ns
5.1
0.9
ns
ns
5.1
0.9
ADVANCE INFORMATION
No.
ns
ns
5.1
0.9
ns
ns
5.1
0.9
ns
ns
5.1
0.9
ns
ns
5.1
0.9
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1
BASIC SDRAM
WRITE OPERATION
2
2
EMB_CLK
3
4
EMB_CS[0]
5
6
EMB_WE_DQM[3:0]
7
8
7
8
EMB_BA[1:0]
EMB_A[12:0]
9
10
EMB_D[31:0]
11
12
ADVANCE INFORMATION
EMB_RAS
13
EMB_CAS
15
16
EMB_WE
Figure 6-19. EMIFB Basic SDRAM Write Operation
BASIC SDRAM
READ OPERATION
1
2
2
EMB_CLK
3
4
EMB_CS[0]
5
6
EMB_WE_DQM[3:0]
7
8
7
8
EMB_BA[1:0]
EMB_A[12:0]
19
17
2 EM_CLK Delay
20
18
EMB_D[31:0]
11
12
EMB_RAS
13
14
EMB_CAS
EMB_WE
Figure 6-20. EMIFB Basic SDRAM Read Operation
70
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6.13 Memory Protection Units
The MPU performs memory protection checking. It receives requests from a bus master in the system and
checks the address against the fixed and programmable regions to see if the access is allowed. If allowed,
the transfer is passed unmodified to its output bus (to the targeted address). If the transfer is illegal (fails
the protection check) then the MPU does not pass the transfer to the output bus but rather services the
transfer internally back to the input bus (to prevent a hang) returning the fault status to the requestor as
well as generating an interrupt about the fault. The following features are supported by the MPU:
• Provides memory protection for fixed and programmable address ranges.
• Supports multiple programmable address region.
• Supports secure and debug access privileges.
• Supports read, write, and execute access privileges.
• Supports privid(8) associations with ranges.
• Generates an interrupt when there is a protection violation, and saves violating transfer parameters.
• MMR access is also protected.
MPU1
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
0x01E1 4000
REVID
0x01E1 4004
CONFIG
0x01E1 4010
IRAWSTAT
0x01E1 4014
IENSTAT
0x01E1 4018
IENSET
Interrupt enable
0x01E1 401C
IENCLR
Interrupt enable clear
Revision ID
Configuration
Interrupt raw status/set
Interrupt enable status/clear
0x01E1 4020 - 0x01E1 41FF
-
0x01E1 4200
PROG1_MPSAR
Programmable range 1, start address
0x01E1 4204
PROG1_MPEAR
Programmable range 1, end address
Reserved
0x01E1 4208
PROG1_MPPA
0x01E1 420C - 0x01E1 420F
-
0x01E1 4210
PROG2_MPSAR
Programmable range 2, start address
0x01E1 4214
PROG2_MPEAR
Programmable range 2, end address
Programmable range 1, memory page protection attributes
Reserved
0x01E1 4218
PROG2_MPPA
0x01E1 421C - 0x01E1 421F
-
0x01E1 4220
PROG3_MPSAR
Programmable range 3, start address
0x01E1 4224
PROG3_MPEAR
Programmable range 3, end address
0x01E1 4228
PROG3_MPPA
0x01E1 422C - 0x01E1 422F
-
0x01E1 4230
PROG4_MPSAR
Programmable range 4, start address
0x01E1 4234
PROG4_MPEAR
Programmable range 4, end address
0x01E1 4238
PROG4_MPPA
0x01E1 423C - 0x01E1 423F
-
0x01E1 4240
PROG5_MPSAR
Programmable range 5, start address
0x01E1 4244
PROG5_MPEAR
Programmable range 5, end address
0x01E1 4248
PROG5_MPPA
Programmable range 2, memory page protection attributes
Reserved
Programmable range 3, memory page protection attributes
Reserved
Programmable range 4, memory page protection attributes
Reserved
Programmable range 5, memory page protection attributes
0x01E1 424C - 0x01E1 424F
-
0x01E1 4250
PROG6_MPSAR
Programmable range 6, start address
0x01E1 4254
PROG6_MPEAR
Programmable range 6, end address
0x01E1 4258
PROG6_MPPA
0x01E1 425C - 0x01E1 42FF
-
Copyright © 2010, Texas Instruments Incorporated
ADVANCE INFORMATION
Table 6-26. MPU1 Configuration Registers
Reserved
Programmable range 6, memory page protection attributes
Reserved
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Table 6-26. MPU1 Configuration Registers (continued)
MPU1
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
0x01E14300
FLTADDRR
0x01E1 4304
FLTSTAT
Fault address
Fault status
0x01E1 4308
FLTCLR
Fault clear
0x01E1 430C - 0x01E1 4FFF
-
Reserved
Table 6-27. MPU2 Configuration Registers
MPU1
BYTE ADDRESS
ACRONYM
0x01E1 5000
REVID
0x01E1 5004
CONFIG
0x01E1 5010
IRAWSTAT
0x01E1 5014
IENSTAT
REGISTER DESCRIPTION
Revision ID
Configuration
Interrupt raw status/set
Interrupt enable status/clear
ADVANCE INFORMATION
0x01E1 5018
IENSET
Interrupt enable
0x01E1 501C
IENCLR
Interrupt enable clear
0x01E1 5020 - 0x01E1 50FF
-
0x01E1 5100
FXD_MPSAR
Fixed range start address
0x01E1 5104
FXD_MPEAR
Fixed range end start address
0x01E1 5108
FXD_MPPA
0x01E1 510C - 0x01E1 51FF
-
0x01E1 5200
PROG1_MPSAR
Programmable range 1, start address
0x01E1 5204
PROG1_MPEAR
Programmable range 1, end address
0x01E1 5208
PROG1_MPPA
Reserved
Fixed range memory page protection attributes
Reserved
Programmable range 1, memory page protection attributes
0x01E1 520C - 0x01E1 520F
-
0x01E1 5210
PROG2_MPSAR
Reserved
Programmable range 2, start address
0x01E1 5214
PROG2_MPEAR
Programmable range 2, end address
0x01E1 5218
PROG2_MPPA
Programmable range 2, memory page protection attributes
0x01E1 521C - 0x01E1 521F
-
0x01E1 5220
PROG3_MPSAR
Reserved
Programmable range 3, start address
0x01E1 5224
PROG3_MPEAR
Programmable range 3, end address
0x01E1 5228
PROG3_MPPA
0x01E1 522C - 0x01E1 522F
-
Programmable range 3, memory page protection attributes
0x01E1 5230
PROG4_MPSAR
Programmable range 4, start address
0x01E1 5234
PROG4_MPEAR
Programmable range 4, end address
0x01E1 5238
PROG4_MPPA
0x01E1 523C - 0x01E1 523F
-
0x01E1 5240
PROG5_MPSAR
Programmable range 5, start address
0x01E1 5244
PROG5_MPEAR
Programmable range 5, end address
0x01E1 5248
PROG5_MPPA
0x01E1 524C - 0x01E1 524F
-
0x01E1 5250
PROG6_MPSAR
Programmable range 6, start address
0x01E1 5254
PROG6_MPEAR
Programmable range 6, end address
0x01E1 5258
PROG6_MPPA
Reserved
Programmable range 4, memory page protection attributes
Reserved
Programmable range 5, memory page protection attributes
Reserved
Programmable range 6, memory page protection attributes
0x01E1 525C - 0x01E1 525F
-
0x01E1 5260
PROG7_MPSAR
Programmable range 7, start address
0x01E1 5264
PROG7_MPEAR
Programmable range 7, end address
0x01E1 5268
PROG7_MPPA
72
Reserved
Programmable range 7, memory page protection attributes
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Table 6-27. MPU2 Configuration Registers (continued)
ACRONYM
REGISTER DESCRIPTION
0x01E1 526C - 0x01E1 526F
-
0x01E1 5270
PROG8_MPSAR
Reserved
Programmable range 8, start address
0x01E1 5274
PROG8_MPEAR
Programmable range 8, end address
0x01E1 5278
PROG8_MPPA
0x01E1 527C - 0x01E1 527F
-
0x01E1 5280
PROG9_MPSAR
Programmable range 9, start address
0x01E1 5284
PROG9_MPEAR
Programmable range 9, end address
0x01E1 5288
PROG9_MPPA
0x01E1 528C - 0x01E1 528F
-
0x01E1 5290
PROG10_MPSAR
Programmable range 10, start address
0x01E1 5294
PROG10_MPEAR
Programmable range 10, end address
0x01E1 5298
PROG10_MPPA
Programmable range 8, memory page protection attributes
Reserved
Programmable range 9, memory page protection attributes
Reserved
Programmable range 10, memory page protection attributes
0x01E1 529C - 0x01E1 529F
-
0x01E1 52A0
PROG11_MPSAR
Reserved
Programmable range 11, start address
0x01E1 52A4
PROG11_MPEAR
Programmable range 11, end address
0x01E1 52A8
PROG11_MPPA
0x01E1 52AC - 0x01E1 52AF
-
0x01E1 52B0
PROG12_MPSAR
Programmable range 12, start address
0x01E1 52B4
PROG12_MPEAR
Programmable range 12, end address
Programmable range 11, memory page protection attributes
Reserved
0x01E1 52B8
PROG12_MPPA
0x01E1 52BC - 0x01E1 52FF
-
0x01E1 5300
FLTADDRR
0x01E1 5304
FLTSTAT
Fault status
0x01E1 5308
FLTCLR
Fault clear
0x01E1 530C - 0x01E1 5FFF
-
Reserved
Copyright © 2010, Texas Instruments Incorporated
ADVANCE INFORMATION
MPU1
BYTE ADDRESS
Programmable range 12, memory page protection attributes
Reserved
Fault address
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6.14 MMC / SD / SDIO (MMCSD)
6.14.1 MMCSD Peripheral Description
The device includes an MMCSD controller which is compliant with MMC V3.31, Secure Digital Part 1
Physical Layer Specification V1.1 and Secure Digital Input Output (SDIO) V2.0 specifications.
The MMC/SD Controller has following features:
• MultiMediaCard (MMC).
• Secure Digital (SD) Memory Card.
• MMC/SD protocol support.
• SDIO protocol support.
• Programmable clock frequency.
• 512 bit Read/Write FIFO to lower system overhead.
• Slave EDMA transfer capability.
The device MMC/SD Controller does not support SPI mode.
ADVANCE INFORMATION
6.14.2
MMCSD Peripheral Register Description(s)
Table 6-28. Multimedia Card/Secure Digital (MMC/SD) Card Controller Registers
BYTE
ADDRESS
ACRONYM
REGISTER DESCRIPTION
0x01C4 0000
MMCCTL
MMC Control Register
0x01C4 0004
MMCCLK
MMC Memory Clock Control Register
0x01C4 0008
MMCST0
MMC Status Register 0
0x01C4 000C
MMCST1
MMC Status Register 1
0x01C4 0010
MMCIM
0x01C4 0014
MMCTOR
MMC Response Time-Out Register
MMC Interrupt Mask Register
0x01C4 0018
MMCTOD
MMC Data Read Time-Out Register
0x01C4 001C
MMCBLEN
MMC Block Length Register
0x01C4 0020
MMCNBLK
MMC Number of Blocks Register
0x01C4 0024
MMCNBLC
MMC Number of Blocks Counter Register
0x01C4 0028
MMCDRR
MMC Data Receive Register
0x01C4 002C
MMCDXR
MMC Data Transmit Register
0x01C4 0030
MMCCMD
MMC Command Register
0x01C4 0034
MMCARGHL
MMC Argument Register
0x01C4 0038
MMCRSP01
MMC Response Register 0 and 1
0x01C4 003C
MMCRSP23
MMC Response Register 2 and 3
0x01C4 0040
MMCRSP45
MMC Response Register 4 and 5
0x01C4 0044
MMCRSP67
MMC Response Register 6 and 7
0x01C4 0048
MMCDRSP
MMC Data Response Register
0x01C4 0050
MMCCIDX
MMC Command Index Register
0x01C4 0064
SDIOCTL
SDIO Control Register
0x01C4 0068
SDIOST0
SDIO Status Register 0
0x01C4 006C
SDIOIEN
SDIO Interrupt Enable Register
0x01C4 0070
SDIOIST
SDIO Interrupt Status Register
0x01C4 0074
MMCFIFOCTLp
74
MMC FIFO Control Register
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6.14.3 MMC/SD Electrical Data/Timing
Table 6-29. Timing Requirements for MMC/SD Module
(see Figure 6-22 and Figure 6-24)
No.
PARAMETER
MIN
MAX
UNIT
1
tsu(CMDV-CLKH)
Setup time, MMCSD_CMD valid before MMCSD_CLK high
3.2
ns
2
th(CLKH-CMDV)
Hold time, MMCSD_CMD valid after MMCSD_CLK high
1.5
ns
3
tsu(DATV-CLKH)
Setup time, MMCSD_DATx valid before MMCSD_CLK high
3.2
ns
4
th(CLKH-DATV)
Hold time, MMCSD_DATx valid after MMCSD_CLK high
1.5
ns
Table 6-30. Switching Characteristics Over Recommended Operating Conditions for MMC/SD Module
(see Figure 6-21 through Figure 6-24)
No.
PARAMETER
MIN
MAX
UNIT
7
f(CLK)
Operating frequency, MMCSD_CLK
0
52
MHz
8
f(CLK_ID)
Identification mode frequency, MMCSD_CLK
0
400
KHz
9
tW(CLKL)
Pulse width, MMCSD_CLK low
6.5
10
tW(CLKH)
Pulse width, MMCSD_CLK high
6.5
11
tr(CLK)
Rise time, MMCSD_CLK
3
ns
12
tf(CLK)
Fall time, MMCSD_CLK
3
ns
13
td(CLKL-CMD)
Delay time, MMCSD_CLK low to MMCSD_CMD transition
-4.5
2.5
ns
14
td(CLKL-DAT)
Delay time, MMCSD_CLK low to MMCSD_DATx transition
-4.5
2
ns
Copyright © 2010, Texas Instruments Incorporated
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10
9
7
MMCSD_CLK
13
13
START
MMCSD_CMD
13
XMIT
Valid
Valid
13
Valid
END
Figure 6-21. MMC/SD Host Command Timing
9
7
10
MMCSD_CLK
1
2
START
MMCSD_CMD
XMIT
Valid
Valid
Valid
END
Figure 6-22. MMC/SD Card Response Timing
10
ADVANCE INFORMATION
9
7
MMCSD_CLK
14
14
START
MMCSD_DATx
14
D0
D1
14
Dx
END
Figure 6-23. MMC/SD Host Write Timing
9
10
7
MMCSD_CLK
4
4
3
MMCSD_DATx
Start
3
D0
D1
Dx
End
Figure 6-24. MMC/SD Host Read and Card CRC Status Timing
76
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6.15 Ethernet Media Access Controller (EMAC)
The Ethernet Media Access Controller (EMAC) provides an efficient interface between the device and the
network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps
in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.
The EMAC controls the flow of packet data from the device to the PHY. The MDIO module controls PHY
configuration and status monitoring.
Both the EMAC and the MDIO modules interface to the device through a custom interface that allows
efficient data transmission and reception. This custom interface is referred to as the EMAC control
module, and is considered integral to the EMAC/MDIO peripheral. The control module is also used to
multiplex and control interrupts.
6.15.1
EMAC Peripheral Register Description(s)
Table 6-31. Ethernet Media Access Controller (EMAC) Registers
BYTE ADDRESS
ACRONYM
0x01E2 3000
TXREV
REGISTER DESCRIPTION
0x01E2 3004
TXCONTROL
0x01E2 3008
TXTEARDOWN
0x01E2 3010
RXREV
0x01E2 3014
RXCONTROL
Transmit Revision Register
Transmit Teardown Register
Receive Revision Register
Receive Control Register
0x01E2 3018
RXTEARDOWN
Receive Teardown Register
0x01E2 3080
TXINTSTATRAW
Transmit Interrupt Status (Unmasked) Register
0x01E2 3084
TXINTSTATMASKED
Transmit Interrupt Status (Masked) Register
0x01E2 3088
TXINTMASKSET
0x01E2 308C
TXINTMASKCLEAR
0x01E2 3090
MACINVECTOR
0x01E2 3094
MACEOIVECTOR
MAC End Of Interrupt Vector Register
0x01E2 30A0
RXINTSTATRAW
Receive Interrupt Status (Unmasked) Register
0x01E2 30A4
RXINTSTATMASKED
0x01E2 30A8
RXINTMASKSET
0x01E2 30AC
RXINTMASKCLEAR
Receive Interrupt Mask Clear Register
0x01E2 30B0
MACINTSTATRAW
MAC Interrupt Status (Unmasked) Register
0x01E2 30B4
MACINTSTATMASKED
Transmit Interrupt Mask Set Register
Transmit Interrupt Clear Register
MAC Input Vector Register
Receive Interrupt Status (Masked) Register
Receive Interrupt Mask Set Register
MAC Interrupt Status (Masked) Register
0x01E2 30B8
MACINTMASKSET
0x01E2 30BC
MACINTMASKCLEAR
0x01E2 3100
RXMBPENABLE
Receive Multicast/Broadcast/Promiscuous Channel Enable Register
0x01E2 3104
RXUNICASTSET
Receive Unicast Enable Set Register
MAC Interrupt Mask Set Register
MAC Interrupt Mask Clear Register
0x01E2 3108
RXUNICASTCLEAR
0x01E2 310C
RXMAXLEN
0x01E2 3110
RXBUFFEROFFSET
0x01E2 3114
RXFILTERLOWTHRESH
Receive Filter Low Priority Frame Threshold Register
0x01E2 3120
RX0FLOWTHRESH
Receive Channel 0 Flow Control Threshold Register
0x01E2 3124
RX1FLOWTHRESH
Receive Channel 1 Flow Control Threshold Register
Receive Unicast Clear Register
Receive Maximum Length Register
Receive Buffer Offset Register
0x01E2 3128
RX2FLOWTHRESH
Receive Channel 2 Flow Control Threshold Register
0x01E2 312C
RX3FLOWTHRESH
Receive Channel 3 Flow Control Threshold Register
0x01E2 3130
RX4FLOWTHRESH
Receive Channel 4 Flow Control Threshold Register
0x01E2 3134
RX5FLOWTHRESH
Receive Channel 5 Flow Control Threshold Register
0x01E2 3138
RX6FLOWTHRESH
Receive Channel 6 Flow Control Threshold Register
0x01E2 313C
RX7FLOWTHRESH
Receive Channel 7 Flow Control Threshold Register
Copyright © 2010, Texas Instruments Incorporated
ADVANCE INFORMATION
Transmit Control Register
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Table 6-31. Ethernet Media Access Controller (EMAC) Registers (continued)
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
0x01E2 3140
RX0FREEBUFFER
Receive Channel 0 Free Buffer Count Register
0x01E2 3144
RX1FREEBUFFER
Receive Channel 1 Free Buffer Count Register
0x01E2 3148
RX2FREEBUFFER
Receive Channel 2 Free Buffer Count Register
0x01E2 314C
RX3FREEBUFFER
Receive Channel 3 Free Buffer Count Register
0x01E2 3150
RX4FREEBUFFER
Receive Channel 4 Free Buffer Count Register
0x01E2 3154
RX5FREEBUFFER
Receive Channel 5 Free Buffer Count Register
0x01E2 3158
RX6FREEBUFFER
Receive Channel 6 Free Buffer Count Register
0x01E2 315C
RX7FREEBUFFER
Receive Channel 7 Free Buffer Count Register
0x01E2 3160
MACCONTROL
MAC Control Register
0x01E2 3164
MACSTATUS
MAC Status Register
Emulation Control Register
0x01E2 3168
EMCONTROL
0x01E2 316C
FIFOCONTROL
0x01E2 3170
MACCONFIG
MAC Configuration Register
Soft Reset Register
FIFO Control Register
ADVANCE INFORMATION
0x01E2 3174
SOFTRESET
0x01E2 31D0
MACSRCADDRLO
MAC Source Address Low Bytes Register
0x01E2 31D4
MACSRCADDRHI
MAC Source Address High Bytes Register
0x01E2 31D8
MACHASH1
MAC Hash Address Register 1
0x01E2 31DC
MACHASH2
MAC Hash Address Register 2
0x01E2 31E0
BOFFTEST
Back Off Test Register
0x01E2 31E4
TPACETEST
Transmit Pacing Algorithm Test Register
0x01E2 31E8
RXPAUSE
Receive Pause Timer Register
0x01E2 31EC
TXPAUSE
Transmit Pause Timer Register
0x01E2 3200 - 0x01E2 32FC
(see Table 6-32)
0x01E2 3500
MACADDRLO
MAC Address Low Bytes Register, Used in Receive Address Matching
0x01E2 3504
MACADDRHI
MAC Address High Bytes Register, Used in Receive Address Matching
0x01E2 3508
MACINDEX
0x01E2 3600
TX0HDP
Transmit Channel 0 DMA Head Descriptor Pointer Register
0x01E2 3604
TX1HDP
Transmit Channel 1 DMA Head Descriptor Pointer Register
0x01E2 3608
TX2HDP
Transmit Channel 2 DMA Head Descriptor Pointer Register
0x01E2 360C
TX3HDP
Transmit Channel 3 DMA Head Descriptor Pointer Register
0x01E2 3610
TX4HDP
Transmit Channel 4 DMA Head Descriptor Pointer Register
0x01E2 3614
TX5HDP
Transmit Channel 5 DMA Head Descriptor Pointer Register
0x01E2 3618
TX6HDP
Transmit Channel 6 DMA Head Descriptor Pointer Register
0x01E2 361C
TX7HDP
Transmit Channel 7 DMA Head Descriptor Pointer Register
0x01E2 3620
RX0HDP
Receive Channel 0 DMA Head Descriptor Pointer Register
0x01E2 3624
RX1HDP
Receive Channel 1 DMA Head Descriptor Pointer Register
78
EMAC Statistics Registers
MAC Index Register
0x01E2 3628
RX2HDP
Receive Channel 2 DMA Head Descriptor Pointer Register
0x01E2 362C
RX3HDP
Receive Channel 3 DMA Head Descriptor Pointer Register
0x01E2 3630
RX4HDP
Receive Channel 4 DMA Head Descriptor Pointer Register
0x01E2 3634
RX5HDP
Receive Channel 5 DMA Head Descriptor Pointer Register
0x01E2 3638
RX6HDP
Receive Channel 6 DMA Head Descriptor Pointer Register
0x01E2 363C
RX7HDP
Receive Channel 7 DMA Head Descriptor Pointer Register
0x01E2 3640
TX0CP
Transmit Channel 0 Completion Pointer Register
0x01E2 3644
TX1CP
Transmit Channel 1 Completion Pointer Register
0x01E2 3648
TX2CP
Transmit Channel 2 Completion Pointer Register
0x01E2 364C
TX3CP
Transmit Channel 3 Completion Pointer Register
0x01E2 3650
TX4CP
Transmit Channel 4 Completion Pointer Register
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Table 6-31. Ethernet Media Access Controller (EMAC) Registers (continued)
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
0x01E2 3654
TX5CP
Transmit Channel 5 Completion Pointer Register
0x01E2 3658
TX6CP
Transmit Channel 6 Completion Pointer Register
0x01E2 365C
TX7CP
Transmit Channel 7 Completion Pointer Register
0x01E2 3660
RX0CP
Receive Channel 0 Completion Pointer Register
0x01E2 3664
RX1CP
Receive Channel 1 Completion Pointer Register
0x01E2 3668
RX2CP
Receive Channel 2 Completion Pointer Register
0x01E2 366C
RX3CP
Receive Channel 3 Completion Pointer Register
0x01E2 3670
RX4CP
Receive Channel 4 Completion Pointer Register
0x01E2 3674
RX5CP
Receive Channel 5 Completion Pointer Register
0x01E2 3678
RX6CP
Receive Channel 6 Completion Pointer Register
0x01E2 367C
RX7CP
Receive Channel 7 Completion Pointer Register
Table 6-32. EMAC Statistics Registers
ACRONYM
0x01E2 3200
RXGOODFRAMES
REGISTER DESCRIPTION
Good Receive Frames Register
0x01E2 3204
RXBCASTFRAMES
Broadcast Receive Frames Register
(Total number of good broadcast frames received)
0x01E2 3208
RXMCASTFRAMES
Multicast Receive Frames Register
(Total number of good multicast frames received)
0x01E2 320C
RXPAUSEFRAMES
Pause Receive Frames Register
0x01E2 3210
RXCRCERRORS
0x01E2 3214
RXALIGNCODEERRORS
0x01E2 3218
RXOVERSIZED
0x01E2 321C
RXJABBER
0x01E2 3220
RXUNDERSIZED
Receive Undersized Frames Register
(Total number of undersized frames received)
0x01E2 3224
RXFRAGMENTS
Receive Frame Fragments Register
Receive CRC Errors Register
(Total number of frames received with CRC errors)
Receive Alignment/Code Errors Register
(Total number of frames received with alignment/code errors)
Receive Oversized Frames Register
(Total number of oversized frames received)
Receive Jabber Frames Register
(Total number of jabber frames received)
0x01E2 3228
RXFILTERED
0x01E2 322C
RXQOSFILTERED
0x01E2 3230
RXOCTETS
0x01E2 3234
TXGOODFRAMES
Good Transmit Frames Register
(Total number of good frames transmitted)
0x01E2 3238
TXBCASTFRAMES
Broadcast Transmit Frames Register
0x01E2 323C
TXMCASTFRAMES
Multicast Transmit Frames Register
0x01E2 3240
TXPAUSEFRAMES
Pause Transmit Frames Register
0x01E2 3244
TXDEFERRED
Deferred Transmit Frames Register
Transmit Collision Frames Register
0x01E2 3248
TXCOLLISION
0x01E2 324C
TXSINGLECOLL
0x01E2 3250
TXMULTICOLL
0x01E2 3254
TXEXCESSIVECOLL
0x01E2 3258
TXLATECOLL
0x01E2 325C
TXUNDERRUN
0x01E2 3260
TXCARRIERSENSE
0x01E2 3264
TXOCTETS
0x01E2 3268
FRAME64
Copyright © 2010, Texas Instruments Incorporated
ADVANCE INFORMATION
BYTE ADDRESS
Filtered Receive Frames Register
Received QOS Filtered Frames Register
Receive Octet Frames Register
(Total number of received bytes in good frames)
Transmit Single Collision Frames Register
Transmit Multiple Collision Frames Register
Transmit Excessive Collision Frames Register
Transmit Late Collision Frames Register
Transmit Underrun Error Register
Transmit Carrier Sense Errors Register
Transmit Octet Frames Register
Transmit and Receive 64 Octet Frames Register
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Table 6-32. EMAC Statistics Registers (continued)
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
0x01E2 326C
FRAME65T127
Transmit and Receive 65 to 127 Octet Frames Register
0x01E2 3270
FRAME128T255
Transmit and Receive 128 to 255 Octet Frames Register
0x01E2 3274
FRAME256T511
Transmit and Receive 256 to 511 Octet Frames Register
0x01E2 3278
FRAME512T1023
Transmit and Receive 512 to 1023 Octet Frames Register
0x01E2 327C
FRAME1024TUP
Transmit and Receive 1024 to 1518 Octet Frames Register
0x01E2 3280
NETOCTETS
Network Octet Frames Register
0x01E2 3284
RXSOFOVERRUNS
Receive FIFO or DMA Start of Frame Overruns Register
0x01E2 3288
RXMOFOVERRUNS
Receive FIFO or DMA Middle of Frame Overruns Register
0x01E2 328C
RXDMAOVERRUNS
Receive DMA Start of Frame and Middle of Frame Overruns Register
Table 6-33. EMAC Control Module Registers
ADVANCE INFORMATION
80
BYTE ADDRESS
ACRONYM
0x01E2 2000
REV
REGISTER DESCRIPTION
EMAC Control Module Revision Register
0x01E2 2004
SOFTRESET
EMAC Control Module Software Reset Register
0x01E2 200C
INTCONTROL
EMAC Control Module Interrupt Control Register
0x01E2 2010
C0RXTHRESHEN
0x01E2 2014
C0RXEN
EMAC Control Module Interrupt Core 0 Receive Interrupt Enable Register
0x01E2 2018
C0TXEN
EMAC Control Module Interrupt Core 0 Transmit Interrupt Enable Register
0x01E2 201C
C0MISCEN
0x01E2 2020
C1RXTHRESHEN
0x01E2 2024
C1RXEN
EMAC Control Module Interrupt Core 1 Receive Interrupt Enable Register
0x01E2 2028
C1TXEN
EMAC Control Module Interrupt Core 1 Transmit Interrupt Enable Register
0x01E2 202C
C1MISCEN
0x01E2 2030
C2RXTHRESHEN
0x01E2 2034
C2RXEN
EMAC Control Module Interrupt Core 2 Receive Interrupt Enable Register
0x01E2 2038
C2TXEN
EMAC Control Module Interrupt Core 2 Transmit Interrupt Enable Register
EMAC Control Module Interrupt Core 0 Receive Threshold Interrupt Enable Register
EMAC Control Module Interrupt Core 0 Miscellaneous Interrupt Enable Register
EMAC Control Module Interrupt Core 1 Receive Threshold Interrupt Enable Register
EMAC Control Module Interrupt Core 1 Miscellaneous Interrupt Enable Register
EMAC Control Module Interrupt Core 2 Receive Threshold Interrupt Enable Register
0x01E2 203C
C2MISCEN
0x01E2 2040
C0RXTHRESHSTAT
EMAC Control Module Interrupt Core 2 Miscellaneous Interrupt Enable Register
0x01E2 2044
C0RXSTAT
EMAC Control Module Interrupt Core 0 Receive Interrupt Status Register
0x01E2 2048
C0TXSTAT
EMAC Control Module Interrupt Core 0 Transmit Interrupt Status Register
EMAC Control Module Interrupt Core 0 Receive Threshold Interrupt Status Register
0x01E2 204C
C0MISCSTAT
0x01E2 2050
C1RXTHRESHSTAT
EMAC Control Module Interrupt Core 0 Miscellaneous Interrupt Status Register
0x01E2 2054
C1RXSTAT
EMAC Control Module Interrupt Core 1 Receive Interrupt Status Register
EMAC Control Module Interrupt Core 1 Transmit Interrupt Status Register
EMAC Control Module Interrupt Core 1 Receive Threshold Interrupt Status Register
0x01E2 2058
C1TXSTAT
0x01E2 205C
C1MISCSTAT
0x01E2 2060
C2RXTHRESHSTAT
0x01E2 2064
C2RXSTAT
EMAC Control Module Interrupt Core 2 Receive Interrupt Status Register
0x01E2 2068
C2TXSTAT
EMAC Control Module Interrupt Core 2 Transmit Interrupt Status Register
0x01E2 206C
C2MISCSTAT
0x01E2 2070
C0RXIMAX
EMAC Control Module Interrupt Core 0 Receive Interrupts Per Millisecond Register
0x01E2 2074
C0TXIMAX
EMAC Control Module Interrupt Core 0 Transmit Interrupts Per Millisecond Register
0x01E2 2078
C1RXIMAX
EMAC Control Module Interrupt Core 1 Receive Interrupts Per Millisecond Register
0x01E2 207C
C1TXIMAX
EMAC Control Module Interrupt Core 1 Transmit Interrupts Per Millisecond Register
0x01E2 2080
C2RXIMAX
EMAC Control Module Interrupt Core 2 Receive Interrupts Per Millisecond Register
0x01E2 2084
C2TXIMAX
EMAC Control Module Interrupt Core 2 Transmit Interrupts Per Millisecond Register
EMAC Control Module Interrupt Core 1 Miscellaneous Interrupt Status Register
EMAC Control Module Interrupt Core 2 Receive Threshold Interrupt Status Register
EMAC Control Module Interrupt Core 2 Miscellaneous Interrupt Status Register
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Table 6-34. EMAC Control Module RAM
HEX ADDRESS RANGE
0x01E2 0000 - 0x01E2 1FFF
EMAC Local Buffer Descriptor Memory
Table 6-35. RMII Timing Requirements
PARAMETER
MIN
TYP
MAX
UNIT
1
tc(REFCLK)
Cycle Time, REF_CLK
20
ns
2
tw(REFCLKH)
Pulse Width, REF_CLK High
7
13
ns
3
tw(REFCLKL)
Pulse Width, REF_CLK Low
7
13
ns
6
tsu(RXD-REFCLK)
Input Setup Time, RXD Valid before REF_CLK High
4
ns
7
th(REFCLK-RXD)
Input Hold Time, RXD Valid after REF_CLK High
2
ns
8
tsu(CRSDV-REFCLK) Input Setup Time, CRSDV Valid before REF_CLK High
4
ns
9
th(REFCLK-CRSDV)
Input Hold Time, CRSDV Valid after REF_CLK High
2
ns
10
tsu(RXER-REFCLK)
Input Setup Time, RXER Valid before REF_CLK High
4
ns
11
th(REFCLKR-RXER)
Input Hold Time, RXER Valid after REF_CLK High
2
ns
ADVANCE INFORMATION
No.
Table 6-36. RMII Timing Requirements
No.
MAX
UNIT
4
td(REFCLK-TXD)
Output Delay Time, REF_CLK High to TXD Valid
PARAMETER
MIN
2.5
TYP
13
ns
5
td(REFCLK-TXEN)
Output Delay Time, REF_CLK High to TXEN Valid
2.5
13
ns
1
2
3
RMII_MHz_50_CLK
5
5
RMII_TXEN
4
RMII_TXD[1:0]
6
7
RMII_RXD[1:0]
8
9
RMII_CRS_DV
10
11
RMII_RXER
Figure 6-25. RMII Timing Diagram
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6.16 Management Data Input/Output (MDIO)
The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to
enumerate all PHY devices in the system.
The Management Data Input/Output (MDIO) module implements the 802.3 serial management interface to
interrogate and control Ethernet PHY(s) using a shared two-wire bus. Host software uses the MDIO
module to configure the auto-negotiation parameters of each PHY attached to the EMAC, retrieve the
negotiation results, and configure required parameters in the EMAC module for correct operation. The
module is designed to allow almost transparent operation of the MDIO interface, with very little
maintenance from the core processor. Only one PHY may be connected at any given time.
6.16.1 MDIO Registers
For a list of supported MDIO registers see Table 6-37 [MDIO Registers].
Table 6-37. MDIO Register Memory Map
ADVANCE INFORMATION
82
BYTE ADDRESS
ACRONYM
0x01E2 4000
REV
0x01E2 4004
CONTROL
REGISTER DESCRIPTION
Revision Identification Register
MDIO Control Register
0x01E2 4008
ALIVE
MDIO PHY Alive Status Register
0x01E2 400C
LINK
MDIO PHY Link Status Register
0x01E2 4010
LINKINTRAW
0x01E2 4014
LINKINTMASKED
0x01E2 4018
–
0x01E2 4020
USERINTRAW
MDIO Link Status Change Interrupt (Unmasked) Register
MDIO Link Status Change Interrupt (Masked) Register
Reserved
MDIO User Command Complete Interrupt (Unmasked) Register
0x01E2 4024
USERINTMASKED
MDIO User Command Complete Interrupt (Masked) Register
0x01E2 4028
USERINTMASKSET
MDIO User Command Complete Interrupt Mask Set Register
0x01E2 402C
USERINTMASKCLEAR
0x01E2 4030 - 0x01E2 407C
–
0x01E2 4080
USERACCESS0
MDIO User Access Register 0
0x01E2 4084
USERPHYSEL0
MDIO User PHY Select Register 0
0x01E2 4088
USERACCESS1
MDIO User Access Register 1
0x01E2 408C
USERPHYSEL1
MDIO User PHY Select Register 1
0x01E2 4090 - 0x01E2 47FF
–
MDIO User Command Complete Interrupt Mask Clear Register
Reserved
Reserved
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6.16.2 Management Data Input/Output (MDIO) Electrical Data/Timing
Table 6-38. Timing Requirements for MDIO Input (see Figure 6-26 and Figure 6-27)
No.
PARAMETER
MIN
MAX
UNIT
1
tc(MDIO_CLK)
Cycle time, MDIO_CLK
400
ns
2
tw(MDIO_CLK)
Pulse duration, MDIO_CLK high/low
180
ns
3
tt(MDIO_CLK)
Transition time, MDIO_CLK
4
tsu(MDIO-MDIO_CLKH) Setup time, MDIO_D data input valid before MDIO_CLK high
10
ns
5
th(MDIO_CLKH-MDIO)
10
ns
5
Hold time, MDIO_D data input valid after MDIO_CLK high
ns
1
3
3
MDIO_CLK
4
MDIO_D
(input)
Figure 6-26. MDIO Input Timing
Table 6-39. Switching Characteristics Over Recommended Operating Conditions for MDIO Output
(see Figure 6-27)
No.
7
PARAMETER
td(MDIO_CLKL-MDIO)
Delay time, MDIO_CLK low to MDIO_D data output valid
MIN
MAX
UNIT
0
100
ns
1
MDIO_CLK
7
MDIO_D
(output)
Figure 6-27. MDIO Output Timing
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ADVANCE INFORMATION
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6.17 Multichannel Audio Serial Ports (McASP0, McASP1)
ADVANCE INFORMATION
The McASP serial port is specifically designed for multichannel audio applications. Its key features are:
• Flexible clock and frame sync generation logic and on-chip dividers
• Up to sixteen transmit or receive data pins and serializers
• Large number of serial data format options, including:
– TDM Frames with 2 to 32 time slots per frame (periodic) or 1 slot per frame (burst)
– Time slots of 8,12,16, 20, 24, 28, and 32 bits
– First bit delay 0, 1, or 2 clocks
– MSB or LSB first bit order
– Left- or right-aligned data words within time slots
• DIT Mode (optional) with 384-bit Channel Status and 384-bit User Data registers
• Extensive error checking and mute generation logic
• All unused pins GPIO-capable
• Transmit & Receive FIFO Buffers for each McASP. Allows the McASP to operate at a higher sample
rate by making it more tolerant to DMA latency.
• Dynamic Adjustment of Clock Dividers
– Clock Divider Value may be changed without resetting the McASP
The three McASPs on the device are configured with the following options:
Table 6-40. McASP Configurations (1)
Module
Serializers
AFIFO
DIT
Pins
McASP0
16
64 Word RX
64 Word TX
N
AXR0[15:0], AHCLKR0, ACLKR0, AFSR0, AHCLKX0, ACLKX0, AFSX0, AMUTE0
McASP1
12
64 Word RX
64 Word TX
N
AXR1[11:10], AXR1[8:0], AHCLKR1, ACLKR1, AFSR1, AHCLKX1, ACLKX1, AFSX1,
AMUTE1
(1)
Pins available are the maximum number of pins that may be configured for a particular McASP; not including pin multiplexing.
Pins
Peripheral
Configuration
Bus
GIO
Control
DIT RAM
384 C
384 U
Optional
McASP
DMA Bus
(Dedicated)
Transmit
Formatter
Receive
Formatter
Function
Receive Logic
Clock/Frame Generator
State Machine
AHCLKRx
ACLKRx
AFSRx
Receive Master Clock
Receive Bit Clock
Receive Left/Right Clock or Frame Sync
Clock Check and
Error Detection
AMUTEINx
AMUTEx
The McASPs DO NOT have
dedicated AMUTEINx pins.
Transmit Logic
Clock/Frame Generator
State Machine
AFSXx
ACLKXx
AHCLKXx
Transmit Left/Right Clock or Frame Sync
Transmit Bit Clock
Transmit Master Clock
Serializer 0
AXRx[0]
Transmit/Receive Serial Data Pin
Serializer 1
AXRx[1]
Transmit/Receive Serial Data Pin
Serializer y
AXRx[y]
Transmit/Receive Serial Data Pin
McASPx (x = 0, 1, 2)
Figure 6-28. McASP Block Diagram
84
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6.17.1 McASP Peripheral Registers Description(s)
Registers for the McASP are summarized in Table 6-41. The registers are accessed through the
peripheral configuration port. The receive buffer registers (RBUF) and transmit buffer registers (XBUF) can
also be accessed through the DMA port, as listed in Table 6-42
Registers for the McASP Audio FIFO (AFIFO) are summarized in Table 6-43. Note that the AFIFO Write
FIFO (WFIFO) and Read FIFO (RFIFO) have independent control and status registers. The AFIFO control
registers are accessed through the peripheral configuration port.
Table 6-41. McASP Registers Accessed Through Peripheral Configuration Port
McASP0
BYTE
ADDRESS
McASP1
BYTE
ADDRESS
ACRONYM
REGISTER DESCRIPTION
0x01D0 0000
0x01D0 4000
REV
0x01D0 0010
0x01D0 4010
PFUNC
Pin function register
0x01D0 0014
0x01D0 4014
PDIR
Pin direction register
0x01D0 0018
0x01D0 4018
PDOUT
Revision identification register
Pin data output register
PDIN
0x01D0 001C 0x01D0 401C
PDSET
Read returns: Pin data input register
Writes affect: Pin data set register (alternate write address: PDOUT)
0x01D0 0020
0x01D0 4020
PDCLR
Pin data clear register (alternate write address: PDOUT)
0x01D0 0044
0x01D0 4044
GBLCTL
Global control register
0x01D0 0048
0x01D0 4048
AMUTE
Audio mute control register
0x01D0 004C 0x01D0 404C
DLBCTL
Digital loopback control register
0x01D0 0050
0x01D0 4050
DITCTL
DIT mode control register
0x01D0 0060
0x01D0 4060
RGBLCTL
0x01D0 0064
0x01D0 4064
RMASK
0x01D0 0068
0x01D0 4068
0x01D0 006C 0x01D0 406C
0x01D0 0070
0x01D0 4070
0x01D0 0074
0x01D0 4074
0x01D0 0078
0x01D0 4078
0x01D0 007C 0x01D0 407C
0x01D0 0080
0x01D0 4080
0x01D0 0084
0x01D0 0088
RFMT
AFSRCTL
ACLKRCTL
ADVANCE INFORMATION
0x01D0 001C 0x01D0 401C
Receiver global control register: Alias of GBLCTL, only receive bits are affected - allows
receiver to be reset independently from transmitter
Receive format unit bit mask register
Receive bit stream format register
Receive frame sync control register
Receive clock control register
AHCLKRCTL Receive high-frequency clock control register
RTDM
RINTCTL
Receive TDM time slot 0-31 register
Receiver interrupt control register
RSTAT
Receiver status register
0x01D0 4084
RSLOT
Current receive TDM time slot register
0x01D0 4088
RCLKCHK
Receive clock check control register
0x01D0 008C 0x01D0 408C
REVTCTL
Receiver DMA event control register
0x01D0 00A0
0x01D0 40A0
XGBLCTL
Transmitter global control register. Alias of GBLCTL, only transmit bits are affected - allows
transmitter to be reset independently from receiver
0x01D0 00A4
0x01D0 40A4
XMASK
0x01D0 00A8
0x01D0 40A8
XFMT
0x01D0 00AC 0x01D0 40AC
0x01D0 00B0
0x01D0 40B0
0x01D0 00B4
0x01D0 40B4
0x01D0 00B8
0x01D0 40B8
AFSXCTL
ACLKXCTL
Transmit format unit bit mask register
Transmit bit stream format register
Transmit frame sync control register
Transmit clock control register
AHCLKXCTL Transmit high-frequency clock control register
XTDM
Transmit TDM time slot 0-31 register
0x01D0 00BC 0x01D0 40BC
XINTCTL
Transmitter interrupt control register
0x01D0 00C0 0x01D0 40C0
XSTAT
Transmitter status register
0x01D0 00C4 0x01D0 40C4
XSLOT
Current transmit TDM time slot register
0x01D0 00C8 0x01D0 40C8
XCLKCHK
Transmit clock check control register
0x01D0 00CC 0x01D0 40CC
XEVTCTL
Transmitter DMA event control register
0x01D0 0100
DITCSRA0
Left (even TDM time slot) channel status register (DIT mode) 0
0x01D0 4100
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Table 6-41. McASP Registers Accessed Through Peripheral Configuration Port (continued)
McASP0
BYTE
ADDRESS
McASP1
BYTE
ADDRESS
ACRONYM
REGISTER DESCRIPTION
0x01D0 0104
0x01D0 4104
DITCSRA1
Left (even TDM time slot) channel status register (DIT mode) 1
0x01D0 0108
0x01D0 4108
DITCSRA2
Left (even TDM time slot) channel status register (DIT mode) 2
0x01D0 010C 0x01D0 410C
DITCSRA3
Left (even TDM time slot) channel status register (DIT mode) 3
0x01D0 0110
0x01D0 4110
DITCSRA4
Left (even TDM time slot) channel status register (DIT mode) 4
0x01D0 0114
0x01D0 4114
DITCSRA5
Left (even TDM time slot) channel status register (DIT mode) 5
0x01D0 0118
ADVANCE INFORMATION
0x01D0 4118
DITCSRB0
Right (odd TDM time slot) channel status register (DIT mode) 0
0x01D0 011C 0x01D0 411C
DITCSRB1
Right (odd TDM time slot) channel status register (DIT mode) 1
0x01D0 0120
0x01D0 4120
DITCSRB2
Right (odd TDM time slot) channel status register (DIT mode) 2
0x01D0 0124
0x01D0 4124
DITCSRB3
Right (odd TDM time slot) channel status register (DIT mode) 3
0x01D0 0128
0x01D0 4128
DITCSRB4
Right (odd TDM time slot) channel status register (DIT mode) 4
0x01D0 012C 0x01D0 412C
DITCSRB5
Right (odd TDM time slot) channel status register (DIT mode) 5
0x01D0 0130
0x01D0 4130
DITUDRA0
Left (even TDM time slot) channel user data register (DIT mode) 0
0x01D0 0134
0x01D0 4134
DITUDRA1
Left (even TDM time slot) channel user data register (DIT mode) 1
0x01D0 0138
0x01D0 4138
DITUDRA2
Left (even TDM time slot) channel user data register (DIT mode) 2
0x01D0 013C 0x01D0 413C
DITUDRA3
Left (even TDM time slot) channel user data register (DIT mode) 3
0x01D0 0140
0x01D0 4140
DITUDRA4
Left (even TDM time slot) channel user data register (DIT mode) 4
0x01D0 0144
0x01D0 4144
DITUDRA5
Left (even TDM time slot) channel user data register (DIT mode) 5
0x01D0 0148
0x01D0 4148
DITUDRB0
Right (odd TDM time slot) channel user data register (DIT mode) 0
0x01D0 014C 0x01D0 414C
DITUDRB1
Right (odd TDM time slot) channel user data register (DIT mode) 1
0x01D0 0150
0x01D0 4150
DITUDRB2
Right (odd TDM time slot) channel user data register (DIT mode) 2
0x01D0 0154
0x01D0 4154
DITUDRB3
Right (odd TDM time slot) channel user data register (DIT mode) 3
0x01D0 0158
0x01D0 4158
DITUDRB4
Right (odd TDM time slot) channel user data register (DIT mode) 4
0x01D0 015C 0x01D0 415C
DITUDRB5
Right (odd TDM time slot) channel user data register (DIT mode) 5
0x01D0 0180
0x01D0 4180
SRCTL0
Serializer control register 0
0x01D0 0184
0x01D0 4184
SRCTL1
Serializer control register 1
0x01D0 0188
0x01D0 4188
SRCTL2
Serializer control register 2
0x01D0 018C 0x01D0 418C
SRCTL3
Serializer control register 3
0x01D0 0190
0x01D0 4190
SRCTL4
Serializer control register 4
0x01D0 0194
0x01D0 4194
SRCTL5
Serializer control register 5
0x01D0 0198
0x01D0 4198
SRCTL6
Serializer control register 6
0x01D0 019C 0x01D0 419C
SRCTL7
Serializer control register 7
0x01D0 01A0
0x01D0 41A0
SRCTL8
Serializer control register 8
0x01D0 01A4
0x01D0 41A4
SRCTL9
Serializer control register 9
0x01D0 01A8
0x01D0 41A8
SRCTL10
Serializer control register 10
0x01D0 01AC 0x01D0 41AC
SRCTL11
Serializer control register 11
0x01D0 01B0
0x01D0 41B0
SRCTL12
Serializer control register 12
0x01D0 01B4
0x01D0 41B4
SRCTL13
Serializer control register 13
0x01D0 01B8
0x01D0 41B8
SRCTL14
Serializer control register 14
0x01D0 01BC 0x01D0 41BC
SRCTL15
Serializer control register 15
0x01D0 0200
0x01D0 4200
XBUF0 (1)
Transmit buffer register for serializer 0
0x01D0 0204
0x01D0 4204
XBUF1 (1)
Transmit buffer register for serializer 1
0x01D0 4208
(1)
Transmit buffer register for serializer 2
0x01D0 020C 0x01D0 420C
XBUF3 (1)
Transmit buffer register for serializer 3
0x01D0 0210
0x01D0 4210
XBUF4 (1)
Transmit buffer register for serializer 4
0x01D0 0214
0x01D0 4214
XBUF5 (1)
Transmit buffer register for serializer 5
0x01D0 0208
(1)
86
XBUF2
Writes to XRBUF originate from peripheral configuration port only when XBUSEL = 1 in XFMT.
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Table 6-41. McASP Registers Accessed Through Peripheral Configuration Port (continued)
McASP1
BYTE
ADDRESS
ACRONYM
0x01D0 0218
0x01D0 4218
XBUF6 (1)
Transmit buffer register for serializer 6
0x01D0 021C 0x01D0 421C
REGISTER DESCRIPTION
XBUF7
Transmit buffer register for serializer 7
0x01D0 0220
0x01D0 4220
XBUF8 (1)
Transmit buffer register for serializer 8
0x01D0 0224
0x01D0 4224
XBUF9
Transmit buffer register for serializer 9
0x01D0 0228
0x01D0 4228
XBUF10 (1)
Transmit buffer register for serializer 10
0x01D0 022C 0x01D0 422C
(1)
Transmit buffer register for serializer 11
XBUF11
0x01D0 0230
0x01D0 4230
XBUF12
Transmit buffer register for serializer 12
0x01D0 0234
0x01D0 4234
XBUF13 (1)
Transmit buffer register for serializer 13
0x01D0 4238
(1)
Transmit buffer register for serializer 14
0x01D0 0238
XBUF14
0x01D0 023C 0x01D0 423C
XBUF15
Transmit buffer register for serializer 15
0x01D0 0280
0x01D0 4280
RBUF0 (2)
Receive buffer register for serializer 0
0x01D0 0284
0x01D0 4284
RBUF1
(2)
Receive buffer register for serializer 1
0x01D0 0288
0x01D0 4288
RBUF2 (2)
Receive buffer register for serializer 2
0x01D0 028C 0x01D0 428C
RBUF3 (2)
Receive buffer register for serializer 3
0x01D0 0290
0x01D0 4290
RBUF4 (3)
Receive buffer register for serializer 4
0x01D0 0294
0x01D0 4294
RBUF5
(3)
Receive buffer register for serializer 5
0x01D0 0298
0x01D0 4298
RBUF6 (3)
Receive buffer register for serializer 6
0x01D0 029C 0x01D0 429C
RBUF7 (3)
Receive buffer register for serializer 7
(3)
Receive buffer register for serializer 8
0x01D0 02A0
0x01D0 42A0
RBUF8
0x01D0 02A4
0x01D0 42A4
RBUF9 (3)
Receive buffer register for serializer 9
0x01D0 02A8
0x01D0 42A8
RBUF10 (3)
Receive buffer register for serializer 10
0x01D0 02AC 0x01D0 42AC
RBUF11
(3)
Receive buffer register for serializer 11
0x01D0 02B0
0x01D0 42B0
RBUF12 (3)
Receive buffer register for serializer 12
0x01D0 02B4
0x01D0 42B4
RBUF13 (3)
Receive buffer register for serializer 13
0x01D0 02B8
0x01D0 42B8
RBUF14 (3)
Receive buffer register for serializer 14
0x01D0 02BC 0x01D0 42BC
(3)
Receive buffer register for serializer 15
(2)
(3)
RBUF15
ADVANCE INFORMATION
McASP0
BYTE
ADDRESS
Reads from XRBUF originate on peripheral configuration port only when RBUSEL = 1 in RFMT.
Reads from XRBUF originate on peripheral configuration port only when RBUSEL = 1 in RFMT.
Table 6-42. McASP Registers Accessed Through DMA Port
McASP0
BYTE
ADDRESS
McASP1
BYTE
ADDRESS
ACRONYM
REGISTER DESCRIPTION
Read
Accesses
01D0 2000
01D0 6000
RBUF
Receive buffer DMA port address. Cycles through receive serializers,
skipping over transmit serializers and inactive serializers. Starts at the
lowest serializer at the beginning of each time slot. Reads from DMA port
only if XBUSEL = 0 in XFMT.
Write
Accesses
01D0 2000
01D0 6000
XBUF
Transmit buffer DMA port address. Cycles through transmit serializers,
skipping over receive and inactive serializers. Starts at the lowest serializer
at the beginning of each time slot. Writes to DMA port only if RBUSEL = 0
in RFMT.
Table 6-43. McASP AFIFO Registers Accessed Through Peripheral Configuration Port
McASP0
BYTE ADDRESS
McASP1
BYTE ADDRESS
ACRONYM
0x01D0 1000
0x01D0 5000
AFIFOREV
AFIFO revision identification register
0x01D0 1010
0x01D0 5010
WFIFOCTL
Write FIFO control register
0x01D0 1014
0x01D0 5014
WFIFOSTS
Write FIFO status register
Copyright © 2010, Texas Instruments Incorporated
REGISTER DESCRIPTION
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Table 6-43. McASP AFIFO Registers Accessed Through Peripheral Configuration Port (continued)
McASP0
BYTE ADDRESS
McASP1
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
0x01D0 1018
0x01D0 5018
RFIFOCTL
Read FIFO control register
0x01D0 101C
0x01D0 501C
RFIFOSTS
Read FIFO status register
ADVANCE INFORMATION
88
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6.17.2 McASP Electrical Data/Timing
6.17.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing
Table 6-44 and Table 6-45 assume testing over recommended operating conditions (see and ).
No.
1
tc(AHCLKRX)
2
tw(AHCLKRX)
3
tc(ACLKRX)
4
tw(ACLKRX)
5
tsu(AFSRX-ACLKRX)
PARAMETER
MIN
Cycle time, AHCLKR0 external, AHCLKR0 input
20
Cycle time, AHCLKX0 external, AHCLKX0 input
20
Pulse duration, AHCLKR0 external, AHCLKR0 input
10
Pulse duration, AHCLKX0 external, AHCLKX0 input
10
Cycle time, ACLKR0 external, ACLKR0 input
greater of 2P or 20
Cycle time, ACLKX0 external, ACLKX0 input
greater of 2P or 20
Pulse duration, ACLKR0 external, ACLKR0 input
10
Pulse duration, ACLKX0 external, ACLKX0 input
10
Setup time, AFSR0 input to ACLKR0 internal (3)
9.4
Setup time, AFSX0 input to ACLKX0 internal
9.4
Setup time, AFSR0 input to ACLKR0 external input (3)
3
Setup time, AFSX0 input to ACLKX0 external input
3
Setup time, AFSR0 input to ACLKR0 external output (3)
3
Setup time, AFSX0 input to ACLKX0 external output
6
th(ACLKRX-AFSRX)
tsu(AXR-ACLKRX)
-1.9
Hold time, AFSX0 input after ACLKX0 internal
-1.9
Hold time, AFSR0 input after ACLKR0 external input (3)
0.5
Hold time, AFSX0 input after ACLKX0 external input
0.8
Hold time, AFSR0 input after ACLKR0 external output (3)
0.5
Hold time, AFSX0 input after ACLKX0 external output
0.5
Setup time, AXR0[n] input to ACLKR0 internal (3)
9.4
(4)
9.4
Setup time, AXR0[n] input to ACLKR0 external input (3)
3
Setup time, AXR0[n] input to ACLKX0 external input (4)
3
Setup time, AXR0[n] input to ACLKR0 external output (3)
3
Setup time, AXR0[n] input to ACLKX0 external output
(4)
Hold time, AXR0[n] input after ACLKR0 internal (3)
th(ACLKRX-AXR)
(2)
(3)
(4)
ns
ns
ns
ns
ns
ns
-1.7
0.6
Hold time, AXR0[n] input after ACLKX0 external input (4)
0.6
Hold time, AXR0[n] input after ACLKR0 external output (3)
0.6
(4)
0.6
Hold time, AXR0[n] input after ACLKX0 external output
(1)
ns
3
(3)
Hold time, AXR0[n] input after ACLKR0 external input
UNIT
-1.7
Hold time, AXR0[n] input after ACLKX0 internal (4)
8
MAX
3
Hold time, AFSR0 input after ACLKR0 internal (3)
Setup time, AXR0[n] input to ACLKX0 internal
7
(2)
ADVANCE INFORMATION
Table 6-44. McASP0 Timing Requirements (1)
ns
ACLKX0 internal – McASP0 ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX0 external output – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR0 internal – McASP0 ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
P = SYSCLK2 period
McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0
McASP0 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX0
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Table 6-45. McASP0 Switching Characteristics (1)
No.
9
tc(AHCLKRX)
10
11
12
ADVANCE INFORMATION
13
14
15
(1)
(2)
(3)
(4)
(5)
(6)
(7)
90
PARAMETER
tw(AHCLKRX)
tc(ACLKRX)
tw(ACLKRX)
td(ACLKRX-AFSRX)
td(ACLKX-AXRV)
tdis(ACLKX-AXRHZ)
MIN
Cycle time, AHCLKR0 internal, AHCLKR0 output
20
Cycle time, AHCLKR0 external, AHCLKR0 output
20
Cycle time, AHCLKX0 internal, AHCLKX0 output
20
Cycle time, AHCLKX0 external, AHCLKX0 output
20
Pulse duration, AHCLKR0 internal, AHCLKR0 output
(AHR/2) – 2.5 (2)
Pulse duration, AHCLKR0 external, AHCLKR0 output
(AHR/2) – 2.5 (2)
Pulse duration, AHCLKX0 internal, AHCLKX0 output
(AHX/2) – 2.5 (3)
Pulse duration, AHCLKX0 external, AHCLKX0 output
(AHX/2) – 2.5 (3)
Cycle time, ACLKR0 internal, ACLKR0 output
greater of 2P or 20 ns (4)
Cycle time, ACLKR0 external, ACLKR0 output
greater of 2P or 20 ns (4)
Cycle time, ACLKX0 internal, ACLKX0 output
greater of 2P or 20 ns (4)
Cycle time, ACLKX0 external, ACLKX0 output
greater of 2P or 20 ns (4)
Pulse duration, ACLKR0 internal, ACLKR0 output
(AR/2) – 2.5 (5)
Pulse duration, ACLKR0 external, ACLKR0 output
(AR/2) – 2.5 (5)
Pulse duration, ACLKX0 internal, ACLKX0 output
(AX/2) – 2.5 (6)
Pulse duration, ACLKX0 external, ACLKX0 output
(AX/2) – 2.5 (6)
MAX
ns
ns
ns
ns
Delay time, ACLKR0 internal, AFSR output (7)
0
Delay time, ACLKX0 internal, AFSX output
0
6
Delay time, ACLKR0 external input, AFSR output (7)
3
11.7
Delay time, ACLKX0 external input, AFSX output
3
11.7
Delay time, ACLKR0 external output, AFSR output (7)
3
11.7
Delay time, ACLKX0 external output, AFSX output
3
11.7
Delay time, ACLKX0 internal, AXR0[n] output
0
6
2.75
11.7
Delay time, ACLKX0 external output, AXR0[n] output
3
11.7
Disable time, ACLKX0 internal, AXR0[n] output
0
6
Disable time, ACLKX0 external input, AXR0[n] output
3
11.7
Disable time, ACLKX0 external output, AXR0[n] output
3
11.7
Delay time, ACLKX0 external input, AXR0[n] output
UNIT
6
ns
ns
ns
McASP0 ACLKX0 internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX0 external output – McASP0ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR0 internal – McASP0 ACLKR0CTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
AHR - Cycle time, AHCLKR0.
AHX - Cycle time, AHCLKX0.
P = SYSCLK2 period
AR - ACLKR0 period.
AX - ACLKX0 period.
McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0
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6.17.2.2 Multichannel Audio Serial Port 1 (McASP1) Timing
Table 6-46 and Table 6-47 assume testing over recommended operating conditions (see and ).
Table 6-46. McASP1 Timing Requirements (1)
PARAMETER
1
tc(AHCLKRX)
2
tw(AHCLKRX)
3
tc(ACLKRX)
4
tw(ACLKRX)
MIN
Cycle time, AHCLKR1 external, AHCLKR1 input
20
Cycle time, AHCLKX1 external, AHCLKX1 input
20
Pulse duration, AHCLKR1 external, AHCLKR1 input
10
Pulse duration, AHCLKX1 external, AHCLKX1 input
10
Cycle time, ACLKR1 external, ACLKR1 input
greater of 2P or 20
Cycle time, ACLKX1 external, ACLKX1 input
greater of 2P or 20
Pulse duration, ACLKR1 external, ACLKR1 input
10
Pulse duration, ACLKX1 external, ACLKX1 input
10
Setup time, AFSR1 input to ACLKR1 internal (3)
10.4
Setup time, AFSX1 input to ACLKX1 internal
5
tsu(AFSRX-ACLKRX)
th(ACLKRX-AFSRX)
Setup time, AFSR1 input to ACLKR1 external input
7
8
(1)
(2)
(3)
(4)
tsu(AXR-ACLKRX)
th(ACLKRX-AXR)
(3)
2.6
Setup time, AFSX1 input to ACLKX1 external input
2.6
Setup time, AFSR1 input to ACLKR1 external output (3)
2.6
Setup time, AFSX1 input to ACLKX1 external output
2.6
(3)
ns
ns
ns
ns
ns
-2.4
Hold time, AFSX1 input after ACLKX1 internal
-2.4
Hold time, AFSR1 input after ACLKR1 external input (3)
0.85
Hold time, AFSX1 input after ACLKX1 external input
0.8
Hold time, AFSR1 input after ACLKR1 external output (3)
0.3
Hold time, AFSX1 input after ACLKX1 external output
0.3
(3)
10.4
Setup time, AXR1[n] input to ACLKX1 internal (4)
10.4
Setup time, AXR1[n] input to ACLKR1 external input (3)
2.6
Setup time, AXR1[n] input to ACLKX1 external input (4)
2.6
Setup time, AXR1[n] input to ACLKR1 external output (3)
2.6
Setup time, AXR1[n] input to ACLKR1 internal
UNIT
10.4
Hold time, AFSR1 input after ACLKR1 internal
6
MAX
ADVANCE INFORMATION
No.
(2)
Setup time, AXR1[n] input to ACLKX1 external output (4)
2.6
Hold time, AXR1[n] input after ACLKR1 internal (3)
-2.4
Hold time, AXR1[n] input after ACLKX1 internal (4)
-2.4
Hold time, AXR1[n] input after ACLKR1 external input (3)
0.65
Hold time, AXR1[n] input after ACLKX1 external input (4)
0.4
Hold time, AXR1[n] input after ACLKR1 external output (3)
0.4
Hold time, AXR1[n] input after ACLKX1 external output (4)
0.4
ns
ns
ns
ACLKX1 internal – McASP1 ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX1 external input – McASP1 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX1 external output – McASP1 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR1 internal – McASP1 ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR1 external input – McASP1 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR1 external output – McASP1 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
P = SYSCLK2 period
McASP1 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR1
McASP1 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX1
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Table 6-47. McASP1 Switching Characteristics (1)
No.
9
tc(AHCLKRX)
10
11
12
ADVANCE INFORMATION
13
14
15
(1)
(2)
(3)
(4)
(5)
(6)
(7)
92
PARAMETER
tw(AHCLKRX)
tc(ACLKRX)
tw(ACLKRX)
td(ACLKRX-AFSRX)
td(ACLKX-AXRV)
tdis(ACLKX-AXRHZ)
MIN
Cycle time, AHCLKR1 internal, AHCLKR1 output
20
Cycle time, AHCLKR1 external, AHCLKR1 output
20
Cycle time, AHCLKX1 internal, AHCLKX1 output
20
Cycle time, AHCLKX1 external, AHCLKX1 output
20
Pulse duration, AHCLKR1 internal, AHCLKR1 output
(AHR/2) – 2.5 (2)
Pulse duration, AHCLKR1 external, AHCLKR1 output
(AHR/2) – 2.5 (2)
Pulse duration, AHCLKX1 internal, AHCLKX1 output
(AHX/2) – 2.5 (3)
Pulse duration, AHCLKX1 external, AHCLKX1 output
(AHX/2) – 2.5 (3)
Cycle time, ACLKR1 internal, ACLKR1 output
greater of 2P or 20 ns (4)
Cycle time, ACLKR1 external, ACLKR1 output
greater of 2P or 20 ns (4)
Cycle time, ACLKX1 internal, ACLKX1 output
greater of 2P or 20 ns (4)
Cycle time, ACLKX1 external, ACLKX1 output
greater of 2P or 20 ns (4)
Pulse duration, ACLKR1 internal, ACLKR1 output
(AR/2) – 2.5 (5)
Pulse duration, ACLKR1 external, ACLKR1 output
(AR/2) – 2.5 (5)
Pulse duration, ACLKX1 internal, ACLKX1 output
(AX/2) – 2.5 (6)
Pulse duration, ACLKX1 external, ACLKX1 output
(AX/2) – 2.5 (6)
MAX
UNIT
ns
ns
ns
ns
Delay time, ACLKR1 internal, AFSR output (7)
0.5
Delay time, ACLKX1 internal, AFSX output
0.5
6.7
Delay time, ACLKR1 external input, AFSR output (7)
3.9
13.8
Delay time, ACLKX1 external input, AFSX output
3.9
13.8
Delay time, ACLKR1 external output, AFSR output (7)
3.9
13.8
Delay time, ACLKX1 external output, AFSX output
3.9
13.8
Delay time, ACLKX1 internal, AXR1[n] output
0.5
6.7
Delay time, ACLKX1 external input, AXR1[n] output
3.8
13.8
Delay time, ACLKX1 external output, AXR1[n] output
3.9
13.8
Disable time, ACLKX1 internal, AXR1[n] output
0.5
6.7
Disable time, ACLKX1 external input, AXR1[n] output
3.9
13.8
Disable time, ACLKX1 external output, AXR1[n] output
3.9
13.8
6.7
ns
ns
ns
McASP1 ACLKX1 internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
McASP1 ACLKX1 external input – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
McASP1 ACLKX1 external output – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
McASP1 ACLKR1 internal – ACLKR1CTL.CLKRM = 1, PDIR.ACLKR =1
McASP1 ACLKR1 external input – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
McASP1 ACLKR1 external output – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
AHR - Cycle time, AHCLKR1.
AHX - Cycle time, AHCLKX1.
P = SYSCLK2 period
AR - ACLKR1 period.
AX - ACLKX1 period.
McASP1 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR1
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6.18 Serial Peripheral Interface Ports (SPI0, SPI1)
Figure 6-29 is a block diagram of the SPI module, which is a simple shift register and buffer plus control
logic. Data is written to the shift register before transmission occurs and is read from the buffer at the end
of transmission. The SPI can operate either as a master, in which case, it initiates a transfer and drives
the SPIx_CLK pin, or as a slave. Four clock phase and polarity options are supported as well as many
data formatting options.
SPIx_SIMO
SPIx_SOMI
Interrupt and
DMA Requests
16-Bit Shift Register
16-Bit Buffer
SPIx_ENA
State
GPIO
Machine SPIx_SCS
Control
(all pins) Clock SPIx_CLK
Control
Figure 6-29. Block Diagram of SPI Module
The SPI supports 3-, 4-, and 5-pin operation with three basic pins (SPIx_CLK, SPIx_SIMO, and
SPIx_SOMI) and two optional pins (SPIx_SCS, SPIx_ENA).
The optional SPIx_SCS (Slave Chip Select) pin is most useful to enable in slave mode when there are
other slave devices on the same SPI port. The device will only shift data and drive the SPIx_SOMI pin
when SPIx_SCS is held low.
In slave mode, SPIx_ENA is an optional output and can be driven in either a push-pull or open-drain
manner. The SPIx_ENA output provides the status of the internal transmit buffer (SPIDAT0/1 registers). In
four-pin mode with the enable option, SPIx_ENA is asserted only when the transmit buffer is full, indicating
that the slave is ready to begin another transfer. In five-pin mode, the SPIx_ENA is additionally qualified
by SPIx_SCS being asserted. This allows a single handshake line to be shared by multiple slaves on the
same SPI bus.
In master mode, the SPIx_ENA pin is an optional input and the master can be configured to delay the start
of the next transfer until the slave asserts SPIx_ENA. The addition of this handshake signal simplifies SPI
communications and, on average, increases SPI bus throughput since the master does not need to delay
each transfer long enough to allow for the worst-case latency of the slave device. Instead, each transfer
can begin as soon as both the master and slave have actually serviced the previous SPI transfer.
Although the SPI module supports two interrupt outputs, SPIx_INT1 is the only interrupt connected on this
device.
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Optional − Slave Chip Select
SPIx_SCS
SPIx_SCS
Optional Enable (Ready)
ADVANCE INFORMATION
SPIx_ENA
SPIx_ENA
SPIx_CLK
SPIx_CLK
SPIx_SOMI
SPIx_SOMI
SPIx_SIMO
SPIx_SIMO
MASTER SPI
SLAVE SPI
Figure 6-30. Illustration of SPI Master-to-SPI Slave Connection
94
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6.18.1 SPI Peripheral Registers Description(s)
Table 6-48 is a list of the SPI registers.
Table 6-48. SPIx Configuration Registers
SPI0
BYTE ADDRESS
SPI1
BYTE ADDRESS
ACRONYM
0x01C4 1000
0x01E1 2000
SPIGCR0
Global Control Register 0
0x01C4 1004
0x01E1 2004
SPIGCR1
Global Control Register 1
0x01C4 1008
0x01E1 2008
SPIINT0
Interrupt Register
0x01C4 100C
0x01E1 200C
SPILVL
Interrupt Level Register
0x01C4 1010
0x01E1 2010
SPIFLG
Flag Register
0x01C4 1014
0x01E1 2014
SPIPC0
Pin Control Register 0 (Pin Function)
0x01C4 1018
0x01E1 2018
SPIPC1
Pin Control Register 1 (Pin Direction)
0x01C4 101C
0x01E1 201C
SPIPC2
Pin Control Register 2 (Pin Data In)
0x01C4 1020
0x01E1 2020
SPIPC3
Pin Control Register 3 (Pin Data Out)
0x01C4 1024
0x01E1 2024
SPIPC4
Pin Control Register 4 (Pin Data Set)
0x01C4 1028
0x01E1 2028
SPIPC5
Pin Control Register 5 (Pin Data Clear)
0x01C4 102C
0x01E1 202C
Reserved
Reserved - Do not write to this register
0x01C4 1030
0x01E1 2030
Reserved
Reserved - Do not write to this register
0x01C4 1034
0x01E1 2034
Reserved
Reserved - Do not write to this register
0x01C4 1038
0x01E1 2038
SPIDAT0
Shift Register 0 (without format select)
0x01C4 103C
0x01E1 203C
SPIDAT1
Shift Register 1 (with format select)
0x01C4 1040
0x01E1 2040
SPIBUF
Buffer Register
0x01C4 1044
0x01E1 2044
SPIEMU
Emulation Register
0x01C4 1048
0x01E1 2048
SPIDELAY
0x01C4 104C
0x01E1 204C
SPIDEF
Default Chip Select Register
0x01C4 1050
0x01E1 2050
SPIFMT0
Format Register 0
0x01C4 1054
0x01E1 2054
SPIFMT1
Format Register 1
0x01C4 1058
0x01E1 2058
SPIFMT2
Format Register 2
0x01C4 105C
0x01E1 205C
SPIFMT3
Format Register 3
0x01C4 1060
0x01E1 2060
Reserved
Reserved - Do not write to this register
0x01C4 1064
0x01E1 2064
INTVEC1
Interrupt Vector for SPI INT1
Copyright © 2010, Texas Instruments Incorporated
ADVANCE INFORMATION
REGISTER DESCRIPTION
Delay Register
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6.18.2 SPI Electrical Data/Timing
6.18.2.1 Serial Peripheral Interface (SPI) Timing
Table 6-49 through Table 6-64 assume testing over recommended operating conditions (see Figure 6-31
through Figure 6-34).
Table 6-49. General Timing Requirements for SPI0 Master Modes (1)
No.
MAX
UNIT
tc(SPC)M
Cycle Time, SPI0_CLK, All Master Modes
2
tw(SPCH)M
Pulse Width High, SPI0_CLK, All Master Modes
0.5tc(SPC)M - 1
ns
3
tw(SPCL)M
Pulse Width Low, SPI0_CLK, All Master Modes
0.5tc(SPC)M - 1
ns
ADVANCE INFORMATION
5
6
7
8
96
MIN
greater of 2P or
20 ns
1
4
(1)
(2)
PARAMETER
td(SIMO_SPC)M
td(SPC_SIMO)M
toh(SPC_SIMO)M
tsu(SOMI_SPC)M
tih(SPC_SOMI)M
Delay, initial data bit valid on SPI0_SIMO
after initial edge on SPI0_CLK (2)
Delay, subsequent bits valid on
SPI0_SIMO after transmit edge of
SPI0_CLK
Output hold time, SPI0_SIMO valid
afterreceive edge of SPI0_CLK
Input Setup Time, SPI0_SOMI valid
beforereceive edge of SPI0_CLK
Input Hold Time, SPI0_SOMI valid after
receive edge of SPI0_CLK
256P
Polarity = 0, Phase = 0,
to SPI0_CLK rising
5
Polarity = 0, Phase = 1,
to SPI0_CLK rising
- 0.5tc(SPC)M + 5
Polarity = 1, Phase = 0,
to SPI0_CLK falling
5
Polarity = 1, Phase = 1,
to SPI0_CLK falling
- 0.5tc(SPC)M + 5
Polarity = 0, Phase = 0,
from SPI0_CLK rising
5
Polarity = 0, Phase = 1,
from SPI0_CLK falling
5
Polarity = 1, Phase = 0,
from SPI0_CLK falling
5
Polarity = 1, Phase = 1,
from SPI0_CLK rising
5
ns
ns
ns
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5tc(SPC)M -3
Polarity = 0, Phase = 1,
from SPI0_CLK rising
0.5tc(SPC)M -3
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5tc(SPC)M -3
Polarity = 1, Phase = 1,
from SPI0_CLK falling
0.5tc(SPC)M -3
ns
Polarity = 0, Phase = 0,
to SPI0_CLK falling
0
Polarity = 0, Phase = 1,
to SPI0_CLK rising
0
Polarity = 1, Phase = 0,
to SPI0_CLK rising
0
Polarity = 1, Phase = 1,
to SPI0_CLK falling
0
Polarity = 0, Phase = 0,
from SPI0_CLK falling
5
Polarity = 0, Phase = 1,
from SPI0_CLK rising
5
Polarity = 1, Phase = 0,
from SPI0_CLK rising
5
Polarity = 1, Phase = 1,
from SPI0_CLK falling
5
ns
ns
P = SYSCLK2 period
First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on
SPI0_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPI0_SOMI.
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Table 6-50. General Timing Requirements for SPI0 Slave Modes (1)
PARAMETER
MIN
greater of 2P or
20 ns
MAX
UNIT
256P
ns
9
tc(SPC)S
Cycle Time, SPI0_CLK, All Slave Modes
10
tw(SPCH)S
Pulse Width High, SPI0_CLK, All Slave Modes
18
ns
11
tw(SPCL)S
Pulse Width Low, SPI0_CLK, All Slave Modes
18
ns
12
13
14
15
16
(1)
(2)
(3)
tsu(SOMI_SPC)S
td(SPC_SOMI)S
toh(SPC_SOMI)S
tsu(SIMO_SPC)S
tih(SPC_SIMO)S
Setup time, transmit data written to SPI
before initial clock edge from master. (2)
(3)
Delay, subsequent bits valid on
SPI0_SOMI after transmit edge of
SPI0_CLK
Output hold time, SPI0_SOMI valid afte
receive edge of SPI0_CLK
Input Setup Time, SPI0_SIMO valid
before receive edge of SPI0_CLK
Input Hold Time, SPI0_SIMO valid after
receive edge of SPI0_CLK
Polarity = 0, Phase = 0,
to SPI0_CLK rising
2P
Polarity = 0, Phase = 1,
to SPI0_CLK rising
2P
Polarity = 1, Phase = 0,
to SPI0_CLK falling
2P
Polarity = 1, Phase = 1,
to SPI0_CLK falling
2P
ns
Polarity = 0, Phase = 0,
from SPI0_CLK rising
18.5
Polarity = 0, Phase = 1,
from SPI0_CLK falling
18.5
Polarity = 1, Phase = 0,
from SPI0_CLK falling
18.5
Polarity = 1, Phase = 1,
from SPI0_CLK rising
18.5
ns
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5tc(SPC)S -3
Polarity = 0, Phase = 1,
from SPI0_CLK rising
0.5tc(SPC)S -3
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5tc(SPC)S -3
Polarity = 1, Phase = 1,
from SPI0_CLK falling
0.5tc(SPC)S -3
ADVANCE INFORMATION
No.
ns
Polarity = 0, Phase = 0,
to SPI0_CLK falling
0
Polarity = 0, Phase = 1,
to SPI0_CLK rising
0
Polarity = 1, Phase = 0,
to SPI0_CLK rising
0
Polarity = 1, Phase = 1,
to SPI0_CLK falling
0
Polarity = 0, Phase = 0,
from SPI0_CLK falling
5
Polarity = 0, Phase = 1,
from SPI0_CLK rising
5
Polarity = 1, Phase = 0,
from SPI0_CLK rising
5
Polarity = 1, Phase = 1,
from SPI0_CLK falling
5
ns
ns
P = SYSCLK2 period
First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on
SPI0_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI0_SIMO.
Measured from the termination of the write of new data to the SPI module, In analyzing throughput requirements, additional internal bus
cycles must be accounted for to allow data to be written to the SPI module by the CPU.
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Table 6-51. Additional (1) SPI0 Master Timings, 4-Pin Enable Option (2)
No.
17
18
ADVANCE INFORMATION
(1)
(2)
(3)
(4)
(5)
PARAMETER
td(ENA_SPC)M
td(SPC_ENA)M
Delay from slave assertion of
SPI0_ENA active to first SPI0_CLK
from master. (4)
Max delay for slave to deassert
SPI0_ENA after final SPI0_CLK edge
to ensure master does not begin the
next transfer. (5)
(3)
MIN
MAX
Polarity = 0, Phase = 0,
to SPI0_CLK rising
3P + 3
Polarity = 0, Phase = 1,
to SPI0_CLK rising
0.5tc(SPC)M + 3P + 3
Polarity = 1, Phase = 0,
to SPI0_CLK falling
3P + 3
Polarity = 1, Phase = 1,
to SPI0_CLK falling
0.5tc(SPC)M + 3P + 3
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5tc(SPC)M + P + 5
Polarity = 0, Phase = 1,
from SPI0_CLK falling
P+5
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5tc(SPC)M + P + 5
Polarity = 1, Phase = 1,
from SPI0_CLK rising
P+5
ns
ns
These parameters are in addition to the general timings for SPI master modes ( Table 6-49 ).
P = SYSCLK2 period
Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
In the case where the master SPI is ready with new data before SPI0_ENA assertion.
In the case where the master SPI is ready with new data before SPI0_EN A deassertion.
Table 6-52. Additional (1) SPI0 Master Timings, 4-Pin Chip Select Option (2)
No.
19
20
(1)
(2)
(3)
(4)
(5)
(6)
(7)
98
UNIT
PARAMETER
td(SCS_SPC)M
td(SPC_SCS)M
Delay from SPI0_SCS active to first
SPI0_CLK (4) (5)
Delay from final SPI0_CLK edge to
master deasserting SPI0_SCS (6) (7)
MIN
(3)
MAX
Polarity = 0, Phase = 0,
to SPI0_CLK rising
2P - 5
Polarity = 0, Phase = 1,
to SPI0_CLK rising
0.5tc(SPC)M + 2P - 5
Polarity = 1, Phase = 0,
to SPI0_CLK falling
2P - 5
Polarity = 1, Phase = 1,
to SPI0_CLK falling
0.5tc(SPC)M + 2P - 5
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5tc(SPC)M + P - 3
Polarity = 0, Phase = 1,
from SPI0_CLK falling
P-3
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5tc(SPC)M + P - 3
Polarity = 1, Phase = 1,
from SPI0_CLK rising
P-3
UNIT
ns
ns
These parameters are in addition to the general timings for SPI master modes ( Table 6-49 ).
P = SYSCLK2 period
Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
In the case where the master SPI is ready with new data before SPI0_SCS assertion.
This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI0_SCS will remain
asserted.
This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
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Table 6-53. Additional (1) SPI0 Master Timings, 5-Pin Option (2)
No.
18
20
21
22
23
PARAMETER
td(SPC_ENA)M
td(SPC_SCS)M
Max delay for slave to
deassert SPI0_ENA after
final SPI0_CLK edge to
ensure master does not
begin the next transfer. (4)
Delay from final
SPI0_CLK edge to
master deasserting
SPI0_SCS (5) (6)
MIN
MAX
td(SCS_SPC)M
td(ENA_SPC)M
Delay from assertion of
SPI0_ENA low to first
SPI0_CLK edge. (10)
UNIT
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5tc(SPC)M + P + 5
Polarity = 0, Phase = 1,
from SPI0_CLK falling
P+5
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5tc(SPC)M + P + 5
Polarity = 1, Phase = 1,
from SPI0_CLK rising
P+5
ns
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5tc(SPC)M + P - 3
Polarity = 0, Phase = 1,
from SPI0_CLK falling
P-3
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5tc(SPC)M + P -3
Polarity = 1, Phase = 1,
from SPI0_CLK rising
P-3
ns
Max delay for slave SPI to drive SPI0_ENA valid
td(SCSL_ENAL)M after master asserts SPI0_SCS to delay the
master from beginning the next transfer,
Delay from SPI0_SCS
active to first
SPI0_CLK (7) (8) (9)
(3)
C2TDELAY + P
Polarity = 0, Phase = 0,
to SPI0_CLK rising
2P -5
Polarity = 0, Phase = 1,
to SPI0_CLK rising
0.5tc(SPC)M + 2P -5
Polarity = 1, Phase = 0,
to SPI0_CLK falling
2P -5
Polarity = 1, Phase = 1,
to SPI0_CLK falling
0.5tc(SPC)M + 2P -5
ns
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ns
Polarity = 0, Phase = 0,
to SPI0_CLK rising
3P + 3
Polarity = 0, Phase = 1,
to SPI0_CLK rising
0.5tc(SPC)M + 3P + 3
Polarity = 1, Phase = 0,
to SPI0_CLK falling
3P + 3
Polarity = 1, Phase = 1,
to SPI0_CLK falling
0.5tc(SPC)M + 3P + 3
ns
(1)
(2)
(3)
(4)
(5)
These parameters are in addition to the general timings for SPI master modes ( Table 6-50 ).
P = SYSCLK2 period
Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
In the case where the master SPI is ready with new data before SPI0_ENA deassertion.
Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI0_SCS will remain
asserted.
(6) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
(7) If SPI0_ENA is asserted immediately such that the transmission is not delayed by SPI0_ENA.
(8) In the case where the master SPI is ready with new data before SPI0_SCS assertion.
(9) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
(10) If SPI0_ENA was initially deasserted high and SPI0_CLK is delayed.
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Table 6-54. Additional (1) SPI0 Slave Timings, 4-Pin Enable Option (2)
No.
24
(1)
(2)
(3)
PARAMETER
td(SPC_ENAH)S
Delay from final
SPI0_CLK edge
to slave
deasserting
SPI0_ENA.
MIN
(3)
MAX
UNIT
Polarity = 0, Phase = 0,
from SPI0_CLK falling
1.5 P -3
2.5 P + 18.5
Polarity = 0, Phase = 1,
from SPI0_CLK falling
– 0.5tc(SPC)M + 1.5 P -3
– 0.5tc(SPC)M + 2.5 P + 18.5
Polarity = 1, Phase = 0,
from SPI0_CLK rising
1.5 P -3
2.5 P + 18.5
Polarity = 1, Phase = 1,
from SPI0_CLK rising
– 0.5tc(SPC)M + 1.5 P -3
– 0.5tc(SPC)M + 2.5 P + 18.5
ns
These parameters are in addition to the general timings for SPI slave modes ( Table 6-50 ).
P = SYSCLK2 period
Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
Table 6-55. Additional (1) SPI0 Slave Timings, 4-Pin Chip Select Option (2)
No.
25
ADVANCE INFORMATION
26
PARAMETER
td(SCSL_SPC)S
td(SPC_SCSH)S
MIN
Required delay from SPI0_SCS asserted at slave to first
SPI0_CLK edge at slave.
Required delay from final
SPI0_CLK edge before SPI0_SCS
is deasserted.
(3)
MAX
P
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5tc(SPC)M + P+5
Polarity = 0, Phase = 1,
from SPI0_CLK falling
P+5
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5tc(SPC)M + P+5
Polarity = 1, Phase = 1,
from SPI0_CLK rising
P+5
UNIT
ns
ns
27
tena(SCSL_SOMI)S
Delay from master asserting SPI0_SCS to slave driving
SPI0_SOMI valid
P + 18.5
ns
28
tdis(SCSH_SOMI)S
Delay from master deasserting SPI0_SCS to slave 3-stating
SPI0_SOMI
P + 18.5
ns
(1)
(2)
(3)
100
These parameters are in addition to the general timings for SPI slave modes ( Table 6-50 ).
P = SYSCLK2 period
Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
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Table 6-56. Additional (1) SPI0 Slave Timings, 5-Pin Option (2)
No.
25
26
PARAMETER
td(SCSL_SPC)S
td(SPC_SCSH)S
(3)
MIN
Required delay from SPI0_SCS asserted at slave to first
SPI0_CLK edge at slave.
Required delay from final
SPI0_CLK edge before
SPI0_SCS is deasserted.
MAX
UNIT
P
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5tc(SPC)M + P + 5
Polarity = 0, Phase = 1,
from SPI0_CLK falling
P+5
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5tc(SPC)M + P + 5
Polarity = 1, Phase = 1,
from SPI0_CLK rising
P+5
ns
ns
27
tena(SCSL_SOMI)S
Delay from master asserting SPI0_SCS to slave driving
SPI0_SOMI valid
P + 18.5
ns
28
tdis(SCSH_SOMI)S
Delay from master deasserting SPI0_SCS to slave
3-stating SPI0_SOMI
P + 18.5
ns
29
tena(SCSL_ENA)S
Delay from master deasserting SPI0_SCS to slave driving
SPI0_ENA valid
18.5
ns
30
(1)
(2)
(3)
(4)
tdis(SPC_ENA)S
Delay from final clock receive
edge on SPI0_CLK to slave
3-stating or driving high
SPI0_ENA. (4)
Polarity = 0, Phase = 0,
from SPI0_CLK falling
2.5 P + 18.5
Polarity = 0, Phase = 1,
from SPI0_CLK rising
2.5 P + 18.5
Polarity = 1, Phase = 0,
from SPI0_CLK rising
2.5 P + 18.5
Polarity = 1, Phase = 1,
from SPI0_CLK falling
2.5 P + 18.5
ns
These parameters are in addition to the general timings for SPI slave modes ( Table 6-50 ).
P = SYSCLK2 period
Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
SPI0_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is
3-stated. If 3-stated, an external pullup resistor should be used to provide a valid level to the master. This option is useful when tying
several SPI slave devices to a single master.
Table 6-57. General Timing Requirements for SPI1 Master Modes (1)
No.
MIN
UNIT
Cycle Time, SPI1_CLK, All Master Modes
2
tw(SPCH)M
Pulse Width High, SPI1_CLK, All Master Modes
0.5tc(SPC)M - 1
ns
3
tw(SPCL)M
Pulse Width Low, SPI1_CLK, All Master Modes
0.5tc(SPC)M - 1
ns
5
td(SIMO_SPC)M
td(SPC_SIMO)M
Delay, initial data bit valid on
SPI1_SIMO to initial edge on
SPI1_CLK (2)
Delay, subsequent bits valid
on SPI1_SIMO after transmit
edge of SPI1_CLK
greater of 2P or 20 ns
MAX
tc(SPC)M
4
(1)
(2)
PARAMETER
1
256P
Polarity = 0, Phase = 0,
to SPI1_CLK rising
5
Polarity = 0, Phase = 1,
to SPI1_CLK rising
- 0.5tc(SPC)M + 5
Polarity = 1, Phase = 0,
to SPI1_CLK falling
5
Polarity = 1, Phase = 1,
to SPI1_CLK falling
- 0.5tc(SPC)M + 5
Polarity = 0, Phase = 0,
from SPI1_CLK rising
5
Polarity = 0, Phase = 1,
from SPI1_CLK falling
5
Polarity = 1, Phase = 0,
from SPI1_CLK falling
5
Polarity = 1, Phase = 1,
from SPI1_CLK rising
5
ns
ns
ns
P = SYSCLK2 period
First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on
SPI1_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPI1_SOMI.
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Table 6-57. General Timing Requirements for SPI1 Master Modes
No.
PARAMETER
toh(SPC_SIMO)M
tsu(SOMI_SPC)M
Polarity = 0, Phase = 1,
Output hold time, SPI1_SIMO from SPI1_CLK rising
valid after
Polarity = 1, Phase = 0,
receive edge of SPI1_CLK
from SPI1_CLK rising
ADVANCE INFORMATION
8
tih(SPC_SOMI)M
Input Setup Time,
SPI1_SOMI valid before
receive edge of SPI1_CLK
Input Hold Time, SPI1_SOMI
valid after receive edge of
SPI1_CLK
MAX
UNIT
0.5tc(SPC)M -3
0.5tc(SPC)M -3
ns
0.5tc(SPC)M -3
Polarity = 1, Phase = 1,
from SPI1_CLK falling
7
(continued)
MIN
Polarity = 0, Phase = 0,
from SPI1_CLK falling
6
(1)
0.5tc(SPC)M -3
Polarity = 0, Phase = 0,
to SPI1_CLK falling
0
Polarity = 0, Phase = 1,
to SPI1_CLK rising
0
Polarity = 1, Phase = 0,
to SPI1_CLK rising
0
Polarity = 1, Phase = 1,
to SPI1_CLK falling
0
Polarity = 0, Phase = 0,
from SPI1_CLK falling
5
Polarity = 0, Phase = 1,
from SPI1_CLK rising
5
Polarity = 1, Phase = 0,
from SPI1_CLK rising
5
Polarity = 1, Phase = 1,
from SPI1_CLK falling
5
ns
ns
Table 6-58. General Timing Requirements for SPI1 Slave Modes (1)
No.
PARAMETER
MIN
MAX
UNIT
greater of 2P or 20 ns
256P
ns
9
tc(SPC)S
Cycle Time, SPI1_CLK, All Slave Modes
10
tw(SPCH)S
Pulse Width High, SPI1_CLK, All Slave Modes
18
ns
11
tw(SPCL)S
Pulse Width Low, SPI1_CLK, All Slave Modes
18
ns
12
13
(1)
(2)
(3)
102
tsu(SOMI_SPC)S
td(SPC_SOMI)S
Setup time, transmit data
written to SPI before initial
clock edge from
master. (2) (3)
Delay, subsequent bits valid
on SPI1_SOMI after transmit
edge of SPI1_CLK
Polarity = 0, Phase = 0,
to SPI1_CLK rising
2P
Polarity = 0, Phase = 1,
to SPI1_CLK rising
2P
Polarity = 1, Phase = 0,
to SPI1_CLK falling
2P
Polarity = 1, Phase = 1,
to SPI1_CLK falling
2P
ns
Polarity = 0, Phase = 0,
from SPI1_CLK rising
19
Polarity = 0, Phase = 1,
from SPI1_CLK falling
19
Polarity = 1, Phase = 0,
from SPI1_CLK falling
19
Polarity = 1, Phase = 1,
from SPI1_CLK rising
19
ns
P = SYSCLK2 period
First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on
SPI1_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI1_SIMO.
Measured from the termination of the write of new data to the SPI module, In analyzing throughput requirements, additional internal bus
cycles must be accounted for to allow data to be written to the SPI module by the CPU.
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Table 6-58. General Timing Requirements for SPI1 Slave Modes
No.
PARAMETER
toh(SPC_SOMI)S
Polarity = 0, Phase = 1,
Output hold time, SPI1_SOMI from SPI1_CLK rising
valid after receive edge of
Polarity = 1, Phase = 0,
SPI1_CLK
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK falling
15
16
tsu(SIMO_SPC)S
tih(SPC_SIMO)S
(continued)
MIN
Polarity = 0, Phase = 0,
from SPI1_CLK falling
14
(1)
Input Setup Time,
SPI1_SIMO valid before
receive edge of SPI1_CLK
Input Hold Time, SPI1_SIMO
valid after receive edge of
SPI1_CLK
MAX
0.5tc(SPC)S -3
0.5tc(SPC)S -3
ns
0.5tc(SPC)S -3
0.5tc(SPC)S -3
Polarity = 0, Phase = 0,
to SPI1_CLK falling
0
Polarity = 0, Phase = 1,
to SPI1_CLK rising
0
Polarity = 1, Phase = 0,
to SPI1_CLK rising
0
Polarity = 1, Phase = 1,
to SPI1_CLK falling
0
Polarity = 0, Phase = 0,
from SPI1_CLK falling
5
Polarity = 0, Phase = 1,
from SPI1_CLK rising
5
Polarity = 1, Phase = 0,
from SPI1_CLK rising
5
Polarity = 1, Phase = 1,
from SPI1_CLK falling
5
ns
ns
Table 6-59. Additional (1) SPI1 Master Timings, 4-Pin Enable Option (2)
No.
17
18
(1)
(2)
(3)
(4)
(5)
PARAMETER
td(EN
A_SPC)M
td(SPC_ENA)M
Delay from slave assertion of SPI1_ENA
active to first SPI1_CLK from master. (4)
Max delay for slave to deassert
SPI1_ENA after final SPI1_CLK edge to
ensure master does not begin the next
transfer. (5)
UNIT
MIN
(3)
MAX
UNIT
Polarity = 0, Phase = 0,
to SPI1_CLK rising
3P + 3
Polarity = 0, Phase = 1,
to SPI1_CLK rising
0.5tc(SPC)M + 3P + 3
Polarity = 1, Phase = 0,
to SPI1_CLK falling
3P + 3
Polarity = 1, Phase = 1,
to SPI1_CLK falling
0.5tc(SPC)M + 3P + 3
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5tc(SPC)M + P + 5
Polarity = 0, Phase = 1,
from SPI1_CLK falling
P+5
Polarity = 1, Phase = 0,
from SPI1_CLK rising
0.5tc(SPC)M + P + 5
Polarity = 1, Phase = 1,
from SPI1_CLK rising
P+5
ns
ns
These parameters are in addition to the general timings for SPI master modes ( Table 6-57 ).
P = SYSCLK2 period
Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
In the case where the master SPI is ready with new data before SPI1_ENA assertion.
In the case where the master SPI is ready with new data before SPI1_ENA deassertion.
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Table 6-60. Additional (1) SPI1 Master Timings, 4-Pin Chip Select Option (2)
No.
19
ADVANCE INFORMATION
20
(1)
(2)
(3)
(4)
(5)
(6)
(7)
PARAMETER
td(SCS_SPC)M
td(SPC_SCS)M
Delay from SPI1_SCS active to first
SPI1_CLK (4) (5)
Delay from final SPI1_CLK edge to master
deasserting SPI1_SCS (6) (7)
MIN
2P -5
Polarity = 0, Phase =
1,
to SPI1_CLK rising
0.5tc(SPC)M + 2P -5
Polarity = 1, Phase =
0,
to SPI1_CLK falling
2P -5
Polarity = 1, Phase =
1,
to SPI1_CLK falling
0.5tc(SPC)M + 2P -5
Polarity = 0, Phase =
0,
from SPI1_CLK
falling
0.5tc(SPC)M + P - 3
Polarity = 0, Phase =
1,
from SPI1_CLK
falling
P-3
Polarity = 1, Phase =
0,
from SPI1_CLK rising
0.5tc(SPC)M + P -3
Polarity = 1, Phase =
1,
from SPI1_CLK rising
P-3
18
20
104
UNIT
ns
ns
These parameters are in addition to the general timings for SPI master modes ( Table 6-57 ).
P = SYSCLK2 period
Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
In the case where the master SPI is ready with new data before SPI1_SCS assertion.
This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI1_SCS will remain
asserted.
This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
No.
(6)
MAX
Polarity = 0, Phase =
0,
to SPI1_CLK rising
Table 6-61. Additional (1) SPI1 Master Timings, 5-Pin Option (2)
(1)
(2)
(3)
(4)
(5)
(3)
PARAMETER
td(SPC_ENA)M
td(SPC_SCS)M
MIN
MAX
Polarity = 0, Phase = 0,
Max delay for slave to from SPI1_CLK falling
deassert SPI1_ENA
Polarity = 0, Phase = 1,
after final SPI1_CLK
from SPI1_CLK falling
edge to ensure
Polarity = 1, Phase = 0,
master does not
from SPI1_CLK rising
begin the next
transfer. (4)
Polarity = 1, Phase = 1,
from SPI1_CLK rising
Delay from final
SPI1_CLK edge to
master deasserting
SPI1_SCS (5) (6)
(3)
UNIT
0.5tc(SPC)M+P+5
P+5
ns
0.5tc(SPC)M+P+5
P+5
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5tc(SPC)M + P -3
Polarity = 0, Phase = 1,
from SPI1_CLK falling
P-3
Polarity = 1, Phase = 0,
from SPI1_CLK rising
0.5tc(SPC)M+ P -3
Polarity = 1, Phase = 1,
from SPI1_CLK rising
P-3
ns
These parameters are in addition to the general timings for SPI master modes ( Table 6-58 ).
P = SYSCLK2 period
Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
In the case where the master SPI is ready with new data before SPI1_ENA deassertion.
Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI1_SCS will remain
asserted.
This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
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No.
21
22
(7)
(8)
(9)
(10)
(2) (3)
SPI1 Master Timings, 5-Pin Option
PARAMETER
(continued)
MIN
MAX
Max delay for slave SPI to drive SPI1_ENA
valid after master asserts SPI1_SCS to delay
the master from beginning the next transfer.
td(SCSL_ENAL)M
Delay from
SPI1_SCS active to
first SPI1_CLK (7) (8)
td(SCS_SPC)M
(9)
23
(1)
Delay from assertion
of SPI1_ENA low to
first SPI1_CLK
edge. (10)
td(ENA_SPC)M
C2TDELAY + P
Polarity = 0, Phase = 0,
to SPI1_CLK rising
2P -5
Polarity = 0, Phase = 1,
to SPI1_CLK rising
0.5tc(SPC)M + 2P -5
Polarity = 1, Phase = 0,
to SPI1_CLK falling
2P -5
Polarity = 1, Phase = 1,
to SPI1_CLK falling
0.5tc(SPC)M + 2P -5
Polarity = 0, Phase = 0,
to SPI1_CLK rising
3P + 3
Polarity = 0, Phase = 1,
to SPI1_CLK rising
0.5tc(SPC)M + 3P + 3
Polarity = 1, Phase = 0,
to SPI1_CLK falling
3P + 3
Polarity = 1, Phase = 1,
to SPI1_CLK falling
0.5tc(SPC)M + 3P + 3
ns
If SPI1_ENA is asserted immediately such that the transmission is not delayed by SPI1_ENA.
In the case where the master SPI is ready with new data before SPI1_SCS assertion.
This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
If SPI1_ENA was initially deasserted high and SPI1_CLK is delayed.
No.
24
PARAMETER
td(SPC_ENAH)S
Delay from
final
SPI1_CLK
edge to slave
deasserting
SPI1_ENA.
MIN
(3)
MAX
UNIT
Polarity = 0, Phase = 0,
from SPI1_CLK falling
1.5 P -3
2.5 P + 19
Polarity = 0, Phase = 1,
from SPI1_CLK falling
– 0.5tc(SPC)M + 1.5 P -3
– 0.5tc(SPC)M + 2.5 P + 19
Polarity = 1, Phase = 0,
from SPI1_CLK rising
1.5 P -3
2.5 P + 19
Polarity = 1, Phase = 1,
from SPI1_CLK rising
– 0.5tc(SPC)M + 1.5 P -3
– 0.5tc(SPC)M + 2.5 P + 19
ns
These parameters are in addition to the general timings for SPI slave modes ( Table 6-58 ).
P = SYSCLK2 period
Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
Table 6-63. Additional (1) SPI1 Slave Timings, 4-Pin Chip Select Option (2)
No.
25
26
27
(1)
(2)
(3)
ns
ns
Table 6-62. Additional (1) SPI1 Slave Timings, 4-Pin Enable Option (2)
(1)
(2)
(3)
UNIT
PARAMETER
td(SCSL_SPC)S
td(SPC_SCSH)S
tena(SCSL_SOMI)S
MIN
Required delay from SPI1_SCS asserted at slave to first
SPI1_CLK edge at slave.
Required delay from final
SPI1_CLK edge before
SPI1_SCS is deasserted.
(3)
MAX
UNIT
P
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5tc(SPC)M + P + 5
Polarity = 0, Phase = 1,
from SPI1_CLK falling
P+5
Polarity = 1, Phase = 0,
from SPI1_CLK rising
0.5tc(SPC)M + P + 5
Polarity = 1, Phase = 1,
from SPI1_CLK rising
P+5
ns
ns
Delay from master asserting SPI1_SCS to slave driving
SPI1_SOMI valid
P + 19
ns
These parameters are in addition to the general timings for SPI slave modes ( Table 6-58 ).
P = SYSCLK2 period
Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
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Table 6-61. Additional
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Table 6-63. Additional
No.
28
(1)
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SPI1 Slave Timings, 4-Pin Chip Select Option
PARAMETER
tdis(SCSH_SOMI)S
(2) (3)
MIN
MAX
Delay from master deasserting SPI1_SCS to slave
3-stating SPI1_SOMI
25
26
PARAMETER
td(SCSL_SPC)S
td(SPC_SCSH)S
MIN
Required delay from SPI1_SCS asserted at slave to
first SPI1_CLK edge at slave.
Required delay from final
SPI1_CLK edge before
SPI1_SCS is deasserted.
UNIT
P + 19
Table 6-64. Additional (1) SPI1 Slave Timings, 5-Pin Option (2)
No.
(continued)
(3)
MAX
UNIT
P
Polarity = 0, Phase = 0,
from SPI1_CLK falling
0.5tc(SPC)M + P + 5
Polarity = 0, Phase = 1,
from SPI1_CLK falling
P+5
Polarity = 1, Phase = 0,
from SPI1_CLK rising
0.5tc(SPC)M + P + 5
Polarity = 1, Phase = 1,
from SPI1_CLK rising
P+5
ns
ns
ns
ADVANCE INFORMATION
27
tena(SCSL_SOMI)S
Delay from master asserting SPI1_SCS to slave
driving SPI1_SOMI valid
P + 19
ns
28
tdis(SCSH_SOMI)S
Delay from master deasserting SPI1_SCS to slave
3-stating SPI1_SOMI
P + 19
ns
29
tena(SCSL_ENA)S
Delay from master deasserting SPI1_SCS to slave
driving SPI1_ENA valid
19
ns
30
(1)
(2)
(3)
(4)
106
tdis(SPC_ENA)S
Delay from final clock
receive edge on SPI1_CLK
to slave 3-stating or driving
high SPI1_ENA. (4)
Polarity = 0, Phase = 0,
from SPI1_CLK falling
2.5 P + 19
Polarity = 0, Phase = 1,
from SPI1_CLK rising
2.5 P + 19
Polarity = 1, Phase = 0,
from SPI1_CLK rising
2.5 P + 19
Polarity = 1, Phase = 1,
from SPI1_CLK falling
2.5 P + 19
ns
These parameters are in addition to the general timings for SPI slave modes ( Table 6-58 ).
P = SYSCLK2 period
Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
SPI1_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is
3-stated. If 3-stated, an external pullup resistor should be used to provide a valid level to the master. This option is useful when tying
several SPI slave devices to a single master.
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1
2
MASTER MODE
POLARITY = 0 PHASE = 0
3
SPIx_CLK
5
4
SPIx_SIMO
MO(0)
7
SPIx_SOMI
6
MO(1)
MO(n−1)
MO(n)
8
MI(0)
MI(1)
MI(n−1)
MI(n)
MASTER MODE
POLARITY = 0 PHASE = 1
4
SPIx_CLK
6
MO(0)
7
SPIx_SOMI
MO(1)
MO(n−1)
MI(1)
MI(n−1)
MO(n)
ADVANCE INFORMATION
5
SPIx_SIMO
8
MI(0)
MI(n)
4
MASTER MODE
POLARITY = 1 PHASE = 0
SPIx_CLK
5
SPIx_SIMO
6
MO(0)
7
SPIx_SOMI
MO(1)
MO(n−1)
MO(n)
8
MI(0)
MI(1)
MI(n−1)
MI(n)
MASTER MODE
POLARITY = 1 PHASE = 1
SPIx_CLK
5
4
SPIx_SIMO
MO(0)
7
SPIx_SOMI
MI(0)
6
MO(1)
MO(n−1)
MI(1)
MI(n−1)
MO(n)
8
MI(n)
Figure 6-31. SPI Timings—Master Mode
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9
12
10
SLAVE MODE
POLARITY = 0 PHASE = 0
11
SPIx_CLK
15
SPIx_SIMO
16
SI(0)
SI(1)
SI(n−1)
13
SPIx_SOMI
SO(0)
SI(n)
14
SO(1)
SO(n−1)
12
SO(n)
SLAVE MODE
POLARITY = 0 PHASE = 1
SPIx_CLK
15
16
ADVANCE INFORMATION
SPIx_SIMO
SI(0)
SPIx_SOMI
SO(0)
SI(1)
13
SI(n−1)
SI(n)
SO(n−1)
SO(n)
14
SO(1)
SLAVE MODE
POLARITY = 1 PHASE = 0
12
SPIx_CLK
15
SPIx_SIMO
16
SI(0)
SI(1)
SI(n−1)
13
SPIx_SOMI
SO(0)
SO(1)
SI(n)
14
SO(n−1)
SO(n)
SLAVE MODE
POLARITY = 1 PHASE = 1
12
SPIx_CLK
15
16
SPIx_SIMO
SI(0)
SPIx_SOMI
SO(0)
SI(1)
13
SI(n−1)
SI(n)
14
SO(1)
SO(n−1)
SO(n)
Figure 6-32. SPI Timings—Slave Mode
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MASTER MODE 4 PIN WITH ENABLE
17
18
SPIx_CLK
SPIx_SIMO
MO(0)
SPIx_SOMI
MI(0)
MO(1)
MO(n−1)
MI(1)
MI(n−1)
MO(n)
MI(n)
SPIx_ENA
MASTER MODE 4 PIN WITH CHIP SELECT
19
20
SPIx_CLK
SPIx_SIMO
MO(0)
SPIx_SOMI
MI(0)
MO(1)
MO(n−1)
MO(n)
MI(1)
MI(n−1)
MI(n)
SPIx_SCS
MASTER MODE 5 PIN
20
ADVANCE INFORMATION
22
MO(1)
23
18
SPIx_CLK
SPIx_SIMO
MO(0)
MO(n−1)
MO(n)
SPIx_SOMI
21
SPIx_ENA
MI(0)
MI(1)
MI(n−1)
MI(n)
DESEL(A)
DESEL(A)
SPIx_SCS
A. DESELECTED IS PROGRAMMABLE EITHER HIGH OR
3−STATE (REQUIRES EXTERNAL PULLUP)
Figure 6-33. SPI Timings—Master Mode (4-Pin and 5-Pin)
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SLAVE MODE 4 PIN WITH ENABLE
24
SPIx_CLK
SPIx_SOMI
SO(0)
SO(1)
SO(n−1)
SO(n)
SPIx_SIMO
SI(0)
SPIx_ENA
SI(1)
SI(n−1) SI(n)
SLAVE MODE 4 PIN WITH CHIP SELECT
26
25
SPIx_CLK
27
SPIx_SOMI
28
SO(n−1)
SO(0)
SO(1)
SO(n)
SPIx_SIMO
SI(0)
SPIx_SCS
SI(1)
SI(n−1)
SI(n)
ADVANCE INFORMATION
SLAVE MODE 5 PIN
26
30
25
SPIx_CLK
27
SPIx_SOMI
28
SO(1)
SO(0)
SO(n−1)
SO(n)
SPIx_SIMO
29
SPIx_ENA
SI(0)
SI(1)
SI(n−1)
SI(n)
DESEL(A)
DESEL(A)
SPIx_SCS
A. DESELECTED IS PROGRAMMABLE EITHER HIGH OR
3−STATE (REQUIRES EXTERNAL PULLUP)
Figure 6-34. SPI Timings—Slave Mode (4-Pin and 5-Pin)
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6.19 Enhanced Capture (eCAP) Peripheral
The device contains up to three enhanced capture (eCAP) modules. Figure 6-35 shows a functional block
diagram of a module.
Uses for ECAP include:
• Speed measurements of rotating machinery (e.g. toothed sprockets sensed via Hall sensors)
• Elapsed time measurements between position sensor triggers
• Period and duty cycle measurements of Pulse train signals
• Decoding current or voltage amplitude derived from cuty cycle encoded current/voltage sensors
ADVANCE INFORMATION
The ECAP module described in this specification includes the following features:
• 32 bit time base
• 4 event time-stamp registers (each 32 bits)
• Edge polarity selection for up to 4 sequenced time-stamp capture events
• Interrupt on either of the 4 events
• Single shot capture of up to 4 event time-stamps
• Continuous mode capture of time-stamps in a 4 deep circular buffer
• Absolute time-stamp capture
• Difference mode time-stamp capture
• All the above resources are dedicated to a single input pin
The eCAP modules are clocked at the SYSCLK2 rate.
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SYNCIn
SYNCOut
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CTRPHS
(phase register−32 bit)
TSCTR
(counter−32 bit)
APWM mode
OVF
RST
CTR_OVF
Delta−mode
CTR [0−31]
PWM
compare
logic
PRD [0−31]
CMP [0−31]
32
CTR=PRD
CTR [0−31]
CTR=CMP
32
32
LD1
CAP1
(APRD active)
APRD
shadow
32
ADVANCE INFORMATION
32
MODE SELECT
PRD [0−31]
Polarity
select
LD
32
CMP [0−31]
CAP2
(ACMP active)
32
LD
LD2
Polarity
select
Event
qualifier
ACMP
shadow
32
CAP3
(APRD shadow)
LD
32
CAP4
(ACMP shadow)
LD
eCAPx
Event
Pre-scale
Polarity
select
LD3
LD4
Polarity
select
4
Capture events
4
CEVT[1:4]
to Interrupt
Controller
Interrupt
Trigger
and
Flag
control
CTR_OVF
Continuous /
Oneshot
Capture Control
CTR=PRD
CTR=CMP
Figure 6-35. eCAP Functional Block Diagram
Table 6-65 is the list of the ECAP registers.
112
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Table 6-65. ECAPx Configuration Registers
ECAP0
BYTE ADDRESS
ECAP1
BYTE ADDRESS
ECAP2
BYTE ADDRESS
ACRONYM
0x01F0 6000
0x01F0 7000
0x01F0 8000
TSCTR
0x01F0 6004
0x01F0 7004
0x01F0 8004
CTRPHS
0x01F0 6008
0x01F0 7008
0x01F0 8008
CAP1
Capture 1 Register
0x01F0 600C
0x01F0 700C
0x01F0 800C
CAP2
Capture 2 Register
0x01F0 6010
0x01F0 7010
0x01F0 8010
CAP3
Capture 3 Register
0x01F0 6014
0x01F0 7014
0x01F0 8014
CAP4
Capture 4 Register
0x01F0 6028
0x01F0 7028
0x01F0 8028
ECCTL1
Capture Control Register 1
0x01F0 602A
0x01F0 702A
0x01F0 802A
ECCTL2
Capture Control Register 2
0x01F0 602C
0x01F0 702C
0x01F0 802C
ECEINT
Capture Interrupt Enable Register
0x01F0 602E
0x01F0 702E
0x01F0 802E
ECFLG
Capture Interrupt Flag Register
0x01F0 6030
0x01F0 7030
0x01F0 8030
ECCLR
Capture Interrupt Clear Register
REGISTER DESCRIPTION
Time-Stamp Counter
0x01F0 6032
0x01F0 7032
0x01F0 8032
ECFRC
Capture Interrupt Force Register
0x01F0 605C
0x01F0 705C
0x01F0 805C
REVID
Revision ID
Table 6-66 shows the eCAP timing requirement and Table 6-67 shows the eCAP switching characteristics.
Table 6-66. Enhanced Capture (eCAP) Timing Requirement
PARAMETER
tw(CAP)
TEST CONDITIONS
Capture input pulse width
MIN
MAX
UNIT
Asynchronous
2tc(SCO)
cycles
Synchronous
2tc(SCO)
cycles
Table 6-67. eCAP Switching Characteristics
PARAMETER
tw(APWM)
MIN
Pulse duration, APWMx output high/low
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20
MAX
UNIT
ns
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Counter Phase Offset Value Register
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6.20 Enhanced Quadrature Encoder (eQEP) Peripheral
The device contains up to two enhanced quadrature encoder (eQEP) modules.
System
control registers
To CPU
EQEPxENCLK
Data bus
SYSCLK2
QCPRD
QCTMR
QCAPCTL
16
16
16
QCTMRLAT
QCPRDLAT
Registers
used by
multiple units
QUTMR
QWDTMR
QUPRD
QWDPRD
32
16
QEPCTL
QEPSTS
UTIME
QFLG
Interrupt Controller
ADVANCE INFORMATION
Quadrature
capture unit
(QCAP)
UTOUT
QDECCTL
QWDOG
16
WDTOUT
EQEPxINT
EQEPxAIN
QCLK
16
QI
Position counter/
control unit
(PCCU)
QPOSLAT
QS
PHE
QPOSSLAT
EQEPxIIN
EQEPxIOUT
Quadrature
decoder
(QDU)
PCSOUT
QPOSILAT
EQEPxIOE
EQEPxSIN
EQEPxSOUT
EQEPxSOE
32
32
QPOSCNT
QPOSCMP
EQEPxA/XCLK
EQEPxBIN
QDIR
EQEPxB/XDIR
GPIO
MUX
EQEPxI
EQEPxS
16
QEINT
QPOSINIT
QFRC
QPOSMAX
QCLR
QPOSCTL
Enhanced QEP (eQEP) peripheral
Figure 6-36. eQEP Functional Block Diagram
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Table 6-68 is the list of the EQEP registers.
Table 6-69 shows the eQEP timing requirement and Table 6-70 shows the eQEP switching
characteristics.
Table 6-68. EQEP Registers
EQEP0
BYTE ADDRESS
EQEP1
BYTE ADDRESS
ACRONYM
0x01F0 9000
0x01F0 A000
QPOSCNT
eQEP Position Counter
0x01F0 9004
0x01F0 A004
QPOSINIT
eQEP Initialization Position Count
0x01F0 9008
0x01F0 A008
QPOSMAX
eQEP Maximum Position Count
0x01F0 900C
0x01F0 A00C
QPOSCMP
eQEP Position-compare
0x01F0 9010
0x01F0 A010
QPOSILAT
eQEP Index Position Latch
0x01F0 9014
0x01F0 A014
QPOSSLAT
eQEP Strobe Position Latch
REGISTER DESCRIPTION
0x01F0 A018
QPOSLAT
0x01F0 A01C
QUTMR
eQEP Position Latch
eQEP Unit Timer
0x01F0 9020
0x01F0 A020
QUPRD
eQEP Unit Period Register
0x01F0 9024
0x01F0 A024
QWDTMR
eQEP Watchdog Timer
0x01F0 9026
0x01F0 A026
QWDPRD
eQEP Watchdog Period Register
0x01F0 9028
0x01F0 A028
QDECCTL
eQEP Decoder Control Register
0x01F0 902A
0x01F0 A02A
QEPCTL
0x01F0 902C
0x01F0 A02C
QCAPCTL
eQEP Capture Control Register
0x01F0 902E
0x01F0 A02E
QPOSCTL
eQEP Position-compare Control Register
0x01F0 9030
0x01F0 A030
QEINT
eQEP Interrupt Enable Register
0x01F0 9032
0x01F0 A032
QFLG
eQEP Interrupt Flag Register
0x01F0 9034
0x01F0 A034
QCLR
eQEP Interrupt Clear Register
0x01F0 9036
0x01F0 A036
QFRC
eQEP Interrupt Force Register
ADVANCE INFORMATION
0x01F0 9018
0x01F0 901C
eQEP Control Register
0x01F0 9038
0x01F0 A038
QEPSTS
eQEP Status Register
0x01F0 903A
0x01F0 A03A
QCTMR
eQEP Capture Timer
0x01F0 903C
0x01F0 A03C
QCPRD
eQEP Capture Period Register
0x01F0 903E
0x01F0 A03E
QCTMRLAT
eQEP Capture Timer Latch
0x01F0 9040
0x01F0 A040
QCPRDLAT
eQEP Capture Period Latch
0x01F0 905C
0x01F0 A05C
REVID
eQEP Revision ID
Table 6-69. Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
tw(QEPP)
QEP input period
Asynchronous/synchronous
2tc(SCO)
cycles
tw(INDEXH)
QEP Index Input High time
Asynchronous/synchronous
2tc(SCO)
cycles
tw(INDEXL)
QEP Index Input Low time
Asynchronous/synchronous
2tc(SCO)
cycles
tw(STROBH)
QEP Strobe High time
Asynchronous/synchronous
2tc(SCO)
cycles
tw(STROBL)
QEP Strobe Input Low time
Asynchronous/synchronous
2tc(SCO)
cycles
Table 6-70. eQEP Switching Characteristics
MAX
UNIT
td(CNTR)xin
Delay time, external clock to counter increment
PARAMETER
4tc(SCO)
cycles
td(PCS-OUT)QEP
Delay time, QEP input edge to position compare sync output
6tc(SCO)
cycles
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MIN
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6.21 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
The device contains up to three enhanced PWM Modules (eHRPWM). Figure 6-37 shows a block diagram
of multiple eHRPWM modules. Figure 4-4 shows the signal interconnections with the eHRPWM.
EPWMSYNCI
EPWM0INT
EPWM0SYNCI
EPWM0A
eHRPWM0 module
EPWM0B
EPWMTZ
EPWM0SYNCO
ADVANCE INFORMATION
EPWM1SYNCI
Interrupt
Controllers
EPWM1INT
EPWM1A
eHRPWM1 module
EPWM1SYNCO
GPIO
MUX
EPWM1B
EPWMTZ
EPWM2SYNCI
EPWM2INT
EPWM2A
eHRPWM2 module
EPWM2SYNCO
To eCAP0
module
(sync in)
EPWM2B
EPWMTZ
EPWMSYNCO
Peripheral Bus
Figure 6-37. Multiple PWM Modules in the System
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Time−base (TB)
Sync
in/out
select
Mux
CTR=ZERO
CTR=CMPB
Disabled
TBPRD shadow (16)
TBPRD active (16)
CTR=PRD
EPWMSYNCO
TBCTL[SYNCOSEL]
TBCTL[CNTLDE]
EPWMSYNCI
Counter
up/down
(16 bit)
CTR=ZERO
CTR_Dir
TBCNT
active (16)
TBPHSHR (8)
16
8
CTR = PRD
CTR = ZERO
CTR = CMPA
CTR = CMPB
CTR_Dir
Phase
control
Counter compare (CC)
CTR=CMPA
CMPAHR (8)
Action
qualifier
(AQ)
8
Event
trigger
and
interrupt
(ET)
EPWMxINT
ADVANCE INFORMATION
TBPHS active (24)
16
TBCTL[SWFSYNC]
(software forced sync)
HiRes PWM (HRPWM)
CMPA active (24)
EPWMxA
EPWMA
CMPA shadow (24)
CTR=CMPB
Dead
band
(DB)
16
PWM
chopper
(PC)
Trip
zone
(TZ)
EPWMxB
EPWMB
CMPB active (16)
EPWMxTZINT
CMPB shadow (16)
CTR = ZERO
TZ
Figure 6-38. eHRPWM Sub-Modules Showing Critical Internal Signal Interconnections
Table 6-71. eHRPWM Module Control and Status Registers Grouped by Submodule
eHRPWM0
BYTE ADDRESS
eHRPWM1
BYTE ADDRESS
eHRPWM2
BYTE ADDRESS
0x01F0 0000
0x01F0 2000
0x01F0 4000
0x01F0 0002
0x01F0 2002
0x01F0 0004
0x01F0 2004
0x01F0 0006
0x01F0 2006
ACRONYM
SIZE
(×16)
SHADOW
REGISTER DESCRIPTION
TIME-BASE SUBMODULE REGISTERS
TBCTL
1
No
Time-Base Control Register
0x01F0 4002
TBSTS
1
No
Time-Base Status Register
0x01F0 4004
TBPHSHR
1
No
Extension for HRPWM Phase Register
0x01F0 4006
TBPHS
1
No
Time-Base Phase Register
0x01F0 0008
0x01F0 2008
0x01F0 4008
TBCNT
1
No
Time-Base Counter Register
0x01F0 000A
0x01F0 200A
0x01F0 400A
TBPRD
1
Yes
Time-Base Period Register
(1)
COUNTER-COMPARE SUBMODULE REGISTER
0x01F0 000E
0x01F0 200E
0x01F0 400E
CMPCTL
1
No
Counter-Compare Control Register
CMPAHR
1
No
Extension for HRPWM Counter-Compare
A Register (1)
0x01F0 0010
0x01F0 2010
0x01F0 4010
0x01F0 0012
0x01F0 2012
0x01F0 4012
CMPA
1
Yes
Counter-Compare A Register
0x01F0 0014
0x01F0 2014
0x01F0 4014
CMPB
1
Yes
Counter-Compare B Register
ACTION-QUALIFIER SUBMODULE REGISTER
(1)
These registers are only available on eHRPWM instances that include the high-resolution PWM (HRPWM) extension; otherwise, these
locations are reserved.
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Table 6-71. eHRPWM Module Control and Status Registers Grouped by Submodule (continued)
eHRPWM0
BYTE ADDRESS
eHRPWM1
BYTE ADDRESS
eHRPWM2
BYTE ADDRESS
0x01F0 0016
0x01F0 2016
0x01F0 4016
0x01F0 0018
0x01F0 2018
0x01F0 4018
0x01F0 001A
0x01F0 201A
0x01F0 401A
0x01F0 001C
0x01F0 201C
0x01F0 401C
0x01F0 001E
0x01F0 201E
0x01F0 401E
0x01F0 0020
0x01F0 2020
0x01F0 4020
0x01F0 0022
0x01F0 2022
0x01F0 4022
0x01F0 003C
0x01F0 203C
0x01F0 403C
ACRONYM
SIZE
(×16)
SHADOW
AQCTLA
1
No
Action-Qualifier Control Register for
Output A (eHRPWMxA)
AQCTLB
1
No
Action-Qualifier Control Register for
Output B (eHRPWMxB)
AQSFRC
1
No
Action-Qualifier Software Force Register
AQCSFRC
1
Yes
Action-Qualifier Continuous S/W Force
Register Set
REGISTER DESCRIPTION
DEAD-BAND GENERATOR SUBMODULE REGISTER
DBCTL
1
No
Dead-Band Generator Control Register
DBRED
1
No
Dead-Band Generator Rising Edge Delay
Count Register
DBFED
1
No
Dead-Band Generator Falling Edge Delay
Count Register
PWM-CHOPPER SUBMODULE REGISTER
PCCTL
1
No
PWM-Chopper Control Register
ADVANCE INFORMATION
TRIP-ZONE SUBMODULE REGISTER
0x01F0 0024
0x01F0 2024
0x01F0 4024
TZSEL
1
No
Trip-Zone Select Register
0x01F0 0028
0x01F0 2028
0x01F0 4028
TZCTL
1
No
Trip-Zone Control Register
0x01F0 002A
0x01F0 202A
0x01F0 402A
TZEINT
1
No
Trip-Zone Enable Interrupt Register
0x01F0 002C
0x01F0 202C
0x01F0 402C
TZFLG
1
No
Trip-Zone Flag Register
0x01F0 002E
0x01F0 202E
0x01F0 402E
TZCLR
1
No
Trip-Zone Clear Register
0x01F0 0030
0x01F0 2030
0x01F0 4030
TZFRC
1
No
Trip-Zone Force Register
EVENT-TRIGGER SUBMODULE REGISTER
0x01F0 0032
0x01F0 2032
0x01F0 4032
ETSEL
1
No
Event-Trigger Selection Register
0x01F0 0034
0x01F0 2034
0x01F0 4034
ETPS
1
No
Event-Trigger Pre-Scale Register
0x01F0 0036
0x01F0 2036
0x01F0 4036
ETFLG
1
No
Event-Trigger Flag Register
0x01F0 0038
0x01F0 2038
0x01F0 4038
ETCLR
1
No
Event-Trigger Clear Register
0x01F0 003A
0x01F0 203A
0x01F0 403A
ETFRC
1
No
Event-Trigger Force Register
HIGH-RESOLUTION PWM (HRPWM) SUBMODULE
0x01F0 1020
(2)
118
0x01F0 3020
0x01F0 5020
HRCNFG
1
No
HRPWM Configuration Register
(2)
These registers are only available on eHRPWM instances that include the high-resolution PWM (HRPWM) extension; otherwise, these
locations are reserved.
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6.21.1 Enhanced Pulse Width Modulator (eHRPWM) Timing
PWM refers to PWM outputs on eHRPWM1-6. Table 6-72 shows the PWM timing requirements and
Table 6-73, switching characteristics.
Table 6-72. eHRPWM Timing Requirements
PARAMETER
tw(SYNCIN)
TEST CONDITIONS
Sync input pulse width
MIN
MAX
UNIT
Asynchronous
2tc(SCO)
cycles
Synchronous
2tc(SCO)
cycles
Table 6-73. eHRPWM Switching Characteristics
TEST CONDITIONS
tw(PWM)
Pulse duration, PWMx output high/low
tw(SYNCOUT)
Sync output pulse width
td(PWM)TZA
Delay time, trip input active to PWM forced high no pin load; no additional
Delay time, trip input active to PWM forced low programmable delay
td(TZ-PWM)HZ
Delay time, trip input active to PWM Hi-Z
MIN
MAX
UNIT
20
ns
8tc(SCO)
cycles
ns
25
no additional programmable
delay
ns
20
6.21.2 Trip-Zone Input Timing
tw(TZ)
TZ
td(TZ-PWM)HZ
PWM(A)
A.
PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM
recovery software.
Figure 6-39. PWM Hi-Z Characteristics
Table 6-74. Trip-Zone input Timing Requirements
PARAMETER
tw(TZ)
MIN
Pulse duration, TZx input low
Asynchronous
Synchronous
MAX
UNIT
1tc(SCO)
cycle
s
2tc(SCO)
cycle
s
Table 6-75 shows the high-resolution PWM switching characteristics.
Table 6-75. High Resolution PWM Characteristics at SYSCLKOUT = (60 - 100 MHz)
PARAMETER
Micro Edge Positioning (MEP) step size (1)
(1)
MIN
TYP
MAX
200
UNIT
ps
MEP step size will increase with low voltage and high temperature and decrease with high voltage and cold temperature.
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PARAMETER
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6.22 Timers
The timers support the following features:
• Configurable as single 64-bit timer or two 32-bit timers
• Period timeouts generate interrupts, DMA events or external pin events
• 8 32-bit compare registers
• Compare matches generate interrupt events
• Capture capability
• 64-bit Watchdog capability (Timer64P1 only)
Table 6-76 lists the timer registers.
Table 6-76. Timer Registers
ADVANCE INFORMATION
120
Timer64P 0
Timer64P 1
ACRONYM
0x01C2 0000
0x01C2 1000
REV
0x01C2 0004
0x01C2 1004
EMUMGT
REGISTER DESCRIPTION
Revision Register
Emulation Management Register
0x01C2 0008
0x01C2 1008
GPINTGPEN
0x01C2 000C
0x01C2 100C
GPDATGPDIR
GPIO Interrupt and GPIO Enable Register
0x01C2 0010
0x01C2 1010
TIM12
Timer Counter Register 12
0x01C2 0014
0x01C2 1014
TIM34
Timer Counter Register 34
GPIO Data and GPIO Direction Register
0x01C2 0018
0x01C2 1018
PRD12
Timer Period Register 12
0x01C2 001C
0x01C2 101C
PRD34
Timer Period Register 34
0x01C2 0020
0x01C2 1020
TCR
0x01C2 0024
0x01C2 1024
TGCR
0x01C2 0028
0x01C2 1028
WDTCR
0x01C2 0034
0x01C2 1034
REL12
Timer Reload Register 12
Timer Control Register
Timer Global Control Register
Watchdog Timer Control Register
0x01C2 0038
0x01C2 1038
REL34
Timer Reload Register 34
0x01C2 003C
0x01C2 103C
CAP12
Timer Capture Register 12
0x01C2 0040
0x01C2 1040
CAP34
Timer Capture Register 34
0x01C2 0044
0x01C2 1044
INTCTLSTAT
0x01C2 0060
0x01C2 1060
CMP0
Compare Register 0
0x01C2 0064
0x01C2 1064
CMP1
Compare Register 1
0x01C2 0068
0x01C2 1068
CMP2
Compare Register 2
0x01C2 006C
0x01C2 106C
CMP3
Compare Register 3
0x01C2 0070
0x01C2 1070
CMP4
Compare Register 4
0x01C2 0074
0x01C2 1074
CMP5
Compare Register 5
0x01C2 0078
0x01C2 1078
CMP6
Compare Register 6
0x01C2 007C
0x01C2 107C
CMP7
Compare Register 7
Timer Interrupt Control and Status Register
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6.22.1
SPRS657A – FEBRUARY 2010 – REVISED APRIL 2010
Timer Electrical Data/Timing
Table 6-77. Timing Requirements for Timer Input (1)
No.
(2)
(see Figure 6-40)
PARAMETER
MIN
MAX
tc(TM64Px_IN12)
Cycle time, TM64Px_IN12
2
tw(TINPH)
Pulse duration, TM64Px_IN12 high
0.45C
0.55C
ns
3
tw(TINPL)
Pulse duration, TM64Px_IN12 low
0.45C
0.55C
ns
4
tt(TM64Px_IN12)
Transition time, TM64Px_IN12
0.05C
ns
(1)
(2)
4P
UNIT
1
ns
P = OSCIN cycle time in ns. For example, when OSCIN frequency is 27 MHz, use P = 37.037 ns.
C = TM64P0_IN12 cycle time in ns. For example, when TM64Px_IN12 frequency is 27 MHz, use C = 37.037 ns
1
2
3
4
4
Figure 6-40. Timer Timing
Table 6-78. Switching Characteristics Over Recommended Operating Conditions for Timer Output
No.
(1)
MAX
(1)
PARAMETER
MIN
5
tw(TOUTH)
Pulse duration, TM64P0_OUT12 high
4P
UNIT
ns
6
tw(TOUTL)
Pulse duration, TM64P0_OUT12 low
4P
ns
P = OSCIN cycle time in ns. For example, when OSCIN frequency is 27 MHz, use P = 37.037 ns.
5
6
TM64P0_OUT12
Figure 6-41. Timer Timing
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6.23 Inter-Integrated Circuit Serial Ports (I2C0, I2C1)
6.23.1 I2C Device-Specific Information
Having two I2C modules on the device simplifies system architecture. Figure 6-42 is block diagram of the
I2C Module.
Each I2C port supports:
• Compatible with Philips® I2C Specification Revision 2.1 (January 2000)
• Fast Mode up to 400 Kbps (no fail-safe I/O buffers)
• Noise Filter to Remove Noise 50 ns or less
• Seven- and Ten-Bit Device Addressing Modes
• Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality
• Events: DMA, Interrupt, or Polling
• General-Purpose I/O Capability if not used as I2C
ADVANCE INFORMATION
Clock Prescaler
I2CPSCx
Control
Prescaler
Register
I2CCOARx
Own Address
Register
I2CSARx
Slave Address
Register
Bit Clock Generator
I2Cx_SCL
Noise
Filter
I2CCLKHx
Clock Divide
High Register
I2CCMDRx
Mode Register
I2CCLKLx
Clock Divide
Low Register
I2CEMDRx
Extended Mode
Register
I2CCNTx
Data Count
Register
I2CPID1
Peripheral ID
Register 1
I2CPID2
Peripheral ID
Register 2
Transmit
I2Cx_SDA
Noise
Filter
I2CXSRx
Transmit Shift
Register
I2CDXRx
Transmit Buffer
Interrupt/DMA
Receive
I2CIERx
I2CDRRx
Receive Buffer
I2CSTRx
I2CRSRx
Receive Shift
Register
I2CSRCx
I2CPFUNC
Pin Function
Register
I2CPDOUT
Interrupt Enable
Register
Interrupt Status
Register
Interrupt Source
Register
Peripheral
Configuration
Bus
Interrupt DMA
Requests
Control
I2CPDIR
I2CPDIN
Pin Direction
Register
Pin Data In
Register
I2CPDSET
I2CPDCLR
Pin Data Out
Register
Pin Data Set
Register
Pin Data Clear
Register
Figure 6-42. I2C Module Block Diagram
6.23.2 I2C Peripheral Registers Description(s)
Table 6-79 is the list of the I2C registers.
122
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Table 6-79. Inter-Integrated Circuit (I2C) Registers
I2C1
BYTE ADDRESS
ACRONYM
0x01C2 2000
0x01E2 8000
ICOAR
I2C Own Address Register
0x01C2 2004
0x01E2 8004
ICIMR
I2C Interrupt Mask Register
0x01C2 2008
0x01E2 8008
ICSTR
I2C Interrupt Status Register
0x01C2 200C
0x01E2 800C
ICCLKL
I2C Clock Low-Time Divider Register
0x01C2 2010
0x01E2 8010
ICCLKH
I2C Clock High-Time Divider Register
0x01C2 2014
0x01E2 8014
ICCNT
I2C Data Count Register
0x01C2 2018
0x01E2 8018
ICDRR
I2C Data Receive Register
0x01C2 201C
0x01E2 801C
ICSAR
I2C Slave Address Register
0x01C2 2020
0x01E2 8020
ICDXR
I2C Data Transmit Register
0x01C2 2024
0x01E2 8024
ICMDR
I2C Mode Register
0x01C2 2028
0x01E2 8028
ICIVR
I2C Interrupt Vector Register
0x01C2 202C
0x01E2 802C
ICEMDR
I2C Extended Mode Register
0x01C2 2030
0x01E2 8030
ICPSC
I2C Prescaler Register
0x01C2 2034
0x01E2 8034
REVID1
I2C Revision Identification Register 1
0x01C2 2038
0x01E2 8038
REVID2
I2C Revision Identification Register 2
0x01C2 2048
0x01E2 8048
ICPFUNC
I2C Pin Function Register
0x01C2 204C
0x01E2 804C
ICPDIR
I2C Pin Direction Register
0x01C2 2050
0x01E2 8050
ICPDIN
I2C Pin Data In Register
0x01C2 2054
0x01E2 8054
ICPDOUT
I2C Pin Data Out Register
0x01C2 2058
0x01E2 8058
ICPDSET
I2C Pin Data Set Register
0x01C2 205C
0x01E2 805C
ICPDCLR
I2C Pin Data Clear Register
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REGISTER DESCRIPTION
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I2C0
BYTE ADDRESS
123
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6.23.3 I2C Electrical Data/Timing
6.23.3.1 Inter-Integrated Circuit (I2C) Timing
Table 6-80 and Table 6-81 assume testing over recommended operating conditions (see Figure 6-43 and
Figure 6-44).
Table 6-80. I2C Input Timing Requirements
No.
PARAMETER
ADVANCE INFORMATION
1
tc(SCL)
Cycle time, I2Cx_SCL
2
tsu(SCLH-SDAL)
Setup time, I2Cx_SCL high before I2Cx_SDA low
3
th(SCLL-SDAL)
Hold time, I2Cx_SCL low after I2Cx_SDA low
4
tw(SCLL)
Pulse duration, I2Cx_SCL low
5
tw(SCLH)
Pulse duration, I2Cx_SCL high
6
tsu(SDA-SCLH)
Setup time, I2Cx_SDA before I2Cx_SCL high
7
th(SDA-SCLL)
Hold time, I2Cx_SDA after I2Cx_SCL low
8
tw(SDAH)
Pulse duration, I2Cx_SDA high
9
tr(SDA)
Rise time, I2Cx_SDA
10
tr(SCL)
Rise time, I2Cx_SCL
11
tf(SDA)
Fall time, I2Cx_SDA
12
tf(SCL)
Fall time, I2Cx_SCL
13
tsu(SCLH-SDAH)
Setup time, I2Cx_SCL high before I2Cx_SDA high
14
tw(SP)
Pulse duration, spike (must be suppressed)
15
Cb
Capacitive load for each bus line
124
MIN
Standard Mode
10
Fast Mode
2.5
Standard Mode
4.7
Fast Mode
0.6
Standard Mode
0.6
Standard Mode
4.7
Fast Mode
1.3
0.6
Standard Mode
250
Fast Mode
100
Standard Mode
0
Fast Mode
0
Standard Mode
4.7
Fast Mode
1.3
Standard Mode
Fast Mode
Standard Mode
Standard Mode
Standard Mode
0.9
0.6
Standard Mode
N/A
0
300
300
300
300
ns
ns
ns
ns
ms
50
Standard Mode
400
Fast Mode
400
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ms
ms
4
Fast Mode
Fast Mode
ns
300
20 + 0.1Cb
Standard Mode
ms
300
20 + 0.1Cb
Fast Mode
ms
1000
20 + 0.1Cb
Fast Mode
ms
1000
20 + 0.1Cb
Fast Mode
ms
4
Fast Mode
UNIT
ms
4
Fast Mode
Standard Mode
MAX
ns
pF
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Table 6-81. I2C Switching Characteristics (1)
PARAMETER
MIN
16
tc(SCL)
Cycle time, I2Cx_SCL
17
tsu(SCLH-SDAL)
Setup time, I2Cx_SCL high before I2Cx_SDA
low
18
th(SDAL-SCLL)
Hold time, I2Cx_SCL low after I2Cx_SDA low
19
tw(SCLL)
Pulse duration, I2Cx_SCL low
20
tw(SCLH)
Pulse duration, I2Cx_SCL high
21
tsu(SDAV-SCLH)
Setup time, I2Cx_SDA valid before I2Cx_SCL
high
22
th(SCLL-SDAV)
Hold time, I2Cx_SDA valid after I2Cx_SCL low
23
tw(SDAH)
Pulse duration, I2Cx_SDA high
28
tsu(SCLH-SDAH)
Setup time, I2Cx_SCL high before I2Cx_SDA
high
(1)
Standard Mode
10
Fast Mode
2.5
Standard Mode
4.7
Fast Mode
0.6
Standard Mode
MAX
UNIT
ms
ms
4
Fast Mode
0.6
Standard Mode
4.7
Fast Mode
1.3
Standard Mode
ms
ms
4
Fast Mode
0.6
Standard Mode
250
Fast Mode
100
Standard Mode
0
Fast Mode
0
Standard Mode
4.7
Fast Mode
1.3
Standard Mode
ms
ns
ms
0.9
ms
4
Fast Mode
ADVANCE INFORMATION
No.
ms
0.6
I2C must be configured correctly to meet the timings in Table 6-81 .
11
9
I2Cx_SDA
6
8
14
4
13
5
10
I2Cx_SCL
1
12
3
2
7
3
Stop
Start
Repeated
Start
Stop
Figure 6-43. I2C Receive Timings
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26
24
I2Cx_SDA
21
23
19
28
20
25
I2Cx_SCL
16
27
18
17
22
18
Stop
Start
Repeated
Start
Stop
Figure 6-44. I2C Transmit Timings
ADVANCE INFORMATION
126
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6.24
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Universal Asynchronous Receiver/Transmitter (UART)
ADVANCE INFORMATION
The device has 3 UART peripherals. Each UART has the following features:
• 16-byte storage space for both the transmitter and receiver FIFOs
• 1, 4, 8, or 14 byte selectable receiver FIFO trigger level for autoflow control and DMA
• DMA signaling capability for both received and transmitted data
• Programmable auto-rts and auto-cts for autoflow control
• Programmable Baud Rate up to 3MBaud
• Programmable Oversampling Options of x13 and x16
• Frequency pre-scale values from 1 to 65,535 to generate appropriate baud rates
• Prioritized interrupts
• Programmable serial data formats
– 5, 6, 7, or 8-bit characters
– Even, odd, or no parity bit generation and detection
– 1, 1.5, or 2 stop bit generation
• False start bit detection
• Line break generation and detection
• Internal diagnostic capabilities
– Loopback controls for communications link fault isolation
– Break, parity, overrun, and framing error simulation
• Modem control functions (CTS, RTS) on UART0 only.
The UART registers are listed in Section 6.24.1
6.24.1 UART Peripheral Registers Description(s)
Table 6-82 is the list of UART registers.
Table 6-82. UART Registers
UART0
BYTE ADDRESS
UART1
BYTE ADDRESS
UART2
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
0x01C4 2000
0x01D0 C000
0x01D0 D000
RBR
Receiver Buffer Register (read only)
0x01C4 2000
0x01D0 C000
0x01D0 D000
THR
Transmitter Holding Register (write only)
0x01C4 2004
0x01D0 C004
0x01D0 D004
IER
Interrupt Enable Register
0x01C4 2008
0x01D0 C008
0x01D0 D008
IIR
Interrupt Identification Register (read only)
0x01C4 2008
0x01D0 C008
0x01D0 D008
FCR
FIFO Control Register (write only)
0x01C4 200C
0x01D0 C00C
0x01D0 D00C
LCR
Line Control Register
0x01C4 2010
0x01D0 C010
0x01D0 D010
MCR
Modem Control Register
0x01C4 2014
0x01D0 C014
0x01D0 D014
LSR
Line Status Register
0x01C4 2018
0x01D0 C018
0x01D0 D018
MSR
Modem Status Register
0x01C4 201C
0x01D0 C01C
0x01D0 D01C
SCR
Scratchpad Register
0x01C4 2020
0x01D0 C020
0x01D0 D020
DLL
Divisor LSB Latch
0x01C4 2024
0x01D0 C024
0x01D0 D024
DLH
Divisor MSB Latch
0x01C4 2028
0x01D0 C028
0x01D0 D028
REVID1
0x01C4 2030
0x01D0 C030
0x01D0 D030
PWREMU_MGMT
0x01C4 2034
0x01D0 C034
0x01D0 D034
MDR
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Revision Identification Register 1
Power and Emulation Management Register
Mode Definition Register
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6.24.2 UART Electrical Data/Timing
Table 6-83. Timing Requirements for UARTx Receive (1) (see Figure 6-45)
No.
PARAMETER
MIN
MAX
UNIT
4
tw(URXDB)
Pulse duration, receive data bit (RXDn)
0.96U
1.05U
ns
5
tw(URXSB)
Pulse duration, receive start bit
0.96U
1.05U
ns
(1)
U = UART baud time = 1/programmed baud rate.
Table 6-84. Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit (1)
(see Figure 6-45)
No.
PARAMETER
MIN
MAX
UNIT
MBaud (4)
f(baud)
Maximum programmable baud rate
2
tw(UTXDB)
Pulse duration, transmit data bit (TXDn)
U-2
U+2
ns
tw(UTXSB)
Pulse duration, transmit start bit
U-2
U+2
ns
3
(1)
(2)
(3)
ADVANCE INFORMATION
(4)
D/E
(2) (3)
1
U = UART baud time = 1/programmed baud rate.
D = UART input clock in MHz. The UART(s) input clock source is PLL0_SYSCLK2.
E = UART divisor x UART sampling rate. The UART divisor is set through the UART divisor latch registers (DLL and DLH). The UART
sampling rate is set through the over-sampling mode select bit (OSM_SEL) of the UART mode definition register (MDR).
Baud rate is not indicative of data rate. Actual data rate will be limited by system factors such as EDMA loading, EMIF loading, system
frequency, etc.
3
2
UART_TXDn
Start
Bit
Data Bits
5
4
UART_RXDn
Start
Bit
Data Bits
Figure 6-45. UART Transmit/Receive Timing
128
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6.25 USB0 OTG (USB2.0 OTG)
Important Notice: On the original device pinout (marked "A" in the lower right corner of the package),
pins USB0_VSSA33 (H4) and USB0_VSSA (F3) were connected to ground outside the package. For
more robust ESD performance, the USB0 ground references are now connected inside the package on
packages marked "B" and the package pins are unconnected. This change will require that any external
filter circuits previously referenced to ground at these pins will need to reference the board ground instead.
Table 6-85 is the list of USB OTG registers.
Table 6-85. Universal Serial Bus OTG (USB0) Registers
BYTE ADDRESS
ACRONYM
0x01E0 0000
REVID
Revision Register
REGISTER DESCRIPTION
0x01E0 0004
CTRLR
Control Register
0x01E0 0008
STATR
Status Register
0x01E0 000C
EMUR
Emulation Register
0x01E0 0010
MODE
Mode Register
0x01E0 0014
AUTOREQ
0x01E0 0018
SRPFIXTIME
Autorequest Register
SRP Fix Time Register
0x01E0 001C
TEARDOWN
Teardown Register
0x01E0 0020
INTSRCR
USB Interrupt Source Register
0x01E0 0024
INTSETR
USB Interrupt Source Set Register
0x01E0 0028
INTCLRR
USB Interrupt Source Clear Register
0x01E0 002C
INTMSKR
USB Interrupt Mask Register
0x01E0 0030
INTMSKSETR
USB Interrupt Mask Set Register
0x01E0 0034
INTMSKCLRR
USB Interrupt Mask Clear Register
0x01E0 0038
INTMASKEDR
USB Interrupt Source Masked Register
0x01E0 003C
EOIR
USB End of Interrupt Register
0x01E0 0040
INTVECTR
USB Interrupt Vector Register
0x01E0 0050
GENRNDISSZ1
Generic RNDIS Size EP1
0x01E0 0054
GENRNDISSZ2
Generic RNDIS Size EP2
0x01E0 0058
GENRNDISSZ3
Generic RNDIS Size EP3
0x01E0 005C
GENRNDISSZ4
Generic RNDIS Size EP4
0x01E0 0400
FADDR
Function Address Register
0x01E0 0401
POWER
Power Management Register
0x01E0 0402
INTRTX
Interrupt Register for Endpoint 0 plus Transmit Endpoints 1 to 4
0x01E0 0404
INTRRX
Interrupt Register for Receive Endpoints 1 to 4
0x01E0 0406
INTRTXE
Interrupt enable register for INTRTX
0x01E0 0408
INTRRXE
Interrupt Enable Register for INTRRX
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ADVANCE INFORMATION
The device USB2.0 peripheral supports the following features:
• USB 2.0 peripheral at speeds high speed (HS: 480 Mb/s ) and full speed (FS: 12 Mb/s)
• USB 2.0 host at speeds HS, FS, and low speed (LS: 1.5 Mb/s)
• All transfer modes (control, bulk, interrupt, and isochronous)
• 4 Transmit (TX) and 4 Receive (RX) endpoints in addition to endpoint 0
• FIFO RAM
– 4K endpoint
– Programmable size
• Integrated USB 2.0 High Speed PHY
• Connects to a standard Charge Pump for VBUS 5 V generation
• RNDIS mode for accelerating RNDIS type protocols using short packet termination over USB
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Table 6-85. Universal Serial Bus OTG (USB0) Registers (continued)
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
0x01E0 040A
INTRUSB
0x01E0 040B
INTRUSBE
Interrupt Register for Common USB Interrupts
0x01E0 040C
FRAME
Frame Number Register
0x01E0 040E
INDEX
Index Register for Selecting the Endpoint Status and Control Registers
0x01E0 040F
TESTMODE
Interrupt Enable Register for INTRUSB
Register to Enable the USB 2.0 Test Modes
INDEXED REGISTERS
These registers operate on the endpoint selected by the INDEX register
ADVANCE INFORMATION
0x01E0 0410
TXMAXP
Maximum Packet Size for Peripheral/Host Transmit Endpoint (Index register set to select
Endpoints 1-4 only)
0x01E0 0412
PERI_CSR0
Control Status Register for Endpoint 0 in Peripheral Mode. (Index register set to select Endpoint
0)
HOST_CSR0
Control Status Register for Endpoint 0 in Host Mode.
(Index register set to select Endpoint 0)
PERI_TXCSR
Control Status Register for Peripheral Transmit Endpoint. (Index register set to select Endpoints
1-4)
HOST_TXCSR
Control Status Register for Host Transmit Endpoint.
(Index register set to select Endpoints 1-4)
0x01E0 0414
RXMAXP
0x01E0 0416
PERI_RXCSR
Control Status Register for Peripheral Receive Endpoint. (Index register set to select Endpoints
1-4)
HOST_RXCSR
Control Status Register for Host Receive Endpoint.
(Index register set to select Endpoints 1-4)
0x01E0 0418
COUNT0
RXCOUNT
0x01E0 041A
HOST_TYPE0
HOST_TXTYPE
0x01E0 041B
HOST_NAKLIMIT0
Maximum Packet Size for Peripheral/Host Receive Endpoint (Index register set to select
Endpoints 1-4 only)
Number of Received Bytes in Endpoint 0 FIFO.
(Index register set to select Endpoint 0)
Number of Bytes in Host Receive Endpoint FIFO.
(Index register set to select Endpoints 1- 4)
Defines the speed of Endpoint 0
Sets the operating speed, transaction protocol and peripheral endpoint number for the host
Transmit endpoint. (Index register set to select Endpoints 1-4 only)
Sets the NAK response timeout on Endpoint 0.
(Index register set to select Endpoint 0)
HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk
transactions for host Transmit endpoint. (Index register set to select Endpoints 1-4 only)
0x01E0 041C
0x01E0 041D
HOST_RXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint number for the host
Receive endpoint. (Index register set to select Endpoints 1-4 only)
HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk
transactions for host Receive endpoint. (Index register set to select Endpoints 1-4 only)
0x01E0 041F
CONFIGDATA
Returns details of core configuration. (Index register set to select Endpoint 0)
0x01E0 0420
FIFO0
Transmit and Receive FIFO Register for Endpoint 0
0x01E0 0424
FIFO1
Transmit and Receive FIFO Register for Endpoint 1
FIFO
0x01E0 0428
FIFO2
Transmit and Receive FIFO Register for Endpoint 2
0x01E0 042C
FIFO3
Transmit and Receive FIFO Register for Endpoint 3
0x01E0 0430
FIFO4
Transmit and Receive FIFO Register for Endpoint 4
OTG DEVICE CONTROL
0x01E0 0460
130
DEVCTL
Device Control Register
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Table 6-85. Universal Serial Bus OTG (USB0) Registers (continued)
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
0x01E0 0462
TXFIFOSZ
Transmit Endpoint FIFO Size
(Index register set to select Endpoints 1-4 only)
0x01E0 0463
RXFIFOSZ
Receive Endpoint FIFO Size
(Index register set to select Endpoints 1-4 only)
0x01E0 0464
TXFIFOADDR
Transmit Endpoint FIFO Address
(Index register set to select Endpoints 1-4 only)
0x01E0 0466
RXFIFOADDR
Receive Endpoint FIFO Address
(Index register set to select Endpoints 1-4 only)
0x01E0 046C
HWVERS
0x01E0 0480
TXFUNCADDR
0x01E0 0482
TXHUBADDR
Address of the hub that has to be accessed through the associated Transmit Endpoint. This is
used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 0483
TXHUBPORT
Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used
only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 0484
RXFUNCADDR
0x01E0 0486
RXHUBADDR
Address of the hub that has to be accessed through the associated Receive Endpoint. This is
used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 0487
RXHUBPORT
Port of the hub that has to be accessed through the associated Receive Endpoint. This is used
only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 0488
TXFUNCADDR
0x01E0 048A
TXHUBADDR
Address of the hub that has to be accessed through the associated Transmit Endpoint. This is
used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 048B
TXHUBPORT
Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used
only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 048C
RXFUNCADDR
0x01E0 048E
RXHUBADDR
Address of the hub that has to be accessed through the associated Receive Endpoint. This is
used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 048F
RXHUBPORT
Port of the hub that has to be accessed through the associated Receive Endpoint. This is used
only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 0490
TXFUNCADDR
0x01E0 0492
TXHUBADDR
Address of the hub that has to be accessed through the associated Transmit Endpoint. This is
used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 0493
TXHUBPORT
Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used
only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 0494
RXFUNCADDR
0x01E0 0496
RXHUBADDR
Address of the hub that has to be accessed through the associated Receive Endpoint. This is
used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 0497
RXHUBPORT
Port of the hub that has to be accessed through the associated Receive Endpoint. This is used
only when full speed or low speed device is connected via a USB2.0 high-speed hub.
DYNAMIC FIFO CONTROL
Hardware Version Register
TARGET ENDPOINT 0 CONTROL REGISTERS, VALID ONLY IN HOST MODE
Address of the target function that has to be accessed through the associated Receive
Endpoint.
TARGET ENDPOINT 1 CONTROL REGISTERS, VALID ONLY IN HOST MODE
Address of the target function that has to be accessed through the associated Transmit
Endpoint.
Address of the target function that has to be accessed through the associated Receive
Endpoint.
TARGET ENDPOINT 2 CONTROL REGISTERS, VALID ONLY IN HOST MODE
Address of the target function that has to be accessed through the associated Transmit
Endpoint.
Address of the target function that has to be accessed through the associated Receive
Endpoint.
TARGET ENDPOINT 3 CONTROL REGISTERS, VALID ONLY IN HOST MODE
0x01E0 0498
TXFUNCADDR
0x01E0 049A
TXHUBADDR
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Address of the target function that has to be accessed through the associated Transmit
Endpoint.
Address of the hub that has to be accessed through the associated Transmit Endpoint. This is
used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
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ADVANCE INFORMATION
Address of the target function that has to be accessed through the associated Transmit
Endpoint.
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Table 6-85. Universal Serial Bus OTG (USB0) Registers (continued)
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
0x01E0 049B
TXHUBPORT
Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used
only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 049C
RXFUNCADDR
0x01E0 049E
RXHUBADDR
Address of the hub that has to be accessed through the associated Receive Endpoint. This is
used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 049F
RXHUBPORT
Port of the hub that has to be accessed through the associated Receive Endpoint. This is used
only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 04A0
TXFUNCADDR
0x01E0 04A2
TXHUBADDR
Address of the hub that has to be accessed through the associated Transmit Endpoint. This is
used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 04A3
TXHUBPORT
Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used
only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 04A4
RXFUNCADDR
0x01E0 04A6
RXHUBADDR
Address of the hub that has to be accessed through the associated Receive Endpoint. This is
used only when full speed or low speed device is connected via a USB2.0 high-speed hub.
0x01E0 04A7
RXHUBPORT
Port of the hub that has to be accessed through the associated Receive Endpoint. This is used
only when full speed or low speed device is connected via a USB2.0 high-speed hub.
Address of the target function that has to be accessed through the associated Receive
Endpoint.
TARGET ENDPOINT 4 CONTROL REGISTERS, VALID ONLY IN HOST MODE
ADVANCE INFORMATION
132
Address of the target function that has to be accessed through the associated Transmit
Endpoint.
Address of the target function that has to be accessed through the associated Receive
Endpoint.
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Table 6-85. Universal Serial Bus OTG (USB0) Registers (continued)
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
0x01E0 0502
PERI_CSR0
Control Status Register for Endpoint 0 in Peripheral Mode
HOST_CSR0
Control Status Register for Endpoint 0 in Host Mode
CONTROL AND STATUS REGISTER FOR ENDPOINT 0
0x01E0 0508
COUNT0
0x01E0 050A
HOST_TYPE0
0x01E0 050B
HOST_NAKLIMIT0
0x01E0 050F
CONFIGDATA
Number of Received Bytes in Endpoint 0 FIFO
Defines the Speed of Endpoint 0
Sets the NAK Response Timeout on Endpoint 0
Returns details of core configuration.
CONTROL AND STATUS REGISTER FOR ENDPOINT 1
0x01E0 0510
TXMAXP
0x01E0 0512
PERI_TXCSR
Maximum Packet Size for Peripheral/Host Transmit Endpoint
Control Status Register for Peripheral Transmit Endpoint (peripheral mode)
HOST_TXCSR
Control Status Register for Host Transmit Endpoint (host mode)
0x01E0 0514
RXMAXP
0x01E0 0516
PERI_RXCSR
Control Status Register for Peripheral Receive Endpoint (peripheral mode)
HOST_RXCSR
Control Status Register for Host Receive Endpoint (host mode)
RXCOUNT
0x01E0 051A
HOST_TXTYPE
0x01E0 051B
0x01E0 051C
0x01E0 051D
Number of Bytes in Host Receive endpoint FIFO
ADVANCE INFORMATION
0x01E0 0518
Maximum Packet Size for Peripheral/Host Receive Endpoint
Sets the operating speed, transaction protocol and peripheral endpoint number for the host
Transmit endpoint.
HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk
transactions for host Transmit endpoint.
HOST_RXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint number for the host
Receive endpoint.
HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk
transactions for host Receive endpoint.
CONTROL AND STATUS REGISTER FOR ENDPOINT 2
0x01E0 0520
TXMAXP
0x01E0 0522
PERI_TXCSR
Maximum Packet Size for Peripheral/Host Transmit Endpoint
Control Status Register for Peripheral Transmit Endpoint (peripheral mode)
HOST_TXCSR
Control Status Register for Host Transmit Endpoint (host mode)
0x01E0 0524
RXMAXP
0x01E0 0526
PERI_RXCSR
Control Status Register for Peripheral Receive Endpoint (peripheral mode)
HOST_RXCSR
Control Status Register for Host Receive Endpoint (host mode)
0x01E0 0528
RXCOUNT
0x01E0 052A
HOST_TXTYPE
0x01E0 052B
0x01E0 052C
0x01E0 052D
Maximum Packet Size for Peripheral/Host Receive Endpoint
Number of Bytes in Host Receive endpoint FIFO
Sets the operating speed, transaction protocol and peripheral endpoint number for the host
Transmit endpoint.
HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk
transactions for host Transmit endpoint.
HOST_RXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint number for the host
Receive endpoint.
HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk
transactions for host Receive endpoint.
CONTROL AND STATUS REGISTER FOR ENDPOINT 3
0x01E0 0530
0x01E0 0532
0x01E0 0534
0x01E0 0536
TXMAXP
Maximum Packet Size for Peripheral/Host Transmit Endpoint
PERI_TXCSR
Control Status Register for Peripheral Transmit Endpoint (peripheral mode)
HOST_TXCSR
Control Status Register for Host Transmit Endpoint (host mode)
RXMAXP
Maximum Packet Size for Peripheral/Host Receive Endpoint
PERI_RXCSR
Control Status Register for Peripheral Receive Endpoint (peripheral mode)
HOST_RXCSR
Control Status Register for Host Receive Endpoint (host mode)
0x01E0 0538
RXCOUNT
0x01E0 053A
HOST_TXTYPE
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Number of Bytes in Host Receive endpoint FIFO
Sets the operating speed, transaction protocol and peripheral endpoint number for the host
Transmit endpoint.
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Table 6-85. Universal Serial Bus OTG (USB0) Registers (continued)
BYTE ADDRESS
0x01E0 053B
0x01E0 053C
0x01E0 053D
ACRONYM
REGISTER DESCRIPTION
HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk
transactions for host Transmit endpoint.
HOST_RXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint number for the host
Receive endpoint.
HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk
transactions for host Receive endpoint.
CONTROL AND STATUS REGISTER FOR ENDPOINT 4
0x01E0 0540
TXMAXP
0x01E0 0542
PERI_TXCSR
Maximum Packet Size for Peripheral/Host Transmit Endpoint
Control Status Register for Peripheral Transmit Endpoint (peripheral mode)
HOST_TXCSR
Control Status Register for Host Transmit Endpoint (host mode)
0x01E0 0544
RXMAXP
0x01E0 0546
PERI_RXCSR
Control Status Register for Peripheral Receive Endpoint (peripheral mode)
HOST_RXCSR
Control Status Register for Host Receive Endpoint (host mode)
0x01E0 0548
RXCOUNT
0x01E0 054A
HOST_TXTYPE
ADVANCE INFORMATION
0x01E0 054B
0x01E0 054C
0x01E0 054D
Maximum Packet Size for Peripheral/Host Receive Endpoint
Number of Bytes in Host Receive endpoint FIFO
Sets the operating speed, transaction protocol and peripheral endpoint number for the host
Transmit endpoint.
HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk
transactions for host Transmit endpoint.
HOST_RXTYPE
Sets the operating speed, transaction protocol and peripheral endpoint number for the host
Receive endpoint.
HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk
transactions for host Receive endpoint.
DMA REGISTERS
0x01E0 1000
DMAREVID
DMA Revision Register
0x01E0 1004
TDFDQ
0x01E0 1008
DMAEMU
DMA Teardown Free Descriptor Queue Control Register
DMA Emulation Control Register
0x01E0 1800
TXGCR[0]
Transmit Channel 0 Global Configuration Register
Receive Channel 0 Global Configuration Register
0x01E0 1808
RXGCR[0]
0x01E0 180C
RXHPCRA[0]
Receive Channel 0 Host Packet Configuration Register A
0x01E0 1810
RXHPCRB[0]
Receive Channel 0 Host Packet Configuration Register B
0x01E0 1820
TXGCR[1]
Transmit Channel 1 Global Configuration Register
Receive Channel 1 Global Configuration Register
0x01E0 1828
RXGCR[1]
0x01E0 182C
RXHPCRA[1]
Receive Channel 1 Host Packet Configuration Register A
0x01E0 1830
RXHPCRB[1]
Receive Channel 1 Host Packet Configuration Register B
0x01E0 1840
TXGCR[2]
Transmit Channel 2 Global Configuration Register
0x01E0 1848
RXGCR[2]
Receive Channel 2 Global Configuration Register
0x01E0 184C
RXHPCRA[2]
Receive Channel 2 Host Packet Configuration Register A
0x01E0 1850
RXHPCRB[2]
Receive Channel 2 Host Packet Configuration Register B
0x01E0 1860
TXGCR[3]
Transmit Channel 3 Global Configuration Register
0x01E0 1868
RXGCR[3]
Receive Channel 3 Global Configuration Register
0x01E0 186C
RXHPCRA[3]
Receive Channel 3 Host Packet Configuration Register A
RXHPCRB[3]
Receive Channel 3 Host Packet Configuration Register B
0x01E0 1870
0x01E0 2C00
DMA_SCHED_CTRL DMA Scheduler Control Register
0x01E0 2D00
ENTRY[0]
DMA Scheduler Table Word 0
0x01E0 2D04
ENTRY[1]
DMA Scheduler Table Word 1
...
...
0x01E0 2DFC
ENTRY[63]
0x01E0 4000
QMGRREVID
...
DMA Scheduler Table Word 63
QUEUE MANAGER REGISTERS
134
Queue Manager Revision Register
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Table 6-85. Universal Serial Bus OTG (USB0) Registers (continued)
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
0x01E0 4008
DIVERSION
0x01E0 4020
FDBSC0
Free Descriptor/Buffer Starvation Count Register 0
0x01E0 4024
FDBSC1
Free Descriptor/Buffer Starvation Count Register 1
Queue Diversion Register
0x01E0 4028
FDBSC2
Free Descriptor/Buffer Starvation Count Register 2
0x01E0 402C
FDBSC3
Free Descriptor/Buffer Starvation Count Register 3
0x01E0 4080
LRAM0BASE
Linking RAM Region 0 Base Address Register
0x01E0 4084
LRAM0SIZE
Linking RAM Region 0 Size Register
0x01E0 4088
LRAM1BASE
Linking RAM Region 1 Base Address Register
0x01E0 4090
PEND0
Queue Pending Register 0
0x01E0 4094
PEND1
Queue Pending Register 1
0x01E0 5000
QMEMRBASE[0]
Memory Region 0 Base Address Register
0x01E0 5004
QMEMRCTRL[0]
Memory Region 0 Control Register
0x01E0 5010
QMEMRBASE[1]
Memory Region 1 Base Address Register
0x01E0 5014
QMEMRCTRL[1]
Memory Region 1 Control Register
...
...
0x01E0 5070
QMEMRBASE[7]
Memory Region 7 Base Address Register
Memory Region 7 Control Register
0x01E0 5074
QMEMRCTRL[7]
0x01E0 600C
CTRLD[0]
Queue Manager Queue 0 Control Register D
0x01E0 601C
CTRLD[1]
Queue Manager Queue 1 Control Register D
...
...
...
0x01E0 63FC
CTRLD[63]
Queue Manager Queue 63 Status Register D
0x01E0 6800
QSTATA[0]
Queue Manager Queue 0 Status Register A
0x01E0 6804
QSTATB[0]
Queue Manager Queue 0 Status Register B
0x01E0 6808
QSTATC[0]
Queue Manager Queue 0 Status Register C
0x01E0 6810
QSTATA[1]
Queue Manager Queue 1 Status Register A
0x01E0 6814
QSTATB[1]
Queue Manager Queue 1 Status Register B
0x01E0 6818
QSTATC[1]
Queue Manager Queue 1 Status Register C
...
...
0x01E0 6BF0
QSTATA[63]
Queue Manager Queue 63 Status Register A
0x01E0 6BF4
QSTATB[63]
Queue Manager Queue 63 Status Register B
0x01E0 6BF8
QSTATC[63]
Queue Manager Queue 63 Status Register C
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ADVANCE INFORMATION
...
...
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6.25.1 USB2.0 (USB0) Electrical Data/Timing
Table 6-86. Switching Characteristics Over Recommended Operating Conditions for USB2.0 [USB0] (see
Figure 6-46)
No.
PARAMETER
LOW SPEED
1.5 Mbps
FULL SPEED
12 Mbps
HIGH SPEED
480 Mbps
MIN
MAX
MIN
MAX
MIN
1
tr(D)
Rise time, USB0_DP and USB0_DM signals (1)
75
300
4
20
0.5
2
tf(D)
Fall time, USB0_DP and USB0_DM signals (1)
75
300
4
20
0.5
3
trfM
Rise/Fall time, matching (2)
80
120
90
111
–
–
1.3
2
1.3
2
–
–
(1)
UNIT
MAX
ns
ns
%
4
VCRS
Output signal cross-over voltage
5
tjr(source)NT
Source (Host) Driver jitter, next transition
2
2
tjr(FUNC)NT
Function Driver jitter, next transition
25
2
(3)
ns
tjr(source)PT
Source (Host) Driver jitter, paired transition (4)
1
1
(3)
ns
tjr(FUNC)PT
Function Driver jitter, paired transition
10
1
(3)
ns
tw(EOPT)
Pulse duration, EOP transmitter
–
ns
8
tw(EOPR)
Pulse duration, EOP receiver
(5)
9
t(DRATE)
Data Rate
480
Mb/s
10
ZDRV
Driver Output Resistance
–
40.5
49.5
Ω
11
ZINP
Receiver Input Impedance
100k
-
-
Ω
6
7
ADVANCE INFORMATION
(1)
(2)
(3)
(4)
(5)
(5)
1250
1500
670
160
175
82
1.5
–
ns
–
–
12
40.5
49.5
100k
V
(3)
ns
Low Speed: CL = 200 pF, Full Speed: CL = 50 pF, High Speed: CL = 50 pF
tRFM = (tr/tf) x 100. [Excluding the first transaction from the Idle state.]
For more detailed information, see the Universal Serial Bus Specification Revision 2.0, Chapter 7. Electrical.
tjr = tpx(1) - tpx(0)
Must accept as valid EOP
USB0_DM
VCRS
USB0_DP
tper - tjr
90% VOH
10% VOL
tr
tf
Figure 6-46. USB0 Integrated Transceiver Interface Timing
6.25.2 USB0 Unused Signal Configuration
If USB0 is unused, then the USB0 signals should be configured as shown below in Table 6-1.
136
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6.26 Power and Sleep Controller (PSC)
The Power and Sleep Controllers (PSC) are responsible for managing transitions of system power on/off,
clock on/off, resets (device level and module level). It is used primarily to provide granular power control
for on chip modules (peripherals and CPU). A PSC module consists of a Global PSC (GPSC) and a set of
Local PSCs (LPSCs). The GPSC contains memory mapped registers, PSC interrupts, a state machine for
each peripheral/module it controls. An LPSC is associated with every module that is controlled by the PSC
and provides clock and reset control.
The PSC includes the following features:
• Provides a software interface to:
– Control module clock enable/disable
– Control module reset
– Control CPU local reset
• Supports ICEpick TAP Router power, clock and reset features. For details on ICEpick features see
http://tiexpressdsp.com/wiki/index.php?title=ICEPICK.
PSC0
BYTE ADDRESS
PSC1
BYTE ADDRESS
ACRONYM
0x01C1 0000
0x01E2 7000
REVID
0x01C1 0018
0x01E2 7018
INTEVAL
0x01C1 0040
0x01E2 7040
MERRPR0
DESCRIPTION
Peripheral Revision and Class Information Register
Interrupt Evaluation Register
Module Error Pending Register 0 (module 0-15)
(PSC0)
Module Error Pending Register 0 (module 0-31)
(PSC1)
0x01C1 0050
0x01E2 7050
MERRCR0
Module Error Clear Register 0 (module 0-15) (PSC0)
0x01C1 0060
0x01E2 7060
PERRPR
Power Error Pending Register
0x01C1 0068
0x01E2 7068
PERRCR
Power Error Clear Register
0x01C1 0120
0x01E2 7120
PTCMD
Power Domain Transition Command Register
0x01C1 0128
0x01E2 7128
PTSTAT
Power Domain Transition Status Register
0x01C1 0200
0x01E2 7200
PDSTAT0
Power Domain 0 Status Register
0x01C1 0204
0x01E2 7204
PDSTAT1
Power Domain 1 Status Register
0x01C1 0300
0x01E2 7300
PDCTL0
Power Domain 0 Control Register
0x01C1 0304
0x01E2 7304
PDCTL1
Power Domain 1 Control Register
0x01C1 0400
0x01E2 7400
PDCFG0
Power Domain 0 Configuration Register
PDCFG1
Power Domain 1 Configuration Register
Module Error Clear Register 0 (module 0-31) (PSC1)
0x01C1 0404
0x01E2 7404
0x01C1 08000x01C1 083C
0x01E2 78000x01E2 787C
0x01C1 0A000x01C1 0A3C
0x01E2 7A000x01E2 7A7C
MDSTAT0-MDSTAT15 Module Status n Register (modules 0-15) (PSC0)
MDSTAT0-MDSTAT31 Module Status n Register (modules 0-31) (PSC1)
MDCTL0-MDCTL15
Module Control n Register (modules 0-15) (PSC0)
MDCTL0-MDCTL31
Module Control n Register (modules 0-31) (PSC1)
6.26.1 Power Domain and Module Topology
The device includes two PSC modules.
Each PSC module controls clock states for several of the on chip modules, controllers and interconnect
components. Table 6-88 and Table 6-89 lists the set of peripherals/modules that are controlled by the
PSC, the power domain they are associated with, the LPSC assignment and the default (power-on reset)
module states. See the device-specific data manual for the peripherals available on a given device. The
module states and terminology are defined in Section 6.26.1.1.
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Table 6-87. Power and Sleep Controller (PSC) Registers
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Table 6-88. PSC0 Default Module Configuration
ADVANCE INFORMATION
LPSC Number
Module Name
Power Domain
Default Module State
Auto Sleep/Wake Only
0
EDMA3 Channel Controller
AlwaysON (PD0)
SwRstDisable
—
1
EDMA3 Transfer Controller 0
AlwaysON (PD0)
SwRstDisable
—
2
EDMA3 Transfer Controller 1
AlwaysON (PD0)
SwRstDisable
—
3
EMIFA (BR7)
AlwaysON (PD0)
SwRstDisable
—
4
SPI 0
AlwaysON (PD0)
SwRstDisable
—
5
MMC/SD 0
AlwaysON (PD0)
SwRstDisable
—
6
ARM Interrupt Controller
AlwaysON (PD0)
SwRstDisable
—
7
ARM RAM/ROM
AlwaysON (PD0)
Enable
Yes
8
-
-
-
-
9
UART 0
AlwaysON (PD0)
SwRstDisable
—
10
SCR0 (Br 0, Br 1, Br 2, Br 8)
AlwaysON (PD0)
Enable
Yes
11
SCR1 (Br 4)
AlwaysON (PD0)
Enable
Yes
12
SCR2 (Br 3, Br 5, Br 6)
AlwaysON (PD0)
Enable
Yes
13
PRUSS
AlwaysON (PD0)
SwRstDisable
—
14
ARM
AlwaysON (PD0)
SwRstDisable
—
15
-
-
-
—
Table 6-89. PSC1 Default Module Configuration
LPSC Number
Module Name
Power Domain
Default Module State
Auto Sleep/Wake Only
0
Not Used
—
—
—
1
USB0 (USB2.0)
AlwaysON (PD0)
SwRstDisable
—
2
Not Used
—
—
—
3
GPIO
AlwaysON (PD0)
SwRstDisable
—
4
Not Used
—
—
—
5
EMAC
AlwaysON (PD0)
SwRstDisable
—
6
EMIFB (Br 20)
AlwaysON (PD0)
SwRstDisable
—
7
McASP0 ( + McASP0 FIFO)
AlwaysON (PD0)
SwRstDisable
—
8
McASP1 ( + McASP1 FIFO)
AlwaysON (PD0)
SwRstDisable
—
9
Not Used
—
—
—
10
SPI 1
AlwaysON (PD0)
SwRstDisable
—
11
I2C 1
AlwaysON (PD0)
SwRstDisable
—
12
UART 1
AlwaysON (PD0)
SwRstDisable
—
13
UART 2
AlwaysON (PD0)
SwRstDisable
—
14-15
Not Used
—
—
—
16
Not Used
—
—
—
17
eHRPWM0/1/2
AlwaysON (PD0)
SwRstDisable
—
18-19
Not Used
—
—
—
20
ECAP0/1/2
AlwaysON (PD0)
SwRstDisable
—
21
EQEP0/1
AlwaysON (PD0)
SwRstDisable
—
22-23
Not Used
—
—
—
24
SCR8 (Br 15)
AlwaysON (PD0)
Enable
Yes
25
SCR7 (Br 12)
AlwaysON (PD0)
Enable
Yes
26
SCR12 (Br 18)
AlwaysON (PD0)
Enable
Yes
27-30
Not Used
—
—
—
31
On-chip RAM (Br 13)
PD_SHRAM
Enable
Yes
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6.26.1.1 Module States
The PSC defines several possible states for a module. This states are essentially a combination of the
module reset asserted or de-asserted and module clock on/enabled or off/disabled. The module states are
defined in Table 6-90.
Module State
Module Reset
Module Clock
Module State Definition
Enable
De-asserted
On
A module in the enable state has its module reset de-asserted and it has its
clock on. This is the normal operational state for a given module
Disable
De-asserted
Off
A module in the disabled state has its module reset de-asserted and it has its
module clock off. This state is typically used for disabling a module clock to
save power. The device is designed in full static CMOS, so when you stop a
module clock, it retains the module’s state. When the clock is restarted, the
module resumes operating from the stopping point.
SyncReset
Asserted
On
A module state in the SyncReset state has its module reset asserted and it has
its clock on. Generally, software is not expected to initiate this state
SwRstDisable
Asserted
Off
A module in the SwResetDisable state has its module reset asserted and it has
its clock disabled. After initial power-on, several modules come up in the
SwRstDisable state. Generally, software is not expected to initiate this state
Auto Sleep
De-asserted
Off
A module in the Auto Sleep state also has its module reset de-asserted and its
module clock disabled, similar to the Disable state. However this is a special
state, once a module is configured in this state by software, it can
“automatically” transition to “Enable” state whenever there is an internal
read/write request made to it, and after servicing the request it will
“automatically” transition into the sleep state (with module reset re de-asserted
and module clock disabled), without any software intervention. The transition
from sleep to enabled and back to sleep state has some cycle latency
associated with it. It is not envisioned to use this mode when peripherals are
fully operational and moving data.
Auto Wake
De-asserted
Off
A module in the Auto Wake state also has its module reset de-asserted and its
module clock disabled, similar to the Disable state. However this is a special
state, once a module is configured in this state by software, it will
“automatically” transition to “Enable” state whenever there is an internal
read/write request made to it, and will remain in the “Enabled” state from then
on (with module reset re de-asserted and module clock on), without any
software intervention. The transition from sleep to enabled state has some
cycle latency associated with it. It is not envisioned to use this mode when
peripherals are fully operational and moving data.
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Table 6-90. Module States
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6.27 Programmable Real-Time Unit Subsystem (PRUSS)
The Programmable Real-Time Unit Subsystem (PRUSS) consists of
• Two Programmable Real-Time Units (PRU0 and PRU1) and their associated memories
• An Interrupt Controller (INTC) for handling system interrupt events. The INTC also supports posting
events back to the device level host CPU.
• A Switched Central Resource (SCR) for connecting the various internal and external masters to the
resources inside the PRUSS.
The two PRUs can operate completely independently or in coordination with each other. The PRUs can
also work in coordination with the device level host CPU. This is determined by the nature of the program
which is loaded into the PRUs instruction memory. Several different signaling mechanisms are available
between the two PRUs and the device level host CPU.
The PRUs are optimized for performing embedded tasks that require manipulation of packed memory
mapped data structures, handling of system events that have tight realtime constraints and interfacing with
systems external to the device.
ADVANCE INFORMATION
The PRUSS comprises various distinct addressable regions. Externally the subsystem presents a single
64Kbyte range of addresses. The internal interconnect bus (also called switched central resource, or SCR)
of the PRUSS decodes accesses for each of the individual regions. The PRUSS memory map is
documented in Table 6-91 and in Table 6-92. Note that these two memory maps are implemented inside
the PRUSS and are local to the components of the PRUSS.
Table 6-91. Programmable Real-Time Unit Subsystem (PRUSS) Local Instruction Space Memory Map
BYTE ADDRESS
PRU0
PRU1
0x0000 0000 - 0x0000 0FFF
PRU0 Instruction RAM
PRU1 Instruction RAM
Table 6-92. Programmable Real-Time Unit Subsystem (PRUSS) Local Data Space Memory Map
BYTE ADDRESS
0x0000 0000 - 0x0000 01FF
(1)
PRU0
Data RAM 0
0x0000 0200 - 0x0000 1FFF
Reserved
0x0000 2000 - 0x0000 21FF
Data RAM 1
PRU1
(1)
Data RAM 1
(1)
Data RAM 0
(1)
Reserved
(1)
0x0000 2200 - 0x0000 3FFF
Reserved
Reserved
0x0000 4000 - 0x0000 6FFF
INTC Registers
INTC Registers
0x0000 7000 - 0x0000 73FF
PRU0 Control Registers
PRU0 Control Registers
0x0000 7400 - 0x0000 77FF
Reserved
Reserved
0x0000 7800 - 0x0000 7BFF
PRU1 Control Registers
PRU1 Control Registers
0x0000 7C00 - 0xFFFF FFFF
Reserved
Reserved
Note that PRU0 accesses Data RAM0 at address 0x0000 0000, also PRU1 accesses Data RAM1 at address 0x0000 0000. Data RAM0
is intended to be the primary data memory for PRU0 and Data RAM1 is intended to be the primary data memory for PRU1. However for
passing information between PRUs, each PRU can access the data ram of the ‘other’ PRU through address 0x0000 2000.
The global view of the PRUSS internal memories and control ports is documented in Table 6-93. The
offset addresses of each region are implemented inside the PRUSS but the global device memory
mapping places the PRUSS slave port in the address range 0x01C3 0000-0x01C3 FFFF. The PRU0 and
PRU1 can use either the local or global addresses to access their internal memories, but using the local
addresses will provide access time several cycles faster than using the global addresses. This is because
when accessing via the global address the access needs to be routed through the switch fabric outside
PRUSS and back in through the PRUSS slave port.
Table 6-93. Programmable Real-Time Unit Subsystem (PRUSS) Global Memory Map
140
BYTE ADDRESS
REGION
0x01C3 0000 - 0x01C3 01FF
Data RAM 0
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Table 6-93. Programmable Real-Time Unit Subsystem (PRUSS) Global Memory Map (continued)
BYTE ADDRESS
REGION
0x01C3 0200 - 0x01C3 1FFF
Reserved
0x01C3 2000 - 0x01C3 21FF
Data RAM 1
0x01C3 2200 - 0x01C3 3FFF
Reserved
0x01C3 4000 - 0x01C3 6FFF
INTC Registers
0x01C3 7000 - 0x01C3 73FF
PRU0 Control Registers
0x01C3 7400 - 0x01C3 77FF
PRU0 Debug Registers
0x01C3 7800 - 0x01C3 7BFF
PRU1 Control Registers
0x01C3 7C00 - 0x01C3 7FFF
PRU1 Debug Registers
0x01C3 8000 - 0x01C3 8FFF
PRU0 Instruction RAM
0x01C3 9000 - 0x01C3 BFFF
Reserved
0x01C3 C000 - 0x01C3 CFFF
PRU1 Instruction RAM
0x01C3 D000 - 0x01C3 FFFF
Reserved
6.27.1 PRUSS Register Descriptions
Table 6-94. Programmable Real-Time Unit Subsystem (PRUSS) Control / Status Registers
PRU0 BYTE ADDRESS
PRU1 BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
0x01C3 7000
0x01C3 7800
CONTROL
PRU Control Register
0x01C3 7004
0x01C3 7804
STATUS
PRU Status Register
0x01C3 7008
0x01C3 7808
WAKEUP
PRU Wakeup Enable Register
0x01C3 700C
0x01C3 780C
CYCLCNT
PRU Cycle Count
0x01C3 7010
0x01C3 7810
STALLCNT
PRU Stall Count
0x01C3 7020
0x01C3 7820
CONTABBLKIDX0
0x01C3 7028
0x01C3 7828
CONTABPROPTR0
PRU Constant Table Programmable
Pointer Register 0
0x01C3 702C
0x01C3 782C
CONTABPROPTR1
PRU Constant Table Programmable
Pointer Register 1
0x01C37400 - 0x01C3747C
0x01C3 7C00 - 0x01C3 7C7C
INTGPR0 – INTGPR31
PRU Internal General Purpose
Registers (for Debug)
0x01C37480 - 0x01C374FC
0x01C3 7C80 - 0x01C3 7CFC
INTCTER0 – INTCTER31
PRU Internal Constants Table
Registers (for Debug)
PRU Constant Table Block Index
Register 0
Table 6-95. Programmable Real-Time Unit Subsystem Interrupt Controller (PRUSS INTC) Registers
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
0x01C3 4000
REVID
0x01C3 4004
CONTROL
0x01C3 4010
GLBLEN
0x01C3 401C
GLBLNSTLVL
Global Nesting Level Register
0x01C3 4020
STATIDXSET
System Interrupt Status Indexed Set Register
0x01C3 4024
STATIDXCLR
System Interrupt Status Indexed Clear Register
0x01C3 4028
ENIDXSET
System Interrupt Enable Indexed Set Register
0x01C3 402C
ENIDXCLR
System Interrupt Enable Indexed Clear Register
0x01C3 4034
HSTINTENIDXSET
Host Interrupt Enable Indexed Set Register
0x01C3 4038
HSTINTENIDXCLR
Host Interrupt Enable Indexed Clear Register
0x01C3 4080
GLBLPRIIDX
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Revision ID Register
Control Register
Global Enable Register
Global Prioritized Index Register
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Each of the PRUs can access the rest of the device memory (including memory mapped peripheral and
configuration registers) using the global memory space addresses
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Table 6-95. Programmable Real-Time Unit Subsystem Interrupt Controller (PRUSS INTC)
Registers (continued)
ADVANCE INFORMATION
142
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
0x01C3 4200
STATSETINT0
System Interrupt Status Raw/Set Register 0
0x01C3 4204
STATSETINT1
System Interrupt Status Raw/Set Register 1
0x01C3 4280
STATCLRINT0
System Interrupt Status Enabled/Clear Register 0
0x01C3 4284
STATCLRINT1
System Interrupt Status Enabled/Clear Register 1
0x01C3 4300
ENABLESET0
System Interrupt Enable Set Register 0
0x01C3 4304
ENABLESET1
System Interrupt Enable Set Register 1
0x01C3 4380
ENABLECLR0
System Interrupt Enable Clear Register 0
System Interrupt Enable Clear Register 1
0x01C3 4384
ENABLECLR1
0x01C3 4400 - 0x01C3 4440
CHANMAP0 - CHANMAP15
0x01C3 4800 - 0x01C3 4808
HOSTMAP0 - HOSTMAP2
0x01C3 4900 - 0x01C3 4928
HOSTINTPRIIDX0 HOSTINTPRIIDX9
0x01C3 4D00
POLARITY0
System Interrupt Polarity Register 0
0x01C3 4D04
POLARITY1
System Interrupt Polarity Register 1
0x01C3 4D80
TYPE0
System Interrupt Type Register 0
0x01C3 4D84
TYPE1
System Interrupt Type Register 1
0x01C3 5100 - 0x01C3 5128
HOSTINTNSTLVL0HOSTINTNSTLVL9
0x01C3 5500
HOSTINTEN
Channel Map Registers 0-15
Host Map Register 0-2
Host Interrupt Prioritized Index Registers 0-9
Host Interrupt Nesting Level Registers 0-9
Host Interrupt Enable Register
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6.28 Emulation Logic
This section describes the steps to use a third party debugger. The debug capabilities and features for
ARM are as shown below.
For TI’s latest debug and emulation information see :
http://tiexpressdsp.com/wiki/index.php?title=Category:Emulation
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ARM:
• Basic Debug
– Execution Control
– System Visibility
• Advanced Debug
– Global Start
– Global Stop
• Advanced System Control
– Subsystem reset via debug
– Peripheral notification of debug events
– Cache-coherent debug accesses
• Program Trace
– Program flow corruption
– Code coverage
– Path coverage
– Thread/interrupt synchronization problems
• Data Trace
– Memory corruption
• Timing Trace
– Profiling
• Analysis Actions
– Stop program execution
– Control trace streams
– Generate debug interrupt
– Benchmarking with counters
– External trigger generation
– Debug state machine state transition
– Combinational and Sequential event generation
• Analysis Events
– Program event detection
– Data event detection
– External trigger Detection
– System event detection (i.e. cache miss)
– Debug state machine state detection
• Analysis Configuration
– Application access
– Debugger access
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Table 6-96. ARM Debug Features
Category
Hardware Feature
Availability
Software breakpoint
Unlimited
Up to 14 HWBPs, including:
Basic Debug
2 precise (1) HWBP inside ARM core which are shared
with watch points.
Hardware breakpoint
8 imprecise (1) HWBPs from ETM’s address comparators,
which are shared with trace function, and can be used
as watch point too.
4 imprecise (1) HWBPs from ICECrusher.
Up to 6 watch points, including:
Watch point
2 from ARM core which is shared with HWBPs and can
be associated with a data.
8 from ETM’s address comparators, which are shared
with trace function, and HWBPs.
2 from ARM core which is shared with HWBPs.
Analysis
ADVANCE INFORMATION
Trace Control
On-chip Trace
Capture
(1)
144
Watch point with Data
8 watch points from ETM can be associated with a data
comparator, and ETM has total 4 data comparators.
Counters/timers
3x32-bit (1 cycle ; 2 event)
External Event Trigger In
1
External Event Trigger Out
1
Address range for trace
4
Data qualification for trace
2
System events for trace control
20
Counters/Timers for trace control
2x16-bit
State Machines/Sequencers
1x3-State State Machine
Context/Thread ID Comparator
1
Independent trigger control units
12
Capture depth PC
4k bytes ETB
Capture depth PC + Timing
4k bytes ETB
Application accessible
Y
Precise hardware breakpoints will halt the processor immediately prior to the execution of the selected instruction. Imprecise breakpoints
will halt the processor some number of cycles after the selected instruction depending on device conditions.
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6.28.1 JTAG Port Description
The device target debug interface uses the five standard IEEE 1149.1(JTAG) signals (TRST, TCK, TMS,
TDI, and TDO), a return clock (RTCK) due to the clocking requirements of the ARM926EJ-S and EMU0 .
TRST holds the debug and boundary scan logic in reset when pulled low (its default state). Since TRST
has an internal pull-down resistor, this ensures that at power up the device functions in its normal
(non-test) operation mode if TRST is not connected. Otherwise, TRST should be driven inactive by the
emulator or boundary scan controller. Boundary scan test cannot be performed while the TRST pin is
pulled low.
Table 6-97. JTAG Port Description
TYPE
NAME
DESCRIPTION
When asserted (active low) causes all test and debug logic in the device to be reset along
with the IEEE 1149.1 interface
TRST
I
Test Logic Reset
TCK
I
Test Clock
RTCK
O
Returned Test Clock
TMS
I
Test Mode Select
TDI
I
Test Data Input
TDO
O
Test Data Output
EMU0
I/O
Emulation 0
This is the test clock used to drive an IEEE 1149.1 TAP state machine and logic.
Depending on the emulator attached to , this is a free running clock or a gated clock
depending on RTCK monitoring.
Synchronized TCK. Depending on the emulator attached to, the JTAG signals are clocked
from RTCK or RTCK is monitored by the emulator to gate TCK.
Directs the next state of the IEEE 1149.1 test access port state machine
Scan data input to the device
Scan data output of the device
Channel 0 trigger + HSRTDX
6.28.2 Scan Chain Configuration Parameters
Table 6-98 shows the TAP configuration details required to configure the router/emulator for this device.
Table 6-98. JTAG Port Description
Router Port ID
Default TAP
TAP Name
Tap IR Length
17
No
Reserved
38
18
No
ARM926
4
19
No
ETB
4
The router is ICEpick revision C and has a 6-bit IR length.
6.28.3 Initial Scan Chain Configuration
The first level of debug interface that sees the scan controller is the TAP router module. The debugger
can configure the TAP router for serially linking up to 16 TAP controllers or individually scanning one of
the TAP controllers without disrupting the IR state of the other TAPs.
6.28.3.1 Adding TAPS to the Scan Chain
The TAP router must be programmed to add additional TAPs to the scan chain. The following JTAG scans
must be completed to add the ARM926EJ-S to the scan chain.
A Power-On Reset (POR) or the JTAG Test-Logic Reset state configures the TAP router to contain only
the router’s TAP.
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Router
TDO
TDI
CLK
Steps
TMS
Router
ARM926EJ-S/ETM
Figure 6-47. Adding ARM926EJ-S to the scan chain
Pre-amble: The device whose data reaches the emulator first is listed first in the board configuration file.
This device is a pre-amble for all the other devices. This device has the lowest device ID.
ADVANCE INFORMATION
Post-amble: The device whose data reaches the emulator last is listed last in the board configuration file.
This device is a post-amble for all the other devices. This device has the highest device ID.
• Function : Update the JTAG preamble and post-amble counts.
– Parameter : The IR pre-amble count is '0'.
– Parameter : The IR post-amble count is '0'.
– Parameter : The DR pre-amble count is '0'.
– Parameter : The DR post-amble count is '0'.
– Parameter : The IR main count is '6'.
– Parameter : The DR main count is '1'.
• Function : Do a send-only JTAG IR/DR scan.
– Parameter : The route to JTAG shift state is 'shortest transition'.
– Parameter : The JTAG shift state is 'shift-ir'.
– Parameter : The JTAG destination state is 'pause-ir'.
– Parameter : The bit length of the command is '6'.
– Parameter : The send data value is '0x00000007'.
– Parameter : The actual receive data is 'discarded'.
• Function : Do a send-only JTAG IR/DR scan.
– Parameter : The route to JTAG shift state is 'shortest transition'.
– Parameter : The JTAG shift state is 'shift-dr'.
– Parameter : The JTAG destination state is 'pause-dr'.
– Parameter : The bit length of the command is '8'.
– Parameter : The send data value is '0x00000089'.
– Parameter : The actual receive data is 'discarded'.
• Function : Do a send-only JTAG IR/DR scan.
– Parameter : The route to JTAG shift state is 'shortest transition'.
– Parameter : The JTAG shift state is 'shift-ir'.
– Parameter : The JTAG destination state is 'pause-ir'.
– Parameter : The bit length of the command is '6'.
– Parameter : The send data value is '0x00000002'.
– Parameter : The actual receive data is 'discarded'.
• Function : Embed the port address in next command.
– Parameter : The port address field is '0x0f000000'.
– Parameter : The port address value is '3'.
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Function : Do a send-only JTAG IR/DR scan.
– Parameter : The route to JTAG shift state is 'shortest transition'.
– Parameter : The JTAG shift state is 'shift-dr'.
– Parameter : The JTAG destination state is 'pause-dr'.
– Parameter : The bit length of the command is '32'.
– Parameter : The send data value is '0xa2002108'.
– Parameter : The actual receive data is 'discarded'.
Function : Do a send-only all-ones JTAG IR/DR scan.
– Parameter : The JTAG shift state is 'shift-ir'.
– Parameter : The JTAG destination state is 'run-test/idle'.
– Parameter : The bit length of the command is '6'.
– Parameter : The send data value is 'all-ones'.
– Parameter : The actual receive data is 'discarded'.
Function : Wait for a minimum number of TCLK pulses.
– Parameter : The count of TCLK pulses is '10'.
Function : Update the JTAG preamble and post-amble counts.
– Parameter : The IR pre-amble count is '0'.
– Parameter : The IR post-amble count is '6'.
– Parameter : The DR pre-amble count is '0'.
– Parameter : The DR post-amble count is '1'.
– Parameter : The IR main count is '4'.
– Parameter : The DR main count is '1'.
The initial scan chain contains only the TAP router module. The following steps must be completed in
order to add ETB TAP to the scan chain.
Router
TDI
ARM926EJ-S/ETM
TDO
CLK
Steps
TMS
Router
•
•
ARM926EJ-S/ETM
ETB
Figure 6-48. Adding ETB to the scan chain
Function : Do a send-only JTAG IR/DR scan.
– Parameter : The route to JTAG shift state is 'shortest transition'.
– Parameter : The JTAG shift state is 'shift-ir'.
– Parameter : The JTAG destination state is 'pause-ir'.
– Parameter : The bit length of the command is '6'.
– Parameter : The send data value is '0x00000007'.
– Parameter : The actual receive data is 'discarded'.
Function : Do a send-only JTAG IR/DR scan.
– Parameter : The route to JTAG shift state is 'shortest transition'.
– Parameter : The JTAG shift state is 'shift-dr'.
– Parameter : The JTAG destination state is 'pause-dr'.
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•
•
•
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•
•
•
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– Parameter : The bit length of the command is '8'.
– Parameter : The send data value is '0x00000089'.
– Parameter : The actual receive data is 'discarded'.
Function : Do a send-only JTAG IR/DR scan.
– Parameter : The route to JTAG shift state is 'shortest transition'.
– Parameter : The JTAG shift state is 'shift-ir'.
– Parameter : The JTAG destination state is 'pause-ir'.
– Parameter : The bit length of the command is '6'.
– Parameter : The send data value is '0x00000002'.
– Parameter : The actual receive data is 'discarded'.
Function : Embed the port address in next command.
– Parameter : The port address field is '0x0f000000'.
– Parameter : The port address value is '3'.
Function : Do a send-only JTAG IR/DR scan.
– Parameter : The route to JTAG shift state is 'shortest transition'.
– Parameter : The JTAG shift state is 'shift-dr'.
– Parameter : The JTAG destination state is 'pause-dr'.
– Parameter : The bit length of the command is '32'.
– Parameter : The send data value is '0xa3302108'.
– Parameter : The actual receive data is 'discarded'.
Function : Do a send-only all-ones JTAG IR/DR scan.
– Parameter : The JTAG shift state is 'shift-ir'.
– Parameter : The JTAG destination state is 'run-test/idle'.
– Parameter : The bit length of the command is '6'.
– Parameter : The send data value is 'all-ones'.
– Parameter : The actual receive data is 'discarded'.
Function : Wait for a minimum number of TCLK pulses.
– Parameter : The count of TCLK pulses is '10'.
Function : Update the JTAG preamble and post-amble counts.
– Parameter : The IR pre-amble count is '0'.
– Parameter : The IR post-amble count is '6 + 4'.
– Parameter : The DR pre-amble count is '0'.
– Parameter : The DR post-amble count is '1 + 1'.
– Parameter : The IR main count is '4'.
– Parameter : The DR main count is '1'.
6.28.4 JTAG 1149.1 Boundary Scan Considerations
To
•
•
•
use boundary scan, the following sequence should be followed:
Execute a valid reset sequence and exit reset
Wait at least 6000 OSCIN clock cycles
Enter boundary scan mode using the JTAG pins
No specific value is required on the EMU0 pin for boundary scan testing. If TRST is not driven by the
boundary scan tool or tester, TRST should be externally pulled high during boundary scan testing.
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6.29 IEEE 1149.1 JTAG
The JTAG (1) interface is used for BSDL testing and emulation of the device.
The device requires that both TRST and RESET be asserted upon power up to be properly initialized.
While RESET initializes the device, TRST initializes the device's emulation logic. Both resets are required
for proper operation.
While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for
the device to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG
port interface and device's emulation logic in the reset state.
TRST only needs to be released when it is necessary to use a JTAG controller to debug the device or
exercise the device's boundary scan functionality. Note: TRST is synchronous and must be clocked by
TCK; otherwise, the boundary scan logic may not respond as expected after TRST is asserted.
For maximum reliability, the device includes an internal pulldown (IPD) on the TRST pin to ensure that
TRST will always be asserted upon power up and the device's internal emulation logic will always be
properly initialized.
JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG
controllers may not drive TRST high but expect the use of a pullup resistor on TRST.
When using this type of JTAG controller, assert TRST to initialize the device after powerup and externally
drive TRST high before attempting any emulation or boundary scan operations.
6.29.1
JTAG Peripheral Register Description(s) – JTAG ID Register (DEVIDR0)
Table 6-99. DEVIDR0 Register
(1)
BYTE ADDRESS
ACRONYM
0x01C1 4018
DEVIDR0
REGISTER DESCRIPTION
JTAG Identification Register
COMMENTS
Read-only. Provides 32-bit JTAG ID of the device.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the
device, the JTAG ID register resides at address location 0x01C1 4018. The register hex value for each
silicon revision is:
• 0x8B7D F02F for silicon revision 1.1
• 0x9B7D F02F for silicon revision 2.0
For the actual register bit names and their associated bit field descriptions, see Figure 6-49 and
Table 6-100.
31-28
27-12
11-1
0
VARIANT (4-Bit)
PART NUMBER (16-Bit)
MANUFACTURER (11-Bit)
LSB
R-xxxx
R-1011 0111 1101 1111
R-0000 0010 111
R-1
LEGEND: R = Read, W = Write, n = value at reset
Figure 6-49. JTAG ID (DEVIDR0) Register Description - Register Value
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RESET must be released only in order for boundary-scan JTAG to read the variant field of IDCODE
correctly. Other boundary-scan instructions work correctly independent of current state of RESET.
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Table 6-100. JTAG ID Register Selection Bit Descriptions
BIT
NAME
31:28
VARIANT
27:12
PART NUMBER
Part Number (16-Bit) value
11-1
MANUFACTURER
Manufacturer (11-Bit) value
0
LSB
6.29.2
DESCRIPTION
Variant (4-Bit) value
LSB. This bit is read as a "1".
JTAG Test-Port Electrical Data/Timing
Table 6-101. Timing Requirements for JTAG Test Port (see Figure 6-50)
No.
PARAMETER
MIN
MAX
UNIT
ADVANCE INFORMATION
1
tc(TCK)
Cycle time, TCK
40
ns
2
tw(TCKH)
Pulse duration, TCK high
16
ns
3
tw(TCKL)
Pulse duration, TCK low
16
ns
4
tc(RTCK)
Cycle time, RTCK
40
ns
5
tw(RTCKH)
Pulse duration, RTCK high
16
ns
6
tw(RTCKL)
Pulse duration, RTCK low
16
ns
7
tsu(TDIV-RTCKH)
Setup time, TDI/TMS/TRST valid before RTCK high
4
ns
8
th(RTCKH-TDIV)
Hold time, TDI/TMS/TRST valid after RTCK high
4
ns
Table 6-102. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port
(see Figure 6-50)
No.
9
PARAMETER
td(RTCKL-TDOV)
MIN
Delay time, RTCK low to TDO valid
MAX
UNIT
15
ns
1
2
3
TCK
4
5
6
RTCK
9
TDO
8
7
TDI/TMS/TRST
Figure 6-50. JTAG Test-Port Timing
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7 Device and Documentation Support
7.1
Device Support
TI offers an extensive line of development tools for the device platform, including tools to evaluate the
performance of the processors, generate code, develop algorithm implementations, and fully integrate and
debug software and hardware modules. The tool's support documentation is electronically available within
the Code Composer Studio™ Integrated Development Environment (IDE).
The following products support development of the device applications:
Hardware Development Tools:
Extended Development System (XDS™) Emulator
For a complete listing of development-support tools for the device, visit the Texas Instruments web site
on the Worldwide Web at http://www.ti.com uniform resource locator (URL). For information on pricing
and availability, contact the nearest TI field sales office or authorized distributor.
7.2
Documentation Support
The following documents describe the device. Copies of these documents are available on the Internet at
www.ti.com. Tip: Enter the literature number in the search box provided at www.ti.com.
Reference Guides
SPRUGU3 AM1705 ARM Microprocessor System Reference Guide
SPRUFU0
AM17x/AM18x ARM Microprocessor Peripherals Overview Reference Guide
Device and Documentation Support
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151
ADVANCE INFORMATION
Software Development Tools:
Code Composer Studio™ Integrated Development Environment (IDE): including Editor
C/C++/Assembly Code Generation, and Debug plus additional development tools
AM1705
SPRS657A – FEBRUARY 2010 – REVISED APRIL 2010
www.ti.com
8 Mechanical Packaging and Orderable Information
This section describes the device orderable part numbers, packaging options, materials, thermal and
mechanical parameters.
8.1
Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
AM1xxx processors and support tools. Each commercial AM1xxx platform member has one of three
prefixes: X, P, or null (no prefix). Texas Instruments recommends two of three possible prefix designators
for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product
development from engineering prototypes (TMDX) through fully qualified production devices/tools (TMDS).
Device development evolutionary flow:
ADVANCE INFORMATION
X
Experimental device that is not necessarily representative of the final device's electrical
specifications.
P
Final silicon die that conforms to the device's electrical specifications but has not completed
quality and reliability verification.
NULL
Fully-qualified production device.
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS
Fully qualified development-support product.
X and P devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
NULL devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be
used.
Figure 8-1 provides a legend for reading the device.
X
AM1705
( )
PTP
( )
DEVICE SPEED RANGE
3 = 375 MHz
4 = 456 MHz
TEMPERATURE RANGE (JUNCTION)
= 0°C to 90°C (Commercial Grade)
Blank
D
= -40°C to 90°C (Industrial Grade)
A
= -40°C to 105°C( Extended Grade)
PREFIX
X = Experimental Device
P = Prototype Device
Blank = Production Device
DEVICE
SILICON REVISION
B
= Silicon Revision 2.0
3
PACKAGE TYPE
TM
PTP = 176-Pin PowerPAD Plastic Quad Flat Pack
[ PTP Suffix], 0.5mm Pin Pitch
Figure 8-1. Device Nomenclature
8.2
Mechanical Drawings
This section contains mechanical drawings for the device.
152
Mechanical Packaging and Orderable Information
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PACKAGE OPTION ADDENDUM
www.ti.com
14-May-2010
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
AM1705BPTP3
ACTIVE
HLQFP
PTP
176
40
TBD
Call TI
Call TI
AM1705BPTP4
ACTIVE
HLQFP
PTP
176
40
TBD
Call TI
Call TI
XAM1705BPTP3
ACTIVE
HLQFP
PTP
176
1
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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