ON MMBT5551LT1 High voltage transistors(npn silicon) Datasheet

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SEMICONDUCTOR TECHNICAL DATA
COLLECTOR
3
NPN Silicon
*Motorola Preferred Device
1
BASE
2
EMITTER
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Collector – Emitter Voltage
VCEO
140
Vdc
Collector – Base Voltage
VCBO
160
Vdc
Emitter – Base Voltage
VEBO
6.0
Vdc
IC
600
mAdc
Collector Current — Continuous
3
1
2
CASE 318 – 08, STYLE 6
SOT– 23 (TO – 236AB)
THERMAL CHARACTERISTICS
Characteristic
Symbol
Max
Unit
Total Device Dissipation FR– 5 Board(1)
TA = 25°C
Derate above 25°C
PD
225
mW
1.8
mW/°C
Thermal Resistance, Junction to Ambient
RqJA
556
°C/W
PD
300
mW
2.4
mW/°C
RqJA
417
°C/W
TJ, Tstg
– 55 to +150
°C
Total Device Dissipation
Alumina Substrate,(2) TA = 25°C
Derate above 25°C
Thermal Resistance, Junction to Ambient
Junction and Storage Temperature
DEVICE MARKING
MMBT5550LT1 = M1F; MMBT5551LT1 = G1
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Max
140
160
—
—
160
180
—
—
6.0
—
—
—
—
—
100
50
100
50
—
50
Unit
OFF CHARACTERISTICS
Collector – Emitter Breakdown Voltage(3)
(IC = 1.0 mAdc, IB = 0)
Collector – Base Breakdown Voltage
(IC = 100 mAdc, IE = 0)
V(BR)CEO
MMBT5550
MMBT5551
V(BR)CBO
MMBT5550
MMBT5551
Emitter – Base Breakdown Voltage
(IE = 10 mAdc, IC = 0)
Collector Cutoff Current
(VCB = 100 Vdc, IE = 0)
(VCB = 120 Vdc, IE = 0)
(VCB = 100 Vdc, IE = 0, TA = 100°C)
(VCB = 120 Vdc, IE = 0, TA = 100°C)
Vdc
V(BR)EBO
Vdc
ICBO
MMBT5550
MMBT5551
MMBT5550
MMBT5551
Emitter Cutoff Current
(VEB = 4.0 Vdc, IC = 0)
Vdc
IEBO
nAdc
µAdc
nAdc
1. FR– 5 = 1.0
0.75 0.062 in.
2. Alumina = 0.4 0.3 0.024 in. 99.5% alumina.
3. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2.0%.
Thermal Clad is a trademark of the Bergquist Company
Preferred devices are Motorola recommended choices for future use and best overall value.
Motorola Small–Signal Transistors, FETs and Diodes Device Data
 Motorola, Inc. 1996
1
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) (Continued)
Characteristic
Symbol
Min
Max
MMBT5550
MMBT5551
60
80
—
—
(IC = 10 mAdc, VCE = 5.0 Vdc)
MMBT5550
MMBT5551
60
80
250
250
(IC = 50 mAdc, VCE = 5.0 Vdc)
MMBT5550
MMBT5551
20
30
—
—
Collector – Emitter Saturation Voltage
(IC = 10 mAdc, IB = 1.0 mAdc)
Both Types
—
0.15
(IC = 50 mAdc, IB = 5.0 mAdc)
MMBT5550
MMBT5551
—
—
0.25
0.20
Base – Emitter Saturation Voltage
(IC = 10 mAdc, IB = 1.0 mAdc)
Both Types
—
1.0
(IC = 50 mAdc, IB = 5.0 mAdc)
MMBT5550
MMBT5551
—
—
1.2
1.0
Unit
ON CHARACTERISTICS
DC Current Gain
(IC = 1.0 mAdc, VCE = 5.0 Vdc)
2
hFE
—
VCE(sat)
Vdc
VBE(sat)
Vdc
Motorola Small–Signal Transistors, FETs and Diodes Device Data
500
300
h FE, DC CURRENT GAIN
200
VCE = 1.0 V
VCE = 5.0 V
TJ = 125°C
25°C
100
– 55°C
50
30
20
10
7.0
5.0
0.1
0.2
0.3
0.5
0.7
1.0
3.0
2.0
5.0
7.0
IC, COLLECTOR CURRENT (mA)
10
20
30
50
70
100
VCE , COLLECTOR–EMITTER VOLTAGE (VOLTS)
Figure 1. DC Current Gain
1.0
0.9
0.8
0.7
0.6
IC = 1.0 mA
10 mA
100 mA
30 mA
0.5
0.4
0.3
0.2
0.1
0
0.005
0.01
0.02
0.05
0.1
0.2
0.5
1.0
IB, BASE CURRENT (mA)
5.0
2.0
10
20
50
Figure 2. Collector Saturation Region
101
1.0
TJ = 25°C
100
10–1
0.8
TJ = 125°C
10–2
IC = ICES
75°C
10–3
REVERSE
FORWARD
25°C
10–4
10–5
0.4
V, VOLTAGE (VOLTS)
IC, COLLECTOR CURRENT ( µA)
VCE = 30 V
VBE(sat) @ IC/IB = 10
0.6
0.4
0.2
VCE(sat) @ IC/IB = 10
0
0.3
0.2 0.1
0
0.1
0.2 0.3
0.4
VBE, BASE–EMITTER VOLTAGE (VOLTS)
0.5
0.6
Figure 3. Collector Cut–Off Region
Motorola Small–Signal Transistors, FETs and Diodes Device Data
0.1
0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 30
IC, COLLECTOR CURRENT (mA)
50
100
Figure 4. “On” Voltages
3
θV, TEMPERATURE COEFFICIENT (mV/ °C)
2.5
2.0
TJ = – 55°C to +135°C
1.5
1.0
Vin
0
tr, tf ≤ 10 ns
DUTY CYCLE = 1.0%
– 2.0
0.2 0.3 0.5 1.0 2.0 3.0 5.0
10 20 30
IC, COLLECTOR CURRENT (mA)
50
100
RC
RB
Vout
5.1 k
Vin
100
1N914
Figure 6. Switching Time Test Circuit
1000
TJ = 25°C
20
200
t, TIME (ns)
300
10
Cibo
7.0
5.0
tr @ VCC = 120 V
tr @ VCC = 30 V
100
Cobo
3.0
IC/IB = 10
TJ = 25°C
500
30
50
td @ VEB(off) = 1.0 V
30
VCC = 120 V
20
2.0
1.0
0.2
3.0 k
Values Shown are for IC @ 10 mA
Figure 5. Temperature Coefficients
100
70
50
0.25 µF
10 µs
INPUT PULSE
qVB for VBE(sat)
– 1.5
– 2.5
0.1
0.3
0.5 0.7 1.0
2.0
3.0
5.0 7.0
10
10
0.2 0.3 0.5
20
1.0
VR, REVERSE VOLTAGE (VOLTS)
Figure 7. Capacitances
20 30 50
2.0 3.0 5.0 10
IC, COLLECTOR CURRENT (mA)
100
200
Figure 8. Turn–On Time
5000
tf @ VCC = 120 V
3000
2000
IC/IB = 10
TJ = 25°C
tf @ VCC = 30 V
1000
t, TIME (ns)
C, CAPACITANCE (pF)
100
– 0.5
– 1.0
VCC
30 V
VBB
– 8.8 V
10.2 V
qVC for VCE(sat)
0.5
500
300
ts @ VCC = 120 V
200
100
50
0.2 0.3 0.5
20 30 50
1.0 2.0 3.0 5.0
10
IC, COLLECTOR CURRENT (mA)
100
200
Figure 9. Turn–Off Time
4
Motorola Small–Signal Transistors, FETs and Diodes Device Data
INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to insure proper solder connection
0.037
0.95
0.037
0.95
0.079
2.0
0.035
0.9
0.031
0.8
inches
mm
SOT–23
SOT–23 POWER DISSIPATION
The power dissipation of the SOT–23 is a function of the
pad size. This can vary from the minimum pad size for
soldering to a pad size given for maximum power dissipation.
Power dissipation for a surface mount device is determined
by T J(max), the maximum rated junction temperature of the
die, RθJA, the thermal resistance from the device junction to
ambient, and the operating temperature, TA . Using the
values provided on the data sheet for the SOT–23 package,
PD can be calculated as follows:
PD =
TJ(max) – TA
RθJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature TA of 25°C, one can
calculate the power dissipation of the device which in this
case is 225 milliwatts.
PD =
150°C – 25°C
556°C/W
= 225 milliwatts
The 556°C/W for the SOT–23 package assumes the use
of the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 225 milliwatts. There
are other alternatives to achieving higher power dissipation
from the SOT–23 package. Another alternative would be to
use a ceramic substrate or an aluminum core board such as
Thermal Clad. Using a board material such as Thermal
Clad, an aluminum core board, the power dissipation can be
doubled using the same footprint.
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
• Always preheat the device.
• The delta temperature between the preheat and
soldering should be 100°C or less.*
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10°C.
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
• When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied during
cooling.
* Soldering a device without preheating can cause excessive
thermal shock and stress which can result in damage to the
device.
Motorola Small–Signal Transistors, FETs and Diodes Device Data
5
PACKAGE DIMENSIONS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE
MATERIAL.
A
L
3
B S
1
V
2
DIM
A
B
C
D
G
H
J
K
L
S
V
G
C
H
D
K
J
CASE 318–08
SOT–23 (TO–236AB)
ISSUE AE
INCHES
MIN
MAX
0.1102 0.1197
0.0472 0.0551
0.0350 0.0440
0.0150 0.0200
0.0701 0.0807
0.0005 0.0040
0.0034 0.0070
0.0180 0.0236
0.0350 0.0401
0.0830 0.0984
0.0177 0.0236
MILLIMETERS
MIN
MAX
2.80
3.04
1.20
1.40
0.89
1.11
0.37
0.50
1.78
2.04
0.013
0.100
0.085
0.177
0.45
0.60
0.89
1.02
2.10
2.50
0.45
0.60
STYLE 6:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
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6
◊
Motorola Small–Signal Transistors, FETs and Diodes Device
Data
MMBT5550LT1/D
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