austriamicrosystems AG is now ams AG The technical content of this austriamicrosystems datasheet is still valid. Contact information: Headquarters: ams AG Tobelbaderstrasse 30 8141 Unterpremstaetten, Austria Tel: +43 (0) 3136 500 0 e-Mail: [email protected] Please visit our website at www.ams.com Datasheet AS1358 / AS1359 1 5 0 m A / 3 0 0 m A , U l t r a -L o w - N o i s e , H i g h - P S R R L o w D r o p o u t R e g u l a t o r s 2 Key Features The AS1358 / AS1359 are ultra-low-noise, low-dropout linear regulators specifically designed to deliver up to 150/300mA continuous output current, and can achieve a low 140mV dropout for 300mA load current. The LDOs are designed and optimized to work with low-cost, small-capacitance ceramic capacitors. The devices are available as the standard products listed in Table 1. Preset Output Voltages: 1.5V to 4.5V (in 50mV steps) al id 1 General Description Output Noise: 9µVRMS @ 100Hz to 100kHz Power-Supply Rejection Ratio: 92dB @ 1kHz Low Dropout: 140mV @ 300mA Load Load Current Output Voltage AS1358 150mA Preset – 1.5V to 4.5V AS1359 300mA Preset – 1.5V to 4.5V Guaranteed 150mA / 300mA Output 1.25V Internal Reference am lc s on A te G nt st il Model lv Stable with 1µF Ceramic Capacitor for any Load Table 1. Standard Products An integrated P-channel MOSFET pass transistor allows the devices to maintain extremely low quiescent current (40µA). The AS1358 / AS1359 uses an advanced architecture to achieve ultra-low output voltage noise of 9µVRMS and a power-supply rejection-ratio of better than 80dB (up to 10kHz). The AS1358 / AS1359 requires only 1µF output capacitor for stability at any load. When the LDO is disabled, current consumption drops below 500nA. The devices are available in a TSOT23 5-pin package. Extremely-Low Quiescent Current: 40µA Excellent Load/Line Transient Overcurrent and Thermal Protection TSOT23 5-pin Package 3 Applications The devices are ideal for mobile phones, wireless phones, PDAs, handheld computers, mobile phone base stations, Bluetooth portable radios and accessories, wireless LANs, digital cameras, personal audio devices, and any other portable, battery-powered application. ca Figure 1. Typical Application Circuit Input 2V to 5.5V Te ch ni CIN 1µF www.austriamicrosystems.com On Off 1 OUT IN 2 Output 1.5V to 4.5V 5 AS1358 / AS1359 GND 3 SHDNN 4 CBYPASS 10nF BYPASS Revision 1.5 COUT 1µF 1 - 16 AS1358 / AS1359 Datasheet - P i n A s s i g n m e n t s 4 Pin Assignments IN 1 5 OUT lv AS1358 / AS1359 am lc s on A te G nt st il GND 2 al id Figure 2. Pin Assignments (Top View) SHDNN 3 4 BYPASS TSOT23 5-pin 4.1 Pin Descriptions Table 2. Pin Descriptions Pin Number 1 IN 2 GND Description Unregulated Input Supply. Ground. Provides the electrical connection to system ground and also serves as a heat sink. Connect pin GND to the system ground using a large pad or ground plane. SHDNN Shutdown. Pull this pin low to disable the LDO. BYPASS Noise Bypass for Low-Noise Operation. Connect a 10nF capacitor from this pin to OUT. Note: This pin is shorted to GND in shutdown mode. ca 3 OUT Regulated Output Voltage. Bypass this pin with a capacitor to GND. Te ch ni 4 5 Pin Name www.austriamicrosystems.com Revision 1.5 2 - 16 AS1358 / AS1359 Datasheet - A b s o l u t e M a x i m u m R a t i n g s 5 Absolute Maximum Ratings Stresses beyond those listed in Table 3 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 4 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 3. Absolute Maximum Ratings Max Units IN to GND -0.3 +7 V OUT, SHDNN to GND -0.3 IN +0.3 V BYPASS to GND -0.3 OUT +0.3 V Output Short-Circuit Duration Infinite Thermal Resistance JA -40 ºC/W +85 ºC +125 ºC +150 ºC Junction-to-ambient thermal resistance is very dependent on application and board-layout. In situations where high maximum power dissipation exists, special attention must be paid to thermal dissipation during board design. am lc s on A te G nt st il Operating Temperature Range 201.7 Comments al id Min lv Parameter Junction Temperature Storage Temperature Range -65 +260 ºC Te ch ni ca Package Body Temperature The reflow peak soldering temperature (body temperature) specified is in accordance with IPC/JEDEC J-STD-020D “Moisture/Reflow Sensitivity Classification for NonHermetic Solid State Surface Mount Devices”. The lead finish for Pb-free leaded packages is matte tin (100% Sn). www.austriamicrosystems.com Revision 1.5 3 - 16 AS1358 / AS1359 Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s 6 Electrical Characteristics All limits are guaranteed. The parameters with Min and Max values are guaranteed by production tests or SQC (Statistical Quality Control) methods. VIN = VOUT +0.5V, CIN = 1µF, COUT = 1µF, CBYPASS = 10nF, TAMB = -40 to +85ºC (unless otherwise specified). Typical values are at TAMB = +25ºC. Table 4. Electrical Characteristics VIN Input Voltage Range Min IOUT = 1mA, TAMB = +25ºC -0.5 IOUT = 100µA to 150mA, TAMB = +25ºC (AS1358) -0.75 IOUT = 100µA to 300mA, TAMB = +25ºC (AS1359) -1.0 Typ 2 Max Unit 5.5 V +0.5 +0.75 +1.0 IOUT = 100µA to 150mA, (AS1358) -1.5 +1.5 IOUT = 100µA to 300mA, (AS1359) -2.0 +2.0 AS1358 150 AS1359 300 am lc s on A te G nt st il Output Voltage Accuracy Condition al id Parameter IOUT Maximum Output Current ILIMIT Current Limit Dropout Voltage IQ 1 Quiescent Current % lv Symbol AS1358, OUT = 90% of nom., TAMB = +25ºC 270 AS1359, OUT = 90% of nom., TAMB = +25ºC 510 VOUT 3V, IOUT = 150mA 70 95 VOUT 3V, IOUT = 300mA, (AS1359 only) 140 200 2.5V VOUT 3V, IOUT = 150mA 90 120 2.5V VOUT 3V, IOUT = 300mA, (AS1359 only) 170 230 2.0V VOUT 2.5V, IOUT = 150mA 140 190 2.0V VOUT 2.5V, IOUT = 300mA, (AS1359 only) 270 350 IOUT = 0.05mA 40 90 VIN = VOUTNOM - 0.1V, IOUT = 0mA 150 250 mA mA mV µA Line Regulation VIN = (VOUT +0.5V) to 5.5V, IOUT = 0.1mA 0.02 %/V VLDR Load Regulation IOUT = 1 to 150mA / 300mA 0.0005 %/mA ISHDNN Shutdown Supply Current SHDNN = 0V 9 f = 1kHz, IOUT = 10mA 92 ca VLNR Ripple Rejection ni PSRR ch Output Noise Voltage (RMS) f = 10kHz, IOUT = 10mA 80 f = 100kHz, IOUT = 10mA 62 f = 100Hz to 100kHz, ILOAD = 0 to 150mA / 300mA 9 500 nA dB µV Shutdown Te 2 RLOAD = 50 300 µs SHDNN Logic Low Level VIN = 2V to 5.5V 0.4 V SHDNN Logic High Level VIN = 2V to 5.5V Shutdown Exit Delay 1.5 V Thermal Protection TSHDNM Thermal Shutdown Temperature 160 ºC TSHDNM Thermal Shutdown Hysteresis 15 ºC 1. Dropout is defined as VIN - VOUT when VOUT is 100mV below the value of VOUT for VIN = VOUT + 0.5V 2. Time needed for VOUT to reach 90% of final value www.austriamicrosystems.com Revision 1.5 4 - 16 AS1358 / AS1359 Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s 7 Typical Operating Characteristics VIN = VOUT + 0.5V, CIN = COUT = 1µF, CBYPASS = 10nF, TAMB = 25°C (unless otherwise specified). Figure 3. Output Voltage vs. Input Voltage Figure 4. Output Voltage Accuracy vs. Load Current 3.5 . 0.5 IOUT = 300mA 2 1.5 1 0 0.3 0.2 0.1 Temp = -45°C 0 -0.1 Temp = 25°C -0.2 Temp = 85°C -0.3 -0.4 am lc s on A te G nt st il 0.5 al id IOUT = 150mA 2.5 lv Output Voltage (V) . Output Voltage Deviation (%) 0.4 3 -0.5 0 1 2 3 4 5 6 0 50 Input Voltage (V) Figure 5. Output Voltage Accuracy vs. Temperature 1 . Dropout Voltage (mV) . 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 300 100 Temp = 85°C Temp = 25°C 80 60 Temp = -45°C 40 20 0 -15 10 35 60 85 ni Figure 7. Dropout Voltage vs. Output Voltage 0 50 100 150 200 250 300 Load Current (mA) Figure 8. Ground Pin Current vs. Input Voltage . 150 Ground Pin Current (µA) ch Dropout Voltage (mV) . 250 120 Temperature (°C) 70 200 Figure 6. Dropout Voltage vs. Load Current ca Output Voltage Deviation (%) 0.6 80 150 140 0.8 -1 -40 100 Load Current (mA) 60 50 Te 40 30 20 10 0 125 100 IOUT= 300mA 75 IOUT = 150mA 50 IOUT = 0mA 25 0 2 2.2 2.4 2.6 2.8 3 3.2 0 Output Voltage (V) www.austriamicrosystems.com 1 2 3 4 5 6 Input Voltage (V) Revision 1.5 5 - 16 AS1358 / AS1359 Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s Figure 9. Ground Pin Current vs. Load Current Figure 10. Ground Pin Current vs. Temperature 50 . 75 60 55 50 45 40 50 100 150 200 250 35 30 25 -40 35 0 40 300 al id 65 45 -15 lv 70 Ground Pin Current (µA) Ground Pin Current (µA) . 80 10 35 60 85 Temperature (°C) am lc s on A te G nt st il Load Current (mA) Figure 11. PSRR vs. Frequency; IOUT = 10mA Figure 12. Output Noise Spectral Density vs. Frequency Output Noise Density (nV/ Hz) . 10000 1000 100 10 0.01 0.1 1 10 100 ca Frequency (kHz) Figure 13. Output Noise vs. Bypass Capacitance ni 15 14 ch IOUT 11 20mA/Div 12 Te 10 9 8 VOUT 20mV/DIV . 13 Noise (µVrms) Figure 14. Load Transient Response, VIN = 3.8V, VOUT = 3.3V 7 6 5 1 10 100 200µs/Div Capacitance (nF) www.austriamicrosystems.com Revision 1.5 6 - 16 AS1358 / AS1359 Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s 200µs/Div am lc s on A te G nt st il 200µs/Div lv 20mV/DIV al id VIN VOUT 20mV/DIV IOUT VOUT 500mV/Div Figure 16. Line Transient Response 20mA/Div Figure 15. Load Transient Response near Dropout, VIN = 3.4V, VOUT = 3.3V VOUT 2V/Div SHDNN 2V/Div Figure 17. Enter & Exit Shutdown Delay Te ch ni ca 200µs/Div www.austriamicrosystems.com Revision 1.5 7 - 16 AS1358 / AS1359 Datasheet - D e t a i l e d D e s c r i p t i o n 8 Detailed Description The AS1358 / AS1359 are ultra-low-noise, low-dropout, low-quiescent current linear-regulators specifically designed for space-limited applications. The devices are available with preset output voltages from 1.5V to 4.5V in 50mV increments. These devices can supply loads up to 150mA / 300mA. As shown in Figure 18, the AS1358 / AS1359 consist of an integrated bandgap core and noise bypass circuitry, error amplifier, P-channel MOSFET pass transistor, and internal feedback voltage-divider. al id Figure 18 shows the block diagram of the AS1358 / AS1359. It identifies the basics of a series linear regulator employing a 0.5 (typ) P-Channel MOSFET as the control element. A stable voltage reference (REF in Figure 18) is compared with an attenuated sample of the output voltage. Any difference between the two voltages (reference and sample) creates an output from the error amplifier that drives the series control element to reduce the difference to a minimum. The error amplifier incorporates additional buffering to drive the relatively large gate capacitance of the series pass P-channel MOSFET, when additional drive current is required under transient conditions. Input supply variations are absorbed by the series element and output voltage variations with loading are absorbed by the low output impedance of the regulator. lv The AS1358 / AS1359 deliver preset output voltages from 1.5V to 4.5V, in 50mV increments (see Ordering Information on page 15). am lc s on A te G nt st il The output voltage is fed back through an internal resistor voltage-divider connected to pin OUT. An external bypass capacitor connected to pin BYPASS reduces noise at the output. Startup time is minimized by internal power-on circuitry which pre-charges CBYPASS. Additional blocks include a current limiter, thermal sensor, and shutdown logic. Figure 18. AS1358 / AS1359 Block Diagram IN SHDNN Shutdown and Power-Down Control Error Amp MOS Driver w/ ILIMIT OUT ca Thermal Sensor BYPASS 1.25 Reference and Noise Bypass AS1358 / AS1359 Te ch ni GND www.austriamicrosystems.com Revision 1.5 8 - 16 AS1358 / AS1359 Datasheet - A p p l i c a t i o n I n f o r m a t i o n 9 Application Information 9.1 Dropout Voltage Dropout is the input to output voltage difference, below which the linear regulator ceases to regulate. At this point, the output voltage change follows the input voltage change. Dropout voltage may be measured at different currents and, in particular at the regulator maximum one. From this is obtained the MOSFET maximum series resistance over temperature etc. More generally: V DROPOUT = I LOAD R SERIES al id (EQ 1) Dropout is probably the most important specification when the regulator is used in a battery application. The dropout performance of the regulator defines the useful “end of life” of the battery before replacement or re-charge is required. lv Figure 19. Graphical Representation of Dropout Voltage am lc s on A te G nt st il VIN VOUT VIN = VOUT(TYP) + 0.5V Dropout Voltage VOUT 100mV VIN VOUT VIN ni 9.2 Efficiency ca Figure 19 shows the variation of VOUT as VIN is varied for a certain load current. The practical value of dropout is the differential voltage (VOUTVIN) measured at the point where the LDO output voltage has fallen by 100mV below the nominal, fully regulated output value. The nominal regulated output voltage of the LDO is that obtained when there is 500mV (or greater) input-output voltage differential. ch Low quiescent current and low input-output voltage differential are important in battery applications amongst others, as the regulator efficiency is directly related to quiescent current and dropout voltage. Efficiency is given by: V I V IN I Q + I LOAD LOAD LOAD Efficiency = --------------------------------------- 100 % (EQ 2) Te Where: IQ = Quiescent current of LDO www.austriamicrosystems.com Revision 1.5 9 - 16 AS1358 / AS1359 Datasheet - A p p l i c a t i o n I n f o r m a t i o n 9.3 Power Dissipation Maximum power dissipation (PD) of the LDO is the sum of the power dissipated by the internal series MOSFET and the quiescent current required to bias the internal voltage reference and the internal error amplifier, and is calculated as: PD MAX Seriespass = I LOAD MAX V IN MAX – V OUT MIN Watts (EQ 3) Internal power dissipation as a result of the bias current for the internal voltage reference and the error amplifier is calculated as: PD MAX Bias = V IN MAX I Q Watts al id (EQ 4) Total LDO power dissipation is calculated as: PD MAX Total = PD MAX Seriespass + PD MAX Bias Watts (EQ 5) 9.4 Junction Temperature lv Under all operating conditions, the maximum junction temperature should not be allowed to exceed 125ºC (unless the data sheet specifically allows). Limiting the maximum junction temperature requires knowledge of the heat path from junction to case (JCºC/W fixed by the IC manufacturer), and adjustment of the case to ambient heat path (CAºC/W) by manipulation of the PCB copper area adjacent to the IC position. am lc s on A te G nt st il Figure 20. Package Physical Arrangements SOTxx Package Chip Package Bond Wire Lead Frame PCB ni ca Figure 21. Steady State Heat Flow Equivalent Circuit Te ch Junction TJ°C Package TC°C RJC Ambient TA°C PCB/Heatsink TS°C RCS RSA Chip Power www.austriamicrosystems.com Revision 1.5 10 - 16 AS1358 / AS1359 Datasheet - A p p l i c a t i o n I n f o r m a t i o n Total Thermal Path Resistance: R JA = R JC + R CS + R SA (EQ 6) T J = PD MAX R JA + T AMB ºC (EQ 7) Junction Temperature (TJºC) is determined by: 9.5.1 al id 9.5 Explanation of Steady State Specifications Line Regulation V V IN OUT Line Regulation = ---------------- and is a pure number lv Line regulation is defined as the change in output voltage when the input (or line) voltage is changed by a known quantity. It is a measure of the regulator’s ability to maintain a constant output voltage when the input voltage changes. Line regulation is a measure of the DC open loop gain of the error amplifier. More generally: (EQ 8) am lc s on A te G nt st il In practise, line regulation is referred to the regulator output voltage in terms of % / VOUT. This is particularly useful when the same regulator is available with numerous output voltage trim options. V V IN 100 V OUT OUT Line Regulation = ---------------- ------------ % / V 9.5.2 Load Regulation (EQ 9) Load regulation is defined as the change of the output voltage when the load current is changed by a known quantity. It is a measure of the regulator’s ability to maintain a constant output voltage when the load changes. Load regulation is a measure of the DC closed loop output resistance of the regulator. More generally: V I OUT OUT Load Regulation = ---------------- and is units of ohms () (EQ 10) In practise, load regulation is referred to the regulator output voltage in terms of % / mA. This is particularly useful when the same regulator is available with numerous output voltage trim options. V I OUT 100 V OUT OUT Load Regulation = ---------------- ---------------- % / mA 9.5.3 Setting Accuracy (EQ 11) 9.5.4 Total Accuracy ca The regulator is supplied pre-trimmed, so that the output voltage accuracy is fully defined in the output voltage specification. Away from dropout, total steady state accuracy is the sum of setting accuracy, load regulation and line regulation. Generally: ni Total % Accuracy = Setting % Accuracy + Load Regulation % + Line Regulation % (EQ 12) ch 9.6 Explanation of Dynamic Specifications 9.6.1 Power Supply Rejection Ratio (PSRR) Te Known also as Ripple Rejection, this specification measures the ability of the regulator to reject noise and ripple beyond DC. PSRR is a summation of the individual rejections of the error amplifier, reference and AC leakage through the series pass transistor. The specification, in the form of a typical attenuation plot with respect to frequency, shows up the gain bandwidth compromises forced upon the designer in low quiescent current conditions. Generally: V OUT V IN PSSR = 20Log ---------------- dB using lower case to indicate AC values (EQ 13) Power supply rejection ratio is fixed by the internal design of the regulator. Additional rejection must be provided externally. www.austriamicrosystems.com Revision 1.5 11 - 16 AS1358 / AS1359 Datasheet - A p p l i c a t i o n I n f o r m a t i o n 9.6.2 Output Capacitor ESR The series regulator is a negative feedback amplifier, and as such is conditionally stable. The ESR of the output capacitor is usually used to cancel one of the open loop poles of the error amplifier in order to produce a single pole response. Excessive ESR values may actually cause instability by excessive changes to the closed loop unity gain frequency crossover point. The range of ESR values for stability is usually shown either by a plot of stable ESR versus load current, or a limit statement in the datasheet. Some ceramic capacitors exhibit large capacitance and ESR variations with temperature. Z5U and Y5V capacitors may be required to ensure stability at temperatures below TAMB = -10ºC. With X7R or X5R capacitors, a 1.0µF capacitor should be sufficient at all operating temperatures. 9.6.3 al id Larger output capacitor values (2.2µF max) help to reduce noise and improve load transient-response, stability and power-supply rejection. Input Capacitor 9.6.4 lv An input capacitor at VIN is required for stability. It is recommended that a 1.0µF capacitor be connected between the AS1358 / AS1359 power supply input pin VIN and ground (capacitance value may be increased without limit subject to ESR limits). This capacitor must be located at a distance of not more than 1cm from the VIN pin and returned to a clean analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input. Noise am lc s on A te G nt st il The regulator output is a DC voltage with noise superimposed on the output. The noise comes from three sources; the reference, the error amplifier input stage, and the output voltage setting resistors. Noise is a random fluctuation and if not minimized in some applications, will produce system problems. The AS1358/9 architecture provides enhance noise reduction when an external 10nF capacitor is connected between Bypass and Output pins, and 1µF connected as the output capacitor. The leakage current going into the BYPASS pin should be less than 10nA. Increasing the capacitance slightly decreases the output noise. Values above 0.1µF and below 0.001µF are not recommended. 9.6.5 Transient Response The series regulator is a negative feedback system, and therefore any change at the output will take a finite time to be corrected by the error loop. This “propagation time” is related to the bandwidth of the error loop. The initial response to an output transient comes from the output capacitance, and during this time, ESR is the dominant mechanism causing voltage transients at the output. More generally: V TRANSIENT = I OUTPUT R ESR Units are Volts, Amps, Ohms. (EQ 14) Thus an initial +50mA change of output current will produce a -12mV transient when the ESR=240m. Remember to keep the ESR within stability recommendations when reducing ESR by adding multiple parallel output capacitors. After the initial ESR transient, there follows a voltage droop during the time that the LDO feedback loop takes to respond to the output change. This drift is approximately linear in time and sums with the ESR contribution to make a total transient variation at the output of: T V TRANSIENT = I OUTPUT R ESR + ---------------- C LOAD Units are Volts, Seconds, Farads, Ohms. (EQ 15) ni ca Where: CLOAD is output capacitor T = Propagation delay of the LDO This shows why it is convenient to increase the output capacitor value for a better support for fast load changes. Of course the formula holds for t < “propagation time”, so that a faster LDO needs a smaller cap at the load to achieve a similar transient response. For instance 50mA load current step produces 50mV output drop if the LDO response is 1usec and the load cap is 1µF. ch There is also a steady state error caused by the finite output impedance of the regulator. This is derived from the load regulation specification discussed above. 9.6.6 Turn On Time Te This specification defines the time taken for the LDO to awake from shutdown. The time is measured from the release of the enable pin to the time that the output voltage is within 5% of the final value. It assumes that the voltage at VIN is stable and within the regulator Min and Max limits. Shutdown reduces the quiescent current to very low, mostly leakage values (<1µA). 9.6.7 Thermal Protection To prevent operation under extreme fault conditions, such as a permanent short circuit at the output, thermal protection is built into the device. Die temperature is measured, and when a 160ºC threshold is reached, the device enters shutdown. When the die cools sufficiently, the device will restart (assuming input voltage exists and the device is enabled). Hysteresis of 15ºC prevents low frequency oscillation between start-up and shutdown around the temperature threshold. www.austriamicrosystems.com Revision 1.5 12 - 16 AS1358 / AS1359 Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s 10 Package Drawings and Markings The devices are available in a TSOT23 5-pin package. c1 0.08 Typ 0.35 0.15 Max 1.00 0.10 0.90 0.45 0.39 0.20 0.13 0.16 0.05 0.87 ca 0.01 0.84 0.30 0.31 0.12 2.90BSC 2.80BSC 1.60BSC 0.95BSC 1.90BSC ch D E E1 e e1 Min ni Symbol A A1 A2 b b1 c am lc s on A te G nt st il lv al id Figure 22. TSOT23 5-pin Package Notes 3,4 3,4 3,4 Symbol L L1 L2 N R R1 1 aaa bbb ccc ddd Min 0.30 Typ 0.40 0.60REF 0.25BSC 5 0.10 0.10 0º Max 0.50 Notes 0.25 4º 8º 4º 10º 12º Tolerances of Form and Position 0.15 0.25 0.10 0.20 Notes: Te 1. Dimensioning and tolerancing conform to ASME Y14.5M - 1994. 2. Dimensions are in millimeters. 3. Dimension D does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, and gate burrs shall not exceed 0.15mm per end. Dimension E1 does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.15mm per side. Dimensions D and E1 are determined at datum H. 4. The package top can be smaller than the package bottom. Dimensions D and E1 are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs, and interlead flash, but include any mistmatches between the top of the package body and the bottom. D and E1 are determined at datum H. www.austriamicrosystems.com Revision 1.5 13 - 16 AS1358 / AS1359 Datasheet Revision History Revision Date 1.4 - 1.5 13 Jun, 2012 Owner Description afe Initial revisions Te ch ni ca am lc s on A te G nt st il lv al id Note: Typos may not be explicitly mentioned under revision history. www.austriamicrosystems.com Revision 1.5 14 - 16 AS1358 / AS1359 Datasheet - O r d e r i n g I n f o r m a t i o n 11 Ordering Information The devices are available as the standard products shown in Table 5. Table 5. Ordering Information Marking Output Current Output Voltage Delivery Form Package AS1358-BTTT-15 ASLI 150mA 1.5V Tape and Reel TSOT23 5-pin AS1358-BTTT-18 ASLJ 150mA 1.8V Tape and Reel TSOT23 5-pin AS1358-BTTT-25 ASLK 150mA 2.5V Tape and Reel AS1358-BTTT-26 ASLL 150mA 2.6V Tape and Reel AS1358-BTTT-27 ASLM 150mA 2.7V Tape and Reel AS1358-BTTT-28 ASLN 150mA 2.8V Tape and Reel AS1358-BTTT-285 ASLO 150mA 2.85V Tape and Reel TSOT23 5-pin AS1358-BTTT-30 ASLP 150mA 3.0V Tape and Reel TSOT23 5-pin AS1358-BTTT-33 ASLQ 150mA 3.3V Tape and Reel TSOT23 5-pin ASLR 150mA 4.5V Tape and Reel TSOT23 5-pin ASLS 300mA 1.5V Tape and Reel TSOT23 5-pin ASLT 300mA 1.8V Tape and Reel TSOT23 5-pin ASLU 300mA 2.5V Tape and Reel TSOT23 5-pin ASLV 300mA 2.6V Tape and Reel TSOT23 5-pin ASLW 300mA 2.7V Tape and Reel TSOT23 5-pin ASLX 300mA 2.8V Tape and Reel TSOT23 5-pin ASLY 300mA 2.85V Tape and Reel TSOT23 5-pin ASLZ 300mA 3.0V Tape and Reel TSOT23 5-pin ASSA 300mA 3.1V Tape and Reel TSOT23 5-pin ASL0 300mA 3.3V Tape and Reel TSOT23 5-pin ASL1 300mA 4.5V Tape and Reel TSOT23 5-pin AS1359-BTTT-15 AS1359-BTTT-18 AS1359-BTTT-25 AS1359-BTTT-26 AS1359-BTTT-27 AS1359-BTTT-28 AS1359-BTTT-285 AS1359-BTTT-30 AS1359-BTTT-31 AS1359-BTTT-33 AS1359-BTTT-45 TSOT23 5-pin TSOT23 5-pin TSOT23 5-pin lv TSOT23 5-pin am lc s on A te G nt st il AS1358-BTTT-45 al id Ordering Code ca Non-standard devices from 1.5V to 4.5V are available in 50mV steps. For more information and inquiries contact http://www.austriamicrosystems.com/contact Note: All products are RoHS compliant and Pb-free. Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect Te ch ni For further information and requests, please contact us mailto:[email protected] or find your local distributor at http://www.austriamicrosystems.com/distributor www.austriamicrosystems.com Revision 1.5 15 - 16 AS1358 / AS1359 Datasheet - O r d e r i n g I n f o r m a t i o n Copyrights Copyright © 1997-2012, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. al id Disclaimer lv Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. ca Contact Information am lc s on A te G nt st il The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Headquarters ni austriamicrosystems AG Tobelbaderstrasse 30 A-8141 Unterpremstaetten, Austria ch Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: Te http://www.austriamicrosystems.com/contact www.austriamicrosystems.com Revision 1.5 16 - 16