ON NTB60N06G 60 v, 60 a, n-channel to-220 and d2pak Datasheet

NTP60N06, NTB60N06
Power MOSFET
60 V, 60 A, N−Channel
TO−220 and D2PAK
Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
circuits.
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60 VOLTS, 60 AMPERES
RDS(on) = 14 m
Features
• Pb−Free Packages are Available
N−Channel
D
Typical Applications
•
•
•
•
Power Supplies
Converters
Power Motor Controls
Bridge Circuits
G
S
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Symbol
Value
Unit
MARKING
DIAGRAMS
Drain−to−Source Voltage
VDSS
60
Vdc
Drain−to−Gate Voltage (RGS = 10 M)
VDGR
60
Vdc
4
Drain
Rating
Gate−to−Source Voltage
− Continuous
− Non−Repetitive (tp10 ms)
Drain Current
− Continuous @ TA = 25°C
− Continuous @ TA = 100°C
− Single Pulse (tp10 s)
Total Power Dissipation @ TA = 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C (Note 1)
VGS
VGS
ID
ID
IDM
PD
20
30
60
42.3
180
Adc
150
1.0
2.4
W
W/°C
W
TJ, Tstg
−55 to
+175
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 75 Vdc, VGS = 10 Vdc, L = 0.3 mH
IL(pk) = 55 A, VDS = 60 Vdc)
EAS
454
mJ
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
October, 2004 − Rev. 3
NTx60N06
AYWW
1
2
1
Gate
3
3
Source
2
Drain
4
Drain
4
2
°C/W
RJC
RJA
1.0
62.5
TL
260
D2PAK
CASE 418B
STYLE 2
1
NTx60N06
AYWW
3
2
1
3
Drain
Gate
Source
°C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits
are exceeded, device functional operation is not implied, damage may occur
and reliability may be affected.
1. When surface mounted to an FR4 board using minimum recommended pad
size, (Cu Area 0.412 in2).
 Semiconductor Components Industries, LLC, 2004
TO−220
CASE 221A
STYLE 5
Apk
Operating and Storage Temperature Range
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient (Note 1)
4
Vdc
NTx60N06
x
A
Y
WW
= Device Code
= P or B
= Assembly Location
= Year
= Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
Publication Order Number:
NTP60N06/D
NTP60N06, NTB60N06
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
60
−
72.3
69.8
−
−
−
−
−
−
1.0
10
−
−
±100
2.0
−
2.85
8.0
4.0
−
−
11.5
14
−
−
0.715
1.43
1.01
−
gFS
−
35
−
mhos
Ciss
−
2300
3220
pF
Coss
−
660
925
Crss
−
144
300
td(on)
−
25.5
50
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage (Note 2)
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)
V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C)
IDSS
Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc)
IGSS
Vdc
mV/°C
Adc
nAdc
ON CHARACTERISTICS (Note 2)
Gate Threshold Voltage (Note 2)
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)
VGS(th)
Static Drain−to−Source On−Resistance (Note 2)
(VGS = 10 Vdc, ID = 30 Adc)
RDS(on)
Static Drain−to−Source On−Voltage (Note 2)
(VGS = 10 Vdc, ID = 60 Adc)
(VGS = 10 Vdc, ID = 30 Adc, TJ = 150°C)
VDS(on)
Forward Transconductance (Note 2) (VDS = 8.0 Vdc, ID = 12 Adc)
Vdc
mV/°C
m
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)
Transfer Capacitance
SWITCHING CHARACTERISTICS (Note 3)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
(VDD = 30 Vdc, ID = 60 Adc,
VGS = 10 Vdc, RG = 9.1 ) (Note 2)
Fall Time
Gate Charge
(VDS = 48 Vdc,
Vd ID = 60 Adc,
Ad
VGS = 10 Vdc) (Note 2)
ns
tr
−
180.7
360
td(off)
−
94.5
200
tf
−
142.5
300
QT
−
62
81
Q1
−
10.8
−
Q2
−
29.4
−
VSD
−
−
0.99
0.87
1.05
−
Vdc
trr
−
64.9
−
ns
ta
−
44.1
−
tb
−
20.8
−
QRR
−
0.146
−
nC
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(IS = 60 Adc, VGS = 0 Vdc) (Note 2)
(IS = 45 Adc, VGS = 0 Vdc, TJ = 150°C)
Reverse Recovery Time
(IS = 60 Adc,
Ad VGS = 0 Vdc,
Vd
dIS/dt = 100 A/s) (Note 2)
Reverse Recovery Stored Charge
2. Pulse Test: Pulse Width ≤ 300 s, Duty Cycle ≤ 2%.
3. Switching characteristics are independent of operating junction temperatures.
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2
C
NTP60N06, NTB60N06
120
VGS = 10 V
VDS ≥ 10 V
7V
9V
100
6V
8V
80
60
5.5 V
40
5V
20
0
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
120
4.5 V
0
1
2
3
4
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
100
80
60
40
TJ = 25°C
20
TJ = 100°C
TJ = −55°C
0
5
3
VDS = 10 V
0.022
TJ = 100°C
0.018
TJ = 25°C
0.01
TJ = −55°C
0.006
0
20
40
60
80
100
ID, DRAIN CURRENT (AMPS)
120
RDS(on), DRAIN−TO−SOURCE RESISTANCE ()
0.026
0.014
0.026
VGS = 15 V
0.022
TJ = 100°C
0.018
0.014
TJ = 25°C
0.01
TJ = −55°C
0.006
0
Figure 3. On−Resistance versus Gate−to−Source
Voltage
20
40
60
80
100
ID, DRAIN CURRENT (AMPS)
120
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
2.2
2
8
Figure 2. Transfer Characteristics
10,000
VGS = 0 V
ID = 30 A
VGS = 10 V
TJ = 150°C
1.8
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
RDS(on), DRAIN−TO−SOURCE RESISTANCE ()
Figure 1. On−Region Characteristics
7
4
5
6
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
1.6
1.4
1.2
1
1000
TJ = 125°C
100
TJ = 100°C
0.8
0.6
−50
10
−25
0
25
50
75
100
125
150
0
175
10
20
30
40
50
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
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3
60
NTP60N06, NTB60N06
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
6400
VDS = 0 V
VGS = 0 V
TJ = 25°C
C, CAPACITANCE (pF)
5600
4800
Ciss
4000
3200
Crss
Ciss
2400
1600
Coss
800
0
10
Crss
5
0
VGS
5
10
15
20
25
VDS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
1000
12
VDS = 30 V
ID = 60 A
VGS = 10 V
QT
10
VGS
8
Q1
Q2
6
tr
t, TIME (ns)
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
NTP60N06, NTB60N06
4
2
tf
100
td(off)
ID = 60 A
TJ = 25°C
0
0
10
20
30
40
50
QG, TOTAL GATE CHARGE (nC)
60
td(on)
10
70
1
10
RG, GATE RESISTANCE ()
Figure 8. Gate−to−Source and Drain−to−Source
Voltage versus Total Charge
100
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
IS, SOURCE CURRENT (AMPS)
60
VGS = 0 V
TJ = 25°C
50
40
TJ = 150°C
30
20
TJ = 25°C
10
0
0.4
0.48
0.56
0.64
0.72
0.8
0.88
0.96
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed
in
AN569,
“Transient
Thermal
Resistance−General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 s. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) − TC)/(RJC).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous ID can safely be assumed to
equal the values indicated.
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5
NTP60N06, NTB60N06
ID, DRAIN CURRENT (AMPS)
1000
VGS = 20 V
SINGLE PULSE
TC = 25°C
10 s
100
100 s
10
1
1 ms
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
10 ms
dc
1
10
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
100
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
SAFE OPERATING AREA
500
ID = 55 A
400
300
200
100
0
25
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
(NORMALIZED)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
50
75
100
125
150
175
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1.0
D = 0.5
0.2
0.1
0.1
P(pk)
0.05
0.02
t1
0.01
t2
DUTY CYCLE, D = t1/t2
SINGLE PULSE
0.01
0.00001
0.0001
0.001
0.01
RJC(t) = r(t) RJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) RJC(t)
0.1
t, TIME (s)
Figure 13. Thermal Response
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 14. Diode Reverse Recovery Waveform
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1.0
10
NTP60N06, NTB60N06
ORDERING INFORMATION
Package
Shipping†
TO−220
50 Units/Rail
TO−220
(Pb−Free)
50 Units/Rail
D2PAK
50 Units/Rail
NTB60N06G
D2PAK
(Pb−Free)
50 Units/Rail
NTB60N06T4
D2PAK
800 Tape & Reel
D2PAK
(Pb−Free)
800 Tape & Reel
Device
NTP60N06
NTP60N06G
NTB60N06
NTB60N06T4G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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7
NTP60N06, NTB60N06
PACKAGE DIMENSIONS
TO−220
CASE 221A−09
ISSUE AA
−T−
B
SEATING
PLANE
C
F
T
S
4
DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
T
U
V
Z
A
Q
1 2 3
U
H
K
Z
L
R
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
J
G
D
N
INCHES
MIN
MAX
0.570
0.620
0.380
0.405
0.160
0.190
0.025
0.035
0.142
0.147
0.095
0.105
0.110
0.155
0.018
0.025
0.500
0.562
0.045
0.060
0.190
0.210
0.100
0.120
0.080
0.110
0.045
0.055
0.235
0.255
0.000
0.050
0.045
−−−
−−−
0.080
STYLE 5:
PIN 1.
2.
3.
4.
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8
GATE
DRAIN
SOURCE
DRAIN
MILLIMETERS
MIN
MAX
14.48
15.75
9.66
10.28
4.07
4.82
0.64
0.88
3.61
3.73
2.42
2.66
2.80
3.93
0.46
0.64
12.70
14.27
1.15
1.52
4.83
5.33
2.54
3.04
2.04
2.79
1.15
1.39
5.97
6.47
0.00
1.27
1.15
−−−
−−−
2.04
NTP60N06, NTB60N06
PACKAGE DIMENSIONS
D2PAK
CASE 418B−04
ISSUE J
C
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 418B−01 THRU 418B−03 OBSOLETE,
NEW STANDARD 418B−04.
E
V
W
−B−
4
DIM
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
S
V
A
1
2
S
3
−T−
SEATING
PLANE
K
W
J
G
D
H
3 PL
0.13 (0.005)
M
T B
M
INCHES
MIN
MAX
0.340 0.380
0.380 0.405
0.160 0.190
0.020 0.035
0.045 0.055
0.310 0.350
0.100 BSC
0.080
0.110
0.018 0.025
0.090
0.110
0.052 0.072
0.280 0.320
0.197 REF
0.079 REF
0.039 REF
0.575 0.625
0.045 0.055
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
SOLDERING FOOTPRINT*
8.38
0.33
1.016
0.04
10.66
0.42
5.08
0.20
3.05
0.12
17.02
0.67
SCALE 3:1
mm inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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9
MILLIMETERS
MIN
MAX
8.64
9.65
9.65 10.29
4.06
4.83
0.51
0.89
1.14
1.40
7.87
8.89
2.54 BSC
2.03
2.79
0.46
0.64
2.29
2.79
1.32
1.83
7.11
8.13
5.00 REF
2.00 REF
0.99 REF
14.60 15.88
1.14
1.40
NTP60N06, NTB60N06
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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For additional information, please contact your
local Sales Representative.
NTP60N06/D