ON NCP1601BPG Compact fixed frequency discontinuous or critical conduction voltage mode power factor correction controller Datasheet

NCP1601A, NCP1601B
Compact Fixed Frequency
Discontinuous or Critical
Conduction Voltage Mode
Power Factor Correction
Controller
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The NCP1601 is a controller designed for Power Factor Correction
(PFC) boost circuits. The device operates in fixed−frequency
Discontinuous Conduction Mode (DCM) and variable−frequency
Critical Conduction Mode (CRM) and takes advantages from both
operating modes. DCM limits the maximum switching frequency. It
simplifies the front−ended EMI filter design. CRM limits the
maximum currents of the boost stage diode, MOSFET and inductor.
It reduces the costs and improves the reliability of the circuit. This
device substantially exhibits unity power factor while operating in
DCM and CRM. The NCP1601 minimizes the required number of
external components. It incorporates high safety protection features
that make the NCP1601 suitable for robust and compact PFC stages.
8
Features
8
•
•
•
•
•
•
•
•
•
•
•
Near−Unity Power Factor in DCM or CRM
Voltage−Mode Operation
Low Startup and Shutdown Current Consumption
Programmable Switching Frequency for DCM
Synchronization Capability
Overvoltage Protection (107% of Nominal Output Level)
Undervoltage Protection or Shutdown
(8% of Nominal Output Level)
Programmable Overcurrent Protection
Thermal Shutdown with Hysteresis (95/140°C)
Two VCC Undervoltage Lockout Hysteresis Options:
4.75 V for NCP1601A and 1.5 V for NCP1601B
Pb−Free Packages are Available
8
SOIC−8
D SUFFIX
CASE 751
1
8
PDIP−8
N SUFFIX
CASE 626
NCP1601x
AWL
YYWWG
1
1
x
A
L, WL
Y, YY
W, WW
G
G
= A or B
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
= Pb−Free Package
PIN CONNECTIONS
FB 1
8 VCC
Vcontrol 2
7 Drv
6 GND
CS 4
Electronic Light Ballast
AC Adapters
TV & Monitors
Mid−Power Applications
1601x
ALYW
G
1
Ramp 3
Typical Applications
•
•
•
•
MARKING
DIAGRAM
5 Osc
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 15 of this data sheet.
© Semiconductor Components Industries, LLC, 2005
December, 2005 − Rev. 4
1
Publication Order Number:
NCP1601A/D
NCP1601A, NCP1601B
AC
Input
EMI
Filter
Output
15 V
FB
VCC
Vcontrol Drv
Ramp GND
CS
Osc
NCP1601X
Figure 1. Typical Application Circuit
L
EMI
Filter
AC
Input
Output Voltage (Vout)
Cfilter
Cbulk
RFB
on
RCS
off
IS
IFB
Vcontrol
1
FB / SD
VCC
Current
Mirror
9V
VCC
V reg
2
Vcontrol Processing
300 k
VCC(on) / 9 V
96% I ref
8
C1
I ref I FB
Regulation Block
+
18 V
RS
−
R1
UVLO
Overvoltage
Protection
(IFB > 107% Iref)
R2
0
R3
1
C3
&
VCC
Reference
Block
Shutdown / UVP
(IFB < 8% Iref)
&
Zero Current
Detection
(IS < 14 mA)
Internal Bias
3.9 Vmax
clamp
Vton
−
+
PFC
Modulation
Ich
CS
Current
Mirror
4
Thermal
Shutdown
(95 / 140 °C)
Overcurrent
Protection
(IS > 203 mA)
9V
Ramp
3
1
OR
0
Cramp
9V
45 mA
Osc / Sync
5
COSC
Ccontrol
9V
+
−
VCC
+
−
&
S
94 mA
9V
Q
Drv
5 / 3.5 V
0
1
R
S
R
delay
Oscillator / Synchronization Block
Figure 2. Functional Block Diagram
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2
Q
7
Output
Driver
GND
6
NCP1601A, NCP1601B
PIN FUNCTION DESCRIPTION
Pin
Symbol
Function
Function
1
FB
Feedback /
Shutdown
This pin receives a current IFB which is proportional to the PFC circuit output voltage. The current is
for the output regulation, output Overvoltage Protection (OVP), and output undervoltage protection
(UVP).
When IFB goes above 107% Iref, OVP is activated and the Drive Output is disabled.
When IFB goes below 8% Iref, the device enters a low−current consumption shutdown mode.
2
Vcontrol
Control
The voltage of this pin Vcontrol directly controls the input impedance and hence the power factor of
the circuit. This pin is connected to an external capacitor to limit the control voltage Vcontrol bandwidth typically below 20 Hz to achieve Power Factor Correction.
3
Ramp
Ramp
This pin is connected to an external capacitor to set a ramp signal. The capacitor value directly
affects the input impedance of the PFC circuit and hence the maximum input power.
4
CS
Current Sense
This pin sources a current IS which depends on the inductor current and an offset voltage. The
current is for Overcurrent Protection (OCP) and zero current detection.
When IS is above 200 mA, OCP is activated and the Drive Output is disabled.
When IS is below 14 mA, the circuit detects a zero current. This information is used by the on−time
modulation arrangement and by the oscillator block.
5
Osc
Oscillator /
Synchronization
In oscillator mode, this pin is connected to an external capacitor to set the oscillator frequency of
the DCM operation.
In synchronization mode, this pin is connected to an external driving signal. The positive edge of the
drive output is synchronized to the negative edge of the external signal in DCM operation.
If the inductor current is non−zero at the end of a switching period, the output drive is not allowed to
turn on. CCM operation is prohibited. Instead, the circuit operates in CRM in this case.
6
GND
The IC ground
−
7
Drv
Drive Output
This pin provides an output to an external MOSFET.
8
VCC
Supply Voltage
This pin is the positive supply of the device. The operating range is between 9 V and 18 V with
UVLO start threshold 13.75 V for NCP1601A and 10.5 V for NCP1601B.
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
FB, Vcontrol, Ramp, CS, Osc Pins (Pins 1−5)
Maximum Voltage Range
Maximum Current
Vmax
Imax
−0.3 to +9
100
V
mA
Drive Output (Pin 7)
Maximum Voltage Range
Maximum Current Range (Note 2)
Vmax
Imax
−0.3 to +18
−500 to +750
V
mA
Power Supply Voltage (Pin 8)
Maximum Voltage Range
Maximum Current
Vmax
Imax
−0.3 to +18
100
V
mA
PD
RqJA
800
100
mW
°C/W
PD
RqJA
450
178
mW
°C/W
Operating Junction Temperature Range
TJ
−40 to +125
°C
Storage Temperature Range
Tstg
−65 to +150
°C
Power Dissipation and Thermal Characteristics
P suffix, Plastic Package, Case 626
Maximum Power Dissipation @ TA=70 °C
Thermal Resistance, Junction−to−Air
D suffix, Plastic Package, Case 751
Maximum Power Dissipation @ TA=70 °C
Thermal Resistance, Junction−to−Air
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values
(not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage
may occur and reliability may be affected.
A. This device series contains ESD protection and exceeds the following tests:
Pins 1−8: Human Body Model 2000 V per MIL−STD−883, Method 3015.
Machine Model Method 200 V.
B. This device contains Latchup protection and exceeds ±100 mA per JEDEC Standard JESD78.
1. Guaranteed by design.
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NCP1601A, NCP1601B
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C. For min/max values, TJ = −40°C to +125°C, VCC = 15 V,
Vcontrol = 100 nF, Ramp = 100 pF, Osc = 220 pF unless otherwise specified)
Characteristic
Pin
Symbol
Min
Typ
Max
Unit
Oscillator Frequency (Osc = 220 pF to GND)
5
fosc
52
58
64
kHz
Internal Capacitance of the Oscillator Pin
5
Cosc(int)
−
36
−
pF
Maximum Oscillator Switching Frequency
5
fosc(max)
−
405
−
kHz
Oscillator Discharge Current (Osc = 5.5 V)
5
Iodch
40
49
60
mA
Oscillator Charge Current (Osc = 3 V)
5
Ioch
40
45
60
mA
Comparator Lower Threshold (Osc = 220 pF to GND) (Note 3)
5
Vsync(L)
3.0
3.5
4.0
V
Comparator Upper Threshold (Osc = 220 pF to GND)
5
Vsync(H)
4.5
5
5.5
V
Synchronization Pulse Width for Detection
5
tsync(min)
500
−
−
ns
Synchronization Propagation Delay
5
tsync(d)
−
371
−
ns
ROH
ROL
5
2
11.6
7.2
20
18
W
W
OSCILLATOR
GATE DRIVE
Gate Drive Resistor
Output High and Draw 100 mA out of Drv Pin (Isource = 100 mA)
Output Low and Insert 100 mA into Drv Pin (Isink = 100 mA)
7
Gate Drive Rise Time from 1.5 V to 13.5 V (Drv = 1 nF to GND)
7
tr
−
53
−
ns
Gate Drive Fall Time from 13.5 V to 1.5 V (Drv = 1 nF to GND)
7
tf
−
32
−
ns
FEEDBACK / OVERVOLTAGE PROTECTION / UNDERVOLTAGE PROTECTION
Reference Current
1
Iref
192
203
208
mA
Regulation Block Ratio
1
IregL / Iref
95
96
97
%
Vcontrol Pin Internal Resistor
2
Rcontrol
−
300
−
kW
Maximum Control Voltage (IFB = 100 mA)
2
Vcontrol(max)
0.95
1.05
1.15
V
Feedback Pin Voltage (IFB = 100 mA)
1
VFB1
−
3
−
V
Overvoltage Protection Current Ratio
1
IOVP / Iref
104
107
−
%
Overvoltage Protection Current
1
IOVP
−
217
225
mA
Undervoltage Protection Current Ratio
1
IUVP / Iref
4
8
15
%
Current Sense Pin Offset Voltage (IS = 100 mA)
4
VS
−
4
−
mV
Overcurrent Protection Level
4
IS(OCP)
190
203
210
mA
Current Sense Pin Offset Voltage at Overcurrent Level
4
VS(OCP)
0
3.2
20
mV
Zero Current Detection Level
4
IS(ZCD)
9
14
19
mA
Current Sense Pin Offset Voltage at Zero Current Level
4
VS(ZCD)
0
7.5
20
mV
Zero Current Sense Resistor (RS(ZCD) = VS(ZCD) / IS(ZCD))
4
RS(ZCD)
−
0.536
1
kW
Charging Current (Ramp = 0 V)
3
Ich
95
100
105
mA
Maximum Power Resistance (Rpower = Vcontrol(max) / Ich)
3
Rpower
9.5
10.5
11.5
kW
Internal Clamping of Voltage Vton
−
Vton(max)
−
3.9
−
V
Internal Capacitance of the Ramp Pin
3
Cramp(int)
−
20
−
pF
Ramp Pin Sink Resistance (Osc = 0 V, Ramp = 1 mA sourcing)
3
Rramp
−
71.5
−
W
Thermal Shutdown Threshold (Note 4)
−
TSD
140
−
−
°C
Thermal Shutdown Hysteresis
−
TH
−
45
−
°C
CURRENT SENSE
RAMP
THERMAL SHUTDOWN
2. Comparator lower threshold is also the synchronization threshold.
3. Guaranteed by design.
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NCP1601A, NCP1601B
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C. For min/max values, TJ = −40°C to +125°C, VCC = 15 V,
Vcontrol = 100 nF, Ramp = 100 pF, Osc = 220 pF unless otherwise specified)
Characteristic
Pin
Symbol
Min
Typ
Max
Unit
Startup Threshold (UVLO) – NCP1601A
Startup Threshold (UVLO) – NCP1601B
8
VCC(on)
12.5
9.6
13.75
10.5
15
11.4
V
V
Minimum Voltage for Operation After Turn−On
8
VCC(off)
8.25
9
9.75
V
UVLO Hysteresis – NCP1601A
UVLO Hysteresis – NCP1601B
8
VCC(H)
4
1
4.75
1.5
−
−
V
V
Power Supply Current:
Startup (VCC = VCC(on) – 0.2 V)
Operating (VCC = 15 V, Drv = open, Osc = 220 pF)
Operating (VCC = 15 V, Drv = 1 nF to GND, Osc = 220 pF)
Shutdown (VCC = 15 V, IFB = 0 A)
8
Istup
ICC1
ICC2
Istdn
−
−
−
−
17
2.7
3.7
24
40
5
5
50
mA
mA
mA
mA
SUPPLY SECTION
TYPICAL CHARACTERISTICS
51
59
58
57
56
55
54
53
52
COSC = 220 pF
51
50
−50
−25
0
25
50
75
100
125
OSCILLATOR CHARGE & DISCHARGE
CURRENT (mA)
fOSC, OSCILLATOR FREQUENCY (kHz)
60
50
Iodch osc pin = 5.5 V
49
48
47
46
Ioch osc pin = 3 V
45
44
−50
−25
TJ, JUNCTION TEMPERATURE (°C)
50
75
100
125
Figure 4. Oscillator Charge and Discharge
Current vs. Temperature
5.5
18
16
Vsync(H)
GATE DRIVE RESISTANCE (W)
OSCILLATOR COMPARATOR
THRESHOLDS (V)
25
TJ, JUNCTION TEMPERATURE (°C)
Figure 3. Oscillator Frequency vs. Temperature
5.0
4.5
COSC = 220 pF
4.0
Vsync(L)
3.5
3
−50
0
−25
0
25
50
75
100
125
ROH
14
12
10
ROL
8
6
4
2
0
−50
TJ, JUNCTION TEMPERATURE (°C)
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. Oscillator Comparator Thresholds
vs. Temperature
Figure 6. Drive Output Resistance vs.
Temperature
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125
NCP1601A, NCP1601B
TYPICAL CHARACTERISTICS
1.2
208
Vcontrol, CONTROL VOLTAGE (V)
IREF, REFERENCE CURRENT (mA)
210
206
204
202
200
198
196
194
192
190
−50
0
−25
25
50
75
100
0.8
TJ = −40°C
0.6
TJ = 25°C
0.4
TJ = 125°C
0.2
0
150
125
160
170
190
200
210
IFB, FEEDBACK CURRENT (mA)
Figure 7. Reference Current vs.
Temperature
Figure 8. Regulation Block Transfer
Function
220
MAXIMUM CONTROL VOLTAGE (V)
1.10
99
98
97
96
95
94
93
92
91
90
−50
0
−25
25
50
75
100
1.08
1.06
1.04
1.02
IFB = 100 mA
1.00
−50
125
−25
TJ, JUNCTION TEMPERATURE (°C)
OVERVOLTAGE PROTECTION RATIO (%)
5
TJ = 125°C
4
TJ = 25°C
TJ = −40°C
2
1
0
0
50
100
150
200
25
50
75
100
125
Figure 10. Maximum Control Voltage vs.
Temperature
6
3
0
TJ, JUNCTION TEMPERATURE (°C)
Figure 9. Regulation Block Ratio vs. Temperature
FEEDBACK PIN VOLTAGE (V)
180
TJ, JUNCTION TEMPERATURE (°C)
100
REGULATION BLOCK RATIO (%)
1.0
250
110
109.5
109
108.5
108
107.5
107
106.5
106
105.5
105
−50
IFB, FEEDBACK PIN CURRENT (mA)
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 11. Feedback Pin Voltage vs. Feedback
Current
Figure 12. Overvoltage Protection Ratio
vs. Temperature
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125
NCP1601A, NCP1601B
TYPICAL CHARACTERISTICS
UNDERVOLTAGE PROTECTION RATIO (%)
OVERVOLTAGE THRESHOLD (mA)
220
218
216
214
212
210
208
206
204
202
200
−50
0
−25
25
50
75
100
125
10
9
8
7
6
5
4
3
2
1
0
−50
−25
TJ, JUNCTION TEMPERATURE (°C)
50
75
100
125
Figure 14. Undervoltage Protection Ratio vs.
Temperature
10
CS PIN OFFSET VOLTAGE (mV)
120
CS PIN OFFSET VOLTAGE (mV)
25
TJ, JUNCTION TEMPERATURE (°C)
Figure 13. Overvoltage Protection Threshold
vs. Temperature
100
80
60
TJ = 125 °C
40
TJ = 25 °C
20
TJ = −40 °C
0
0
100
50
150
200
9
8
VS(ZCD)
7
6
5
4
VS(OCP)
3
2
1
0
−50
250
IS, CS PIN CURRENT (mA)
ZERO CURRENT DETECTION LEVEL (mA)
208
206
204
202
200
198
196
194
192
−25
0
25
50
75
0
25
50
75
100
125
Figure 16. CS Pin Offset Voltage at OCP, ZCD
vs. Temperature
210
190
−50
−25
TJ, JUNCTION TEMPERATURE (°C)
Figure 15. CS Pin Offset Voltage vs. Current
OVERCURRENT PROTECTION LEVEL (mA)
0
100
125
15.0
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
−50
TJ, JUNCTION TEMPERATURE (°C)
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 17. Overcurrent Protection Level vs.
Temperature
Figure 18. Zero Current Detection Level
vs. Temperature
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125
NCP1601A, NCP1601B
105
700
600
ICH, CHARGING CURRENT (mA)
ZERO CURRENT SENSE RESISTOR (W)
TYPICAL CHARACTERISTICS
500
400
300
200
100
0
−50
−25
0
25
50
75
100
102
101
100
99
98
97
96
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 19. Zero Current Sense Resistor vs.
Temperature
Figure 20. Charging Current vs. Temperature
VCC UNDERVOLTAGE LOCKOUT
THRESHOLDS (V)
15
11.5
11.0
10.5
10.0
9.5
9.0
−50
−25
0
25
50
75
100
13
12
VCC(on) for NCP1601B
11
10
VCC(off)
9
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 21. Maximum Power Resistance vs.
Temperature
Figure 22. Supply Voltage Undervoltage
Lockout Thresholds vs. Temperature
125
4
35
30
25
Istdn
20
15
Istup
10
5
0
−50
VCC(on) for NCP1601A
14
8
−50
125
VCC SUPPLY CURRENT WITH 1.0 nF
LOAD AND WITHOUT LOAD (mA)
MAXIMUM POWER RESISTANCE (kW)
103
95
−50
125
12.0
VCC SUPPLY CURRENT IN STARTUP
AND SHUTDOWN MODE (mA)
104
−25
0
25
50
75
100
125
3.8
3.6
ICC2, 1 nF Load
3.4
3.2
3
2.8
2.6
ICC1, No Load
2.4
2.2
2
−50
TJ, JUNCTION TEMPERATURE (°C)
VCC = 15 V, COSC = 220 pF
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 23. Supply Current in Startup and
Shutdown Mode vs. Temperature
Figure 24. Supply Current vs. Temperature
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125
NCP1601A, NCP1601B
FUNCTIONAL DESCRIPTION
Introduction
conditions, CRM can be an alternative option which is
without power factor degradation. On the other hand, the
NCP1601 can be viewed as a CRM controller with a
frequency clamp (maximum switching frequency limit)
alternative option which is also without power factor
degradation. In summary, the NCP1601 can cover both
CRM and DCM without power factor degradation. Based
on the selections of the boost inductor and the oscillator
frequency, the circuit is capable of the following three
applications.
1. “Mostly in CRM” with a frequency clamp set by
the oscillator or synchronization frequency.
2. “Mostly in fixed−frequency mode DCM” and
only run in CRM at high load and low line.
3. “Fixed−frequency DCM” only.
The NCP1601 is a Power Factor Correction (PFC) boost
controller designed to operate in Discontinuous
Conduction Mode (DCM) and Critical Conduction Mode
(CRM). The fixed−frequency nature of DCM limits the
maximum switching frequency. It limits the possible
conducted and radiated EMI noise that may pollute
surrounding systems. NCP1601 offers the simplest solution
to PFC including fewer external circuit components and
simple voltage−mode feedback. The diode turn−off
switching loss is negligible and hence there is no need to
use a low reverse−recovery time trr diode. On the other
hand, the CRM feature is added to limit the maximum
current stress to twice of the average current. The NCP1601
incorporates high safety protection features and combines
the advantages of DCM and CRM so that the NCP1601 is
suitable for robust and compact PFC stages.
Current
Inductor current, IL
The NCP1601 provides the following protection features:
1. Overvoltage Protection (OVP) is activated and
the output drive goes low when the output voltage
exceeds 107% of the nominal regulation level
which is a user−defined value. The circuit
automatically resumes operation when the output
voltage becomes lower than 107%.
2. Undervoltage Protection (UVP) is activated and
the device is shut down when the output voltage
goes below 8% of the nominal regulation level.
The circuit automatically resumes operation when
the output voltage goes above 8% of the nominal
regulation level. This feature also provides output
open−loop protection and external shutdown
feature.
3. Overcurrent Protection (OCP) is activated and
the output device goes low when the inductor
current exceeds a user−defined value. The
operation automatically resumes when the
inductor current becomes lower than this
user−defined value at the next clock cycle.
4. Thermal Shutdown (TSD) is activated and the
output drive is disabled when the junction
temperature exceeds 140°C. The operation
resumes when the junction temperature falls
down by typical 45°C.
Input current, Iin
time
DCM
Critical Mode
DCM
Figure 25. Operating Modes
DCM needs higher peak inductor current comparing to
CRM in the same averaged input current. Hence, CRM is
generally preferred at around the sinusoidal peak for lower
the maximum current stress but DCM is also preferred at
the non−peak region to avoid excessive switching
frequencies. Because of the variable−frequency feature of
the CRM and constant−frequency feature of DCM,
switching frequency is the maximum in the DCM region
and hence the minimum switching frequency will be found
at the moment of the sinusoidal peak.
DCM PFC Circuit
A DCM/CRM PFC boost converter is shown in Figure 26.
Input voltage is a rectified 50 or 60 Hz sinusoidal signal. The
MOSFET is switching at a high frequency (typically around
100 kHz) so that the inductor current IL basically consists of
high−frequency and low−frequency components.
Filter capacitor Cfilter is an essential and very small value
capacitor in order to eliminate the high−frequency content
of the DCM inductor current IL. This filter capacitor cannot
The NCP1601 is available in two versions. The
NCP1601A has a typical 4.75 V undervoltage lockout
(UVLO) hysteresis, while NCP1601B has a typical 1.5 V
UVLO hysteresis. It allows the use of different VCC biasing
schemes.
Operating Modes of NCP1601
The NCP1601 is a PFC driver primarily designed to
operate in fixed−frequency DCM. In the most stressful
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NCP1601A, NCP1601B
be too bulky because it can pollute the power factor by
distorting the rectified sinusoidal input voltage.
Iin
IL
Power factor is corrected when the input impedance Zin
in (eq.3) are constant or slowly varying.
The MOSFET on time t1 or PFC modulation duty is
generated by a feedback signal Vton and a ramp. The PFC
modulation circuit and timing diagram are shown in
Figure 28. A relationship in (eq.4) is obtained.
L
Vout
Vin
Cfilter
Cbulk
t1 +
Figure 26. DCM/CRM PFC Boost Converter
Cramp Vton
Ich
Ich
PFC
Modulation
+
−
Ramp
PFC Methodology
3
NCP1601 uses a proprietary PFC methodology
particularly designed for both DCM and CRM operation.
The PFC methodology is described in this section.
closed when
output low
Cramp
(eq.4)
Turns off
MOSFET
Vton
Inductor Current
Vton
ramp
output
Ipk
Figure 28. PFC Modulation Circuit and Timing
Diagram
t1
t2
The charging current Ich is constant 100 mA current and
the ramp capacitor Cramp is constant for a particular design.
Hence, according to (eq.4) the MOSFET on time t1 is
proportional to Vton.
In order to protect the PFC modulation comparator, the
maximum voltage of Vton is limited to internal clamp
Vton(max) (3.9 V typical) and the ramp pin (Pin 3) is with a
9 V ESD Zener diode. The 3.9 V maximum limit of this
Vton indirectly limits the maximum on time.
time
t3
T
Figure 27. Inductor Current in DCM
As shown in Figure 27, the inductor current IL of each
switching cycle starts from zero in DCM. CRM is a special
case of DCM when t3 = 0. When the PFC boost converter
MOSFET is on, the inductor current IL increases from zero
to Ipk for a time duration t1 with inductance L and input
voltage Vin. (eq.1) is formulated.
Ipk
Vin + L
t1
closed when zero current
R1
R2
(eq.1)
The input filter capacitor Cfilter and the front−ended EMI
filter absorb the high−frequency component of inductor
current. It makes the input current Iin a low−frequency
signal.
C1
Vcontrol
2
−
+
R3
C3
Ccontrol
Ipk (t1 ) t2)
Iin +
2T
for DCM
(eq.2a)
Ipk
Iin +
2
for CRM
(eq.2b)
Figure 29. Vcontrol Processing Circuit
The Vcontrol processing circuit generates Vton from
control voltage Vcontrol and time information of zero
inductor current. The circuit in Figure 29 makes (eq.5)
where the value of resistor R1 is much higher than the value
of resistor R2 (R1 >> R2).
From (eq.1) and (eq.2), the input impedance Zin is
formulated.
V
2TL
for DCM
Zin + in +
Iin
t1(t1 ) t2)
(eq.3a)
V
2L
Zin + in +
t1
Iin
(eq.3b)
for CRM
Vton
Vton +
http://onsemi.com
10
T Vcontrol
t1 ) t2
for DCM
(eq.5a)
NCP1601A, NCP1601B
Vton + Vcontrol
for CRM
(eq.5b)
Rpower +
It is noted that Vton is always greater than or equal to
Vcontrol (i.e., Vton ≥ Vcontrol).
In summary, the input impedance Zin in (eq.6) is obtained
from (eq.1)−(eq.5)
2 L Ich
V
Zin + in +
Iin
Cramp Vcontrol
Pin(max) +
Iac(max) +
Pin(max)
VacCrampRpower
+
2L
Vac
V
* VFB1
V
IFB + out
[ out
RFB
RFB
(eq.12)
where RFB is the feedback resistor connected between the
FB pin (Pin 1) and the output voltage referring to Figure 2.
Then, the feedback current IFB represents the output
voltage Vout and will be used in the output voltage
regulation, Undervoltage Protection (UVP), and
Overvoltage Protection (OVP).
Output Voltage Regulation
2
Vcontrol
Feedback current IFB, which presents output voltage
Vout, is regulated with a reference current (Iref = 203 mA
typical) as shown in Figure 31.
Ccontrol
Vreg
Figure 30. Vcontrol Low−Pass Filtering
1.05 V
Maximum Power
Input and output power (Pin and Pout) are derived in
(eq.8) when the circuit efficiency h is obtained or assumed.
The variable Vac stands for the RMS input voltage.
Vac2CrampVcontrol
V 2
Pin + ac +
Zin
2LIch
Pout + h Pin +
(eq.11)
The output voltage Vout of the PFC circuit is sensed as a
feedback current IFB flowing into the FB pin (Pin 1) of the
device. The FB pin voltage VFB1 is typically less than 5 V
referring to Figure 11. It is much lower than Vout which is
typically 400 V. Therefore, VFB1 is generally neglected.
(eq.7)
Vcontrol
Processing
Circuit
Regulation Block
(eq.10b)
Output Feedback
Vreg
300k
hVac2CrampRpower
2L
(eq.10a)
The maximum input current Iac(max) to deliver the
maximum input power Pin(max) is also derived in (eq.11).
The suffix ac stands for RMS value.
If the bandwidth of Vcontrol is much less than the 50 or
60 Hz line frequency, the input impedance Zin is slowly
varying or roughly constant. Then, the power factor
correction is achieved in DCM and CRM.
Iref IFB
Vac2CrampRpower
2L
Pout(max) +
Control voltage Vcontrol comes from the PFC output
voltage Vout which is a slowly varying signal. The
bandwidth of Vcontrol can be additionally limited by
inserting an external capacitor Ccontrol to the Vcontrol pin
(Pin 2) in Figure 28. The internal 300 kW resistor and the
capacitor Ccontrol create a low−pass filter which has a
bandwidth fcontrol in (eq.7). It is generally recommended to
limit the bandwidth below 20 Hz to achieve power factor
correction. Typical value of Ccontrol is 0.1 mF.
96% Iref
(eq.9)
It means that the maximum input and output power
(Pin(max) and Pout(max)) are limited to ±10% variation.
(eq.6)
1
Ccontrol u
2p300kW fcontrol
Vcontrol(max)
1.05 V
+
+ 10.5 kW
100 mA
Ich
hVac2CrampVcontrol
2LIch
96% Iref
Iref
IFB
Figure 31. Regulation Block
(eq.8a)
When IFB is lower than 96% of Iref, the Vreg which is the
output of the regulation block is as high as Vcontrol(max)
(1.05 V typical) that gives the maximum value on Vton. As
a result, it gives the maximum MOSFET on time and Vout
increases. When IFB is higher than Iref, the Vreg becomes 0
V that gives no MOSFET on time and Vout decreases. As
a result, the output voltage Vout is regulated around the
range between 96% and 100% of the nominal value of RFB
× Iref.
Based on (eq.8) for a particular power level, the Vcontrol
is inversely proportional to Vac2. Hence, in high Vac
condition Vcontrol is lower. It means that IFB or output
(eq.8b)
From (eq.8), control voltage Vcontrol controls the amount
of output power, input power, or input impedance. The
maximum value of the control voltage Vcontrol is 1.05 V
(i.e., Vcontrol(max) = 1.05 V). A parameter called maximum
power resistor Rpower (10.5 kW typical) is defined in (eq.9)
and restricted to have a maximum ±10% variation
(i.e., 9.5 kW ≤ Rpower ≤ 11.5 kW) for defining the maximum
power in an application.
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11
NCP1601A, NCP1601B
IL
voltage is higher based on the regulation block
characteristic in Figure 31. On the other hand, the Vcontrol
in the low Vac condition is much higher than the high Vac
condition. In order to not over−design the circuit in the
application, the Vcontrol in the low Vac condition is usually
very closed to Vcontrol(max). It makes the output voltage be
almost 96% of the nominal value of RFB × Iref in low Vac
condition while the output voltage is almost 100% of the
nominal value RFB × Iref in high Vac condition.
The feedback resistor RFB consists of two or three high
precision resistors in order to set the nominal Vout precisely
and safety purpose.
The regulation block output Vreg is connected to control
voltage Vcontrol through an internal resistor Rcontrol
(300 kW typical) for the low−pass filter in Figure 30. The
Vcontrol and the time information of zero current are
collected in the Vcontrol processing circuit to generate Vton
which is then compared to a ramp signal to generate the
MOSFET on time t1 for power factor correction.
RS
RCS
IS
CS
+
NCP1601
Gnd
VS
−
IL
Figure 32. Current Sensing
Inductor current IL passes through RCS and creates a
negative voltage. This voltage is measured by a current IS
flowing out of the CS pin (Pin 4). The CS pin has an offset
voltage VS. This offset voltage is studied in the setting of
zero inductor current IL(ZCD) and the maximum inductor
current IL(OCP) (i.e., overcurrent protection threshold). A
typical variation of offset voltage VS versus sense current
IS is shown in Figure 15. Higher the value of the offset
voltage at low current region creates lower the zero current
threshold for better accuracy. Based on Figure 32, (eq.13)
is derived.
Overvoltage Protection (OVP)
When the feedback current IFB is higher than 107% of the
reference current Iref (i.e., the output voltage Vout is higher
than 107% of its nominal value), the Drive Output pin
(Pin 7) of the device goes low for protection and the switch
of the Vcontrol processing circuit is kept off. The circuit
automatically resumes operation when the output voltage
is lower than 107%.
The maximum OVP threshold is limited to 225 mA which
corresponds to 225 mA × 1.95 MW + 5 V = 443.75 V when
RFB = 1.95 MW (1.8 MW + 150 kW) and VFB1 = 5 V (for
the worst case referring to Figure 11). Hence, it is generally
recommended to use 450 V rating output capacitor to allow
some design margin.
VS * RS IS + −RCS IL
(eq.13)
Zero Current Detection (ZCD)
The device recognizes zero inductor current when the CS
pin (Pin 4) sense current IS is lower than IS(ZCD) (14 mA
typical). The offset voltage of the CS pin in this condition
is VS(ZCD) (7.5 mV typical). It is illustrated in Figure 33.
The inductor current IL(ZCD) at the ZCD condition is
derived in (eq.14).
IL(ZCD) +
RSIS(ZCD) * VS(ZCD)
RCS
(eq.14)
It is obvious that the IL(ZCD) is not always zero. In order
to make it reasonably close to zero, the settings of RS and
RCS are crucial.
Undervoltage Protection (UVP)
When the feedback current IFB is lower than 8% of the
reference current Iref (i.e., the output voltage Vout is lower
than 8% of its nominal value), the device is shut down and
consumes lower than 50 mA. In normal situation of boost
converter configuration, the output voltage Vout is always
higher than the input voltage Vin and the feedback current
IFB is always higher than 8% of the reference current Iref.
It enables the NCP1601 to operate. Hence, UVP happens
when the output voltage is abnormally undervoltage, the
FB pin (Pin 1) is opened, or the FB pin (Pin 1) is manually
pulled low.
VS
RS > RS(ZCD)
Operating ZCD point
RS = RS(ZCD)
Ideal ZCD point
VS(ZCD)
Current Sense
The device senses the inductor current IL by the current
sense scheme in Figure 32. This scheme has the advantages
of: (1) the inrush current limitation by the resistor RCS, and
(2) the overcurrent protection and zero current detection
implemented in the same pin.
IS
IS(ZCD)
Figure 33. CS Pin Characteristic when IL = 0
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12
NCP1601A, NCP1601B
Based on the CS pin (Pin 4) characteristics in Figure 15,
Figure 33 is studied. When the inductor current is exactly
zero (i.e., IL(ZCD) = 0), the ideal ZCD point in the Figure is
reached where RS is RS(ZCD) (536 W typical). Considering
the tolerance, the actual sense resistor RS is needed to be
higher than the ideal value of RS(ZCD) to ensure that zero
current signal is generated when sense current is smaller
than the ZCD threshold (i.e., IS < IS(ZCD)). That is,
VS(ZCD)
RS u RS(ZCD) +
IS(ZCD)
When overcurrent protection threshold is reached, the
Drive Output of the device goes low.
Oscillator / Synchronization Block
Oscillator Clock
45 mA
Osc 5
94 mA
(eq.15)
0
The higher value of RS makes the longer distance
between the operating and ideal ZCD points in Figure 33.
Hence, RS has to be as low as possible. The best
recommended value of RS is therefore the maximum of
RS(ZCD) which is 1 kW.
Now that the RS is set at a particular value which is
greater than RS(ZCD). From (eq.13), the operating lines in
(eq.16) with different inductor currents IL of (eq.13) are
studied.
VS + RS * RCSIL
Turn on
MOSFET
R
delay
clock edge
(latch set signal)
clock latch
(latch output)
inductor
current
(eq.16)
time
Discontinuous mode
Critical mode
Figure 36. Oscillator Block Timing Diagram
The NCP1601 is a DCM / CRM PFC controller. In order
to keep the operation in DCM or CRM only, the Drive
Output cannot turn on as long as there is some inductor
current flowing through the circuit. Hence, the zero current
signal is provided to the oscillator / synchronization block
in Figure 35. An input comparator monitors the Osc pin
(Pin 5) voltage and generates a clock signal. The negative
edge of the clock signal is stored in a RS latch. When zero
current is detected, the RS latch will be reset and a set signal
is sent to the output drive latch which turns on the MOSFET
in the PFC boost circuit. Figure 36 illustrates a typical
timing diagram of the oscillator block.
IL > IL(ZCD)
Best
ZCD
point
VS(ZCD)
&
clock
VS
IL = IL(ZCD)
5 V/3.5 V
1
S Q
Figure 35. Oscillator / Synchronization Block
These operating lines are added in Figure 33 to formulate
Figure 34. When the inductor current IL is lower than
IL(ZCD), the sense current IS is lower than IS(ZCD) and hence
the zero current signal is generated.
IL = 0
+
−
Zero Current
IS
Oscillator Mode
IS(ZCD)
Operating
ZCD point
The Osc pin (Pin 5) is connected to an external capacitor
Cosc. When the voltage of this pin is above Vsync(H) (5 V
typical), the pin sinks a current Iodch (94 – 45 = 49 mA
typical) and the external capacitor Cosc discharges. When
the voltage reaches Vsync(L) (3.5 V typical), the pin sources
a current Ioch (45 mA typical) and the external capacitor
Cosc is charged. It is noted that there is a typical 300 ns
propagation delay and the 3.5 V and 5 V threshold
conditions are measured on 220 pF Cosc capacitor. Hence,
the actual oscillator hysteresis is a slightly smaller.
Figure 34. CS Pin Characteristic with Different
Inductor Current
It is noted in Figure 34 and (eq.16) that when the (RCS IL)
term is smaller the error or distance between the lines to the
line IL = 0 is smaller. Therefore, the value of the current
sense resistor RCS is also recommended to be as small as
possible to minimize the error in the zero current detection.
Overcurrent Protection (OCP)
Osc pin
voltage
Overcurrent protection is reached when IS is higher than
IS(OCP) (200 mA typical). The offset voltage of the CS pin
is VS(OCP) (3.2 mV typical) in this condition. That is
IL(OCP) +
RSIS(OCP) * VS(OCP)
RCS
5V
3.5 V
Osc clock
Clock edge
(eq.17)
Drive output
(DCM)
Figure 37. Oscillator Mode Timing Diagram in DCM
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13
NCP1601A, NCP1601B
There is an internal capacitance Cosc(int) (36 pF typical)
in the oscillator pin and the oscillator frequency is to
fosc(max) (405 kHz typical) when the Osc pin is opened.
Hence, the oscillator switching frequency can be
formulated in (eq.18) and represented in Figure 38.
Cosc +
36 pF @ 405 kHz
* 36 pF
fosc
signal turns to 3.5 V. A timing diagram of synchronization
mode is summarized in Figure 39.
5V
3.5 V
Sync Signal
(eq.18)
Osc Clock
Clock Edge
C osc , Oscillator Capacitor (pF)
700
Drive Output
(DCM)
600
500
Figure 39. Synchronization Mode Timing Diagram in
DCM
400
VCC Undervoltage Lockout (UVLO)
300
There are two UVLO options. The device typically starts
to operate when the supply voltage VCC exceeds 13.75 V
for NCP1601A and 10.5 V for NCP1601B. It turns off when
the supply voltage VCC goes below 9 V. An 18 V internal
ESD Zener diode is connected to the VCC pin (Pin 8).
Hence, the operating range is 9 V to 18 V.
The 4.75 V UVLO hysteresis option of the NCP1601A
and 14 mA low startup current make the self−supply design
easier. The 1.5 V UVLO hysteresis option of NCP1601B
makes it more flexible to match with the second−stage
PWM controller biasing VCC supply voltage.
200
100
0
0
50
100
150
f osc , Oscillator Frequency (kHz)
200
Figure 38. Osc Pin Frequency Setting
Synchronization Mode
The Osc pin (Pin 5) receives an external digital signal
with level high defined to be higher than Vsync(H) (5 V
typical) and level low defined to be lower than Vsync(L)
(3.5 V typical). An internal 9 V ESD Zener diode is
connected to the Osc pin and hence the maximum
synchronization voltage is 9 V. The circuit recognizes a
synchronization frequency by the time difference between
two falling edge instants when the synchronization signal
across the 3.5 V threshold points. The actual
synchronization threshold point is a slightly higher than the
3.5 V threshold point. The minimum synchronization pulse
width is 500 ns.
There is a typical 350 ns propagation delay from
synchronization threshold point to the moment of output goes
high and there is also a typical 300 ns propagation delay from
the synchronization threshold point to the moment of crossing
3.5 V. Hence, the output goes high apparently when the sync
Thermal Shutdown
An internal thermal circuitry disables the circuit gate
drive and then keeps the power switch off when the junction
temperature exceeds 140°C. The output stage is then
enabled once the temperature drops below typically 95°C
(i.e., 45°C hysteresis). The thermal shutdown is provided
to prevent possible device failures that could result from an
accidental overheating.
Output Drive
The output stage of the device is designed for direct drive
of power MOSFET. It is capable of up to −500 mA and
+750 mA peak drive current and has a typical rise and fall
time of 53 and 32 ns with a 1.0 nF load.
Table 1. Power Factor Controller Test Data
Vin (Vac)
Pin (W)
Vout (V)
Iout (mA)
PF
THD (%)
Efficiency (%)
90
143.4
327
400
0.998
4
91.2
110
161.1
373
400
0.997
6
92.6
130
160.5
378
400
0.996
6
94.2
150
160.9
382
400
0.993
7
95.0
180
161.6
386
400
0.990
6
95.5
190
161.7
387
400
0.986
8
95.7
210
162.0
389
400
0.980
8
96.0
230
162.2
391
400
0.973
9
96.4
250
162.8
393
400
0.959
16
96.6
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14
NCP1601A, NCP1601B
Input
90 Vac
to
260 Vac
450 mH / 4.5 A
KBP06
3.15 A Fuse
1 mF
100 nF
1 mF
MUR460
680 k
68 mF
450 V
Output
390 V
680 k
SPP11N60S5
SPF47283900
0.1
560 k
Vcc
2.2 k
NCP1601B
56
1N4934
1.5 nF
68 nF
1.5 nF
220 pF
10 k
Figure 40. 130 W Power Factor Correction Circuit
ORDERING INFORMATION
Device
Package
Shipping†
NCP1601AP
PDIP−8
50 Units / Rail
NCP1601APG
PDIP−8
(Pb−Free)
50 Units / Rail
NCP1601ADR2
SOIC−8
2500 Units / Tape & Reel
SOIC−8
(Pb−Free)
2500 Units / Tape & Reel
PDIP−8
50 Units / Rail
NCP1601BPG
PDIP−8
(Pb−Free)
50 Units / Rail
NCP1601BDR2
SOIC−8
2500 Units / Tape & Reel
SOIC−8
(Pb−Free)
2500 Units / Tape & Reel
NCP1601ADR2G
NCP1601BP
NCP1601BDR2G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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15
NCP1601A, NCP1601B
Appendix I – Summary of Equations in NCP1601 Boost PFC
Description
Boost converter
Critical Mode (CRM)
t ) t2
Vout
+ 1
t2
Vin
t ) t2
Vout
+ 1
t2
Vin
³ Vout * Vin + t
³ Vout * Vin + t
Ipk
Iin +
2
t ) t2 Ipk
Iin + 1
2
T
Vton + Vcontrol
T
Vton +
V
t1 ) t2 control
t1
1 ) t2
Vout
Input current averaged by
filter capacitor
Voltage for on time Vton
MOSFET on−time t1
Switching period
Minimum Inductor for
CRM
LIpk
t1 +
, or
Vin
Maximum input power
when Vcontrol = 1 V
Minimum ramp capacitor
when Vcontrol = 1 V
Control voltage Vcontrol
CrampVcontrol
Ich
LIpk
t1 +
, or
Vin
t1 +
* Vin CrampVcontrol
ǸVoutVout
T
Ich
³ t1 (t1 + t2) is constant for unity PFC
³ Vcontrol is constant for unity PFC
CrampVcontrol
Vout
t1 ) t2 +
, or
Vout * Vin
Ich
T CrampVcontrol
t1 ) t2 +
, or
t1
Ich
LIpk
Vout
t1 ) t2 +
Vout * Vin Vin
t1 ) t2 +
Same as CRM
2LIch
CrampVcontrol
Same as CRM
Vac2CrampVcontrol
Pin +
2LIch
hV 2C
V
Pout + hPin + ac ramp control
2LIch
Pin_max +
ǸVoutVout* Vin T CrampIchVcontrol
Same as CRM
V
* Vin Vin 1
L u L(CRM) + out
Ipk f
Vout
Zin +
Output power
t1 +
t1
1 ) t2
Vout
³ t1 is constant for unity PFC
³ Vcontrol is constant for unity PFC
Input impedance
Input power
Discontinuous Mode (DCM)
Same as CRM
Same as CRM
Vac2Cramp
2LIch
Same as CRM
P
Cramp u in2 @ 2LIch
Vac
Same as CRM
2LIchPin
Vctrl +
CrampVac2
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16
NCP1601A, NCP1601B
PACKAGE DIMENSIONS
SOIC−8
D SUFFIX
CASE 751−07
ISSUE AG
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
−X−
A
8
5
0.25 (0.010)
S
B
1
M
Y
M
4
K
−Y−
G
C
N
X 45 _
DIM
A
B
C
D
G
H
J
K
M
N
S
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
17
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0 _
8 _
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
NCP1601A, NCP1601B
PACKAGE DIMENSIONS
PDIP−8
N SUFFIX
CASE 626−05
ISSUE L
8
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5
−B−
1
4
F
−A−
NOTE 2
L
C
J
−T−
MILLIMETERS
MIN
MAX
9.40
10.16
6.10
6.60
3.94
4.45
0.38
0.51
1.02
1.78
2.54 BSC
0.76
1.27
0.20
0.30
2.92
3.43
7.62 BSC
−−−
10_
0.76
1.01
INCHES
MIN
MAX
0.370
0.400
0.240
0.260
0.155
0.175
0.015
0.020
0.040
0.070
0.100 BSC
0.030
0.050
0.008
0.012
0.115
0.135
0.300 BSC
−−−
10_
0.030
0.040
N
SEATING
PLANE
D
H
DIM
A
B
C
D
F
G
H
J
K
L
M
N
M
K
G
0.13 (0.005)
M
T A
M
B
M
The products described herein (NCP1601A, NCP1601B), may be covered by the following U.S. patents: 6,271,735, 6,362,067, 6,970,365.
There may be other patents pending.
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NCP1601A/D