OBSOLETE CLC410 www.ti.com SNOS854D – AUGUST 2000 – REVISED APRIL 2013 CLC410 Fast Settling, Video Op Amp with Disable Check for Samples: CLC410 FEATURES DESCRIPTION • • • • • • • The current-feedback CLC410 is a fast settling, wideband, monolithic op amp with fast disable/enable feature. Designed for low gain applications (AV = ±1 to ±8), the CLC410 consumes only 160mW of power (180mW max) yet provides a -3dB bandwidth of 200MHz (AV = +2) and 0.05% settling in 12ns (15ns max). Plus, the disable feature provides fast turn on (100ns) and turn off (200ns). In addition, the CLC410 offers both high performance and stability without compensation - even at a gain of +1. 1 2 -3dB Bandwidth of 200MHz 0.05% Settling in 12ns Low Power, 160mW (40mW Disabled) Low Distortion, -60dBc at 20MHz Fast Disable (200ns) Differential Gain/Phase: 0.01%/0.01° ±1 to ±8 Closed-Loop Gain Range APPLICATIONS • • • • • • • Video Switching and Distribution Analog Bus Driving (with Disable) Low Power “Standby” using Disable Fast, Precision A/D Conversion D/A Current-to-Voltage Conversion IF Processors High Speed Communications The CLC410 provides a simple, high performance solution for video switching and distribution applications, especially where analog buses benefit from use of the disable function to “multiplex” signals onto the bus. Differential gain/phase of 0.01%/0.01° provide high fidelity and the 60mA output current offers ample drive capability. The CLC410's fast settling, low distortion, and high drive capabilities make it an ideal ADC driver. The low 160mW quiescent power consumption and very low 40mW disabled power consumption suggest use where power is critical and/or “system off” power consumption must be minimized. The CLC410 is available in several versions to meet a variety of requirements. A three letter suffix determines the version. Enhanced Solutions (Military/Aerospace) SMD Number: 5962-90600 Space level versions also available. Figure 1. Enable/Disable Response 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2000–2013, Texas Instruments Incorporated OBSOLETE CLC410 SNOS854D – AUGUST 2000 – REVISED APRIL 2013 www.ti.com CONNECTION DIAGRAM Figure 3. Pinout PDIP & SOIC See Package Numbers P and D Figure 2. Non-Inverting Frequency Response These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) (2) Supply Voltage (VCC) IOUT ±7V Output is short circuit protected to ground, but maximum reliability will be maintained if IOUT does not exceed... 60mA Common Mode Input Voltage ±VCC Differential Input Voltage 5V ±VCC−1V Disable Input Voltage (pin 8) Applied output voltage when disabled ±VCC Junction Temperature +150°C −40°C to +85°C Operating Temperature Range −65°C to +150°C Storage Temperature Range Lead Solder Duration (+300°C) 10 sec ESD Rating (human body model) (1) (2) 500V “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be ensured. They are not meant to imply that the devices should be operated at these limits. The table of ELECTRICAL CHARACTERISTICS specifies conditions of device operation. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. OPERATING RATINGS Thermal Resistance Package (θJC) (θJA) PDIP 65°C/W 120°C/W SOIC 60°C/W 140°C/W ELECTRICAL CHARACTERISTICS AV = +2, VCC = ±5V, RL = 100Ω, Rf = 250Ω; unless specified Symbol Parameter Ambient Temperature Max/Min (1) Conditions Typ CLC410AJ +25°C −40°C +25°C +85°C Units VOUT <0.5VPP 200 >150 >150 >120 MHz VOUT <5VPP, AV = +5 50 >35 >35 >35 MHz Frequency Domain Response SSBW -3dB Bandwidth LSBW (1) 2 Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: CLC410 OBSOLETE CLC410 www.ti.com SNOS854D – AUGUST 2000 – REVISED APRIL 2013 ELECTRICAL CHARACTERISTICS (continued) AV = +2, VCC = ±5V, RL = 100Ω, Rf = 250Ω; unless specified Symbol Parameter Conditions Max/Min (1) Typ Units Gain Flatness VOUT< 0.5VPP GFPL Peaking DC to 40MHz 0 <0.4 <0.3 <0.4 dB GFPH Peaking >40MHz 0 <0.7 <0.5 <0.7 dB GFR Rolloff DC to 75MHz 0.6 <1 <1 <1.3 dB DC to 75MHz 0.2 <1 <1 <1.2 deg 0.5V Step 1.6 <2.4 <2.4 <2.4 ns LPD Linear Phase Deviation Time Domain Response TRS Rise and Fall Time TRL TSP Settling Time to TS OS Overshoot SR Slew Rate 5V Step 6.5 <10 <10 <10 ns ±0.1% 2V Step 10 <13 <13 <13 ns ±0.05% 2V Step 12 <15 <15 <15 ns 0.5V Step SR1 0 <15 <10 <10 % AV = +2 700 >430 >430 >430 V/µs AV = −2 1600 – – – V/µs Distortion And Noise Response HD2 2nd Harmonic Distortion 2VPP, 20MHz −60 <−40 <−45 <−45 dBc HD3 3rd harmonic distortion 2VPP, 20MHz −60 <−50 <−50 <−50 dBc −157 <−154 <−154 <−153 dBm (1Hz) Equivalent Input Noise SNF Noise Floor >1MHz (2) INV Integrated Noise 1MHz to 200MHz (2) 40 <54 <57 <63 µV DG Differential Gain (3) (See TYPICAL PERFORMANCE CHARACTERISTICS) 0.01 0.05 0.04 0.04 % DP Differential Phase (3) (See TYPICAL PERFORMANCE CHARACTERISTICS) 0.01 0.1 0.02 0.02 deg Disable/Enable Performance TOFF Disable Time to >50dB Attenuation at 10MHz 200 <1000 <1000 <1000 ns TON Enable Time 100 <200 <200 <200 ns DIS Voltage VDIS To Disable 1.0 0.5 0.5 0.5 V VEN To Enable 2.6 2.3 3.2 4.0 V DIS current (sourced from CLC410, see Figure 23) IDIS To Disable 200 250 250 250 µA IEN To Enable 80 60 60 60 µA 59 >55 >55 >55 dB OSD Off Isolation At 10MHz Static, DC Performance VIO Input Offset Voltage DVIO IBN IBI (4) (4) Non Inverting Average Temperature Coefficient Input Bias Current DIBI (2) (3) average temperature coefficient Input Bias Current DIBN (4) (4) Inverting Average Temperature Coefficient 2 <±8.2 <±5.0 <±9.0 mV 20 <±40 – <±40 µV/°C 10 <±36 <±20 <±20 µA 100 <±200 – <±100 nA/°C 10 <±36 <±20 <±30 µA 50 <±200 – <±100 nA/°C Noise tests are performed from 5MHz to 200MHz. Differential gain and phase measured at: AV = +2, Rf = 250Ω, RL = 150Ω 1VPP equivalent video signal, 0-100 IRE, 40 IREPP, 3.58 MHz, IRE =0 volts, at 75Ω load. See text. AJ-level: spec. is 100% tested at +25°C, sample at 85°C. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: CLC410 3 OBSOLETE CLC410 SNOS854D – AUGUST 2000 – REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) AV = +2, VCC = ±5V, RL = 100Ω, Rf = 250Ω; unless specified Conditions Max/Min (1) Symbol Parameter PSRR Power Supply Rejection Ratio 50 >45 >45 >45 CMRR Common Mode Rejection Ratio 50 >45 >45 >45 dB ICC Supply Current No Load,Quiescent 16 <18 <18 <18 mA ISD Supply Current, Disabled No Load,Quiescent 4 <6 <6 <6 mA Resistance 200 >50 >100 >100 kΩ Capacitance 0.5 <2 <2 <2 pF (4) Typ Units dB Miscellaneous Performance RIN Non-Inverting Input CIN RO Output Impedance At DC 0.1 <0.2 <0.2 <0.2 Ω ROD Output Impedance, Disabled Resistance,at DC 200 <100 <100 <100 kΩ Capacitance,at DC 0.5 <2 <2 <2 pF V COD VO Output Voltage Range No Load ±3.5 >±3 >±3.2 >±3.2 CMIR Common Mode Input Range For Rated Performance ±2.1 >±1.2 >±2 >±2 V IO Output Current −40°C to +85°C ±70 >±35 >±50 >±50 mA −55°C to +125°C ±60 >±30 >±50 >±50 mA IO 4 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: CLC410 OBSOLETE CLC410 www.ti.com SNOS854D – AUGUST 2000 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS (TA = 25°, AV = +2, VCC = ±5V, RL = 100Ω; Unless Specified). Non-Inverting Frequency Response Inverting Frequency Response Figure 4. Figure 5. Frequency Response for Various RLS Forward and Reverse Gain During Disable Figure 6. Figure 7. 2nd and 3rd Harmonic Distortion 2-Tone, 3rd Order, Intermodulation Intercept Figure 8. Figure 9. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: CLC410 5 OBSOLETE CLC410 SNOS854D – AUGUST 2000 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) (TA = 25°, AV = +2, VCC = ±5V, RL = 100Ω; Unless Specified). 6 Equivalent Input Noise CMRR and PSRR Figure 10. Figure 11. Pulse Response Settling Time Figure 12. Figure 13. Long-Term Settling Time Settling Time vs. Capacitive Load Figure 14. Figure 15. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: CLC410 OBSOLETE CLC410 www.ti.com SNOS854D – AUGUST 2000 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) (TA = 25°, AV = +2, VCC = ±5V, RL = 100Ω; Unless Specified). Enable/Disable Response Differential Gain and Phase (3.58MHz) Figure 16. Figure 17. Differential Gain and Phase (4.43MHz) Figure 18. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: CLC410 7 OBSOLETE CLC410 SNOS854D – AUGUST 2000 – REVISED APRIL 2013 www.ti.com APPLICATION DIVISION Figure 19. Recommended Non-Inverting Gain Circuit Figure 20. Recommended Inverting Gain Circuit ENABLE/DISABLE OPERATION The CLC410 has an enable/disable feature that is useful for conserving power and for multiplexing the outputs of several amplifiers onto an analog bus (Figure 21). Disabling an amplifier while not in use reduces power supply current and the output and inverting input pins become a high impedance. 8 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: CLC410 OBSOLETE CLC410 www.ti.com SNOS854D – AUGUST 2000 – REVISED APRIL 2013 Figure 21. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: CLC410 9 OBSOLETE CLC410 SNOS854D – AUGUST 2000 – REVISED APRIL 2013 www.ti.com Figure 22. Pin 8, the DIS pin, can be driven from either open-collector TTL or from 5V CMOS. A logic low disables the amplifier and an internal 15kΩ pull-up resistor ensures that the amplifier is enabled if pin 8 is not connected (Figure 23). Both TTL and 5V CMOS logic are ensured to drive a high enough high-level output voltage (VOH) to ensure that the CLC410 is enabled. Whichever type used, “break-before-make” operation should be established when outputs of several amplifiers are connected together. This is important for avoiding large, transient currents flowing between amplifiers when two or more are simultaneously enabled. Typically, proper operation is ensured if all the amplifiers are driven from the same decoder integrated circuit because logic output rise times tend to be longer than fall times. As a result, the amplifier being disabled will reach the 2V threshold sooner than the amplifier being enabled (see tD of Figure 22 timing diagram). Figure 23. Equivalent of DIS input 10 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: CLC410 OBSOLETE CLC410 www.ti.com SNOS854D – AUGUST 2000 – REVISED APRIL 2013 During disable, supply current drops to approximately 4mA and the inverting input and output pin impedances become 200kΩ‖0.5pF each. The total impedance that a disabled amplifier and its associated feedback network presents to the analog bus is determined from Figure 24. For example, at a non-inverting gain of 1, the output impedance at video frequencies is 100kΩ‖1pF since the 250Ω feedback resistor is a negligible impedance. Similarly, output impedance is 500Ω‖0.5pF at a non-inverting gain of 2 (with Rf = Rg = 250Ω). Figure 24. DIFFERENTIAL GAIN AND PHASE Plots on the preceding page illustrate the differential gain and phase performance of the CLC410 at both 3.58MHz and 4.43MHz. Application Note OA-08 presents a measurement technique for measuring the very low differential gain and phase of the CLC410. Observe that the gain and phase errors remain low even as the output loading increases, making the device attractive for driving multiple video outputs. UNDERSTANDING THE LOOP GAIN The CLC410 is a current-feedback op amp. Referring to the equivalent circuit of Figure 26, any current flowing in the inverting input is amplified to a voltage at the output through the transimpedance gain shown below. This Z(s) is analogous to the open-loop gain of a voltage feedback amplifier. Figure 25. Open-Loop Transimpedance Gain, Z(s) Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: CLC410 11 OBSOLETE CLC410 SNOS854D – AUGUST 2000 – REVISED APRIL 2013 www.ti.com Developing the non-inverting frequency response for the topology of Figure 21 yields: (1) where LG is the loop gain defined by, (2) Equation 1 has a form identical to that for a voltage feedback amplifier with the differences occurring in the LG expression, eq.2. For an idealized treatment, set Zi = 0 which results in a very simple LG=Z(s)/Rf (Derivation of the transfer function for the case where Zi = 0 is given in Application Note AN300-1). Using the Z(s) (open-loop transimpedance gain) plot shown on the previous page and dividing by the recommended Rf = 250Ω, yields a large loop gain at DC. As a result, Equation 1 shows that the closed-loop gain at DC is very close to (1+Rf/Rg). Figure 26. Current Feedback Topology At higher frequencies, the roll-off of Z(s) determines the closed-loop frequency response which, ideally, is dependent only on Rf. The specifications reported on the previous pages are therefore valid only for the specified Rf = 250Ω. Increasing Rf from 250Ω will decrease the loop gain and band width, while decreasing it will increase the loop gain possibly leading to inadequate phase margin and closed-loop peaking. Conversely, fixing Rf will hold the frequency response constant while the closed-loop gain can be adjusted using Rg. The CLC410 departs from this idealized analysis to the extent that the inverting input impedance is finite. With the low quiescent power of the CLC410, Zi≊50Ω leading to drop in loop gain and bandwidth at high gain settlings, as given by Equation 2. The second term in Equation 2 accounts for the division in feedback current that occurs between Zi and Rf∥Rg at the inverting node of the CLC410. This decrease in bandwidth can be circumvented as described in “Increasing Bandwidth at High Gains.” Also see “Current Feedback Amplifiers” in the TI Databook for a thorough discussion of current feedback op amps. INCREASING BANDWIDTH AT HIGH GAINS Bandwidth may be increased at high closed-loop gains by adjusting Rf and Rg to make up for the losses in loop gain that occur at these high gain settlings due to current division at the inverting input. An approximate relationship may be obtained by holding the LG expression constant as the gain is changed from the design point used in the specifications (that is, Rf = 250Ω and Rg = 250Ω). For the CLC400 this gives, 12 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: CLC410 OBSOLETE CLC410 www.ti.com SNOS854D – AUGUST 2000 – REVISED APRIL 2013 where • AVis the non-inverting gain (3) Note that with AV = +2 we get the specified Rf = 250Ω, while at higher gains, a lower value gives stable performance with improved bandwidth. DC ACCURACY AND NOISE Since the two inputs for the CLC410 are quite dissimilar, the noise and offset error performance differs somewhat from that of a standard differential input amplifier. Specifically, the inverting input current noise is much larger than the non-inverting current noise. Also the two input bias currents are physically unrelated rendering bias current cancellation through matching of the inverting and non-inverting pin resistors ineffective. In Equation 4, the output offset is the algebraic sum of the equivalent input voltage and current sources that influence DC operation. Output noise is determined similarly except that a root-sum-of-squares replaces the algebraic sum. Rs is the non-inverting pin resistance. Equation Output Offset VO=±IBN× RS(1+Rf/Rg)± VIO (1+Rf/Rg)±IBI× Rf (4) An important observation is that for fixed Rf, offsets as referred to the input improve as the gain is increased (divide all terms by 1+Rf/Rg). A similar result is obtained for noise where noise figure improves as a gain increases. The input noise plot shown in the CLC400 datasheet applies equally as well to the CLC410. CAPACITIVE FEEDBACK Capacitive feedback should not be used with the CLC410 because of the potential for loop instability. See Application Note OA-7 for active filter realizations with the CLC410. OFFSET ADJUSTMENT PIN Pin 1 can be connected to a potentiometer as shown in Figure 19 and used to adjust the input offset of the CLC410. Full range adjustment of ±5V on pin 1 will yield a ±10mV input offset adjustment range. Pin 1 should always be bypassed to ground with a ceramic capacitor located close to the package for best settling performance. PRINTED CIRCUIT LAYOUT As with any high frequency device, a good PCB layout will enhance performance. Ground plane construction and good power supply bypassing close to the package are critical to achieving full performance. In the non-inverting configuration, the amplifier is sensitive to stray capacitance to ground at the inverting input. Hence, the inverting node connections should be small with minimal coupling to the ground plane. Shunt capacitance across the feedback resistor should not be used to compensate for this effect. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: CLC410 13 OBSOLETE CLC410 SNOS854D – AUGUST 2000 – REVISED APRIL 2013 www.ti.com Parasitic or load capacitance directly on the output will introduce additional phase shift in the loop degrading the loop phase margin and leading to frequency response peaking. A small series resistor before the capacitance effectively decouples this effect. The graphs on the preceding page illustrates the required resistor value and resulting performance vs. capacitance. Precision buffed resistors (PRP8351 series from Precision Resistive Products) with low parasitic reactances were used to develop the data sheet specifications. Precision carbon composition resistors will also yield excellent results. Standard spirally-trimmed RN55D metal film resistors will work with a slight decrease in bandwidth due to their reactive nature at high frequencies. Evaluation PC boards (part no. 730013 for through-hole and 730027 for SOIC) for the CLC404 are available. 14 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: CLC410 OBSOLETE CLC410 www.ti.com SNOS854D – AUGUST 2000 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision C (April 2013) to Revision D • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 14 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: CLC410 15 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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