Product Folder Sample & Buy Support & Community Tools & Software Technical Documents SN5407, SN5417, SN7407, SN7417 SDLS032H – DECEMBER 1983 – REVISED SEPTEMBER 2016 SNx407 and SNx417 Hex Buffers and Drivers With Open-Collector High-Voltage Outputs 1 Features 3 Description • • • • • These TTL hex buffers and drivers feature highvoltage open-collector outputs for interfacing with high-level circuits (such as MOS) or for driving highcurrent loads (such as lamps or relays), and also are characterized for use as buffers for driving TTL inputs. The SN5407 and SN7407 devices have minimum breakdown voltages of 30 V, and the SN5417 and SN7417 devices have minimum breakdown voltages of 15 V. The maximum sink current is 30 mA for the SN5407 and SN5417 devices and 40 mA for the SN7407 and SN7417 devices. 1 Convert TTL Voltage Levels to MOS Levels High Sink-Current Capability Design Open-Collector Driver for Indicator Lamps Inputs Fully Compatible With Most TTL Circuits On Products Compliant to MIL-PRF-38535, All Parameters Are Tested Unless Otherwise Noted. On All Other Products, Production Processing Does Not Necessarily Include Testing of All Parameters. 2 Applications These devices perform the Boolean function Y = A in positive logic. • • • • • These circuits are completely compatible with most TTL families. Inputs are diode clamped to minimize transmission-line effects, which simplifies design. Typical power dissipation is 145 mW, and average propagation delay time is 14 ns. • • • • • Audio Docks: Portable Blu-ray Disc® Players and Home Theaters MP3 Players or Recorders Personal Digital Assistants (PDAs) Power: Telecom and Server AC or DC Supply: Single Controllers: Analog and Digital Solid-State Drive (SSD): Client and Enterprise TV: LCD, Digital, and High-Definition (HDTV) Tablets: Enterprise Video Analytics: Servers Wireless Headsets, Keyboards, and Mice Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) SNx407J, SNx417J CDIP (14) 19.56 mm × 6.92 mm SN74x7D SOIC (14) 8.65 mm × 3.91 mm SN74x7N PDIP (14) 19.30 mm × 6.35 mm SNJ5407FK LCCC (20) 8.89 mm × 8.89 mm SNJ5407W CFP (14) 9.21 mm × 5.97 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Logic Diagram, Each Buffer and Driver (Positive Logic) A Y Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN5407, SN5417, SN7407, SN7417 SDLS032H – DECEMBER 1983 – REVISED SEPTEMBER 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 5 5 5 6 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics .......................................... Typical Characteristics .............................................. Parameter Measurement Information .................. 7 Detailed Description .............................................. 8 8.1 Overview ................................................................... 8 8.2 Functional Block Diagram ......................................... 8 8.3 Feature Description................................................... 8 8.4 Device Functional Modes.......................................... 8 9 Application and Implementation .......................... 9 9.1 Application Information.............................................. 9 9.2 Typical Application .................................................... 9 10 Power Supply Recommendations ..................... 10 11 Layout................................................................... 10 11.1 Layout Guidelines ................................................. 10 11.2 Layout Example .................................................... 10 12 Device and Documentation Support ................. 11 12.1 12.2 12.3 12.4 12.5 12.6 12.7 Documentation Support ........................................ Related Links ........................................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 11 11 11 11 11 11 11 13 Mechanical, Packaging, and Orderable Information ........................................................... 12 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision G (May 2004) to Revision H Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1 • Deleted Ordering Information table; see POA at the end of the data sheet........................................................................... 1 • Added Military Disclaimer to Features.................................................................................................................................... 1 • Changed RθJA values for SN7404: D (SOIC) from 86 to 86.8, N (PDIP) from 80 to 52.1, and NS (SO) from 76 to 85.9 ...... 5 2 Submit Documentation Feedback Copyright © 1983–2016, Texas Instruments Incorporated Product Folder Links: SN5407 SN5417 SN7407 SN7417 SN5407, SN5417, SN7407, SN7417 www.ti.com SDLS032H – DECEMBER 1983 – REVISED SEPTEMBER 2016 5 Pin Configuration and Functions D, N, NS, J, or W Package 14-Pin SOIC, PDIP, CDIP, or CFP Top View 11 5A 3A 5 10 5Y 3Y 6 9 4A GND 7 8 4Y 6A 4 19 2Y 2A 4 18 6Y NC 5 17 NC 2Y 6 16 5A NC 7 15 NC 3A 8 14 5Y 13 6Y VCC 12 20 3 12 2A NC 6A 1 13 11 2 1A 1Y 2 VCC 10 14 1Y 1 9 1A 3 FK Package 20-Pin LCCC Top View 4A 4Y NC GND 3Y Not to scale Not to scale NC – No internal connection Pin Functions PIN I/O DESCRIPTION SOIC, PDIP, CDIP, CFP LCCC 1A 1 2 I Input 1 1Y 2 3 O Output 1 2A 3 4 I Input 2 2Y 4 6 O Output 2 3A 5 8 I Input 3 3Y 6 9 O Output 3 4A 9 13 I Input 4 4Y 8 12 O Output 4 5A 11 16 I Input 5 5Y 10 14 O Output 5 6A 13 19 I Input 6 6Y 12 18 O Output 6 GND 7 10 — Ground Pin NC — 1, 5, 7, 11, 15, 17 — No Connect VCC 14 20 — Power Pin NAME Copyright © 1983–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: SN5407 SN5417 SN7407 SN7417 3 SN5407, SN5417, SN7407, SN7417 SDLS032H – DECEMBER 1983 – REVISED SEPTEMBER 2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN VCC Supply voltage VI Input voltage (2) VO Output voltage (2) (3) TJ Junction temperature Tstg Storage temperature (1) (2) (3) MAX UNIT 7 V 5.5 V SN5407, SN7407 30 SN5417, SN7417 15 –65 V 150 ºC 150 ºC Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to GND. This is the maximum voltage that can safely be applied to any output when it is in the OFF state. 6.2 ESD Ratings VALUE UNIT SN7407 AND SN7417 V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000 Human-body model (HBM) ±2000 V SN5407 AND SN5417 V(ESD) (1) (2) Electrostatic discharge V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage MAX 5 5.5 SN7407, SN7417 4.75 5 5.25 IOL Low-level output current TA Operating free-air temperature UNIT V V 0.8 High-level output voltage 4 NOM 4.5 2 VOH (1) MIN SN5407, SN5417 SN5407, SN7407 30 SN5417, SN7417 15 SN5407, SN5417 30 SN7407, SN7417 40 SN5407, SN5417 –55 125 SN7407, SN7417 0 70 V V mA °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating CMOS Inputs,. Submit Documentation Feedback Copyright © 1983–2016, Texas Instruments Incorporated Product Folder Links: SN5407 SN5417 SN7407 SN7417 SN5407, SN5417, SN7407, SN7417 www.ti.com SDLS032H – DECEMBER 1983 – REVISED SEPTEMBER 2016 6.4 Thermal Information SN7407 THERMAL METRIC (1) SN7417 D (SOIC) N (PDIP) NS (SO) D (SOIC) N (PDIP) 14 PINS 14 PINS 14 PINS 14 PINS 14 PINS UNIT RθJA Junction-to-ambient thermal resistance (2) 86.8 52.1 85.9 88.8 52.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 47.1 39.4 43.9 50.4 39.4 °C/W RθJB Junction-to-board thermal resistance 41 32 44.7 43 32 °C/W ψJT Junction-to-top characterization parameter 15.6 24.2 14.6 16.5 24.2 °C/W ψJB Junction-to-board characterization parameter 40.8 31.8 44.4 42.8 31.8 °C/W (1) (2) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. The package thermal impedance is calculated in accordance with JESD 51-7. 6.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) (1) (2) PARAMETER TEST CONDITIONS VIK Input clamp voltage VCC = MIN, II = –12 mA VOL Low-level output voltage VCC = MIN, VIL = 0.8 V MIN TYP MAX UNIT –1.5 V IOL = 16 mA 0.4 IOL = 30 mA, SN5407, SN5417 0.7 IOL = 40 mA, SN7407, SN7417 0.7 VOH = 30 V, SN5407, SN7407 0.25 VOH = 15 V, SN5417, SN7417 0.25 V IOH High-level output current VCC = MIN, VIH = 2 V II Input current VCC = MAX, VI = 5.5 V 1 mA IIH High-level input current VCC = MAX, VIH = 2.4 V 40 µA IIL Low-level input current VCC = MAX, VIL = 0.4 V –1.6 mA ICCH High-level supply current VCC = MAX 29 41 mA ICCL Low-level supply current VCC = MAX 21 30 mA (1) (2) mA All typical values are at VCC = 5 V, TA = 25°C. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. 6.6 Switching Characteristics VCC = 5 V, TA = 25°C (see Figure 2) PARAMETER tPLH tPHL tPLH tPHL FROM (INPUT) TO (OUTPUT) A Y RL = 110 Ω, CL = 15 pF A Y RL = 150 Ω, CL = 50 pF Copyright © 1983–2016, Texas Instruments Incorporated TEST CONDITIONS MIN TYP MAX 6 10 20 30 15 26 Submit Documentation Feedback Product Folder Links: SN5407 SN5417 SN7407 SN7417 UNIT ns ns 5 SN5407, SN5417, SN7407, SN7417 SDLS032H – DECEMBER 1983 – REVISED SEPTEMBER 2016 www.ti.com 6.7 Typical Characteristics 15 tpd (ns) 12 9 6 3 0 0 5 10 15 20 25 Vout (V) 30 C001 Figure 1. Time Low to High vs VOUT 6 Submit Documentation Feedback Copyright © 1983–2016, Texas Instruments Incorporated Product Folder Links: SN5407 SN5417 SN7407 SN7417 SN5407, SN5417, SN7407, SN7417 www.ti.com SDLS032H – DECEMBER 1983 – REVISED SEPTEMBER 2016 7 Parameter Measurement Information VCC RL From Output Under Test Test Point CL (see Note A) LOAD CIRCUIT 3V 1.5 V Input 1.5 V 0V tPLH High-Level Pulse 1.5 V 1.5 V VOH In-Phase Output 1.5 V 1.5 V 1.5 V VOLTAGE WAVEFORMS PULSE WIDTHS 1.5 V VOL tPHL tw Low-Level Pulse tPHL tPLH VOH Out-of-Phase Output 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES A. CL includes probe and jig capacitance. B. In the examples above, the phase relationships between inputs and outputs have been chosen arbitrarily. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 7 ns, tf ≤ 7 ns. D. The outputs are measured one at a time, with one input transition per measurement. Figure 2. Load Circuit and Voltage Waveforms Copyright © 1983–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: SN5407 SN5417 SN7407 SN7417 7 SN5407, SN5417, SN7407, SN7417 SDLS032H – DECEMBER 1983 – REVISED SEPTEMBER 2016 www.ti.com 8 Detailed Description 8.1 Overview The SN74x7 is a high sink current capable open-collector buffer. This device is high-voltage tolerant on the output of up to 30 V on the SNx407 model and 15 V on the SNx417 model. The SN74x7 is also useful for converting TTL voltage levels to MOS levels. 8.2 Functional Block Diagram VCC 3.4 kΩ 6 kΩ 1.6 kΩ Input A Output Y 100 Ω 1 kΩ GND Copyright © 2016, Texas Instruments Incorporated Resister values shown are nominal. Figure 3. Schematic 8.3 Feature Description The SNx407 and SNx417 devices are ideal for high voltage outputs. The SNx407 device has a maximum output voltage 30 V and the SNx417 device has a maximum output voltage 15 V. The high sink current is up to 40 mA for the SN74x7. 8.4 Device Functional Modes Table 1 lists the functions of the devices. Table 1. Function Table 8 Submit Documentation Feedback INPUT A OUTPUT Y H High-Z L L Copyright © 1983–2016, Texas Instruments Incorporated Product Folder Links: SN5407 SN5417 SN7407 SN7417 SN5407, SN5417, SN7407, SN7417 www.ti.com SDLS032H – DECEMBER 1983 – REVISED SEPTEMBER 2016 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The SN74x7 device is a high-drive, open-collector device that is used for multiple buffer-type functions. The device produces 30 mA of drive current. Therefore, this device is ideal for driving multiple inputs and for highspeed applications up to 100 MHz. The outputs are high voltage tolerant up to 30 V for the SNx407. 9.2 Typical Application Figure 4. Typical Application Diagram 9.2.1 Design Requirements Avoid bus contention because it can drive currents that would exceed maximum limits. The high drive also creates fast edges into light loads; therefore, routing and load conditions must be considered to prevent ringing. 9.2.2 Detailed Design Procedure 1. Recommended Input Conditions – Rise time and fall time specs: See tPHL and tPLH in Switching Characteristics. – Specified high and low levels: See VIH and VIL in Recommended Operating Conditions. 2. Recommend Output Conditions – Load currents must not exceed 30 mA. – Outputs must not be pulled above 30 V for the SNx407 device. Copyright © 1983–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: SN5407 SN5417 SN7407 SN7417 9 SN5407, SN5417, SN7407, SN7417 SDLS032H – DECEMBER 1983 – REVISED SEPTEMBER 2016 www.ti.com Typical Application (continued) 9.2.3 Application Curve 40 IOL (mA) 35 30 25 20 15 0.4 0.5 0.6 0.7 VOL(V) C002 Figure 5. VOL vs IOL 10 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating (see Recommended Operating Conditions). Each VCC pin must have a good bypass capacitor to prevent power disturbance. TI recommends 0.1 µF for devices with a single supply. If there are multiple VCC pins, then TI recommends 0.01 µF or 0.022 µF for each power pin. It is acceptable to parallel multiple bypass capacitors to reject different frequencies of noise. A 0.1 µF and a 1 µF are commonly used in parallel. The bypass capacitor must be installed as close to the power pin as possible for best results. 11 Layout 11.1 Layout Guidelines When using multiple bit logic devices inputs must never float. In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Figure 6 specifies the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally they are tied to GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float outputs, unless the part is a transceiver. 11.2 Layout Example Vcc Input Unused Input Output Output Unused Input Input Figure 6. Layout Diagram 10 Submit Documentation Feedback Copyright © 1983–2016, Texas Instruments Incorporated Product Folder Links: SN5407 SN5417 SN7407 SN7417 SN5407, SN5417, SN7407, SN7417 www.ti.com SDLS032H – DECEMBER 1983 – REVISED SEPTEMBER 2016 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation see the following: Implications of Slow or Floating CMOS Inputs, (SCBA004) 12.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 2. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY SN5407 Click here Click here Click here Click here Click here SN5417 Click here Click here Click here Click here Click here SN7407 Click here Click here Click here Click here Click here SN7417 Click here Click here Click here Click here Click here 12.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert meto register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.5 Trademarks E2E is a trademark of Texas Instruments. Blu-ray Disc is a registered trademark of Blue-ray Disc Association. All other trademarks are the property of their respective owners. 12.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.7 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Copyright © 1983–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: SN5407 SN5417 SN7407 SN7417 11 SN5407, SN5417, SN7407, SN7417 SDLS032H – DECEMBER 1983 – REVISED SEPTEMBER 2016 www.ti.com 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser based versions of this data sheet, refer to the left hand navigation. 12 Submit Documentation Feedback Copyright © 1983–2016, Texas Instruments Incorporated Product Folder Links: SN5407 SN5417 SN7407 SN7417 PACKAGE OPTION ADDENDUM www.ti.com 24-Apr-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) JM38510/00803BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 00803BCA JM38510/00803BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 00803BDA M38510/00803BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 00803BCA M38510/00803BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 00803BDA SN5407J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SN5407J SN5417J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SN5417J SN7407D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 7407 SN7407DE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 7407 SN7407DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 7407 SN7407DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 7407 SN7407DRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 7407 SN7407DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 7407 TBD Call TI Call TI 0 to 70 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN7407J OBSOLETE CDIP J 14 SN7407N ACTIVE PDIP N 14 SN7407N SN7407N3 OBSOLETE PDIP N 14 TBD Call TI Call TI 0 to 70 SN7407NE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN7407N SN7407NSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 SN7407 SN7407NSRE4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 SN7407 Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 24-Apr-2015 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) SN7407NSRG4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 SN7407 SN7417D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 7417 SN7417DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 7417 SN7417N ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SN7417N SN7417N3 OBSOLETE PDIP N 14 TBD Call TI Call TI 0 to 70 SN7417NE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 SNJ5407FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 SNJ5407FK SNJ5407J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ5407J SNJ5407W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ5407W SNJ5417J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ5417J SN7417N (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com (4) 24-Apr-2015 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN5407, SN5417, SN7407, SN7417 : • Catalog: SN7407, SN7417 • Military: SN5407, SN5417 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Military - QML certified for Military and Defense Applications Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 11-Feb-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SN7407DR SOIC SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) D 14 2500 330.0 16.4 6.5 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 9.0 2.1 8.0 16.0 Q1 SN7407DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN7407NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN7417DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Feb-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN7407DR SOIC D 14 2500 333.2 345.9 28.6 SN7407DR SOIC D 14 2500 367.0 367.0 38.0 SN7407NSR SO NS 14 2000 367.0 367.0 38.0 SN7417DR SOIC D 14 2500 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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