Fujitsu MB82DBS08164C-70LWT 128 m bit (8 m wordã 16 bit) mobile phone application specific memory Datasheet

FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-11435-1E
MEMORY Mobile FCRAMTM
CMOS
128 M Bit (8 M word×16 bit)
Mobile Phone Application Specific Memory
MB82DBS08164C-70L
■ DESCRIPTION
The FUJITSU MB82DBS08164C is a CMOS Fast Cycle Random Access Memory (FCRAM*) with asynchronous
Static Random Access Memory (SRAM) interface containing 134,217,728 storages accessible in a 16-bit format.
MB82DBS08164C is utilized using a FUJITSU advanced FCRAM core technology and improved integration in
comparison to regular SRAM.
The MB82DBS08164C adopts asynchronous mode and synchronous burst mode for fast memory access as user
configurable options.
This MB82DBS08164C is suited for mobile applications such as Cellular Handset and PDA.
* : FCRAM is a trademark of Fujitsu Limited, Japan
■ FEATURES
• Asynchronous SRAM Interface
• COSMORAM Revision 3 Compliance
(COSMORAM : Common Specifications of Mobile RAM)
• Fast Access Time : tCE = 70 ns Max
• Burst Read/Write Access Capability :
tCK = 9.5 ns Min /104 MHz Max
tAC = 6 ns Max
• Low Voltage Operating Condition : VDD = 1.7 V to 1.95 V
• Wide Operating Temperature : TA = − 30 °C to + 85 °C
Junction Temperature : TJ = − 30 °C to + 90 °C
• Byte Control by LB and UB
• Low-Power Consumption : IDDA1 = 40 mA Max
IDDS1 = 300 µA Max
• Various Power Down mode : Sleep
16 M-bit Partial
32 M-bit Partial
64 M-bit Partial
• Shipping Form : Wafer/Chip
Copyright©2006 FUJITSU LIMITED All rights reserved
MB82DBS08164C-70L
■ PRODUCT LINEUP
Parameter
Access Time (Max) (tCE, tAA)
RL = 6, 7
CLK Access Time (Max) (tAC)
Active Current (Max) (IDDA1)
Standby Current (Max) (IDDS1)
Power Down Current (Max) (IDDPS)
MB82DBS08164C-70L
70 ns
6 ns
40 mA
300 µA
10 µA
■ PIN DESCRIPTION
Pin Name
A22 to A0
Description
Address Input
CE1
Chip Enable 1 (Low Active)
CE2
Chip Enable 2(High Active)
WE
Write Enable (Low Active)
OE
Output Enable (Low Active)
LB
Lower Byte Control (Low Active)
UB
Upper Byte Control (Low Active)
CLK
Clock Input
ADV
Address Valid Input (Low Active)
WAIT
Wait Output
DQ7 to DQ0
Lower Byte Data Input/Output
DQ15 to DQ8
Upper Byte Data Input/Output
VDD
Power Supply Voltage
VSS
Ground
Note : Refer to "■PACKAGE FOR ENGINEERING SAMPLES" for additional pin descriptions of FBGA package
supply.
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MB82DBS08164C-70L
■ BLOCK DIAGRAM
VDD
VSS
A22 to A0
CLK
WAIT
COMMAND
DECODER
BURST
ADDRESS
COUNTER
MEMORY
CELL
ARRAY
134,217,728 bits
ADDRESS
CONTROLLER
MEMORY
CORE
CONTROLLER
BURST
CONTROLLER
X CONTROLLER
MODE
CONTROLLER
CE2
CE1
ADV
WE
OE
LB
UB
Y CONTROLLER
ADDRESS
LATCH &
BUFFER
BUS
CONTROLLER
READ
AMP
WRITE
AMP
PARALLEL
SERIAL
TO SERIAL
TO PARALLEL
CONVERSION CONVERSION
CONVERTER
DQ15 to DQ8
I/O
BUFFER
DQ7 to DQ0
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MB82DBS08164C-70L
■ FUNCTION TRUTH TABLE
1. Asynchronous Operation
Mode
Standby
(Deselect)
CE2 CE1 CLK ADV
H
H
WE
OE
LB
UB A22 to A0 DQ7 to DQ0 DQ15 to DQ8
WAIT
X
X
X
X
X
X
X
High-Z
High-Z
High-Z
Output Disable*1
X
*3
H
H
X
X
*5
High-Z
High-Z
High-Z
Output Disable
(No Read)
X
*3
H
H
Valid
High-Z
High-Z
High-Z
Read (Upper Byte)
X
*3
H
L
Valid
High-Z
Output
Valid
High-Z
H
L
X
*3
L
H
Valid
Output
Valid
High-Z
High-Z
X
*3
L
L
Valid
Output
Valid
Output
Valid
High-Z
No Write
X
*3
H
H
Valid
Invalid
Invalid
High-Z
Write (Upper Byte)
X
*3
H
L
Valid
Invalid
Write (Lower Byte)
X
*3
L
H
Valid
Input
Valid
Write (Word)
X
*3
L
L
Valid
Input
Valid
X
X
X
X
X
High-Z
Read (Lower Byte)
Read (Word)
Power Down*2
H
L
L
X
L
X
H*4
X
Input Valid High-Z
Invalid
High-Z
Input Valid High-Z
High-Z
High-Z
Note : L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High Impedance
*1 : Should not be kept this logic condition longer than 1 µs.
*2 : Power Down mode can be entered from Standby state and all output are in High-Z state.
Data retention depends on the selection of Partial Size for Power Down Program. Refer to "Power Down" in
"■FUNCTIONAL DESCRIPTION" for the details.
*3 : "L" for address pass through and "H" for address latch on the rising edge of ADV.
*4 : OE can be VIL during write operation if the following conditions are satisfied;
(1) Write pulse is initiated by CE1. Refer to "(11) Asynchronous Read/Write Timing 1-1 (CE1 Control)" in
"■TIMING DIAGRAMS".
(2) OE stays VIL during Write cycle.
*5 : Can be either VIL or VIH but must be valid before Read or Write.
4
MB82DBS08164C-70L
2. Synchronous Operation (Burst Mode)
Mode
CE2 CE1 CLK ADV WE
Standby(Deselect)
Start Address Latch*
H
X
X
1
3
X*
Advance Burst Read to
Next Address*1
Burst Read
Suspend*1
Advance Burst Write to
Next Address*1
Burst Write Suspend*
X
OE
LB
X
X
UB A22 to A0 DQ7 to DQ0 DQ15 to DQ8
X
3
X*
X
Valid*
High-Z
6
H
H
High-Z*10
Output
Valid*8
Output
Valid
H
High-Z
High-Z
High*11
Input
Valid*9
Input
Valid*9
High*12
Input
Invalid
Input
Invalid
High*11
X*5
L*4
H*
High-Z*
Output
Valid*8
X*5
X
H
1
High-Z
7
L
H
L
High-Z*
High-Z
7
WAIT
4
Terminate Burst Read
X
H
X
High-Z
High-Z
High-Z
Terminate Burst Write
X
X
H
High-Z
High-Z
High-Z
X
X
High-Z
High-Z
High-Z
Power Down*
2
L
X
X
X
Note : L = VIL, H = VIH, X can be either VIL or VIH,
High-Z = High impedance
X
= valid edge,
X
X
= rising edge of Low pulse,
*1
: Should not be kept this logic condition longer than 4 µs.
*2
: Power Down mode can be entered from Standby state and all output are in High-Z state.
Data retention depends on the selection of Partial Size for Power Down Program.
Refer to "Power Down" in “■FUNCTIONAL DESCRIPTION” for the details.
*3
: Can be either VIL or VIH except for the case the both of OE and WE are VIL.
It is prohibited to bring the both of OE and WE to VIL.
*4
: When device is operating in "WE Single Clock Pulse Control" mode, WE is a “don't care” once write operation
is determined by WE Low Pulse at the beginning of write access together with address latching. Burst write
suspend feature is not supported in "WE Single Clock Pulse Control" mode.
*5
: Can be either VIL or VIH. During burst write operation, byte write control by LB and UB can be performed at
each clock cycle. During read operation, LB and UB must be valid before read operation is initiated. And once
LB and UB input levels are determined, they must not be changed until the end of burst.
*6
: Once a valid address is determined, the input address must not be changed during ADV = L.
*7
: If OE = L, output is either Invalid or High-Z depending on the level of LB and UB input. If WE = L, input is
Invalid. If OE = WE = H, output is High-Z.
*8
: Outputs is either Valid or High-Z depending on the level of LB and UB input.
*9
: Input is either Valid or Invalid depending on the level of LB and UB input.
*10 : Output is either High-Z or Invalid depending on the level of OE and WE input.
*11 : Keep the level from previous cycle except for suspending on last data. Refer to "WAIT Output Function" in
"■FUNCTIONAL DESCRIPTION" for the details.
*12 : WAIT output is driven in High level during burst write operation.
5
MB82DBS08164C-70L
■ STATE DIAGRAM
• Initial/Standby State
Asynchronous Operation
(Page Mode)
Power Up
Synchronous Operation
(Burst Mode)
Power
Down
@M = 1
CE2 = H
CE2 = L
Common State
CR Set
Pause Time
Power
Down
CE2 = H
@M = 0
Standby
Standby
CE2 Low Pulse
@RA = 0
CE2 = L
@RA = 1
• Asynchronous Operation
Standby
CE1 = L
CE1 = L &
WE = L
CE1 = H
Byte
Control
CE1 = L &
OE = L
CE1 = H
Output
Disable
CE1 = H
WE = H
Address Change
or Byte Control
OE = L
WE = L
OE = H
Write
Read
Byte Control @OE = L
• Synchronous Operation
Standby
CE1 = H
Write
Suspend
CE1 = H
CE1 = H
WE = H
WE = L
Write
CE1 = L,
ADV Low Pulse,
& WE = L
CE1 = H
CE1 = L,
ADV Low Pulse,
& OE = L
Read
Suspend
OE = H
OE = L
Read
Note : Assuming all the parameters specified in AC CHARACTERISTICS are satisfied. Refer to the "■FUNCTIONAL
DESCRIPTION", "2. AC Characteristics" in "■ELECTRICAL CHARACTERISTICS", and "■TIMING DIAGRAMS" for details.
6
MB82DBS08164C-70L
■ FUNCTIONAL DESCRIPTION
This device supports asynchronous read & normal write operation and synchronous burst read and burst write
operations for faster memory access and features four kinds of power down modes for power saving as user
configurable option.
• Power-up
It is required to follow the power-up timing to start executing proper device operation. Refer to "Power-up Timing".
After Power-up, the device defaults to asynchronous read & normal write operation mode with sleep power down
feature.
• Configuration Register
The Configuration Register(CR) is used to configure the type of device function among optional features. Each
selection of features is set through CR Set sequence after power-up. If CR Set sequence is not performed after
power-up, the device is configured for asynchronous operations with sleep power down feature as default configuration. The content of CR can be confirmed using CR Verify sequence.
• CR Set & Verify Sequence
The CR Set and CR Verify requires total 6 read/write operations with unique address. The device should be in
standby mode in the interval between each read/write operation. The following table shows the detail sequence
of CR Set and CR Verify.
Cycle #
Address
1st
CR Set
CR Verify
Operation
Data
Operation
Data
7FFFFFh (MSB)
Read
Read Data (RDa)
Read
Read Data (RDa)
2nd
7FFFFFh
Write
RDa
Write
RDa
3rd
7FFFFFh
Write
RDa
Write
RDa
4th
7FFFFFh
Write
CR Key 0
Write
CR Key 0
5th
7FFFFFh
Write
CR Key 1
Read
CR Key 1
6th
7FFFFFh
Write
CR Key 2
Read
CR Key 2
The first cycle is to read from most significant address(MSB).
The second and third cycles are to write to MSB. If the second or third cycle is written into the different address,
the CR Set is cancelled and the data written by the second or third cycle is valid as a normal write operation. It
is recommended to write back the data(RDa) read by first cycle to MSB in order to secure the data.
The fourth cycle is to write the appropriate “CR Key 0” to select the CR Set or CR Verify.
The fifth and sixth cycle is to access into MSB to set the “CR Keys” or to verify the “CR Keys”. Refer to the "CR
Key Table". If the fourth to sixth cycle are not access into MSB , the CR Set or CR Verify are cancelled and CR
input or output data will be invalid.
Once this CR Set sequence is performed from an initial CR Set to the other new CR Set, the written data stored
in the memory cell array may be lost. Therefore CR Set sequence should be performed prior to regular read/
write operation if necessary to change from the default configuration.
7
MB82DBS08164C-70L
• CR Key Table
CR Key 0
CR Key 0 should be set at 4th cycle of the CR Set or Verify sequence.
Register
Pin Name
Function
Key
Name
Description
Note
0
CR Verify
1
CR Set
⎯
1
Reserved for future use
*1
⎯
1
Unused bits must be 1
*2
DQ0
CRSV
CR Set/Verify
DQ7 to DQ1
⎯
DQ15 to DQ8
⎯
CR Key 1
CR Key 1 should be set or read at 5th cycle of the CR Set or Verify sequence.
Register
Pin Name
Function
Key
Description
Name
DQ1, DQ0
PS
Partial Size
00
32M-bit Partial
*3
01
16M-bit Partial
*3
10
64M-bit Partial
*3
11
Sleep [Default]
*3
Reserved for future use
*1
000, 001
DQ4 to DQ2
BL
Burst Length
010
8 words
011
16 words
100 to 110 Reserved for future use
111
DQ5
DQ7, DQ6
DQ15 to DQ8
8
M
DS
⎯
⎯
*1
Continuous
0
Synchronous Mode
(Burst Read/Write)
*4
1
Asynchronous Mode [Default]
(Random Read/Write)
*5
00
+
01
Reserved for future use
10
−
11
Center [Default]
1
Unused bits must be 1
Mode
Driver Size
Note
*1
*2
MB82DBS08164C-70L
CR Key 2
CR Key 2 should be set or read at 6th cycle of the CR Set or Verify sequence.
Register
Pin Name
Function
Key
Description
Name
000, 001
DQ2 to DQ0
RL
Read Latency
DQ3
⎯
⎯
DQ4
SW
Single Write
DQ5
VE
Valid Clock Edge
DQ6
RA
Reset to Asynchronous
DQ7
DQ15 to DQ8
WC
010
4 clocks
011
5 clocks
100
6 clocks
101
7 clocks
⎯
*1
110, 111
Reserved for future use
*1
1
Reserved for future use
*2
0
Burst Read & Burst Write
1
Reserved for future use
*1
0
Reserved for future use
*1
1
Rising Clock Edge
0
Reset to Asynchronous mode
*6
1
Remain the previous mode
*3
0
WE Single Clock Pulse Control
without Write Suspend Function
1
WE Level Control
with Write Suspend Function
1
Unused bits must be 1
Write Control
⎯
Reserved for future use
Note
*2
*1 : It is prohibited to apply this key.
*2 : Must be set to “1”.
*3 : Sleep and Partial power down mode are effective only when RA = 1.
*4 : If M = 0, all the registers must be set with appropriate Key input at the same time.
*5 : If M = 1, PS and DS must be set with appropriate Key input at the same time. Except for PS and DS, all the
other key inputs must be “1”.
*6 : In case of RA = 0, CE2 brought to Low reset the device to asynchronous standby state regardless PS set
value therefore Sleep and Partial power down mode are not available.
9
MB82DBS08164C-70L
• Power Down
The Power Down is low power idle state controlled by CE2. CE2 Low drives the device in power down mode
and maintains low power idle state as long as CE2 is kept Low. CE2 High resumes the device from power down
mode.
This device has four power down modes, Sleep, 16 M-bit Partial, 32 M-bit Partial, and 64 M-bit Partial. Those
power down modes are effective when RA = 1. The selection of power down mode is set through CR Set
sequence. Each mode has following data retention features.
Mode
Data Retention Size
Retention Address
Sleep [default]
No
N/A
16 M-bit Partial
16 M bits
000000h to 0FFFFFh
32 M-bit Partial
32 M bits
000000h to 1FFFFFh
64 M-bit Partial
64 M bits
000000h to 3FFFFFh
The default state after power-up is Sleep and it is the lowest power consumption. However all data will be lost
once CE2 is brought to Low for Power Down. It is not required to perform CR Set sequence to set to Sleep mode
after power-up in case of asynchronous operation.
When RA = 0, CE2 brought to Low reset the device to asynchronous standby state regardless PS set value.
• Burst Read/Write Operation
Synchronous burst read/write operation provides faster memory access that synchronized to the microcontroller
or system bus frequency. Configuration Register(CR) Set is required to perform a burst read & write operation
after power-up. Once CR Set sequence is performed to select the synchronous burst mode, the device is
configured to synchronous burst read/write operation mode with corresponding RL and BL that is set through
CR Set sequence together with the operation mode. In order to perform synchronous burst read & write operation,
it is required to control new signals, CLK, ADV and WAIT that Low Power SRAMs don’t have.
10
MB82DBS08164C-70L
• Burst Read Operation
CLK
Address
Valid address
ADV
CE1
OE
WE
High
RL
DQ
High-Z
WAIT
High-Z
Q1
Q2
QBL
BL
• Burst Write Operation
CLK
Address
Valid address
ADV
CE1
OE
High
WE
RL-1
DQ
High-Z
D1
D2
DBL
BL
WAIT
High-Z
• CLK Input Function
The CLK is input signal to synchronize the memory to the microcontroller or system bus frequency during
synchronous burst read & write operation. The CLK input increments the device internal address counter and
the valid edge of CLK is referred for latency counts from address latch, burst write data latch, and the burst read
data output. During synchronous operation mode, CLK input must be supplied except for standby state and
power down state. CLK is a “don't care” during asynchronous operation.
11
MB82DBS08164C-70L
• ADV Input Function
The ADV is input signal to latch the valid address. It is applicable to the synchronous operation as well as
asynchronous operation. ADV input is active during CE1 = L and CE1 = H disables ADV input. All addresses
are determined on the rising edge of ADV.
During synchronous burst read/write operation, ADV = H disables all address inputs. Once ADV is brought to
High after the valid address latch, it is inhibited to bring ADV Low until the end of burst or until the burst operation
is terminated. ADV Low pulse is mandatory for the synchronous burst read/write operation mode to latch the
valid address input.
During asynchronous operation, ADV = H also disables all address inputs. ADV can be tied to Low during
asynchronous operations and it is not necessary to control ADV to High.
• WAIT Output Function
The WAIT is output signal to indicate the data bus status when the device is operating in the synchronous burst
mode.
During burst read operation, WAIT output is enabled after specified time duration from OE = L or CE1 = L
whichever occurs last. WAIT output Low indicates data output at next clock cycle is invalid, and WAIT output
becomes High one clock cycle prior to valid data output. During OE read suspend, WAIT output doesn’t indicate
the data bus status but carries the same level from previous clock cycle (kept High) except for the burst read
suspend on the final data output. If final read data output is suspended, WAIT output becomes high impedance
after specified time duration from OE = H.
During burst write operation, WAIT output is enabled to High level after specified time duration from WE = L or
CE1 = L whichever occurs last and kept High for entire write cycles including WE write suspend. The actual write
data latching starts on the appropriate clock edge with respect to Read Latency, and Burst Length. During WE
write suspend, WAIT output doesn’t indicate the data bus status but carries the same level from previous clock
cycle (kept High) except for write suspend on the final data input. If final write data input is suspended, WAIT
output becomes high impedance after specified time duration from WE = H.
This device doesn’t incur additional output delay against crossing device-row boundary or internal refresh
operation. Therefore, the burst operation is always started after the fixed latency with respect to Read Latency.
And there is no waiting cycle asserted in the middle of burst operation except for the burst read or write suspend
by OE brought to High or WE brought to High. Thus, once WAIT output is enabled and brought to High, WAIT
output keeps High level until the end of burst or until the burst operation is terminated.
When the device is operating in the asynchronous mode, WAIT output is always in High Impedance.
• Latency
Read Latency (RL) is the number of clock cycles between the address being latched and first read data becoming
available during synchronous burst read operation. It is set through CR Set sequence after power-up. Once
specific RL is set through CR Set sequence, write latency, that is the number of clock cycles between address
being latched and first write data being latched, is automatically set to RL-1.
The burst operation is always started after the fixed latency with respect to Read Latency set in CR.
12
MB82DBS08164C-70L
CLK
0
Address
1
2
3
4
5
6
7
Valid address
ADV
CE1
OE or WE
RL = 4
DQ [Output]
WAIT
Q2
Q3
Q4
D2
D3
D4
D5
Q1
Q2
Q3
D2
D3
D4
Q1
Q2
D2
D3
High-Z
D1
DQ [Input]
WAIT
Q1
High-Z
RL = 5
DQ [Output]
WAIT
High-Z
D1
DQ [Input]
WAIT
High-Z
RL = 6
DQ [Output]
WAIT
High-Z
D1
DQ [Input]
WAIT
High-Z
RL = 7
DQ [Output]
WAIT
Q1
High-Z
D1
DQ [Input]
WAIT
D2
High-Z
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MB82DBS08164C-70L
• Address Latch by ADV
The ADV latches the valid address presence on address inputs. During synchronous burst read/write operation
mode, all the addresses are determined on the rising edge of ADV when CE1 = L. The specified minimum value
of ADV = L setup time and hold time against valid edge of clock where RL count is begun must be satisfied.
Valid address must be determined with specified setup time against either the falling edge of ADV or falling edge
of CE1 whichever comes late. And the determined valid address must not be changed during ADV = L period.
• Burst Length
Burst Length is the number of word to be read or written during synchronous burst read/write operation as the
result of a single address latch cycle. It can be set on 8,16 words boundary or continuous for entire address
through CR Set sequence. The burst type is sequential that is incremental decoding scheme within a boundary
address. Starting from an initial address being latched, the device internal address counter assigns +1 to the
previous address until reaching the end of boundary address and then wrap round to least significant address
(= 0). After completing read data output or write data latch for the set burst length, operation automatically ended
except for continuous burst length. When continuous burst length is set, read/write is endless unless it is terminated by the rising edge of CE1.
• Write Control
The device has two types of WE signal control method, "WE Level Control" and "WE Single Clock Pulse Control",
for synchronous burst write operation. It is configured through CR Set sequence.
CLK
0
Address
1
2
3
4
5
D1
D2
D3
D4
D1
D2
D3
D4
6
Valid address
ADV
RL = 5
CE1
tCLTH
WAIT
High-Z
tWLTH
WE Level Control
tWLD
WE
DQ
[Input]
WE Single Clock Pulse Control
tWSCK
WE
tCKWH
DQ
14
[Input]
MB82DBS08164C-70L
• Burst Read Suspend
Burst read operation can be suspended by OE High pulse. During burst read operation, OE brought to High
from Low suspends the burst read operation. Once OE is brought to High with the specified setup time against
clock where the data being suspended, the device internal counter is suspended, and the data output becomes
high impedance after specified time duration. It is inhibited to suspend the first data output at the beginning of
burst read.
OE brought to Low from High resumes the burst read operation. Once OE is brought to Low, data output becomes
valid after specified time duration, and the internal address counter is reactivated. The last data output being
suspended as the result of OE = H and first data output as the result of OE = L are from the same address.
In order to guarantee to output last data before suspension and first data after resumption, the specified minimum
value of OE = L hold time and setup time against clock edge must be satisfied respectively.
CLK
tCKOH tOSCK
tCKOH tOSCK
OE
tOHZ
tAC
Q1
DQ
tCKQX
tCKTV
tAC
Q2
tOLZ
tAC
tAC
Q2
Q4
Q3
tCKQX
tCKQX
WAIT
• Burst Write Suspend
Burst write operation can be suspended by WE High pulse. During burst write operation, WE brought to High
from Low suspends the burst write operation. Once WE is brought to High with the specified setup time against
clock where the data being suspended, the device internal counter is suspended, data input is ignored. It is
inhibited to suspend the first data input at the beginning of burst write.
WE brought to Low from High resumes the burst write operations. Once WE is brought to Low, data input becomes
valid after specified time duration, and the internal address counter is reactivated. The write address of the cycle
where data being suspended and the first write address as the result of WE = L are the same address.
In order to guarantee to latch the last data input before suspension and first data input after resumption, the
specified minimum value of WE = L hold time and setup time against clock edge must be satisfied respectively.
Burst write suspend function is available when the device is operating in WE level controlled burst write only.
CLK
tCKWH tWSCK
tCKWH tWSCK
WE
tDSCK
tDSCK
D1
DQ
tDHCK
WAIT
D2
tDSCK
D2
tDHCK
tDSCK
D3
D4
tDHCK
High
15
MB82DBS08164C-70L
• Burst Read Termination
Burst read operation can be terminated by CE1 brought to High. If BL is set on Continuous, the burst read
operation is continued endlessly unless terminated by CE1 = H. It is inhibited to terminate the burst read before
first data output is completed. In order to guarantee last data output, the specified minimum value of CE1 = L
hold time from the clock edge must be satisfied. After termination, the specified minimum recovery time is required
to start a new access.
CLK
Vaild
Address
ADV
tTRB
tCKCLH
tCHZ
tCKOH
tOHZ
CE1
OE
WAIT
DQ
High-Z
tCHTZ
Q2
Q1
Q0
tCKQX
tAC
tCKQX
tAC
• Burst Write Termination
Burst write operation can be terminated by CE1 brought to High. If BL is set on Continuous, the burst write
operation is continued endlessly unless terminated by CE1 = H. It is inhibited to terminate the burst write before
first data input is completed. In order to guarantee last data input being latched, the specified minimum values
of CE1 = L hold time from the clock edge must be satisfied. After termination, the specified minimum recovery
time is required to start a new access.
CLK
Vaild
Address
ADV
tTRB
tCHCK
tCKCLH
CE1
WAIT
tWSCK
tCKWH
WE
tDSCK
tCHTZ
tDSCK
High-Z
tDSCK
DQ
D1
tDHCK
16
D2
tDHCK
D0
tDHCK
MB82DBS08164C-70L
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Min
Max
VDD
− 0.5
+ 2.6
V
VIN, VOUT
− 0.5
+ 2.6
V
Short Circuit Output Current
IOUT
− 50
+ 50
mA
Storage Temperature
Tstg
− 55
+ 125
°C
Voltage of VDD Supply Relative to VSS *
Voltage at Any Pin Relative to VSS *
* : All voltages are referenced to VSS = 0 V.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Value
Unit
Min
Max
VDD
1.7
1.95
V
VSS
0
0
V
High Level Input Voltage* *
VIH
VDD × 0.8
VDD + 0.2
V
Low Level Input Voltage*1, *3
VIL
− 0.3
VDD × 0.2
V
Ambient Temperature
TA
− 30
+ 85
°C
Junction Temperature
TJ
− 30
+ 90
°C
Power Supply Voltage*1
Ground
1, 2
*1 : All voltages are referenced to VSS = 0 V.
*2 : Maximum DC voltage on input and I/O pins is VDD + 0.2 V. During voltage transitions, inputs may overshoot to
VDD + 1.0 V for the periods of up to 5.0 ns.
*3 : Minimum DC voltage on input or I/O pins is -0.3 V. During voltage transitions, inputs may undershoot VSS to
-1.0 V for the periods of up to 5.0 ns.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
17
MB82DBS08164C-70L
■ ELECTRICAL CHARACTERISTICS
1. DC Characteristics
Parameter
Symbol
(At recommended operating conditions unless otherwise noted)
Value
Test Conditions
Unit
Min
Max
Input Leakage Current
ILI
VSS ≤ VIN ≤ VDD
− 1.0
+ 1.0
µA
Output Leakage Current
ILO
0 V ≤ VOUT ≤ VDD,
Output Disable
− 1.0
+ 1.0
µA
Output High Voltage Level
VOH
VDD = VDD (Min), IOH = − 0.5 mA
1.4
⎯
V
Output Low Voltage Level
VOL
IOL = 1 mA
⎯
0.4
V
Sleep
⎯
10
µA
16 M-bit Partial
⎯
130
µA
32 M-bit Partial
⎯
160
µA
64 M-bit Partial
⎯
210
µA
IDDPS
VDD Power Down Current
IDDP16
IDDP32
VDD = VDD (Max),
VIN = VIH or VIL,
CE2 ≤ 0.2 V
IDDP64
VDD Standby Current
IDDS
VDD = VDD (Max),
VIN (including CLK) = VIH or VIL,
CE1 = CE2 = VIH
⎯
1.5
mA
IDDS1
VDD = VDD (Max),
VIN (including CLK) ≤ 0.2 V or
VIN (including CLK) ≥ VDD − 0.2 V,
CE1 = CE2 ≥ VDD − 0.2 V
⎯
300
µA
IDDS2
VDD = VDD (Max), tCK = tCK (Min)
VIN ≤ 0.2 V or VIN ≥ VDD − 0.2 V,
CE1 = CE2 ≥ VDD − 0.2 V
⎯
400
µA
tRC/tWC = Min
⎯
40
mA
tRC/tWC = 1 µs
⎯
5
mA
⎯
40
mA
IDDA1
VDD Active Current
IDDA2
VDD Burst Access Current
IDDA4
VDD = VDD (Max),
VIN = VIH or VIL,
CE1 = VIL and CE2 = VIH,
IOUT = 0 mA
VDD = VDD (Max),
VIN = VIH or VIL,
CE1 = VIL and CE2 = VIH,
tCK = tCK (Min), BL = Continuous,
IOUT = 0 mA
Notes : • All voltages are referenced to VSS = 0 V.
• IDD depends on the output termination, load conditions, and AC characteristics.
• After power on, initialization following POWER-UP timing is required. DC characteristics are guaranteed
after the initialization.
18
MB82DBS08164C-70L
2. AC Characteristics
(1) Asynchronous Read Operation
Parameter
(At recommended operating conditions unless otherwise noted)
Value
Symbol
Unit
Notes
Min
Max
Read Cycle Time
tRC
70
1000
ns
*1, *2
CE1 Access Time
tCE
⎯
70
ns
*3
OE Access Time
tOE
⎯
40
ns
*3
Address Access Time
tAA
⎯
70
ns
*3, *5
ADV Access Time
tAV
⎯
70
ns
*3
LB, UB Access Time
tBA
⎯
30
ns
*3
Output Data Hold Time
tOH
3
⎯
ns
*3
CE1 Low to Output Low-Z
tCLZ
10
⎯
ns
*4
OE Low to Output Low-Z
tOLZ
10
⎯
ns
*4
LB, UB Low to Output Low-Z
tBLZ
10
⎯
ns
*4
CE1 High to Output High-Z
tCHZ
⎯
10
ns
*3
OE High to Output High-Z
tOHZ
⎯
10
ns
*3
LB, UB High to Output High-Z
tBHZ
⎯
10
ns
*3
Address Setup Time to OE Low
tASO
5
⎯
ns
Address Setup Time to ADV Low
tASVL
−2
⎯
ns
*6
Address Setup Time to CE1 Low
tASC
−5
⎯
ns
*6
Address Hold Time from ADV High
tAHV
5
⎯
ns
ADV Low Pulse Width
tVPL
10
⎯
ns
*6
Address Invalid Time
tAX
⎯
10
ns
*5, *7
Address Hold Time from CE1 High
tCHAH
−5
⎯
ns
*8
Address Hold Time from OE High
tOHAH
−5
⎯
ns
WE High to OE Low Time for Read
tWHOL
10
1000
ns
tCP
10
⎯
ns
CE1 High Pulse Width
*9
*1 : Maximum value is applicable if CE1 is kept at Low without change of address input.
*2 : Address should not be changed within a minimum tRC.
*3 : The output load 50 pF with 50 Ω termination to VDD × 0.5 V.
*4 : The output load 5 pF without any other load.
*5 : Applicable when CE1 is kept at Low.
*6 : tVPL is specified from the falling edge of either CE1 or ADV whichever comes late. The sum of actual tVPL and
tASVL (or tASC) must be equal or greater than the specified minimum value of tVPL.
*7 : Applicable to address access when at least two of address inputs are switched from the previous state.
*8 : tRC (Min) must be satisfied.
*9 : Applicable to Write to Read sequence controlled by WE and OE, Read operation is initiated after tWHOL (Min)
from the rising edge of WE therefore tAA is specified after tWHOL (Min) .
19
MB82DBS08164C-70L
(2) Asynchronous Write Operation
Parameter
(At recommended operating conditions unless otherwise noted)
Value
Symbol
Unit
Notes
Min
Max
Write Cycle Time
tWC
70
1000
ns
*1, *2
Address Setup Time
tAS
0
⎯
ns
*3
Address Setup Time to ADV Low
tASVL
−2
⎯
ns
*4
Address Hold Time from ADV High
tAHV
5
⎯
ns
ADV Low Pulse Width
tVPL
10
⎯
ns
*4
CE1 Write Pulse Width
tCW
45
⎯
ns
*3
WE Write Pulse Width
tWP
45
⎯
ns
*3
LB, UB Write Pulse Width
tBW
45
⎯
ns
*3
LB, UB Byte Mask Setup Time
tBS
−5
⎯
ns
*5
LB, UB Byte Mask Hold Time
tBH
−5
⎯
ns
*6
Write Recovery Time
tWR
0
⎯
ns
*7
CE1 High Pulse Width
tCP
10
⎯
ns
WE High Pulse Width
tWHP
10
1000
ns
LB, UB High Pulse Width
tBHP
10
1000
ns
Data Setup Time
tDS
15
⎯
ns
Data Hold Time
tDH
0
⎯
ns
OE High to CE1 Low Setup Time for Write
tOHCL
−5
⎯
ns
*8
OE High to Address Setup Time for Write
tOES
0
⎯
ns
*9
*1 : Maximum value is applicable if CE1 is kept at Low without any address change.
*2 : Minimum value must be equal or greater than the sum of write pulse width (tCW, tWP or tBW) and write recovery
time (tWR).
*3 : Write pulse width is defined from High to Low transition of CE1, WE, LB, or UB, whichever occurs last.
*4 : tVPL is specified from the falling edge of either CE1 or ADV whichever comes late. The sum of actual tVPL and
tASVL must be equal or greater than the specified minimum value of tVPL.
*5 : Applicable for byte mask only. Byte mask setup time is defined to the High to Low transition of CE1 or WE
whichever occurs last.
*6 : Applicable for byte mask only. Byte mask hold time is defined from the Low to High transition of CE1 or WE
whichever occurs first.
*7 : Write recovery time is defined from Low to High transition of CE1, WE, LB, or UB, whichever occurs first.
*8 : If OE is Low after minimum tOHCL, read cycle is initiated. In other word, OE must be brought to High within 5 ns
after CE1 is brought to Low.
*9 : If OE is Low after a new address input, read cycle is initiated. In other word, OE must be brought to High at the
same time or before a new address becomes valid.
20
MB82DBS08164C-70L
(3) Synchronous Operation - Clock Input (Burst Mode)
(At recommended operating conditions unless otherwise noted)
Value
Parameter
Symbol
Unit
Notes
Min
Max
RL = 7
Clock Period
RL = 6
tCK
RL = 5
RL = 4
9.5
⎯
ns
*1
12
⎯
ns
*1
13
⎯
ns
*1
18
⎯
ns
*1
Clock High Time
tCKH
3
⎯
ns
Clock Low Time
tCKL
3
⎯
ns
Clock Transition Time
tCKT
⎯
1.5
ns
*2
*1 : Clock period is defined between valid clock edges.
*2 : Clock transition time is defined between VIH (Min) and VIL (Max)
(4) Synchronous Operation - Address Latch (Burst Mode)
(At recommended operating conditions unless otherwise noted)
Value
Parameter
Symbol
Unit
Notes
Min
Max
Address Setup Time to CE1 Low
tASCL
−2
⎯
ns
*1
Address Setup Time to ADV Low
tASVL
−2
⎯
ns
*2
Address Hold Time from ADV High
tAHV
0
⎯
ns
ADV Low Pulse Width
tVPL
7
⎯
ns
*3
3
⎯
5
⎯
ns
*4
3
⎯
5
⎯
ns
*4
1
⎯
ns
*4
ADV Low Setup Time to CLK
CE1 Low Setup Time to CLK
RL = 6, 7
RL = 4, 5
RL = 6, 7
RL = 4, 5
ADV Low Hold Time from CLK
tVSCK
tCLCK
tCKVH
*1 : tASCL is applicable if CE1 is brought to Low after ADV is brought to Low.
*2 : tASVL is applicable if ADV is brought to Low after CE1 is brought to Low.
*3 : tVPL is specified from the falling edge of either CE1 or ADV whichever comes late. The sum of actual tVPL and
tASVL (or tASCL) must be equal or greater than the specified minimum value of tVPL.
*4 : Applicable to the 1st valid clock edge.
21
MB82DBS08164C-70L
(5) Synchronous Read Operation (Burst Mode)
(At recommended operating conditions unless otherwise noted)
Value
Parameter
Symbol
Unit
Notes
Min
Max
Burst Read Cycle Time
CLK Access Time
tRCB
RL = 6, 7
RL = 4, 5
tAC
⎯
8000
ns
⎯
6
ns
*1
⎯
9
ns
*1
Output Hold Time from CLK
tCKQX
2
⎯
ns
*1
CE1 Low to WAIT Low
tCLTL
5
15
ns
*1
OE Low to WAIT Low
tOLTL
5
15
ns
*1, *2
CLK to WAIT Valid Time
tCKTV
⎯
6
ns
*1, *3
WAIT Valid Hold Time from CLK
tCKTX
2
⎯
ns
*1
CE1 Low to Output Low-Z
tCLZ
10
⎯
ns
*4
OE Low to Output Low-Z
tOLZ
10
⎯
ns
*4
LB, UB Low to Output Low-Z
tBLZ
10
⎯
ns
*4
CE1 High to Output High-Z
tCHZ
⎯
9.5
ns
*1
OE High to Output High-Z
tOHZ
⎯
9.5
ns
*1
LB, UB High to Output High-Z
tBHZ
⎯
9.5
ns
*1
CE1 High to WAIT High-Z
tCHTZ
⎯
9.5
ns
*1
OE High to WAIT High-Z
tOHTZ
⎯
9.5
ns
*1
OE Low Setup Time to 1st Data-output
tOLQ
34
⎯
ns
LB, UB Setup Time to 1st Data-output
tBLQ
26
⎯
ns
OE Setup Time to CLK
tOSCK
3
⎯
ns
OE Hold Time from CLK
tCKOH
1
⎯
ns
Burst End CE1 Low Hold Time from CLK
tCKCLH
1
⎯
ns
Burst End LB, UB Hold Time from CLK
tCKBH
1
⎯
ns
tCP
9.5
⎯
ns
9.5
⎯
ns
*6
70
⎯
ns
*6
CE1 High Pulse Width
Burst Terminate
Recovery Time
BL = 8, 16
BL = Continuous
tTRB
*5
*1 : The output load 50 pF with 50 Ω termination to VDD × 0.5 V.
*2 : WAIT drives High at the beginning depending on OE falling edge timing.
*3 : tCKTV is guaranteed after tOLTL (Max) from OE falling edge and tOSCK must be satisfied.
*4 : The output load 5 pF without any other load.
*5 : Once LB, UB are determined, LB, UB must not be changed until the end of burst read.
*6 : Defined from the Low to High transition of CE1 to the High to Low transition of either ADV or CE1 whichever
occurs late.
22
MB82DBS08164C-70L
(6) Synchronous Write Operation (Burst Mode)
(At recommended operating conditions unless otherwise noted)
Value
Parameter
Symbol
Unit
Notes
Min
Max
Burst Write Cycle Time
tWCB
⎯
8000
ns
Data Setup Time to CLK
tDSCK
3
⎯
ns
Data Hold Time from CLK
tDHCK
1
⎯
ns
WE Low Setup Time to 1st Data Input
tWLD
45
⎯
ns
WE Setup Time to CLK
tWSCK
3
⎯
ns
WE Hold Time from CLK
tCKWH
1
⎯
ns
LB, UB Setup Time to CLK
tBSCK
3
⎯
ns
*1
LB, UB Hold Time from CLK
tCKBH
1
⎯
ns
*1
CE1 Low to WAIT High
tCLTH
5
15
ns
*2
WE Low to WAIT High
tWLTH
5
15
ns
*2
CE1 High to WAIT High-Z
tCHTZ
⎯
9.5
ns
*2
WE High to WAIT High-Z
tWHTZ
⎯
9.5
ns
*2
Burst End CE1 Low Hold Time from CLK
tCKCLH
1
⎯
ns
Burst End CE1 High Setup Time to next CLK
tCHCK
3
⎯
ns
tCP
9.5
⎯
ns
9.5
⎯
ns
*3
70
⎯
ns
*3
CE1 High Pulse Width
Burst Terminate
Recovery Time
BL = 8, 16
BL = Continuous
tTRB
*1 : tBSCK and tCKBH should be satisfied for byte mask control.
*2 : The output load 50 pF with 50 Ω termination to VDD × 0.5 V.
*3 : Defined from the Low to High transition of CE1 to the High to Low transition of either ADV or CE1 whichever
occurs late for the next access.
23
MB82DBS08164C-70L
(7) Power Down Parameters
Parameter
(At recommended operating conditions unless otherwise noted)
Value
Symbol
Unit
Notes
Min
Max
CE2 Low Setup Time for Power Down Entry
tCSP
10
⎯
ns
CE2 Low Hold Time after Power Down Entry
tC2LP
70
⎯
ns
CE2 Low Hold Time for Reset to Asynchronous Mode
tC2LPR
70
⎯
ns
*1
CE1 High Hold Time following CE2 High
after Power Down Exit [Sleep mode only]
tCHH
300
⎯
µs
*2
CE1 High Hold Time following CE2 High
after Power Down Exit [not in Sleep mode]
tCHHP
70
⎯
ns
*3
CE1 High Setup Time following CE2 High
after Power Down Exit
tCHS
0
⎯
ns
*2
*1 : Applicable when RA = 0 (Reset to Asynchronous mode) .
*2 : Applicable also to power-up.
*3 : Applicable when Partial mode is set.
(8) Other Timing Parameters
Parameter
(At recommended operating conditions unless otherwise noted)
Value
Symbol
Unit
Notes
Min
Max
CE1 High to OE Invalid Time for Standby Entry
tCHOX
10
⎯
ns
CE1 High to WE Invalid Time for Standby Entry
tCHWX
10
⎯
ns
CE2 Low Hold Time after Power-up
tC2LH
50
⎯
µs
CE1 High Hold Time following CE2 High after Power-up
tCHH
300
⎯
µs
tT
1
25
ns
Input Transition Time (except for CLK)
*1
*2, *3
*1 : Some data might be written into any address location if tCHWX (Min) is not satisfied.
*2 : Except for the CLK input transition time.
*3 : The Input Transition Time (tT) at AC testing is 3 ns for Asynchronous operation and 1.5 ns for Synchronous
operation respectively. If actual tT is longer than 3 ns or 1.5 ns specified as AC test condition, it may violate AC
specification of some timing parameters. Refer to " (9) AC Test Conditions".
24
MB82DBS08164C-70L
(9) AC Test Conditions
Description
Symbol
Test Setup
Value
Unit
Input High Level
VIH
⎯
VDD × 0.8
V
Input Low Level
VIL
⎯
VDD × 0.2
V
VREF
⎯
VDD × 0.5
V
tT
Between VIL and VIH
3
ns
1.5
ns
Input Timing Measurement Level
Async.
Input Transition Time
Sync.
Notes
• AC MEASUREMENT OUTPUT LOAD CIRCUIT
VDD
50
VDD
0.1 µF
VSS
0.5 V
Device under
Test
Output
50 pF
25
MB82DBS08164C-70L
■ TIMING DIAGRAMS
(1) Asynchronous Read Timing 1-1 (Basic Timing)
tRC
Address
ADV
Address Valid
Low
tASC
tCHAH
tCE
CE1
tASC
tCP
tCHZ
tOE
OE
tOHZ
tBA
LB, UB
tBHZ
tBLZ
tOLZ
tOH
DQ
(Output)
Valid Data Output
Note : This timing diagram assumes CE2 = H and WE = H.
26
MB82DBS08164C-70L
(2) Asynchronous Read Timing 1-2 (Basic Timing)
tRC
Address
Address Valid
tAHV
tAV
ADV
tASVL
tASVL
tASC
tVPL
tCE
CE1
tCP
tCHZ
tASC
tOE
OE
tOHZ
tBA
LB, UB
tBHZ
tBLZ
tOLZ
DQ
(Output)
tOH
Valid Data Output
Note : This timing diagram assumes CE2 = H and WE = H.
27
MB82DBS08164C-70L
(3) Asynchronous Read Timing 2 (OE Control & Address Access)
tRC
Address
tAX
tRC
Address Valid
Address Valid
tAA
tOHAH
tAA
CE1
Low
tASO
tOE
OE
LB, UB
tOHZ
tOLZ
DQ
(Output)
tOH
Valid Data
Output
Note : This timing diagram assumes CE2 = H, ADV = L and WE = H.
28
tOH
Valid Data
Output
MB82DBS08164C-70L
(4) Asynchronous Read Timing 3 (LB, UB Byte Control Access)
tAX
tRC
Address
tAX
Address Valid
tAA
CE1, OE
Low
tBA
tBA
LB
tBA
UB
tBHZ
tBLZ
tBHZ
tOH
tBLZ
tOH
DQ7 to DQ0
(Output)
Valid Data Output
Valid Data Output
tBLZ
tBHZ
tOH
DQ15 to DQ8
(Output)
Valid Data Output
Note : This timing diagram assumes CE2 = H, ADV = L and WE = H.
29
MB82DBS08164C-70L
(5) Asynchronous Write Timing 1-1 (Basic Timing)
tWC
Address
ADV
Address Valid
Low
tWR
tCW
tAS
CE1
tCP
tAS
tWR
tWP
WE
tAS
tWHP
tAS
tWR
tBW
LB, UB
tAS
tBHP
tOHCL
OE
tDS
tDH
DQ
(Input)
Valid Data Input
Note : This timing diagram assumes CE2 = H and ADV = L.
30
tAS
MB82DBS08164C-70L
(6) Asynchronous Write Timing 1-2 (Basic Timing)
tWC
Address
Address Valid
tAHV
tVPL
ADV
tASVL
tASVL
tWR
tCW
tAS
CE1
tAS
tCP
tAS
tWR
tWP
WE
tAS
tWHP
tAS
tWR
tBW
LB, UB
tAS
tBHP
tOHCL
OE
tDS
tDH
DQ
(Input)
Valid Data Input
Note : This timing diagram assumes CE2 = H.
31
MB82DBS08164C-70L
(7) Asynchronous Write Timing 2 (WE Control)
tWC
Address
tWC
Address Valid
Address Valid
tOHAH
CE1
Low
tAS
tWR
tWP
WE
tAS
tWR
tWP
tWHP
LB, UB
tOES
OE
tOHZ
tDS
tDH
tDS
tDH
DQ
(Input)
Valid Data Input
Note : This timing diagram assumes CE2 = H and ADV = L.
32
Valid Data Input
MB82DBS08164C-70L
(8) Asynchronous Write Timing 3-1 (WE, LB, UB Byte Write Control)
tWC
Address
CE1
tWC
Address Valid
Address Valid
Low
tAS
tAS
tWP
tWP
tWHP
WE
tWR
tBH
tBS
LB
tBH
tBS
tWR
UB
tDS
tDH
DQ7 to DQ0
(Input)
tDS
DQ15 to DQ8
(Input)
tDH
Valid Data Input
Valid Data Input
Note : This timing diagram assumes CE2 = H, ADV = L and OE = H.
33
MB82DBS08164C-70L
(9) Asynchronous Write Timing 3-2 (WE, LB, UB Byte Write Control)
tWC
Address
CE1
tWC
Address Valid
Address Valid
Low
tWR
WE
tWR
tWHP
tAS
tBW
tBS
tBH
LB
tBH
tBS
tAS
tBW
UB
tDS
tDH
DQ7 to DQ0
(Input)
tDS
DQ15 to DQ8
(Input)
tDH
Valid Data Input
Valid Data Input
Note : This timing diagram assumes CE2 = H, ADV = L and OE = H.
34
MB82DBS08164C-70L
(10) Asynchronous Write Timing 3-3 (WE, LB, UB Byte Write Control)
tWC
Address
CE1
tWC
Address Valid
Address Valid
Low
tWHP
WE
tAS
tBW
tWR
tBH
tBS
LB
tBS
tBH
tAS
tWR
tBW
UB
tDS
tDH
DQ7 to DQ0
(Input)
tDS
DQ15 to DQ8
(Input)
tDH
Valid Data Input
Valid Data Input
Note : This timing diagram assumes CE2 = H, ADV = L and OE = H.
35
MB82DBS08164C-70L
(11) Asynchronous Read/Write Timing 1-1 (CE1 Control)
Address
tCHAH
tWC
tRC
Write Address
Read Address
tAS
tWR
tCHAH
tASC
tCW
tCE
CE1
tCP
tCP
WE
LB, UB
tOHCL
OE
tCHZ
tOH
tDS
tDH
tCLZ
tOH
DQ
Read Data Output
Write Data Input
Notes : • This timing diagram assumes CE2 = H and ADV = L.
• Write address is valid from either CE1 or WE of last falling edge.
36
Read Data Output
MB82DBS08164C-70L
(12) Asynchronous Read/Write Timing 1-2 (CE1, WE, OE Control)
tWC
Address
tRC
Write Address
tAS
tCHAH
Read Address
tWR
tASC
tCHAH
tCE
CE1
tCP
tCP
tWP
WE
LB, UB
tOHCL
tOE
OE
tCHZ
tOH
tDS
tDH
tOLZ
tOH
DQ
Read Data Output
Write Data Input
Read Data Output
Notes : • This timing diagram assumes CE2 = H and ADV = L.
• OE can be fixed Low during write operation if it is CE1 controlled write at Read-Write-Read
sequence.
37
MB82DBS08164C-70L
(13) Asynchronous Read/Write Timing 2 (OE, WE Control)
tWC
Address
tRC
Write Address
Read Address
tAA
tOHAH
tOHAH
CE1
Low
tAS
tWR
tWP
WE
tOES
LB, UB
tASO
tOE
OE
tWHOL
tOHZ
tOH
tDS
tDH
tOHZ
tOLZ
tOH
DQ
Read Data Output
Write Data Input
Notes : • This timing diagram assumes CE2 = H and ADV = L.
• CE1 can be tied to Low for WE and OE controlled operation.
38
Read Data Output
MB82DBS08164C-70L
(14) Asynchronous Read/Write Timing 3 (OE, WE, LB, UB Control)
tWC
Address
tRC
Write Address
Read Address
tAA
tOHAH
tOHAH
CE1
Low
WE
tOES
tAS
tBW
tWR
tBA
LB, UB
tASO
tBHZ
OE
tWHOL
tBHZ
tOH
tDS
tDH
tBLZ
tOH
DQ
Read Data Output
Write Data Input
Read Data Output
Notes : • This timing diagram assumes CE2 = H and ADV = L.
• CE1 can be tied to Low for WE and OE controlled operation.
39
MB82DBS08164C-70L
(15) Clock Input Timing
tCK
CLK
tCK
tCKH
tCKT
tCKL
tCKT
Notes : • Stable clock input must be required during CE1 = L.
• tCK is defined between valid clock edges.
• tCKT is defined between VIH (Min) and VIL (Max).
(16) Address Latch Timing (Synchronous Mode)
Case #1
Case #2
CLK
Address
Valid
Valid
tAHV
tASCL
tVSCK
tASVL
tAHV
tVSCK
tCKVH
tCKVH
ADV
tVPL
tVPL
tCLCK
CE1
Low
Notes : • Case #1 is the timing when CE1 is brought to Low after ADV is brought to Low.
Case #2 is the timing when ADV is brought to Low after CE1 is brought to Low.
• tVPL is specified from the falling edge of either CE1 or ADV whichever comes late.
At least one valid clock edge must be input during ADV = L.
• tVSCK and tCLCK are applied to the 1st valid clock edge during ADV=L.
40
MB82DBS08164C-70L
(17) Synchronous Read Timing 1 (OE Control)
RL = 5
CLK
tRCB
Address
Valid
Address
Valid
Address
tASVL
tAHV
tASVL
tVSCK tCKVH
tVSCK
tCKVH
ADV
tVPL
tVPL
tASCL
tASCL
CE1
tCLCK
tCKOH
tCP
tCLCK
OE
tOLQ
WE
High
tCKBH
tBLQ
LB, UB
tOHTZ
tCKTV
WAIT
High-Z
tOLTL
DQ
High-Z
tCKTX
tAC
tAC
Q1
tOLZ
tCKQX
tOHZ
tAC
QBL
tCKQX
Note : This timing diagram assumes CE2 = H, the valid clock edge on rising edge and BL = 8 or 16.
41
MB82DBS08164C-70L
(18) Synchronous Read Timing 2 (CE1 Control)
RL = 5
CLK
tRCB
Address
Valid
Address
Address
Valid
tAHV
tASVL
tVSCK
tASVL
tCKVH
tAHV
tVSCK
tCKVH
ADV
tVPL
tVPL
tASCL
tASCL
CE1
tCP
tCLCK
tCLCK
tCKCLH
OE
WE
High
tCKBH
LB, UB
tCKTV
tCHTZ
tCLTL
WAIT
tCLTL
tCKTX
tAC
tAC
Q1
DQ
tCLZ
tCKQX
tCLZ
tAC
tCHZ
QBL
tCKQX
Note : This timing diagram assumes CE2 = H, the valid clock edge on rising edge and BL = 8 or 16.
42
MB82DBS08164C-70L
(19) Synchronous Write Timing 1 (WE Level Control)
RL = 5
CLK
tWCB
Address
Valid
Address
Address
Valid
tAHV
tASVL
tVSCK
tAHV
tASVL
tVSCK
tCKVH
tCKVH
ADV
tVPL
tCLCK
tVPL
tASCL
tASCL
CE1
tCP
tCLCK
OE
tCKCLH
High
tCKWH
tWLD
WE
tCKBH
tBSCK
LB, UB
WAIT
High-Z
tWLTH
DQ
tDSCK
tDSCK
D1
tDHCK
D2
tDSCK
tWHTZ
DBL
tDHCK
Note : This timing diagram assumes CE2 = H, the valid clock edge on rising edge and BL = 8 or 16.
43
MB82DBS08164C-70L
(20) Synchronous Write Timing 2 (WE Single Clock Pulse Control)
RL = 5
CLK
tWCB
Address
Valid
Address
Address
Valid
tASVL
tAHV
tASVL
tVSCK
tAHV
tVSCK
tCKVH
tCKVH
ADV
tVPL
tVPL
tCLCK
tASCL
tASCL
CE1
tCLCK
tCP
tCKCLH
OE
High
tWSCK
tWSCK
tCKWH
tCKWH
WE
tBSCK
tCKBH
LB, UB
WAIT
High-Z
tWLTH
DQ
tDSCK
tDSCK
D1
tDHCK
tCHTZ
tDSCK
D2
tWLTH
DBL
tDHCK
Note : This timing diagram assumes CE2 = H, the valid clock edge on rising edge and BL = 8 or 16.
44
MB82DBS08164C-70L
(21) Synchronous Write Timing 3 (LB, UB Byte Mask Control)
RL = 5
CLK
tWCB
Address
Valid
Address
Valid
Address
tASVL
tAHV
tASVL
tVSCK
tAHV
tVSCK
tCKVH
tCKVH
ADV
tVPL
tASCL
tCLCK
tASCL
tVPL
tCLCK
CE1
tCKCLH
OE
tCP
High
tCKWH
tWLD
WE
tCKBH
tCKBH
LB, UB
tBSCK
tBSCK
tBSCK
High-Z
WAIT
tWLTH
tWHTZ
tDSCK
DQ
D1
tDHCK
tDSCK
DBL
tDHCK
Note : This timing diagram assumes CE2 = H, the valid clock edge on rising edge and BL = 8 or 16.
45
MB82DBS08164C-70L
(22) Synchronous Read to Write Timing 1 (CE1 Control)
RL = 5
CLK
tWCB
Address
Valid
Address
tAHV
tASVL
tVSCK
tCKVH
ADV
tVPL
tCLCK
tCKCLH
CE1
tCKCLH
tASCL
tCP
OE
WE
tCKBH
tBSCK
tCKBH
LB,UB
tCHTZ
WAIT
tCHZ
tAC
DQ
QBL-1
tCKQX
QBL
tCKQX
tCLTH
tDSCK
tDSCK
tDSCK
D1
D2
D3
tDHCK
tDHCK
tDHCK
tDSCK
DBL
tDHCK
Note : This timing diagram assumes CE2 = H, the valid clock edge on rising edge and BL = 8 or 16.
46
MB82DBS08164C-70L
(23) Synchronous Write to Read Timing 1 (CE1 Control)
RL = 5
CLK
Address
Address
Valid
tAHV
tASVL
tVSCK
tCKVH
ADV
tASCL
CE1
tCKCLH
tVPL
tCLCK
tCP
OE
WE
LB,UB
tCKTV
tCLTL
WAIT
tDSCK
DQ
tCHTZ
tDSCK
DBL-1
tDHCK
tCKTX
DBL
tDHCK
tCLZ
tAC
tAC
tAC
tAC
Q1
Q2
Q3
Q4
tCKQX
tCKQX
tCKQX
tCKQX
Note : This timing diagram assumes CE2 = H, the valid clock edge on rising edge and BL = 8 or 16.
47
MB82DBS08164C-70L
(24) Power-up Timing 1
CE1
tCHS
tCHH
tC2LH
CE2
VDD (Min)
VDD
0V
Note : The tC2LH specifies after VDD reaches specified minimum level.
(25) Power-up Timing 2
CE1
tCHH
CE2
VDD (Min)
VDD
0V
Note : The tCHH specifies after VDD reaches specified minimum level and applicable to both CE1 and CE2.
If transition time of VDD (from 0 V to VDD (Min)) is longer than 50 ms, Power-up Timing 1 must be
applied.
48
MB82DBS08164C-70L
(26) Power Down Entry and Exit Timing
CE1
tCHS
CE2
tCSP
tC2LP
tCHH (tCHHP)
High-Z
DQ
Power Down Entry
Power Down Mode
Power Down Exit
Note : This Power Down mode can be also used as a reset timing if “Power-up timing” above could
not be satisfied and Power Down program was not performed prior to this reset.
(27) Standby Entry Timing after Read or Write
CE1
tCHOX
tCHWX
OE
WE
Active (Read)
Standby
Active (Write)
Standby
Note : Both tCHOX and tCHWX define the earliest entry timing for Standby mode.
49
MB82DBS08164C-70L
(28) Configuration Register Set Timing 1 (Asynchronous Operation)
tRC
Address
tWC
MSB*1
MSB*1
tCP
tWC
tWC
tWC
MSB*1
MSB*1
MSB*1
tCP
tCP
tCP
tWC
MSB*1
tRC*6
tCP
CE1
OE
WE
LB, UB
DQ
*2
*2
RDa
Cycle #1
*2
*3
RDa
RDa
Cycle #2
Cycle #3
CR
Key 0*4
Cycle #4
*3
*3
CR
Key 1*5
Cycle #5
CR
Key 2*5
Cycle #6
*1 : The all address inputs must be High from Cycle #1 to #6.
*2 : At least either LB or UB must be brought to Low during Cycle #1 to #3.
*3 : LB must be brought to Low in order to input the CR Keys during Cycle #4 to #6.
*4 : The CR Key 0 must be set “1” for the CR Set as specified in “■FUNCTIONAL DESCRIPTION”.
*5 : The CR Keys must conform to the format specified in “■FUNCTIONAL DESCRIPTION”. If not, any
operations and data are not guaranteed.
*6 : After tRC following Cycle #6, the Configuration Register Set is completed and returned to the normal
operation.
50
MB82DBS08164C-70L
(29) Configuration Register Verify Timing 1 (Asynchronous Operation)
tRC
Address
tWC
MSB*1
MSB*1
tCP
tWC
tWC
tRC
tRC
MSB*1
MSB*1
MSB*1
MSB*1
tCP
tCP
tCP
tRC*6
tCP
CE1
OE
WE
LB, UB
DQ*3
*2
*2
RDa
Cycle #1
*2
*3
RDa
RDa
Cycle #2
Cycle #3
CR
Key 0*4
Cycle #4
*3
CR
Key 1*5
Cycle #5
*3
CR
Key 2*5
Cycle #6
*1 : The all address inputs must be High from Cycle #1 to #6.
*2 : At least either LB or UB must be brought to Low during Cycle #1 to #3.
*3 : LB must be brought to Low in order to input or output the CR Keys during Cycle #4 to #6.
*4 : The CR Key 0 must be set “0” for the CR Verify as specified in “■FUNCTIONAL DESCRIPTION”.
*5 : The CR Keys must conform to the format specified in “■FUNCTIONAL DESCRIPTION”. If not, any
operations and data are not guaranteed.
*6 : After tRC following Cycle #6, the Configuration Register Verify is completed and returned to the normal
operation.
51
MB82DBS08164C-70L
(30) Configuration Register Set Timing 2 (Synchronous Operation)
CLK
Address
MSB
MSB
MSB
MSB
MSB
MSB
1
1
1
1
1
*1
*
*
tRCB
*
*
tWCB
tWCB
*
tWCB
tWCB
tWCB
ADV
tTRB
tTRB
tTRB
tTRB
6
tRC*
tTRB
CE1
OE
WE
*2
*2
*2
*3
*3
*3
LB,UB
RL
DQ
RL-1
RDa
Cycle #1
RDa
Cycle #2
RL-1
RL-1
RL-1
RDa
Cycle #3
CR
Key 0
*4
Cycle #4
RL-1
CR
Key 1
*5
Cycle #5
CR
Key 2
*5
Cycle #6
*1 : The all address inputs must be High from Cycle #1 to #6.
*2 : At least either LB or UB must be brought to Low during Cycle #1 to #3.
*3 : LB must be brought to Low in order to input the CR Keys during Cycle #4 to #6.
*4 : The CR Key 0 must be set “1” for the CR Set as specified in “■FUNCTIONAL DESCRIPTION”.
*5 : The CR Keys must conform to the format specified in “■FUNCTIONAL DESCRIPTION”. If not,
any operations and data are not guaranteed.
*6 : After tRC following Cycle #6, the Configuration Register Set is completed and returned to the normal
operation.
52
MB82DBS08164C-70L
(31) Configuration Register Verify Timing 2 (Synchronous Operation)
CLK
Address
MSB
MSB
MSB
MSB
MSB
MSB
*1
*1
*1
*1
*1
*1
tRCB
tWCB
tWCB
tWCB
tRCB
tRCB
ADV
tTRB
tTRB
tTRB
tTRB
6
tRC*
tTRB
CE1
OE
WE
*2
*2
*3
*2
*3
*3
LB,UB
RL
DQ
RL-1
RL-1
RL-1
RL
RDa
RDa
RDa
CR
Key 0
Cycle #1
Cycle #2
Cycle #3
Cycle #4
*4
RL
CR
Key 1
CR
Key 2
*5
Cycle #5
*5
Cycle #6
*1 : The all address inputs must be High from Cycle #1 to #6.
*2 : At least either LB or UB must be brought to Low during Cycle #1 to #3.
*3 : LB must be brought to Low in order to input or output the CR Keys during Cycle #4 to #6.
*4 : The CR Key 0 must be set “0” for the CR Verify as specified in “■FUNCTIONAL DESCRIPTION”.
*5 : The CR Keys must conform to the format specified in “■FUNCTIONAL DESCRIPTION”. If not, any
operations and data are not guaranteed.
*6 : After tRC following Cycle #6, the Configuration Register Verify is completed and returned to the normal
operation.
53
MB82DBS08164C-70L
■ PACKAGE FOR ENGINEERING SAMPLES
• Pin Assignment
(TOP VIEW)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
10
NC
NC
NC
NC
NC
NC
VDD
VSS
NC
NC
NC
NC
NC
NC
9
NC
NC
NC
NC
A15
A21
A22
A16
NC
VSS
NC
NC
NC
NC
8
NC
A11
A12
A13
A14
NC
DQ15
DQ7 DQ14
NC
7
NC
A8
A19
A9
A10
DQ6
DQ13 DQ12 DQ5
NC
6
NC
WE
CE2
A20
NC
NC
DQ4
VDD
NC
NC
5
NC
CLK
ADV WAIT
NC
VDD
DQ3
VDD
DQ11
VDD
4
NC
LB
UB
A18
A17
DQ1
DQ9
DQ10
DQ2
VSS
3
VSS
A7
A6
A5
A4
VSS
OE
DQ0
DQ8
NC
NC
NC
A3
A2
A1
A0
NC
CE1
NC
NC
NC
NC
NC
NC
NC
VDD
VSS
NC
NC
NC
NC
NC
NC
2
NC
NC
1
NC
NC
(BGA-115P-M03)
54
MB82DBS08164C-70L
• Pin Description
Pin Name
A22 to A0
Description
Address Input
CE1
Chip Enable 1 (Low Active)
CE2
Chip Enable 2 (High Active)
WE
Write Enable (Low Active)
OE
Output Enable (Low Active)
LB
Lower Byte Control (Low Active)
UB
Upper Byte Control (Low Active)
CLK
Clock Input
ADV
Address Valid Input (Low Active)
WAIT
Wait Output
DQ7 to DQ0
Lower Byte Data Input/Output
DQ15 to DQ8
Upper Byte Data Input/Output
VDD
Power Supply Voltage
VSS
Ground
NC
No Connection
55
MB82DBS08164C-70L
• Package Capacitance
(f = 1 MHz, TA = +25 °C)
Test
conditions
Min
Typ
Max
Address Input Capacitance
CIN1
VIN = 0 V
⎯
⎯
5
pF
Control Input Capacitance
CIN2
VIN = 0 V
⎯
⎯
5
pF
Data Input/Output Capacitance
CI/O
VIO = 0 V
⎯
⎯
8
pF
• Package View
115-ball plastic FBGA
(BGA-115P-M03)
56
Value
Symbol
Parameter
Unit
MB82DBS08164C-70L
• Package Dimension
115-ball plastic FBGA
(BGA-115P-M03)
12.00±0.10(.472±.004)
0.20(.008) S B
B
1.25±0.10
(Seated height)
(.049±.004)
0.80(.031)
REF
0.40(.016)
REF
10
9
8
7
6
5
4
3
2
1
0.80(.031)
REF
A
9.00±0.10
(.354±.004)
0.40(.016)
REF
0.08(.003) S
INDEX-MARK AREA
0.10±0.05
(Stand off)
(.004±.002)
P N M L K J H G F E D C B A
S
+.010
115-ø0.40 –0.05
0.20(.008) S A
115-ø.016
+.004
–.002
ø0.08(.003)
M
S A B
0.08(.003) S
C
2003 FUJITSU LIMITED B115003S-c-1-1
Dimensions in mm (inches)
Note : The values in parentheses are reference values.
■ ORDERING INFORMATION
Part Number
MB82DBS08164C-70LWT
Shipping Form
Remarks
wafer
57
MB82DBS08164C-70L
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-party’s
intellectual property right or other right by using such information.
Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
Edited
Business Promotion Dept.
F0605