ON LC87F2K08AU-DIP-E 8-bit microcontroller Datasheet

Ordering number : EN*A2275
LC87F2K08A
Advance Information
CMOS LSI
8-bit Microcontroller
http://onsemi.com
8K-Byte Flash ROM / 256-Byte RAM / 24-pin
Overview
The LC87F2K08A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of
83.3ns, integrates on a single chip a number of hardware features such as 8K-byte flash ROM (onboard
programmable), 256-byte RAM, an on-chip debugger function, two sophisticated 16-bit timers/counters (may be
divided into 8-bit timers), an asynchronous/synchronous SIO interface, a 5-channel AD converter with 12/8-bit
resolution selector, eight analog comparators, two AMP circuits, an IGBT control circuit (PPG), a watchdog timer, an
internal reset circuit, a system clock frequency divider, and a 18-source 10-vector interrupt feature.
It is optimal for controlling the IH cooking heaters and other appliances.
Features
 Flash ROM
 8192  8 bits
 Capable of on-board programming with a power voltage range of 4.5 to 5.5V
 Block-erasable in 128 byte units
 Writing in 2-byte units
 ROM
 256  9 bits
 Package : DIP24S(300mil), Lead-free type
 Minimum bus cycle time
 83.3ns (12MHz)
Note : The bus cycle time here refers to the ROM read speed.
 Minimum instruction cycle time
 250ns (12MHz)
DIP24S(300mil)
* This product is licensed from Silicon Storage Technology, Inc. (USA).
This document contains information on a new product. Specifications and information
herein are subject to change without notice.
ORDERING INFORMATION
See detailed ordering and shipping information on page 24 of this data sheet.
Semiconductor Components Industries, LLC, 2014
July, 2014 Ver. 1.03
71514HK No.A2275-1/24
LC87F2K08A
 Ports
 I/O ports
Ports I/O direction can be designated in 1 bit units:
 Dedicated PPG ports
 Reset pin
 Dedicated on-chip debugger pin
 Power pins
9 (P00 to P07, P30)
10 (PPGO, AMP1I, AMP2O, CMP1IA, CMP1IB, CMP2I,
CMP4I, CMP45I, CMP5I, CMP6I)
1 (RES#)
1 (OWP0)
3 (VSS1, VSS2, VDD1)
 Timers
 Timer 0: 16-bit timer/counter with a capture register
Mode 0 : 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) 2 channels
Mode 1 : 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter
(with an 8-bit capture register)
Mode 2 : 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register)
Mode 3 : 16-bit counter (with a 16-bit capture register)
 Timer 1 : 16-bit timer/counter
Mode 0 : 8-bit timer with an 8-bit prescaler + 8-bit timer/counter with an 8-bit prescaler
Mode 2 : 16-bit timer/counter with an 8-bit prescaler
Mode 3 : 16-bit timer with an 8-bit prescaler
 Timer 6 : 8-bit timer with a 6-bit prescaler (with toggle outputs)
 Timer 7 : 8-bit timer with a 6-bit prescaler (with toggle outputs)
 Base timer
1) The clock is selectable from the system clock and timer 0 prescaler output.
2) Interrupts are programmable in 5 different time schemes.
 Serial interface
 SIO1: 8-bit asynchronous/synchronous serial interface
Mode 0 : Synchronous 8-bit serial I/O (2-wire configuration, 2 to 512 Tcyc transfer clocks)
Mode 2 : Bus mode 1 (start bit, 8 data bits, 2 to 512 Tcyc transfer clocks)
Mode 3 : Bus mode 2 (start detect, 8 data bits, stop detect)
 UART
 Full duplex
 7/8/9 bit data bits selectable
 1 stop bit (2 bits in continuous data transmission)
 Built-in baudrate generator
 AD converter : 12 bits 5 channels
 12/8 bits AD converter resolution selectable
 Clock output function
 Can generate clock outputs with a frequency of
1 1
,
1 2
,
1
4
,
1
8
,
1
16
,
1
32
, or
1
64
of the source clock selected as the
system clock.
No.A2275-2/24
LC87F2K08A
 Analog comparator : 8 channels
● CMP1:
● CMP2:
● CMP3:
● CMP4:
● CMP5:
● CMP6:
● CMP7:
● CMP8:
"+" and "–" input pins
Output: For PPG output timing generation and capture timer input (INT2)
"+" input pin, "–" input is the internal Vref set to 2/3 VDD
Output for interrupt flag setting (INT0)
"+" input is the output of AMP1.
"–" input is the internal Vref (user selectable options: 1/6, 2/6, 3/6, or 4/6 VDD).
Output for the PPG output control (only the existing cycle set to OFF) and interrupt flag set (INT1)
"+" and "–" input pins
Output for the PPG output control (forced OFF)
"–" input pin, "+" input is multiplexed with the "–" input pin of CMP4
Output for the PPG output control (forced OFF)
"+" input pin, "–" input is the internal Vref (register setting: 1/6, 2/6, 3/6, or 4/6 VDD)
Output for the PPG output control (forced OFF) and interrupt flag set (CMP6)
"+" input is multiplexed with the "+" input pin of CMP1
"–" input is the internal Vref (user selectable options: 1/20 or 2/20 VDD)
Output for the PPG output control and sets the interrupt flag (INT3).
"+" input is multiplexed with the "+" input pin of CMP4
"–" input is the internal Vref (user selectable options: 12/20, 13/20, or 14/20 VDD)
Output for the PPG output control (forced OFF).
 AMP circuit: 2 channels
● AMP1:
● AMP2:
The gain is set by user selectable options (6×/8×/10×).
Input pin (AMP1I)
Output is CMP3 input and AMP2 input.
The gain (1×/2×/4×) is set by using a register.
Input is AMP1 output.
Output pin (AMP2O)
 Pulse output control circuit (PPG output): 1 channel
● Output sync signal switching: Set by a register (1-pulse output / continuous pulse output synchronized with the
CMP1 output)
● Duty control: Pulse start delay time and pulse end time with respect to a sync signal are set by using a register.
● PPG output control using CMP3 to CMP8 outputs
● Surge detection using CMP4/5/6/8 outputs
● CMP1 output: Pulse signal timing detection
● Output polarity selectable: User selectable options
Setting pulse end time
Setting pulse start delay time
 Watchdog timer
● Can generate an internal reset signal on an overflow of timer that runs on the WDT-dedicated low-speed
RC oscillation clock (30kHz).
● Allows selection of continue, stop, or hold mode operation of the counter on entry into the HALT/
HOLD mode.
No.A2275-3/24
LC87F2K08A
 Interrupts
● 18 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt request
of the level equal to or lower than the current interrupt is not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest
level takes precedence over the other interrupts. For interrupts of the same level, an interrupt into the smallest
vector address is given priority.
No.
Vector Address
Level
1
2
3
4
5
6
7
8
9
10
00003H
0000BH
00013H
0001BH
00023H
0002BH
00033H
0003BH
00043H
0004BH
X or L
X or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
Interrupt Source
INT0
INT1
INT2/T0L/INT4
INT3/base timer
T0H
T1L/T1H
UART receive
SIO1/UART transmit
ADC/T6/T7
CMP6/Surge detection
● Priority levels X > H > L
● For interrupts of the same level, an interrupt with a smaller vector address is given priority.
 Subroutine stack levels: Up to 128 levels (the stack is allocated in RAM)
 Internal high-speed multiplication/division instructions
● 16 bits  8 bits
● 24 bits  16 bits
● 16 bits ÷ 8 bits
● 24 bits ÷ 16 bits
(5 Tcyc execution time)
(12 Tcyc execution time)
(8 Tcyc execution time)
(12 Tcyc execution time)
 Oscillation circuits
● Internal oscillation circuits
1) Low-speed RC oscillation circuit 1
2) Medium-speed RC oscillation circuit
3) Multi-frequency RC oscillation circuit
4) Low-speed RC oscillation circuit 2
: For system clock (100kHz)
: For system clock (1MHz)
: For system clock (12MHz)
: For watchdog timer (30kHz)
 System clock divider function
●Can run on low current.
●The minimum instruction cycle selectable from 250 ns, 500 ns, 1 μs, 2 μs, 4 μs, 8 μs, 16 μs, 32 μs, and 64 μs
(at a main clock rate of 12 MHz).
 Internal reset circuit
● Power-on reset (POR) function
1) POR reset is generated only at power-on time.
2) The POR release level can be selected from 8 levels
(1.67V, 1.97V, 2.07V, 2.37V, 2.57V, 2.87V, 3.86V, and 4.35V) by configuring options.
● Low-voltage detection reset (LVD) function
1) LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls
below a certain level.
2) The use/disuse of the LVD function and the low voltage threshold level
(7 levels : 1.91V, 2.01V, 2.31V, 2.51V, 2.81V, 3.79V, 4.28V) selectable by configuring options.
No.A2275-4/24
LC87F2K08A
 Standby function
● HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) There are three ways of releasing the HALT mode.
(1) Setting the reset pin to the low level
(2) System resetting by watchdog timer or low-voltage detection
(3) Occurrence of an interrupt
● HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, RC, and crystal oscillators automatically stop operation.
2) There are four ways of releasing the HOLD mode.
(1) Setting the reset pin to the lower level.
(2) System resetting by watchdog timer or low-voltage detection
(3) Having an interrupt source established at either INT0, INT1, INT2, or INT4
* INT0 and INT1 HOLD mode release is available only when level detection is set.
 On-chip debugger
● Supports software debugging with the IC mounted on the target board.
 Data security function
● Protects the program data stored in flash memory from unauthorized read or copy.
Note: This data security function does not necessarily provide absolute data security.
 Development tools
● On-chip debugger: TCB87 Type C + LC87F2K08A
 Programming board
Package
Programming board
DIP24S
W87F2KD
 Flash ROM programmer
Maker
Model
Supported version
Single/Gang
SKK/SKK Type B
ON
Programmer
(SanyoFWS)
Semiconductor
Gang
SKK-4G
Chip data version:
Programmer
(SanyoFWS)
2.24 or later
Device
Application version:
1.05 or later
LC87F2K08
Note : Be sure to check for the latest version.
No.A2275-5/24
LC87F2K08A
Package Dimensions
unit : mm
PDIP24 / DIP24S (300 mil)
CASE 646AW
ISSUE A
GENERIC
MARKING DIAGRAM*
XXXXXXXXXX
YMDDD
XXXXX = Specific Device Code
Y = Year
M = Month
DDD = Additional Traceability Data
*This information is generic. Please refer to
device data sheet for actual part marking.
No.A2275-6/24
LC87F2K08A
Pin Assignment
P30/BUZ/CMP1O
1
24
OWP0
PPGO
2
23
P07/T7O
RES#
3
22
P06/SCK1/URX/T6O
VSS1
4
21
P05/SI1/SB1/UTX/CLKO
VDD1
5
20
P04/AN4/INT4
AMP1I
6
19
P03/AN3
CMP1IA
7
18
AMP2O
CMP1IB
8
17
VSS2
CMP2I
9
16
CMP6I
P00/AN0
10
15
CMP5I
P01/AN1
11
14
CMP45I
P02/AN2
12
13
CMP4I
DIP24S “Lead-free Type”
DIP24S
1
2
3
4
5
6
7
8
9
10
11
12
NAME
P30/BUZ/CMP1O
PPGO
RES#
VSS1
VDD1
AMP1I
CMP1IA
CMP1IB
CMP2I
P00/AN0
P01/AN1
P02/AN2
DIP24S
13
14
15
16
17
18
19
20
21
22
23
24
NAME
CMP4I
CMP45I
CMP5I
CMP6I
VSS2
AMP2O
P03/AN3
P04/AN4/INT4
P05/SI1/SB1/UTX/CLKO
P06/SCK1/URX/T6O
P07/T7O
OWP0
No.A2275-7/24
LC87F2K08A
System Block Diagram
Interrupt control
IR
SRC1
RC
MRC
Flash ROM
Clock
generator
Standby control
PLA
PC
RES#
(SRC2)
Reset circuit
(LVD/POR)
ACC
Reset control
WDT
B register
C register
PPG
Bus interface
ALU
SIO1
Port 0
Timer 0
Port 3
PSW
Timer 1
ADC
RAR
Timer 6
INT0 to 4
RAM
Timer 7
UART
Stack pointer
Base timer
On-chip debugger
No.A2275-8/24
LC87F2K08A
Pin Function Chart
Pin Name
VSS1, VSS2
VDD1
Port 0
I/O


I/O
Description
 power supply pins
power supply pin
 8-bit I/O port
 I/O specifiable in 1 bit units
 Pull-up resistors can be turned on and off in 1 bit units. (No pull-up resistor
on P07)
 Pin functions
P04 : INT4 input / HOLD release input / Timer 1 event input / Timer 0L
capture input / Timer 0H capture input
P05 : SIO1 data I-O / UART transmit / System clock output
P06 : SIO1 clock I-O / UART receive / Timer 6 toggle output
P07 : Timer 7 toggle output
P00 (AN0) to P04 (AN4) : AD convertor input ports
Interrupt acknowledge type
INT4
Port 3
P30
AMP1I
AMP2O
CMP1IA
CMP1IB
CMP2I
CMP4I
CMP45I
CMP5I
CMP6I
PPGO
RES#
OWP0
I/O
I
O
I
I
I
I
I
I
I
I/O
I/O
I/O
Rising
Falling


Rising &
Falling

H level
L level


Option
No
No
P00 to
P06 : Yes
P07 : No
 1-bit I/O port
 I/O specifiable in 1 bit units
 Pull-up resistors can be turned on and off in 1 bit units.
 Pin functions
P30 : BUZ output / CMP1O output
Yes
AMP1 input
No
AMP2 output
CMP1 input()
CMP1 input(+) , CMP7 input (+)
CMP2 input(+)
CMP4 input(+), CMP8 input (+)
CMP4 input (), CMP5 input (+)
CMP5 input ()
CMP6 input (+)
PPG I/O port
External reset Input / internal reset output
Debugger-dedicated pin
No
No
No
No
No
No
No
No
Yes
No
No
No.A2275-9/24
LC87F2K08A
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode.
Port Name
Option
selected in
units of
P00 to P06
1 bit
P07

P30
1 bit
PPGO

Option type
1
2
No
1
2
1
2
Output type
Pull-up resistor
CMOS
N-channel open drain
N-channel open drain
CMOS
N-channel open drain
CMOS
N-channel open drain
Programmable
Programmable
No
Programmable
Programmable
No
No
User Option Table
Option to be applied on
Flash-ROM
version
Option selected in
units of
P00 to P06

1 bit
P30

1 bit
PPGO

-
PPGO output
polarity
PPGO

-
AMP1 gain
-

-
Option name
Port output type
CMP3Vref

CMP7Vref

CMP8Vref

PPG Pulse End
Program start
address
Low-voltage
detection reset
function
Power-on reset
function
PPG-Pulse-End upper
limit

Option selection
CMOS
N-channel open drain
CMOS
N-channel open drain
CMOS
N-channel open drain
Not inverted
Inverted
6x
8x
10 x
1 / 6VDD
2 / 6VDD
3 / 6VDD
4 / 6VDD
1 / 20VDD
2 / 20VDD
12 / 20VDD
13 / 20VDD
14 / 20VDD
Disabled
080h
100h
180h
200h
280h
300h
380h
3FFh
00000h
-

Detection function

-
Detection level

-
7-level
Power-on reset level

-
8-level
-
01E00h
Enabled: Use
Disabled: Disuse
No.A2275-10/24
LC87F2K08A
Recommended Unused Pin Connections
Pin Name
Recommended Unused Pin Connections
Board
Software
P00 to P07
Open
Output low
P30
Open
Output low
On-chip Debugger pin connection requirements
The on-chip debugger pin (OWPO) must be pulled down (with 100 KΩ) on the user's board.
It is also recommended that a connector be installed to cable with the debugger tool (TCB87 Type C).
The connector must have three connections, i.e., GND, OWPO, and VDD.
Note : Be sure to electrically short-circuit between the VSS1 and VSS2 pins.
No.A2275-11/24
LC87F2K08A
1. Absolute Maximum Ratings at Ta=25C, VSS1= VSS2= 0V
Symbol
Pin / Remarks
Conditions
VDD[V]
min.
Specification
typ.
max.
VDDMAX
VDD1
0.3
-
+6.5
VI
0.3
-
VDD+0.3
Output voltage
Input/output
voltage
Peak output
current
Mean output
current
(Note 1-1)
Total output
current
Peak output
current
VO
VIO
RES#, AMP1I,
CMP1IA,CMP1IB,
CMP2I, CMP4I
CMP45I, CMP5I
CMP6I
AMP2O
P00 to P07, P30,
OWP0, PPGO
P00 to P06, P30,
PPGO, OWP0
P00 to P06, P30,
PPGO, OWP0
0.3
0.3
-
VDD+0.3
VDD+0.3
IOPL(2)
IOML(1)
High level output
current
Maximum supply
voltage
Input voltage
Low level output current
Parameter
Mean output
current
(Note 1-1)
Total output
current
IOPH
IOMH
ΣIOAH
IOPL(1)
IOML(2)
ΣIOAL(1)
ΣIOAL(2)
ΣIOAL(3)
Allowable power
dissipation
Pdmax(1)
Pdmax(2)
Operating ambient
temperature
Storage ambient
temperature
P00 to P06, P30,
PPGO, OWP0
P02 to P07, P30,
PPGO, OWP0
P00, P01
P02 to P07, P30,
PPGO, OWP0
P00, P01
P00 to P03
P04 to P07, P30,
PPGO, OWP0
P00 to P07, P30,
PPGO, OWP0
DIP24S
CMOS output select
Per 1 applicable pin
CMOS output select
Per 1 applicable pin
Total of all applicable
pins
Per 1 applicable pin
10
unit
V
mA
7.5
25
20
Per 1 applicable pin
Per 1 applicable pin
30
15
Per 1 applicable pin
Total of all applicable
pins
Total of all applicable
pins
Total of all applicable
pins
Ta=40 to +85C
Package only
Ta=40 to +85C
Mounted on thermal
resistance test board
(Note 1-2)
20
40
40
70
300
mW
470
Topr
40
-
+85
Tstg
55
-
+125
C
Note 1-1 : The mean output current is a mean value measured over 100ms.
Note 1-2 : SEMI standards thermal resistance board (size : 76.1×114.3×1.6t mm, glass epoxy) is used.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
No.A2275-12/24
LC87F2K08A
2. Allowable Operating Conditions at Ta=40 to +85C, VSS1= VSS2=0V
Parameter
Operating
supply voltage
Memory
sustaining
supply voltage
High level
input voltage
Low level input
voltage
Instruction
cycle time
(Note 2-1)
Oscillation
frequency
range
Symbol
Pin / Remarks
Conditions
VDD[V]
min.
Specification
typ.
max.
VDD
VDD1
0.238µs  tCYC  200µs
4.5
VHD
VDD1
RAM and register contents
sustained in HOLD mode.
2.0
VIH(1)
P30, OWP0,
PPGO
4.5 to 5.5
0.3VDD
+0.7
VDD
VIH(2)
P00 to P07
4.5 to 5.5
VDD
5.5
unit
V
VIH(3)
RES#
4.5 to 5.5
0.3VDD
+0.7
0.75VDD
VIL(1)
P30, OWP0,
PPGO
4.5 to 5.5
VSS
0.1VDD
+0.4
VIL(2)
P00 to P07
4.5 to 5.5
VSS
VIL(3)
RES#
4.5 to 5.5
VSS
0.15VDD
+0.4
0.25VDD
4.5 to 5.5
0.238
120
µs
4.5 to 5.5
11.4
12.0
12.6
MHz
4.5 to 5.5
0.5
1.0
2.0
4.5 to 5.5
50
100
200
4.5 to 5.5
15
30
60
tCYC
(Note 2-1)
FmMRC
FmRC
FmSRC1
FmSRC2
Multi-frequency RC
oscillation.
1/2 frequency division ratio.
(RCCTD=0) (Note 2-2)
Internal medium-speed RC
oscillation
Internal low-speed RC1
oscillation
Internal low-speed RC2
oscillation
VDD
kHz
Note 2-1 : Relationship between tCYC and oscillation frequency is 3/FmMRC at a division ratio of 1/1 and 6/FmMRC
at a division ratio of 1/2.
Note 2-2 : When switching the system clock, allow an oscillation stabilization time of 100 μs or longer after the
multi-frequency RC oscillator circuit transmits from the "oscillation stopped" to "oscillation enabled" state.
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
No.A2275-13/24
LC87F2K08A
3. Electrical Characteristics at Ta=40 to +85C, VSS1= VSS2=0V
Parameter
Symbol
Pin / Remarks
min.
Specification
typ.
max.
Output disabled
Pull-up resistor off
VIN=VDD
(Including output Tr's off
leakage current)
Output disabled
Pull-up resistor off
VIN=VSS
(Including output Tr's off
leakage current)
4.5 to 5.5
1
5.0
2.0
IOH=-1mA
4.5 to 5.5
VDD1
P30, PPGO, OWP0
IOH=-6mA
4.5 to 5.5
VDD1
P00 to P07, P30,
PPGO, OWP0
IOL=10mA
4.5 to 5.5
1.5
IOL=1.4mA
4.5 to 5.5
0.4
P00, P01
IOL=25mA
4.5 to 5.5
1.5
IIH
Low level input
current
IIL
AMP allowable
output current
(Note 3-1)
IAMPO
P00 to P07, P30,
CMP1IA, CMP1IB,
CMP2I, CMP4I,
CPM45I, CMP5I,
CMP6I, AMP1I,
OWP0, RES#
P00 to P07, P30,
CMP1IA, CMP1IB,
CMP2I, CMP4I,
CPM45I, CMP5I,
CMP6I, AMP1I,
OWP0, RES#
AMP2O
High level output
voltage
VOH(1)
P00 to P06
VOH(2)
Low level output
voltage
VOL(1)
VOL(3)
VDD[V]
4.5 to 5.5
High level input
current
VOL(2)
Conditions
VOL(4)
AMP1 gain is 8 x and
AMP2 gain is 1 x
selected
AMP1I=0.445V
unit
1
µA
0.30
mA
V
IOL=4mA
4.5 to 5.5
Pull-up resistance
Rpu
P00 to P06, P30
VOH=0.9VDD
4.5 to 5.5
0.4
Hysteresis
voltage
VHYS
P04 only when detecting
INT4 interrupt
4.5 to 5.5
0.1VDD
V
Pin capacitance
CP
P04 to P07, P30,
RES#, OWP0,
PPGO
All pins
For pins other than that
under test:
VIN=VSS
f=1MHz
Ta=25C
4.5 to 5.5
10
pF
15
35
80
k
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
Note 3-1 :
O u t put C h ar ac t er ist ic s C u r rent S o urc ing
O u t put C h ar ac t er ist ic s C u r rent S in king
5
5
4.5
4.5
4
4
AMP2O (V)
3
3
2.5
2.5
2
2
AMP2O (V)
3.5
3.5
1.5
1.5
1
1
0.5
0.5
0
0
-5
-4
-3
-2
Output Source Current (mA)
-1
0
0
0.05
0.1
0.15
0.2
0.25
Output Sink Current (mA)
0.3
0.35
No.A2275-14/24
LC87F2K08A
4. Serial I/O Characteristics at Ta=40 to +85C, VSS1= VSS2=0V
(Note 4-1)
Output clock
Pin / Remarks
Period
tSCK(3)
SCK1 (P06)
Low level pulse
width
tSCKL(3)
1
High level pulse
width
tSCKH(3)
1
Period
tSCK(4)
Low level pulse
width
tSCKL(4)
1/2
High level pulse
width
tSCKH(4)
1/2
Data setup time
tsDI(2)
Data hold time
thDI(2)
Output delay time
tdD0(4)
SCK1 (P06)
SB1 (P05)
SB1 (P05)
Conditions
Specification
typ.
max.
Symbol
Serial output
Serial input
Serial clock
Input clock
Parameter
 See Fig. 5.
 CMOS output
selected
 See Fig. 5.
VDD[V]
min.
4.5 to 5.5
2
4.5 to 5.5
4.5 to 5.5
 Must be specified
with respect to rising
edge of SIOCLK.
 See Fig. 2.
unit
tCYC
2
tSCK
0.05
µs
0.05
4.5 to 5.5
 Must be specified
with respect to
falling edge of
SIOCLK.
 Must be specified as
the time to the
beginning of
output state change
in open drain output
mode.
 See Fig. 2.
(1/3)tCYC
+0.08
Note 4-1 : These specifications are theoretical values. Be sure to add a margin depending on its use.
5. Pulse Input Conditions at Ta=40 to +85C, VSS1= VSS2=0V
Parameter
Symbol
Pin / Remarks
High/low
level pulse
width
tPIH(1)
tPIL(1)
INT4 (P04)
tPIL(2)
RES#
Conditions
VDD[V]
 Interrupt source flag can be set. 4.5 to 5.5
 Event inputs for timer 0 or 1 are
enabled.
 Resetting is enabled.
4.5 to 5.5
min.
Specification
typ. max.
unit
1
tCYC
200
µs
No.A2275-15/24
LC87F2K08A
6. AD Converter Characteristics at VSS1= VSS2=0V
< 12 bits AD Converter Mode / Ta=40 to +85C >
Parameter
Symbol
Pin / Remarks
Resolution
Absolute
accuracy
Conversion
time
N
ET
AN0 (P00) to
AN4 (P04)
Analog input
voltage range
Analog port
input current
VAIN
TCAD
Conditions
VDD[V]
4.5 to 5.5
4.5 to 5.5
(Note 6-1)
See conversion time
calculation formulas.
(Note 6-2)
●
IAINH
IAINL
min.
VAIN=VDD
VAIN=VSS
Specification
typ.
max.
12
unit
16
bit
LSB
4.5 to 5.5
32
115
µs
4.5 to 5.5
VSS
VDD
V
4.5 to 5.5
4.5 to 5.5
1
µA
1
VDD[V]
min.
< 8 bits AD Converter Mode / Ta=40 to +85C >
Parameter
Symbol
Pin / Remarks
Resolution
Absolute
accuracy
Conversion
time
N
ET
AN0 (P00) to
AN4 (P04)
Analog input
voltage range
Analog port
input current
VAIN
TCAD
Conditions
4.5 to 5.5
4.5 to 5.5
(Note 6-1)
See conversion time
calculation formulas.
(Note 6-2)
●
IAINH
IAINL
VAIN=VDD
VAIN=VSS
Specification
typ.
max.
8
unit
1.5
bit
LSB
4.5 to 5.5
20
90
µs
4.5 to 5.5
VSS
VDD
V
4.5 to 5.5
4.5 to 5.5
1
µA
1
Conversion time calculation formulas :
12bits AD Converter Mode: TCAD (Conversion time) = ((52 / (AD division ratio)) + 2) × (1/3) × tCYC
8bits AD Converter Mode: TCAD (Conversion time) = ((32 / (AD division ratio)) + 2) × (1/3) × tCYC
<Recommended Operating Conditions>
Internal
oscillation
(FmMRC)
Operating supply
voltage range
(VDD)
System
division ratio
(SYSDIV)
Cycle time
(tCYC)
AD division
ratio
(ADDIV)
12MHz
4.5V to 5.5V
1/1
250ns
1/8
AD conversion time
(TCAD)
12-bit AD
8-bit AD
34.8µs
21.5µs
Note 6-1 : The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy
must be measured in the microcontroller's state in which no change in I/O status occurs at the pins adjacent
to the analog input channel.
Note 6-2 : The conversion time refers to the period from the time an instruction for starting a conversion process till
the time the conversion results register(s) are loaded with a complete digital conversion value
corresponding to the analog input value.
The conversion time is 2 times the normal-time conversion time when :
● The first AD conversion is performed in the 12-bit AD conversion mode after a system reset.
● The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit
conversion mode.
No.A2275-16/24
LC87F2K08A
7. Power-on Reset (POR) Characteristics at Ta=40 to +85C, VSS1= VSS2=0V
Specification
Parameter
POR release
voltage
Symbol
Pin /
Remarks
Conditions
 Select from options.
(Note 7-1)
PORRL
Detection
voltage
unknown state
POUKS
 See Fig. 4.
(Note 7-2)
Power supply
rise time
PORIS
 Power supply rise time
from VDD=0V to 1.6V.
Option
selected
voltage
min.
typ.
max.
unit
1.67V
1.97V
2.07V
2.37V
2.57V
1.55
1.85
1.95
2.25
2.45
1.67
1.97
2.07
2.37
2.57
1.79
2.09
2.19
2.49
2.69
V
2.87V
3.86V
4.35V
2.75
3.73
4.21
2.87
3.86
4.35
0.7
2.99
3.99
4.49
0.95
100
ms
Note7-1 : The POR release level can be selected out of 8 levels when the LVD reset function is disabled.
Note7-2 : POR is in an unknown state before transistors start operation.
8. Low Voltage Detection Reset (LVD) Characteristics at Ta=40 to +85C, VSS1= VSS2=0V
Specification
Parameter
Symbol
Pin /
Remarks
Conditions
LVD reset
voltage
(Note 8-2)
LVDET
Select from options.
See Fig. 5.
(Note 8-1)
(Note 8-3)
LVD detection
voltage
hysteresis
LVHYS
Detection
voltage
unknown state
Low voltage
detection
minimum width
(Reply
sensitivity)
LVUKS
See Fig. 5.
(Note 8-4)
TLVDW
LVDET-0.5V
See Fig. 6.
Option
selected
voltage
1.91V
2.01V
2.31V
2.51V
2.81V
3.79V
4.28V
1.91V
2.01V
2.31V
2.51V
2.81V
3.79V
4.28V
min.
typ.
max.
unit
1.81
1.91
2.21
2.41
2.71
3.69
4.18
1.91
2.01
2.31
2.51
2.81
3.79
4.28
55
55
55
55
60
65
65
0.7
2.01
2.11
2.41
2.61
2.91
3.89
4.38
V
0.2
mV
0.95
V
ms
Note8-1 : The LVD reset level can be selected out of 7 levels when the LVD reset function is enabled.
Note8-2 : LVD reset voltage specification values do not include hysteresis voltage.
Note8-3 : LVD reset voltage may exceed its specification values when port output state changes and/or when a large
current flows through port.
Note8-4 : LVD is in an unknown state before transistors start operation.
No.A2275-17/24
LC87F2K08A
9. Amplifier and Comparator Characteristics at Ta=40 to +85C, VSS1= VSS2=0V
Parameter
Symbol
Pin / Remarks
Conditions
Specification
VDD[V]
min.
4.5 to 5.5
VREF(1)
CMP1IA, CMP1IB,
CMP2I,CMP4I
CMP45I, CMP5I,
CMP6I
CMP2,
4.5 to 5.5
VREF(2)
CMP3, CMP6
4.5 to 5.5
VREF(3)
CMP7
4.5 to 5.5
1/20VDD
0.02
VREF(4)
CMP8
4.5 to 5.5
12/20VDD
0.02
VAMIN
AMP1I
4.5 to 5.5
VSS
VOFF(1)
VOFF(3)
CMP1IA, CMP1IB,
(CMP1)
CMP4I, CMP45I,
(CMP4)
CMP45I, CMP5I,
(CMP5)
CMP2I (CMP2),
CMP6I (CMP6),
CMP1IB (CMP7),
CMP4I,(CMP8)
AMP1I (CMP3)
AMP output
error
VAER
AMP2O
CMP1
response time
(Note 9-3)
tC1RT
CMP1O(P30)
CMP3
response time
tC3RT
PPGO
Common
mode input
voltage range
(Note 9-1)
Internal
reference
voltage
AMP input
voltage range
(Note 9-2)
Offset voltage
VCMIN
VOFF(2)
CMP4 /CMP5
response time
tC45RT
PPGO
CMP6 /CMP8
response time
tC68RT
PPGO
CMP7
response time
tC7RT
PPGO
typ.
max.
unit
VSS
VDD
1.5V
V
2/3VDD
0.02
1/6VDD
0.02
2/3VDD
+0.02
4/6VDD
+0.02
2/20VDD
+0.02
14/20VDD
+0.02
(VDD
1.5V)
/AMP gain
 Within common mode
input voltage range
4.5 to 5.5
20
 Within common mode
input voltage range
 Including VREF error
4.5 to 5.5
40
 Within AMP Input voltage
range
 AMP1 gain set at 8x
4.5 to 5.5
28
 Including VREF error
 Within AMP Input voltage
range
 AMP1 gain set at 8x
 AMP2 gain set at 1x
 Within common mode
input voltage range
 Input amplitude=100mV
 Over drive=50mV
 AMP1 gain set at 8x
 AMP1I rising time
 MP1I=(VREF±100mV)/8
 See Fig. 7.
 Within common mode
input voltage range
 Input amplitude=100mV
 Over drive=50mV
 CMP input pin rising time
CMP input=VREF±50mV
 See Fig. 7.
 CMP input pin falling time
4.5 to 5.5
155
4.5 to 5.5
200
4.5 to 5.5
600
4.5 to 5.5
200
4.5 to 5.5
200
4.5 to 5.5
200
200
mV
mV
ns
 CMP input=VREF±50mV
 See Fig. 8.
Note 9-1 : When VDD=5V, the comparator input voltage is effective from 0 to 3.5V.
Note 9-2 : AMP gain = AMP1 gain × AMP2 gain
When VDD =5V, AMP1 gain 8, AMP2 gain 1, the AMP input voltage is effective from 0 to 0.4375V.
Note 9-3 : PPG output has a delay of 1/6tCYC to 1/2tCYC from CMP1O falling timing for synchronization with
system clock, when the pulse start delay setup register is set to 000H.
No.A2275-18/24
LC87F2K08A
10. Consumption Current Characteristics at Ta=40 to +85C, VSS1= VSS2=0V
Parameter
Normal
mode
consumption
current
(Note 10-1)
(Note 10-2)
Symbol
IDDOP(1)
IDDOP(2)
IDDOP(3)
Halt mode
consumption
current
(Note 10-1)
(Note 10-2)
IDDHALT (1)
IDDHALT (2)
IDDHALT (3)
HOLD mode
consumption
current
(Note 10-1)
(Note 10-2)
IDDHOLD
Pin / Remarks
VDD1
Conditions
 System clock set to 12MHz of
multi-frequency RC oscillator.
 Internal low speed/medium
speed RC oscillator stopped.
 1/1 frequency division ratio
 System clock: Internal mediumspeed RC oscillator
 Internal low speed RC
oscillator/multi-frequency RC
oscillator stopped.
 1/2 frequency division ratio
 System clock: Internal lowspeed RC oscillator
 Internal medium speed RC
oscillator/multi-frequency RC
oscillator stopped.
 1/1 frequency division ratio
 HALT mode
 System clock set to 12MHz of
multi-frequency RC oscillator
 Internal low speed/medium
speed RC oscillator stopped.
 1/1 frequency division ratio
 HALT mode
 System clock set to internal
medium- speed RC oscillator
 Internal low speed RC
oscillator/multi-frequency RC
oscillator stopped.
 1/2 frequency division ratio
 HALT mode
 System clock set to internal
low speed RC oscillation.
 Internal medium speed RC
oscillator/multi-frequency RC
oscillator stopped.
 1/1 frequency division ratio
 HOLD mode.
 When LVD option selected
Specification
VDD[V]
min.
typ.
Max.
unit
4.5 to 5.5
8
12
mA
4.5 to 5.5
2.5
4
4.5 to 5.5
2.1
3.1
4.5 to 5.5
4.2
7
4.5 to 5.5
2.3
3.5
4.5 to 5.5
2
3
4.5 to 5.5
2
3
(Note 10-3)
Note10-1 : Values of the consumption current do not include current that flows into the output transistors and internal
pull-up resistors.
Note10-2 : The consumption current values do not include operational current of LVD function if not specified.
Note10-3 : AMP/CMP circuits are operating in HOLD mode.
No.A2275-19/24
LC87F2K08A
11. F-ROM Programming Characteristics at Ta=+10 to +55C, VSS1= VSS2=0V
Parameter
Symbol
IDDFW
Onboard
programming
current
Programming
time
Pin / Remarks
VDD1
tFW(1)
tFW(2)
Conditions
Specification
VDD[V]
min.
typ.
max.
unit
 Excluding current consumption
of the microcontroller block
4.5 to 5.5
5
10
mA
 Erasing operation
 Programming operation
4.5 to 5.5
20
40
30
60
ms
µs
12. UART (Full Duplex) Operating Conditions at Ta=40 to +85C, VSS1= VSS2=0V
Parameter
Transfer rate
Symbol
UBR
Pin / Remarks
Conditions
UTX(P05)
URX(P06)
VDD[V]
min.
Specification
typ.
max.
unit
4.5 to 5.5
16/3
8192/3
tCYC
Data length : 7/8/9 bits (LSB first)
Stop bits
: 1 bit(2-bit in continuous data transmission)
Parity bits : None
Example of Continuous 8-bit Data Transmission Mode Processing (First Transmit Data=55H)
Start bit
Start of
transmission
Stop bit
End of
transmission
Transmit data (LSB first)
UBR
Example of Continuous 8-bit Data Reception Mode Processing (First Receive Data=55H)
Start bit
Start of
reception
Stop bit
Receive data (LSB first)
End of
reception
UBR
No.A2275-20/24
LC87F2K08A
VDD
RRES
Note:
External circuits for reset may vary depending on the usage of
POR and LVD. Please refer to the reset function in the user’s
manual for more information.
RES#
CRES
Figure 1. Sample Reset Circuit
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
tSCK
tSCKL
tSCKH
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Figure 2. Serial I/O Waveforms
tPIL
tPIH
Figure 3. Pulse Input Timing Signal Waveform
No.A2275-21/24
LC87F2K08A
(a)
POR release voltage
(PORRL)
(b)
VDD
Reset period
Reset period
100μs or longer
Reset unknown-state
(POUKS)
RES#
Figure 4. Example of waveforms observed when only POR is used (LVD not used)
(RESET pin : Pull-up resistor RRES only)
• The POR function generates a reset only when power is turned on starting at the VSS level.
• No stable reset will be generated if power is turned on again when the power level does not go down to
the VSS level as shown in (a). If such a case is anticipated, use the LVD function together with the POR
function or implement an external reset circuit.
• A reset is generated only when the power level goes down to the VSS level as shown in (b) and power is
turned on again after this condition continues for 100μs or longer.
LVD hysteresis width
(LVHYS)
LVD release voltage
(LVDET+LVHYS)
VDD
LVD reset voltage
(LVDET)
Reset period
Reset period
Reset period
Reset
unknown-state
(LVUKS)
RES#
Figure 5. Example of waveforms observed when both POR and LVD functions are used
(RESET pin : Pull-up resistor RRES only)
• Resets are generated both when power is turned on and when the power level lowers.
• A hysteresis width (LVHYS) is provided to prevent the repetitions of reset release and entry cycles near
the detection level.
No.A2275-22/24
LC87F2K08A
VDD
LVD release voltage
LVD detection
voltage
LVDET-0.5V
TLVDW
VSS
Figure 6. Low voltage detection minimum width
(Example of momentary power loss / Voltage variation waveform)
(VREF+100mV) / 8
VREF / 8
(VREF100mV) / 8
AMP1I
VREF + 50mV
VREF
VREF  50mV
CMP4I / CMP6I
PPGO
tC678RT
tC3RT
Figure 7. CMP response time 1
VREF+50mV
VREF
VREF50mV
CMP7I
PPGO
tC678RT
Figure 8. CMP response time 2
No.A2275-23/24
LC87F2K08A
ORDERING INFORMATION
Device
LC87F2K08AU-DIP-E
Package
Shipping (Qty / Packing)
DIP24S(300mil)
(Pb-Free)
1100 / Fan-Fold
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nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can
and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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PS No.A2275-24/24