LTC3547 Dual Monolithic 300mA Synchronous Step-Down Regulator DESCRIPTIO U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High Efficiency Dual Step-Down Outputs: Up to 96% 300mA Output Current per Channel at VIN = 3V Automatic Low Ripple Burst Mode Operation (20mVP-P) Only 40µA Quiescent Current During Operation (Both Channels) 2.25MHz Constant-Frequency Operation 2.5V to 5.5V Input Voltage Range Low Dropout Operation: 100% Duty Cycle Internally Compensated for All Ceramic Capacitors Independent Internal Soft-Start for Each Channel Current Mode Operation for Excellent Line and Load Transient Response 0.6V Reference Allows Low Output Voltages Short-Circuit Protected Ultralow Shutdown Current: IQ < 1µA Low Profile (0.75mm) 8-Lead 3mm × 2mm DFN Package U APPLICATIO S ■ ■ ■ ■ ■ Cellular Telephones Digital Still Cameras Wireless and DSL Modems PDAs/Palmtop PCs Portable Media Players The LTC®3547 is a dual, 2.25MHz, constant-frequency, synchronous step-down DC/DC converter in a tiny 3mm × 2mm DFN package. 100% duty cycle provides low dropout operation, extending battery life in portable systems. Low output voltages are supported with the 0.6V feedback reference voltage. Each regulator can supply 300mA continuous output current. The input voltage range is 2.5V to 5.5V, making it ideal for Li-Ion and USB powered applications. Supply current during operation is only 40µA and drops to < 1µA in shutdown. Automatic Burst Mode® operation increases efficiency at light loads, further extending battery life. An internally set 2.25MHz switching frequency allows the use of tiny surface mount inductors and capacitors. Internal soft-start reduces inrush current during startup. All outputs are internally compensated to work with ceramic capacitors. The LTC3547 is available in a low profile (0.75mm) 3mm × 2mm DFN package. The LTC3547 is also available in a fixed output voltage configuration, eliminating the need for the external feedback networks (see Table 2). , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Burst Mode is a registered trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 6580258, 5481178, 6304066, 6127815, 6498466, 6611131. U TYPICAL APPLICATIO 100 Dual Monolithic Buck Regulator in 8-Lead 3mm × 2mm DFN 80 SW1 10pF 10pF VOUT1 2.5V AT 300mA EFFICIENCY (%) LTC3547 SW2 L1 4.7µH 60 40 30 20 VFB2 237k GND VFB1 150k 475k 4.7µF 10 0 0.1 3547 TA01 0.01 50 POWER LOSS (W) RUN2 VIN RUN1 L2 4.7µH 475k 0.1 70 4.7µF 4.7µF 1 90 VIN 2.5V TO 5.5V VOUT2 1.8V AT 300mA Efficiency vs Output Current for VOUT = 2.5V 0.001 VIN = 2.7V VIN = 3.6V VIN = 4.2V 1 10 100 OUTPUT CURRENT (mA) 0.0001 1000 3547 TA01b 3547fa 1 LTC3547 U W W W ABSOLUTE AXI U RATI GS U W U PACKAGE/ORDER I FOR ATIO (Note 1) TOP VIEW VIN ............................................................... –0.3V to 6V VFB1, VFB2 ......................................... –0.3V to VIN +0.3V RUN1, RUN2 ..................................... –0.3V to VIN +0.3V SW1, SW2 (DC) ................................ –0.3V to VIN +0.3V P-Channel Switch Source Current (DC) ...............500mA N-Channel Switch Sink Current (DC) ...................500mA Peak SW Sink and Source Current (Note 5) .........700mA Ambient Operating Temperature Range ... –40°C to 85°C Maximum Junction Temperature .......................... 125°C Storage Temperature Range................... –65°C to 125°C 8 VFB2 VFB1 1 RUN1 2 VIN 3 9 SW1 4 7 RUN2 6 SW2 5 GND DDB PACKAGE 8-LEAD (3mm × 2mm) PLASTIC DFN TJMAX = 125°C, θJA = 76°C/W EXPOSED PAD (PIN 9) IS GND MUST BE SOLDERED TO PCB ORDER PART NUMBER DDB PART MARKING LTC3547EDDB LTC3547EDDB-1 LCDP LCPC Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, unless otherwise noted. SYMBOL PARAMETER VIN VIN Operating Voltage VUV VIN Undervoltage Lockout VIN Low to High ● IFB Feedback Pin Input Current LTC3547, VFB = VFBREG LTC3547-1, VFB = VFBREG ● ● VFBREG1 VFBREG2 Regulated Feedback Voltage (VFB1) Regulated Feedback Voltage (VFB2) CONDITIONS MIN ● LTC3547, 0°C ≤ TA ≤ 85°C LTC3547, –40°C ≤ TA ≤ 85°C LTC3547-1, 0°C ≤ TA ≤ 85°C LTC3547-1, –40°C ≤ TA ≤ 85°C LTC3547, 0°C ≤ TA ≤ 85°C LTC3547, –40°C ≤ TA ≤ 85°C LTC3547-1, 0°C ≤ TA ≤ 85°C LTC3547-1, –40°C ≤ TA ≤ 85°C ● ● ● ● TYP 2.5 MAX UNITS 5.5 V 2.0 2.5 V 3 30 6 nA µA 0.590 0.588 1.770 1.764 0.600 0.600 1.800 1.800 0.610 0.612 1.830 1.836 V V V V 0.590 0.588 1.180 1.176 0.600 0.600 1.200 1.200 0.610 0.612 1.220 1.224 V V V V 0.5 ΔVLINEREG ΔVLOADREG Reference Voltage Line Regulation VIN = 2.5V to 5.5V 0.3 Output Voltage Load Regulation ILOAD = 0mA to 300mA 0.5 IS Input DC Supply Current Active Mode (Note 3) Sleep Mode Shutdown VFB1 = VFB2 = 0.95V × VFBREG VFB1 = VFB2 = 1.05V × VFBREG, VIN = 5.5V RUN1 = RUN2 = 0V, VIN = 5.5V 450 40 0.1 700 60 1 µA µA µA fOSC Oscillator Frequency VFB = 0.6V 1.8 2.25 2.7 MHz ILIM Peak Switch Current Limit Channel 1 (300mA) Channel 2 (300mA) VIN = 3V, VFB < VFBREG , Duty Cycle < 35% 400 400 550 550 ● %/V % mA mA 3547fa 2 LTC3547 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 3.6V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS RDS(ON) Channel 1 (Note 4) Top Switch On-Resistance Bottom Switch On-Resistance Channel 2 (Note 4) Top Switch On-Resistance Bottom Switch On-Resistance MIN TYP MAX UNITS VIN = 3.6V, ISW = 100mA VIN = 3.6V, ISW = 100mA 0.8 0.75 1.05 1.05 Ω Ω VIN = 3.6V, ISW = 100mA VIN = 3.6V, ISW = 100mA 0.8 0.75 1.05 1.05 Ω Ω 0.01 1 µA 0.450 0.650 0.850 ms 0.4 1 1.2 V 0.01 1 µA ISW(LKG) Switch Leakage Current VIN = 5V, VRUN = 0V tSOFTSTART Soft-Start Time VFB From 10% to 90% Full-Scale VRUN RUN Threshold High ● IRUN RUN Leakage Current ● VBURST Output Ripple in Burst Mode Operation VOUT = 1.5V, COUT = 4.7µF Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3547E is guaranteed to meet specified performance from 0°C to 85°C. Specifications over the –40°C and 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: Dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. 20 mVP-P Note 4: The DFN switch on-resistance is guaranteed by correlation to wafer level measurements. Note 5: Guaranteed by long term current density limitations. Note 6: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. U W TYPICAL PERFOR A CE CHARACTERISTICS Burst Mode Operation Efficiency vs Input Voltage 100 SW, AC COUPLED 5V/DIV Supply Current vs Temperature 60 VOUT = 1.8V 55 SUPPLY CURRENT (µA) 90 80 EFFICIENCY (%) VOUT 50mV/DIV IL 50mA/DIV 70 60 50 3547 G01 2.5µs/DIV VIN = 3.6V VOUT = 1.8V ILOAD = 20mA 40 30 2.5 IOUT = 0.1mA IOUT = 1mA IOUT = 10mA IOUT = 100mA IOUT = 300mA 3 3.5 RUN1 = RUN2 = VIN ILOAD = 0A 50 45 VIN = 5.5V 40 35 VIN = 2.7V 30 25 4.5 4 VIN (V) 5 5.5 3547 G02 20 –50 –25 50 25 0 TEMPERATURE (ºC) 75 100 3547 G03 3547fa 3 LTC3547 U W TYPICAL PERFOR A CE CHARACTERISTICS Oscillator Frequency vs Temperature Switch Leakage vs Temperature 2.6 Switch Leakage vs Input Voltage 50 500 40 400 FREQUENCY (MHz) 2.3 LEAKAGE CURRENT (nA) VIN = 4.2V 2.4 VIN = 3.6V 2.2 VIN = 2.7V 2.1 2.0 30 SYNCHRONOUS SWITCH 20 10 0 50 75 25 TEMPERATURE (°C) 100 0 – 50 – 25 125 0 50 75 25 TEMPERATURE (°C) 3547 G04 300 SYNCHRONOUS SWITCH 200 100 MAIN SWITCH 1.9 1.8 – 50 – 25 LEAKAGE CURRENT (pA) 2.5 MAIN SWITCH 100 0 2.5 125 3 3.5 4.5 4 VIN (V) 5 5.5 3547 G06 3547 G05 Reference Voltage vs Temperature RDS(ON) vs Input Voltage 612 RDS(ON) vs Temperature 1.3 1.0 MAIN SWITCH 608 6 VIN = 2.7V 1.2 0.9 1.1 SYNCHRONOUS SWITCH 0.7 596 0.6 592 0.5 RDS(ON) (Ω) 600 VIN = 3.6V 1.0 0.8 RDS(ON) (Ω) VFB (mV) 604 0.9 0.8 0.7 0.6 0.5 588 – 50 – 25 75 0 50 25 TEMPERATURE (°C) 0.4 2.5 100 3 3.5 4.5 4 VIN (V) 5 5.5 3547 G07 VOUT = 1.2V 90 VOUT = 1.8V 90 80 70 70 40 EFFICIENCY (%) 80 70 50 60 50 40 30 20 20 0 0.1 1 10 100 OUTPUT CURRENT (mA) 1000 3547 G10 0 0.1 VIN = 2.7V VIN = 3.6V VIN = 4.2V 10 100 1 OUTPUT CURRENT (mA) 1000 3547 G11 VOUT = 2.5V 40 20 10 125 50 30 VIN = 2.7V VIN = 3.6V VIN = 4.2V 100 60 30 10 50 75 25 TEMPERATURE (°C) Efficiency vs Load Current 100 80 60 0 3547 G09 Efficiency vs Load Current 100 EFFICIENCY (%) EFFICIENCY (%) 90 0.4 – 50 – 25 6 MAIN SWITCH SYNCHRONOUS SWITCH 3547 G08 Efficiency vs Load Current 100 VIN = 4.2V 10 0 0.1 VIN = 2.7V VIN = 3.6V VIN = 4.2V 1 10 100 OUTPUT CURRENT (mA) 1000 3547 G12 3547fa 4 LTC3547 U W TYPICAL PERFOR A CE CHARACTERISTICS Load Regulation 1.2 VOUT = 1.2V VOUT = 1.8V VOUT = 2.5V 1.O VIN = 3.6V 0.4 0.8 VOUT ERROR (%) VOUT ERROR (%) Line Regulation 0.6 Burst Mode OPERATION 0.4 0.6 VOUT = 1.8V ILOAD = 100mA 0.2 0 –0.2 0.2 –0.4 0 –0.6 2.5 –0.2 0 50 150 200 250 LOAD CURRENT (mA) 100 300 350 3 3.5 4.5 4 VIN (V) 5 3547 G14 3547 G13 Start-Up From Shutdown Load Step Start-Up From Shutdown RUN 2V/DIV RUN 2V/DIV VOUT 1V/DIV VOUT 1V/DIV IL 100mA/DIV IL 200mA/DIV VOUT, AC COUPLED 100mV/DIV IL 200mA/DIV ILOAD 200mA/DIV 3547 G15 3547 G16 250µs/DIV VIN = 3.6V VOUT = 1.8V ILOAD = 0A 200µs/DIV VIN = 3.6V VOUT = 1.8V ILOAD = 300mA Load Step 3547 G17 10µs/DIV VIN = 3.6V VOUT = 1.8V ILOAD = 0mA TO 300mA Load Step VOUT, AC COUPLED 100mV/DIV VOUT, AC COUPLED 100mV/DIV IL 200mA/DIV IL 200mA/DIV ILOAD 200mA/DIV ILOAD 200mA/DIV 3547 G18 10µs/DIV VIN = 3.6V VOUT = 1.8V ILOAD = 20mA TO 300mA 5.5 3547 G19 10µs/DIV VIN = 3.6V VOUT = 1.8V ILOAD = 50mA TO 300mA 3547fa 5 LTC3547 U U U PI FU CTIO S VFB1 (Pin 1): Regulator 1 Output Feedback. Receives the feedback voltage from the external resistor divider across the regulator 1 output. Nominal voltage for this pin is 0.6V. SW2 (Pin 6): Regulator 2 Switch Node Connection to the Inductor. This pin swings from VIN to GND. RUN2 (Pin 7): Regulator 2 Enable. Forcing this pin to VIN enables regulator 2, while forcing it to GND causes regulator 2 to shut down. RUN1 (Pin 2): Regulator 1 Enable. Forcing this pin to VIN enables regulator 1, while forcing it to GND causes regulator 1 to shut down. VFB2 (Pin 8): Regulator 2 Output Feedback. Receives the feedback voltage from the external resistor divider across the regulator 2 output. Nominal voltage for this pin is 0.6V. VIN (Pin 3): Main Power Supply. Must be closely decoupled to GND. SW1 (Pin 4): Regulator 1 Switch Node Connection to the Inductor. This pin swings from VIN to GND. Exposed Pad (Pin 9): Electrically Connected to GND. Must be soldered to the PCB for optimum thermal performance. GND (Pin 5): Ground. Connect to the (–) terminal of COUT, and the (–) terminal of CIN. FUNCTIONAL DIAGRAM REGULATOR 1 BURST CLAMP 3 VIN SLOPE COMP VFB1 – – 1 EA 0.6V VSLEEP + – SLEEP ITH + 5Ω ICOMP + BURST S Q RS LATCH R Q SOFT-START SWITCHING LOGIC AND BLANKING CIRCUIT ANTI SHOOTTHRU 4 SW1 + IRCMP – SHUTDOWN RUN1 2 SLEEP2 0.6V REF RUN2 5 GND SLEEP1 OSC 7 OSC VFB2 8 REGULATOR 2 (IDENTICAL TO REGULATOR 1) 6 SW2 3547 FD 6 3547fa LTC3547 U OPERATIO (Refer to Functional Diagram ) The LTC3547 uses a constant-frequency current mode architecture. The operating frequency is set at 2.25MHz. Both channels share the same clock and run in-phase. The output voltage is set by an external resistor divider returned to the VFB pins. An error amplifier compares the divided output voltage with a reference voltage of 0.6V and regulates the peak inductor current accordingly. Main Control Loop During normal operation, the top power switch (P-channel MOSFET) is turned on at the beginning of a clock cycle when the VFB voltage is below the reference voltage. The current into the inductor and the load increases until the peak inductor current (controlled by ITH) is reached. The RS latch turns off the synchronous switch and energy stored in the inductor is discharged through the bottom switch (N-channel MOSFET) into the load until the next clock cycle begins, or until the inductor current begins to reverse (sensed by the IRCMP comparator). Dropout Operation When the input supply voltage decreases toward the output voltage the duty cycle increases to 100%, which is the dropout condition. In dropout, the PMOS switch is turned on continuously with the output voltage being equal to the input voltage minus the voltage drops across the internal P-channel MOSFET and the inductor. An important design consideration is that the RDS(ON) of the P-channel switch increases with decreasing input supply voltage (see Typical Performance Characteristics). Therefore, the user should calculate the worst-case power dissipation when the LTC3547 is used at 100% duty cycle with low input voltage (see Thermal Considerations in the Applications Information Section). Soft-Start The peak inductor current is controlled by the internally compensated ITH voltage, which is the output of the error amplifier. This amplifier regulates the VFB pin to the internal 0.6V reference by adjusting the peak inductor current accordingly. In order to minimize the inrush current on the input bypass capacitor, the LTC3547 slowly ramps up the output voltage during start-up. Whenever the RUN1 or RUN2 pin is pulled high, the corresponding output will ramp from zero to full-scale over a time period of approximately 650µs. This prevents the LTC3547 from having to quickly charge the output capacitor and thus supplying an excessive amount of instantaneous current. Burst Mode Operation Short-Circuit Protection To optimize efficiency, the LTC3547 automatically switches from continuous operation to Burst Mode operation when the load current is relatively light. During Burst Mode operation, the peak inductor current (as set by ITH) remains fixed at approximately 60mA and the PMOS switch operates intermittently based on load demand. By running cycles periodically, the switching losses are minimized. When either regulator output is shorted to ground, the corresponding internal N-channel switch is forced on for a longer time period for each cycle in order to allow the inductor to discharge, thus preventing current runaway. This technique has the effect of decreasing switching frequency. Once the short is removed, normal operation resumes and the regulator output will return to its nominal voltage. The duration of each burst event can range from a few cycles at light load to almost continuous cycling with short sleep intervals at moderate loads. During the sleep intervals, the load current is being supplied solely from the output capacitor. As the output voltage droops, the error amplifier output rises above the sleep threshold, signaling the burst comparator to trip and turn the top MOSFET on. This cycle repeats at a rate that is dependent on load demand. 3547fa 7 LTC3547 U U W U APPLICATIO S I FOR ATIO A general LTC3547 application circuit is shown in Figure 1. External component selection is driven by the load requirement, and begins with the selection of the inductor L. Once the inductor is chosen, CIN and COUT can be selected. Inductor Selection Although the inductor does not influence the operating frequency, the inductor value has a direct effect on ripple current. The inductor ripple current ΔIL decreases with higher inductance and increases with higher VIN or VOUT : ⎞ ⎛ V V ∆IL = OUT • ⎜ 1 − OUT ⎟ fO • L ⎝ VIN ⎠ (1) Accepting larger values of ΔIL allows the use of low inductances, but results in higher output voltage ripple, greater core losses, and lower output current capability. A reasonable starting point for setting ripple current is 40% of the maximum output load current. So, for a 300mA regulator, ΔIL = 120mA (40% of 300mA). The inductor value will also have an effect on Burst Mode operation. The transition to low current operation begins when the peak inductor current falls below a level set by the internal burst clamp. Lower inductor values result in higher ripple current which causes the transition to occur at lower load currents. This causes a dip in efficiency in the upper range of low current operation. Furthermore, lower inductance values will cause the bursts to occur with increased frequency. Inductor Core Selection Different core materials and shapes will change the size/current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and do not radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. The choice of which style inductor to use often depends more on the price vs size requirements, and any radiated field/EMI requirements, than on what the LTC3547 requires to operate. Table 1 shows some typical surface mount inductors that work well in LTC3547 applications. Table 1. Representative Surface Mount Inductors MANUFACTURER PART NUMBER MAX DC VALUE CURRENT DCR HEIGHT Taiyo Yuden CB2016T2R2M CB2012T2R2M CB2016T3R3M 2.2µH 2.2µH 3.3µH 510mA 530mA 410mA 0.13Ω 1.6mm 0.33Ω 1.25mm 0.27Ω 1.6mm Panasonic ELT5KT4R7M 4.7µH 950mA 0.2Ω 1.2mm Sumida CDRH2D18/LD 4.7µH 630mA 0.086Ω 2mm Murata LQH32CN4R7M23 4.7µH 450mA 0.2Ω 2mm Taiyo Yuden NR30102R2M NR30104R7M 2.2µH 4.7µH 1100mA 750mA 0.1Ω 0.19Ω 1mm 1mm FDK FDKMIPF2520D FDKMIPF2520D FDKMIPF2520D 4.7µH 3.3µH 2.2µH 1100mA 1200mA 1300mA 0.11Ω 0.1Ω 0.08Ω 1mm 1mm 1mm TDK VLF3010AT4R7MR70 VLF3010AT3R3MR87 VLF3010AT2R2M1RD 4.7µH 700mA 0.24Ω 1mm 3.3µH 870mA 0.17Ω 1mm 2.2µH 1000mA 0.12Ω 1mm VIN 2.5V TO 5.5V C1 RUN2 VIN RUN1 L2 VOUT2 LTC3547 SW2 CF2 VFB2 COUT2 R4 R3 L1 SW1 GND CF1 VOUT1 VFB1 R1 R2 COUT1 3547 F01 Figure 1. LTC3547 General Schematic 3547fa 8 LTC3547 U W U U APPLICATIO S I FOR ATIO Input Capacitor (CIN) Selection In continuous mode, the input current of the converter is a square wave with a duty cycle of approximately VOUT/VIN. To prevent large voltage transients, a low equivalent series resistance (ESR) input capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by: IRMS ≈ IMAX VOUT ( VIN − VOUT ) VIN (2) Where the maximum average output current IMAX equals the peak current minus half the peak-to-peak ripple current, IMAX = ILIM – ΔIL/2. This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case is commonly used to design because even significant deviations do not offer much relief. Note that capacitor manufacturer’s ripple current ratings are often based on only 2000 hours lifetime. This makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet the size or height requirements of the design. An additional 0.1µF to 1µF ceramic capacitor is also recommended on VIN for high frequency decoupling when not using an all-ceramic capacitor solution. Output Capacitor (COUT) Selection The selection of COUT is driven by the required effective series resistance (ESR). Typically, once the ESR requirement for COUT has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement. The output ripple ΔVOUT is determined by: ⎛ 1 ⎞ ∆ VOUT ≅ ∆ IL ⎜ ESR + 8 fCOUT ⎟⎠ ⎝ where f = operating frequency, COUT = output capacitance and ΔIL = ripple current in the inductor. For a fixed output voltage, the output ripple is highest at maximum input voltage since ΔIL increases with input voltage. If tantalum capacitors are used, it is critical that the capacitors are surge tested for use in switching power supplies. An excellent choice is the AVX TPS series of surface mount tantalum. These are specially constructed and tested for low ESR so they give the lowest ESR for a given volume. Other capacitor types include Sanyo POSCAP, Kemet T510 and T495 series, and Sprague 593D and 595D series. Consult the manufacturer for other specific recommendations. Using Ceramic Input and Output Capacitors Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. Because the LTC3547 control loop does not depend on the output capacitor’s ESR for stable operation, ceramic capacitors can be used freely to achieve very low output ripple and small circuit size. However, care must be taken when ceramic capacitors are used at the input. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, VIN. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN, large enough to damage the part. For more information, see Application Note 88. When choosing the input and output ceramic capacitors, choose the X5R or X7R dielectric formulations. These dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size. (3) 3547fa 9 LTC3547 U W U U APPLICATIO S I FOR ATIO Setting the Output Voltage The LTC3547 regulates the VFB1 and VFB2 pins to 0.6V during regulation. Thus, the output voltage is set by a resistive divider according to the following formula: ⎛ R2 ⎞ VOUT = 0 . 6 V ⎜ 1 + ⎟ ⎝ R1⎠ (4) Keeping the current small (< 5µA) in these resistors maximizes efficiency, but making it too small may allow stray capacitance to cause noise problems or reduce the phase margin of the error amp loop. To improve the frequency response of the main control loop, a feedback capacitor (CF) may also be used. Great care should be taken to route the VFB line away from noise sources, such as the inductor or the SW line. Fixed output versions of the LTC3547 (e.g. LTC3547-1) include an internal resistive divider, eliminating the need for external resistors. The resistor divider is chosen such that the VFB input current is 3µA. For these versions the VFB pin should be connected directly to VOUT. Table 2 lists the fixed output voltages available for the LTC35476-1. Table 2. Fixed Output Voltage Versions PART NUMBER LTC3547 LTC3547-1 VOUT1 VOUT2 Adjustable Adjustable 1.8V 1.2V Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ΔILOAD • ESR, where ESR is the effective series resistance of COUT. ΔILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. The initial output voltage step may not be within the bandwidth of the feedback loop, so the standard second-order overshoot/DC ratio cannot be used to determine the phase margin. In addition, feedback capacitors (CF1 and CF2) can be added to improve the high frequency response, as shown in Figure 1. Capacitor CF provides phase lead by creating a high frequency zero with R2 which improves the phase margin. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. For a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to Application Note 76. In some applications, a more severe transient can be caused by switching in loads with large (>1µF) input capacitors. The discharged input capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem if the switch connecting the load has low resistance and is driven quickly. The solution is to limit the turn-on speed of the load switch driver. A Hot Swap™ controller is designed specifically for this purpose and usually incorporates current limiting, short-circuit protection, and soft-starting. Hot Swap is a trademark of Linear Technology Corporation. 3547fa 10 LTC3547 U W U U APPLICATIO S I FOR ATIO Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: % Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc., are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, four sources usually account for the losses in LTC3547 circuits: 1) VIN quiescent current, 2) switching losses, 3) I2R losses, 4) other system losses. 1) The VIN current is the DC supply current given in the Electrical Characteristics which excludes MOSFET driver and control currents. VIN current results in a small (<0.1%) loss that increases with VIN, even at no load. 2) The switching current is the sum of the MOSFET driver and control currents. The MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from VIN to ground. The resulting dQ/dt is a current out of VIN that is typically much larger than the DC bias current. In continuous mode, IGATECHG = fO(QT + QB), where QT and QB are the gate charges of the internal top and bottom MOSFET switches. The gate charge losses are proportional to VIN and thus their effects will be more pronounced at higher supply voltages. 3) I2R losses are calculated from the DC resistances of the internal switches, RSW, and external inductor, RL. In continuous mode, the average output current flows through inductor L, but is “chopped” between the internal top and bottom switches. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows: RSW = (RDS(ON)TOP) • (DC) + (RDS(ON)BOT) • (1– DC) (5) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus, to obtain I2R losses: I2R losses = IOUT2 • (RSW + RL) 4) Other “hidden” losses, such as copper trace and internal battery resistances, can account for additional efficiency degradations in portable systems. It is very important to include these “system” level losses in the design of a system. The internal battery and fuse resistance losses can be minimized by making sure that CIN has adequate charge storage and very low ESR at the switching frequency. Other losses, including diode conduction losses during dead-time, and inductor core losses, generally account for less than 2% total additional loss. 3547fa 11 LTC3547 U W U U APPLICATIO S I FOR ATIO Thermal Considerations PC Board Layout Considerations In a majority of applications, the LTC3547 does not dissipate much heat due to its high efficiency. In the unlikely event that the junction temperature somehow reaches approximately 150°C, both power switches will be turned off and the SW node will become high impedance. When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3547. These items are also illustrated graphically in the layout diagrams of Figures 2 and 3. Check the following in your layout: The goal of the following thermal analysis is to determine whether the power dissipated causes enough temperature rise to exceed the maximum junction temperature (125°C) of the part. The temperature rise is given by: 1. Does the capacitor CIN connect to the power VIN (Pin 3) and GND (Pin 5) as closely as possible? This capacitor provides the AC current of the internal power MOSFETs and their drivers. TRISE = PD • θJA (6) Where PD is the power dissipated by the regulator and θJA is the thermal resistance from the junction of the die to the ambient temperature. The junction temperature, TJ, is given by: TJ = TRISE + TAMBIENT (7) As a worst-case example, consider the case when the LTC3547 is in dropout on both channels at an input voltage of 2.7V with a load current of 300mA and an ambient temperature of 70°C. From the Typical Performance Characteristics graph of Switch Resistance, the RDS(ON) of the main switch is 0.9Ω. Therefore, power dissipated by each channel is: PD = IOUT2 • RDS(ON) = 81mV Given that the thermal resistance of a properly soldered DFN package is approximately 76°C/W, the junction temperature of an LTC3547 device operating in a 70°C ambient temperature is approximately: TJ = (2 • 0.081W • 76°C/W) + 70°C = 82.3°C which is well below the absolute maximum junction temperature of 125°C. 2. Are the respective COUT and L closely connected? The (–) plate of COUT returns current to GND and the (–) plate of CIN. 3. The resistor divider, R1 and R2, must be connected between the (+) plate of COUT1 and a ground sense line terminated near GND (Pin 5). The feedback signals VFB1 and VFB2 should be routed away from noisy components and traces, such as the SW lines (Pins 4 and 6), and their trace length should be minimized. 4. Keep sensitive components away from the SW pins if possible. The input capacitor CIN and the resistors R1, R2, R3 and R4 should be routed away from the SW traces and the inductors. 5. A ground plane is preferred, but if not available, keep the signal and power grounds segregated with small signal components returning to the GND pin at a single point. These ground traces should not share the high current path of CIN or COUT. 6. Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power components. These copper areas should be connected to VIN or GND. 3547fa 12 LTC3547 U U W U APPLICATIO S I FOR ATIO VIN 2.5V TO 5.5V C1 RUN2 VIN RUN1 LTC3547 L2 VOUT2 SW2 L1 VOUT1 SW1 CF2 CF1 VFB2 R4 COUT2 R3 GND VFB1 R1 R2 COUT1 3547 F02 BOLD LINES INDICATE HIGH CURRENT PATHS Figure 2. LTC3547 Layout Diagram (See Board Layout Checklist) R1 VIA TO GND VFB1 R3 VFB2 R2 R4 CF2 CF2 VIA TO GND VIA TO VOUT1 VIA TO VOUT2 VIA TO VIN VIN SW1 L1 SW2 L2 CIN GND COUT2 VOUT2 COUT1 3547 F03 VOUT1 Figure 3. LTC3547 Suggested Layout 3547fa 13 LTC3547 U U W U APPLICATIO S I FOR ATIO Design Example The feedback resistors program the output voltage. To maintain high efficiency at light loads, the current in these resistors should be kept small. Choosing 2µA with the 0.6V feedback voltage makes R1~300k. A close standard 1% resistor is 280k. Using Equation 4: As a design example, consider using the LTC3547 in a portable application with a Li-Ion battery. The battery provides a VIN ranging from 2.8V to 4.2V. The load on each channel requires a maximum of 300mA in active mode and 2mA in standby mode. The output voltages are VOUT1 = 2.5V and VOUT2 = 1.8V. ⎛V ⎞ R2 = ⎜ OUT − 1⎟ • R1 = 887k ⎝ 0.6 ⎠ Start with channel 1. First, calculate the inductor value for about 40% ripple current (120mA in this example) at maximum VIN. Using a derivation of Equation 1: 2 . 5V ⎛ 2 . 5V ⎞ L1 = • ⎜ 1− = 3 . 7 5µH 2 . 25MHz • (120mA) ⎝ 4 . 2V ⎟⎠ An optional 10pF feedback capacity (CF1) may be used to improve transient response. Using the same analysis for channel 2 (VOUT2 = 1.8V), the results are: L2 = 3.81µH R3 = 280k R4 = 560k For the inductor, use the closest standard value of 4.7µH. A 4.7µF capacitor should be more than sufficient for this output capacitor. As for the input capacitor, a typical value of CIN = 4.7µF should suffice, as the source impedance of a Li-Ion battery is very low. VIN 2.5V TO 5.5V C1 4.7µF RUN2 VIN RUN1 L2 4.7µH VOUT2 1.8V AT 300mA Figure 4 shows the complete schematic for this example, along with the efficiency curve and transient response. L1 4.7µH LTC3547 SW2 SW1 CF2, 10pF CF1, 10pF VFB2 COUT2 4.7µF R4 562k R3 280k GND VOUT1 2.5V AT 300mA VFB1 R1 280k R2 887k COUT1 4.7µF 3547 F04a C1, C2, C3: TAIYO YUDEN JMK316BJ475ML L1, L2: MURATA LQH32CN4R7M33 Figure 4a. Design Example Circuit 100 100 VOUT = 1.8V 90 80 80 70 70 EFFICIENCY (%) EFFICIENCY (%) 90 60 50 40 60 50 40 30 30 20 20 10 0 0.1 VIN = 2.7V VIN = 3.6V VIN = 4.2V 1 10 100 OUTPUT CURRENT (mA) 1000 VOUT = 2.5V VIN = 2.7V VIN = 3.6V VIN = 4.2V 10 0 0.1 1 10 100 OUTPUT CURRENT (mA) 1000 3547 F04b Figure 4b. Efficiency vs Output Current 3547fa 14 LTC3547 U U W U APPLICATIO S I FOR ATIO VOUT, AC COUPLED 100mV/DIV VOUT, AC COUPLED 100mV/DIV IL 200mA/DIV IL 200mA/DIV ILOAD 200mA/DIV ILOAD 200mA/DIV 3547 F04c 10µs/DIV 10µs/DIV VIN = 3.6V VOUT = 1.8V ILOAD = 20mA TO 300mA VIN = 3.6V VOUT = 2.5V ILOAD = 20mA TO 300mA Figure 4c. Transient Response U PACKAGE DESCRIPTIO DDB Package 8-Lead Plastic DFN (3mm × 2mm) (Reference LTC DWG # 05-08-1702 Rev B) 0.61 ±0.05 (2 SIDES) 3.00 ±0.10 (2 SIDES) R = 0.115 TYP 5 R = 0.05 TYP 0.40 ± 0.10 8 0.70 ±0.05 2.55 ±0.05 1.15 ±0.05 PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 2.20 ±0.05 (2 SIDES) PIN 1 BAR TOP MARK (SEE NOTE 6) 0.200 REF 2.00 ±0.10 (2 SIDES) 0.56 ± 0.05 (2 SIDES) 0.75 ±0.05 0 – 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 4 0.25 ± 0.05 1 PIN 1 R = 0.20 OR 0.25 × 45° CHAMFER (DDB8) DFN 0905 REV B 0.50 BSC 2.15 ±0.05 (2 SIDES) BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 3547fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LTC3547 U TYPICAL APPLICATIO Dual 300mA Buck Converter VIN 2.5V TO 5.5V C1 4.7µF RUN2 VIN RUN1 L2 4.7µH VOUT2 1.8V AT 300mA L1 4.7µH LTC3547 SW2 CF2, 10pF CF1, 10pF VFB2 COUT2 4.7µF VOUT1 2.5V AT 300mA SW1 R4 562k R3 280k GND VFB1 R1 280k R2 887k COUT1 4.7µF 3547 TA02 C1, C2, C3: TAIYO YUDEN JMK316BJ475ML L1, L2: MURATA LQH32CN4R7M33 1.8V/1.2V Dual 300mA Buck Converter VIN 2.5V TO 5.5V C1 4.7µF L2 4.7µH VOUT2 1.2V AT 300mA RUN2 VIN RUN1 SW2 L1 4.7µH SW1 VOUT1 1.8V AT 300mA LTC3547-1 COUT2 4.7µF VFB2 GND VFB1 COUT1 4.7µF 3547 TA03 C1, COUT1, COUT2: TAIYO YUDEN JMK316BJ475ML L1, L2: MURATA LQH32CN4R7M33 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC3405/LTC3405A 300mA (IOUT), 1.5MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN : 2.5V to 5.5V, VOUT = 0.8V, IQ = 20µA, ISD <1µA, ThinSOT TM Package LTC3406/LTC3406B 600mA (IOUT), 1.5MHz, Synchronous Step-Down DC/DC Converter 96% Efficiency, VIN : 2.5V to 5.5V, VOUT = 0.6V, IQ = 20µA, ISD <1µA, ThinSOT Package LTC3407/LTC3407-2 Dual 600mA/800mA (IOUT), 1.5MHz/2.25MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN : 2.5V to 5.5V, VOUT = 0.6V, IQ = 40µA, ISD <1µA, MS10E, DFN Packages LTC3409 600mA (IOUT), 1.7MHz/2.6MHz, Synchronous Step-Down DC/DC Converter 96% Efficiency, VIN : 1.6V to 5.5V, VOUT = 0.6V, IQ = 65µA, ISD <1µA, DFN Package LTC3410/LTC3410B 300mA (IOUT), 2.25MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN : 2.5V to 5.5V, VOUT = 0.8V, IQ = 26µA, ISD <1µA, SC70 Package LTC3411 1.25A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN : 2.5V to 5.5V, VOUT = 0.8V, IQ = 60µA, ISD <1µA, MS10, DFN Packages LTC3531/LTC3531-3/ LTC3531-3.3 200mA (IOUT), 1.5MHz, Synchronous Buck-Boost DC/DC Converter 95% Efficiency, VIN : 1.8V to 5.5V, VOUT: 2V to 5V, IQ = 16µA, ISD <1µA, ThinSOT, DFN Packages LTC3532 500mA (IOUT), 2MHz, Synchronous Buck-Boost DC/DC Converter 95% Efficiency, VIN : 2.4V to 5.5V, VOUT: 2.4V to 5.25V, IQ = 35µA, ISD <1µA, MS10, DFN Packages LTC3548/LTC3548-1/ LTC3548-2 Dual 400mA and 800mA (IOUT), 2.25MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN : 2.5V to 5.5V, VOUT = 0.6V, IQ = 40µA, ISD <1µA, MS10E, DFN Packages ThinSOT is a trademark of Linear Technology Corporation 3547fa 16 Linear Technology Corporation LT 0906 REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2006