ETC FM25L256-G 256kb fram serial 3v memory Datasheet

Pre-Production
FM25L256
256Kb FRAM Serial 3V Memory
Features
256K bit Ferroelectric Nonvolatile RAM
• Organized as 32,768 x 8 bits
• Unlimited Read/Write Cycles
• 10 Year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
Write Protection Scheme
• Hardware Protection
• Software Protection
Low Power Consumption
• Low Voltage Operation 2.7V – 3.6V
• 1 µA (typ) Standby Current
Very Fast Serial Peripheral Interface - SPI
• Up to 25 MHz Frequency
• Direct Hardware Replacement for EEPROM
• SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1)
Industry Standard Configurations
• Industrial Temperature -40°C to +85°C
• 8-pin SOIC and 8-pin DFN Packages
• “Green” Packaging Options
Description
Pin Configuration
The FM25L256 is a 256-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or FRAM is
nonvolatile and performs reads and writes like a
RAM. It provides reliable data retention for 10 years
while eliminating the complexities, overhead, and
system level reliability problems caused by
EEPROM and other nonvolatile memories.
CS
SO
WP
1
8
2
7
3
6
VSS
4
5
Unlike serial EEPROMs, the FM25L256 performs
write operations at bus speed. No write delays are
incurred. The next bus cycle may commence
immediately without the need for data polling. The
next bus cycle may start immediately. In addition, the
product offers virtually unlimited write endurance.
Also, FRAM exhibits much lower power
consumption than EEPROM.
These capabilities make the FM25L256 ideal for
nonvolatile memory applications requiring frequent
or rapid writes or low power operation. Examples
range from data collection, where the number of
write cycles may be critical, to demanding industrial
controls where the long write time of EEPROM can
cause data loss.
The FM25L256 provides substantial benefits to users
of serial EEPROM as a hardware drop-in
replacement. The FM25L256 uses the high-speed SPI
bus, which enhances the high-speed write capability
of FRAM technology. Device specifications are
guaranteed over an industrial temperature range of
-40°C to +85°C.
This is a product in the pre-production phase of development. Device
characterization is complete and Ramtron does not expect to change the
specifications. Ramtron will issue a Product Change Notice if any
specification changes are made.
Rev. 2.0
Apr. 2005
/CS
SO
/WP
VSS
1
8
2
7
3
6
4
5
VDD
HOLD
SCK
SI
VDD
/HOLD
SCK
SI
Top View
Pin Name
/CS
/WP
/HOLD
SCK
SI
SO
VDD
VSS
Function
Chip Select
Write Protect
Hold
Serial Clock
Serial Data Input
Serial Data Output
Supply Voltage (2.7 to 3.6V)
Ground
Ordering Information
FM25L256-S
FM25L256-G
FM25L256-DG
8-pin SOIC
“Green” 8-pin SOIC
“Green” 8-pin DFN
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
www.ramtron.com
Page 1 of 14
FM25L256
WP
Instruction Decode
Clock Generator
Control Logic
Write Protect
CS
HOLD
SCK
8192 x 32
FRAM Array
Instruction Register
Address Register
Counter
15
SI
8
Data I/O Register
SO
3
Nonvolatile Status
Register
Figure 1. Block Diagram
Pin Descriptions
Pin Name
/CS
I/O
Input
SCK
Input
/HOLD
Input
/WP
Input
SI
Input
SO
Output
VDD
VSS
Supply
Supply
Rev. 2.0
Apr. 2005
Description
Chip Select: This active low input activates the device. When high, the device enters
low-power standby mode, ignores other inputs, and all outputs are tri-stated. When
low, the device internally activates the SCK signal. A falling edge on /CS must occur
prior to every op-code.
Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on
the rising edge and outputs occur on the falling edge. Since the device is static, the
clock frequency may be any value between 0 and 25 MHz and may be interrupted at
any time.
Hold: The /HOLD pin is used when the host CPU must interrupt a memory operation
for another task. When /HOLD is low, the current operation is suspended. The device
ignores any transition on SCK or /CS. All transitions on /HOLD must occur while
SCK is low.
Write Protect: This active low pin prevents write operations to the status register only.
A complete explanation of write protection is provided on pages 6 and 7.
Serial Input: All data is input to the device on this pin. The pin is sampled on the
rising edge of SCK and is ignored at other times. It should always be driven to a valid
logic level to meet IDD specifications.
* SI may be connected to SO for a single pin data interface.
Serial Output: This is the data output pin. It is driven during a read and remains tristated at all other times including when /HOLD is low. Data transitions are driven on
the falling edge of the serial clock.
* SO may be connected to SI for a single pin data interface.
Power Supply (2.7V to 3.6V)
Ground
Page 2 of 14
FM25L256
Overview
The FM25L256 is a serial FRAM memory. The
memory array is logically organized as 32,768 x 8
and is accessed using an industry standard Serial
Peripheral Interface or SPI bus. Functional operation
of the FRAM is similar to serial EEPROMs. The
major difference between the FM25L256 and a serial
EEPROM with the same pinout is the FRAM’s
superior write performance and power consumption.
Memory Architecture
When accessing the FM25L256, the user addresses
32K locations of 8 data bits each. These data bits are
shifted serially. The addresses are accessed using the
SPI protocol, which includes a chip select (to permit
multiple devices on the bus), an op-code, and a twobyte address. The upper bit of the address range is a
“don’t care” value. The complete address of 15-bits
specifies each byte address uniquely.
Most functions of the FM25L256 either are
controlled by the SPI interface or are handled
automatically by on-board circuitry. The access time
for memory operation is essentially zero, beyond the
time needed for the serial protocol. That is, the
memory is read or written at the speed of the SPI bus.
Unlike an EEPROM, it is not necessary to poll the
device for a ready condition since writes occur at bus
speed. So, by the time a new bus transaction can be
shifted into the device, a write operation will be
complete. This is explained in more detail in the
interface section.
Users expect several obvious system benefits from
the FM25L256 due to its fast write cycle and high
endurance as compared to EEPROM. In addition
there are less obvious benefits as well. For example
in a high noise environment, the fast-write operation
is less susceptible to corruption than an EEPROM
since it is completed quickly. By contrast, an
EEPROM requiring milliseconds to write is
vulnerable to noise during much of the cycle.
Note that the FM25L256 contains no power
management circuits other than a simple internal
power-on reset circuit. It is the user’s
responsibility to ensure that VDD is within
datasheet tolerances to prevent incorrect
operation. It is recommended that the part is not
powered down with chip enable active.
Serial Peripheral Interface – SPI Bus
microcontroller. Many common microcontrollers
have hardware SPI ports allowing a direct interface.
It is quite simple to emulate the port using ordinary
port pins for microcontrollers that do not. The
FM25L256 operates in SPI Mode 0 and 3.
The SPI interface uses a total of four pins: clock,
data-in, data-out, and chip select. A typical system
configuration uses one or more FM25L256 devices
with a microcontroller that has a dedicated SPI port,
as Figure 2 illustrates. Note that the clock, data-in,
and data-out pins are common among all devices.
The Chip Select and Hold pins must be driven
separately for each FM25L256 device.
For a microcontroller that has no dedicated SPI bus, a
general purpose port may be used. To reduce
hardware resources on the controller, it is possible to
connect the two data pins together and tie off the
Hold pin. Figure 3 shows a configuration that uses
only three pins.
Protocol Overview
The SPI interface is a synchronous serial interface
using clock and data pins. It is intended to support
multiple devices on the bus. Each device is activated
using a chip select. Once chip select is activated by
the bus master, the FM25L256 will begin monitoring
the clock and data lines. The relationship between the
falling edge of /CS, the clock and data is dictated by
the SPI mode. The device will make a determination
of the SPI mode on the falling edge of each chip
select. While there are four such modes, the
FM25L256 supports only modes 0 and 3. Figure 4
shows the required signal relationships for modes 0
and 3. For both modes, data is clocked into the
FM25L256 on the rising edge of SCK and data is
expected on the first rising edge after /CS goes
active. If the clock starts from a high state, it will fall
prior to the first data transfer in order to create the
first rising edge.
The SPI protocol is controlled by op-codes. These
op-codes specify the commands to the device. After
/CS is activated the first byte transferred from the bus
master is the op-code. Following the op-code, any
addresses and data are then transferred. Note that the
WREN and WRDI op-codes are commands with no
subsequent data transfer.
Important: The /CS must go inactive after an
operation is complete and before a new op-code
can be issued. There is one valid op-code only per
active chip select.
The FM25L256 employs a Serial Peripheral Interface
(SPI) bus. It is specified to operate at speeds up to 25
MHz. This high-speed serial bus provides high
performance serial communication to a host
Rev. 2.0
Apr. 2005
Page 3 of 14
FM25L256
SCK
MOSI
MISO
SO
SPI
Microcontroller
SI
SCK
SO
SI
SCK
FM25L256
FM25L256
CS
CS
HOLD
HOLD
SS1
SS2
HOLD1
HOLD2
MOSI : Master Out Slave In
MISO : Master In Slave Out
SS : Slave Select
Figure 2. System Configuration with SPI port
P1.0
P1.1
SO
Microcontroller
SI
SCK
FM25 L256
CS
HOLD
P1.2
Figure 3. System Configuration without SPI port
SPI Mode 0: CPOL=0, CPHA=0
7
6
5
4
3
2
1
0
SPI Mode 3: CPOL=1, CPHA=1
7
6
5
4
3
2
1
0
Figure 4. SPI Modes 0 & 3
Rev. 2.0
Apr. 2005
Page 4 of 14
FM25L256
Power Up to First Access
The FM25L256 is not accessible for a period of time
(10 ms) after power up. Users must comply with the
timing parameter tPU, which is the minimum time
from VDD (min) to the first /CS low.
WREN - Set Write Enable Latch
The FM25L256 will power up with writes disabled.
The WREN command must be issued prior to any
write operation. Sending the WREN op-code will
allow the user to issue subsequent op-codes for
write operations. These include writing the status
register and writing the memory.
Data Transfer
All data transfers to and from the FM25L256 occur in
8-bit groups. They are synchronized to the clock
signal (SCK), and they transfer most significant bit
(MSB) first. Serial inputs are registered on the rising
edge of SCK. Outputs are driven from the falling
edge of SCK.
Sending the WREN op-code causes the internal
Write Enable Latch to be set. A flag bit in the status
register, called WEL, indicates the state of the latch.
WEL=1 indicates that writes are permitted.
Attempting to write the WEL bit in the status
register has no effect on the state of this bit.
Completing any write operation will automatically
clear the write-enable latch and prevent further
writes without another WREN command. Figure 5
below illustrates the WREN command bus
configuration.
Command Structure
There are six commands called op-codes that can be
issued by the bus master to the FM25L256. They are
listed in the table below. These op-codes control the
functions performed by the memory. They can be
divided into three categories. First, there are
commands that have no subsequent operations. They
perform a single function such as to enable a write
operation. Second are commands followed by one
byte, either in or out. They operate on the status
register. The third group includes commands for
memory transactions followed by address and one or
more bytes of data.
Table 1. Op-code Commands
Name
Description
Set Write Enable Latch
WREN
Write Disable
WRDI
Read Status Register
RDSR
Write Status Register
WRSR
Read Memory Data
READ
WRITE Write Memory Data
WRDI - Write Disable
The WRDI command disables all write activity by
clearing the Write Enable Latch. The user can verify
that writes are disabled by reading the WEL bit in
the status register and verifying that WEL=0. Figure
6 illustrates the WRDI command bus configuration.
Op-code
0000
0000
0000
0000
0000
0000
0110b
0100b
0101b
0001b
0011b
0010b
CS
0
1
2
3
4
5
6
7
0
1
1
0
SCK
SI
SO
0
0
0
0
Hi-Z
Figure 5. WREN Bus Configuration
Rev. 2.0
Apr. 2005
Page 5 of 14
FM25L256
CS
0
1
2
3
4
5
6
7
0
1
0
0
SCK
SI
0
0
0
0
Hi-Z
SO
Figure 6. WRDI Bus Configuration
RDSR - Read Status Register
The RDSR command allows the bus master to verify
the contents of the Status register. Reading Status
provides information about the current state of the
write protection features. Following the RDSR opcode, the FM25L256 will return one byte with the
contents of the Status register. The Status register is
described in detail in a later section.
WRSR – Write Status Register
The WRSR command allows the user to select
certain write protection features by writing a byte to
the Status register. Prior to issuing a WRSR
command, the /WP pin must be high or inactive.
Prior to sending the WRSR command, the user must
send a WREN command to enable writes. Note that
executing a WRSR command is a write operation
and therefore clears the Write Enable Latch.
Figure 7. RDSR Bus Configuration
Figure 8. WRSR Bus Configuration
Status Register & Write Protection
The write protection features of the FM25L256 are
multi-tiered. Taking the /WP pin to a logic low state
is the hardware write protect function. All write
operations are blocked when /WP is low. To write the
memory with /WP high, a WREN op-code must first
be issued. Assuming that writes are enabled using
WREN and by /WP, writes to memory are controlled
by the Status register. As described above, writes to
the status register are performed using the WRSR
command and subject to the /WP pin. The Status
register is organized as follows.
Rev. 2.0
Apr. 2005
Table 2. Status Register
Bit
Name
7
6
5
4
3
2
1
0
WPEN
0
0
0
BP1
BP0
WEL
0
Bits 0 and 4-6 are fixed at 0 and cannot be modified.
Note that bit 0 (Ready in EEPROMs) is unnecessary
as the FRAM writes in real-time and is never busy.
The BP1 and BP0 control software write protection
features. They are nonvolatile (shaded yellow). The
WEL flag indicates the state of the Write Enable
Latch. Attempting to directly write the WEL bit in
the status register has no effect on its state. This bit
Page 6 of 14
FM25L256
is internally set and cleared via the WREN and
WRDI commands, respectively.
BP1 and BP0 are memory block write protection bits.
They specify portions of memory that are write
protected as shown in the following table.
Table 3. Block Memory Write Protection
BP1
BP0 Protected Address Range
0
0
None
0
1
6000h to 7FFFh (upper ¼)
1
0
4000h to 7FFFh (upper ½)
1
1
0000h to 7FFFh (all)
The BP1 and BP0 bits and the Write Enable Latch
are the only mechanisms that protect the memory
from writes. The remaining write protection features
protect inadvertent changes to the block protect bits.
Table 4. Write Protection
WEL
WPEN
/WP
0
X
X
1
0
X
1
1
0
1
1
1
Protected Blocks
Protected
Protected
Protected
Protected
Memory Operation
The SPI interface, which is capable of a relatively
high clock frequency, highlights the fast write
capability of the FRAM technology. Unlike SPI-bus
EEPROMs, the FM25L256 can perform sequential
writes at bus speed. No page register is needed and
any number of sequential writes may be performed.
Write Operation
All writes to the memory array begin with a WREN
op-code. The next op-code is the WRITE instruction.
This op-code is followed by a two-byte address
value. The upper bit of the address is a “don’t care”.
In total, 15-bits specify the address of the first data
byte of the write operation. Subsequent bytes are data
and they are written sequentially. Addresses are
incremented internally as long as the bus master
continues to issue clocks. If the last address of 7FFFh
is reached, the counter will roll over to 0000h. Data is
written MSB first. A write operation is shown in
Figure 9.
Unlike EEPROMs, any number of bytes can be
written sequentially and each byte is written to
memory immediately after it is clocked in (after the
8th clock). The rising edge of /CS terminates a
WRITE op-code operation. Asserting /WP active in
Rev. 2.0
Apr. 2005
The WPEN bit controls the effect of the hardware
/WP pin. When WPEN is low, the /WP pin is
ignored. When WPEN is high, the /WP pin controls
write access to the status register. Thus the Status
register is write protected if WPEN=1 and /WP=0.
This scheme provides a write protection mechanism,
which can prevent software from writing the
memory under any circumstances. This occurs if the
BP1 and BP0 are set to 1, the WPEN bit is set to 1,
and /WP is set to 0. This occurs because the block
protect bits prevent writing memory and the /WP
signal in hardware prevents altering the block
protect bits (if WPEN is high). Therefore in this
condition, hardware must be involved in allowing a
write operation. The following table summarizes the
write protection conditions.
Unprotected Blocks
Protected
Unprotected
Unprotected
Unprotected
Status Register
Protected
Unprotected
Protected
Unprotected
the middle of a write operation will have no affect
until the next falling edge of /CS.
Read Operation
After the falling edge of /CS, the bus master can issue
a READ op-code. Following this instruction is a twobyte address value. The upper bit of the address is a
don’t care. In total, 15-bits specify the address of the
first byte of the read operation. After the op-code and
address are complete, the SI line is ignored. The bus
master issues 8 clocks, with one bit read out for each.
Addresses are incremented internally as long as the
bus master continues to issue clocks. If the last
address of 7FFFh is reached, the counter will roll
over to 0000h. Data is read MSB first. The rising
edge of /CS terminates a READ op-code operation.
A read operation is shown in Figure 10.
Hold
The /HOLD pin can be used to interrupt a serial
operation without aborting it. If the bus master pulls
the /HOLD pin low while SCK is low, the current
operation will pause. Taking the /HOLD pin high
while SCK is low will resume an operation. The
transitions of /HOLD must occur while SCK is low,
but the SCK and /CS pins can toggle during a hold
state.
Page 7 of 14
FM25L256
CS
0
1
2
3
4
5
6
7
0
1
2
14
13
3
4
6
7
0
1
2
6
5
3
4
5
6
3
2
1
7
7
SCK
SI
0
0
0
Op-code
0
16-bit Address
1
0
0
0
X
11
Data In
1
MSB
Hi-Z
SO
12
0
LSB
7
4
MSB
0
0
LSB
Figure 9. Memory Write
CS
0
1
2
3
4
5
6
7
0
1
2
14
13
3
4
6
7
0
1
2
3
4
5
6
6
5
Data Out
4
3
2
1
7
7
SCK
SI
0
SO
0
0
Op-code
0
Hi-Z
16-bit Address
0
0
1
1
X
MSB
12
11
1
0
LSB
7
MSB
0
0
LSB
Figure 10. Memory Read
Rev. 2.0
Apr. 2005
Page 8 of 14
FM25L256
Electrical Specifications
Absolute Maximum Ratings
Symbol
Description
VDD
Power Supply Voltage with respect to VSS
VIN
Voltage on any pin with respect to VSS
TSTG
TLEAD
VESD
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Electrostatic Discharge Voltage
- Human Body Model (JEDEC Std JESD22-A114-B)
- Charged Device Model (JEDEC Std JESD22-C101-A)
- Machine Model (JEDEC Std JESD22-A115-A)
Package Moisture Sensitivity Level
Ratings
-1.0V to +5.0V
-1.0V to +5.0V
and VIN < VDD+1.0V
-55°C to + 125°C
300° C
3kV
1kV
100V
MSL-1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress
rating only, and the functional operation of the device at these or any other conditions above those listed in the operational
section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may
affect device reliability.
DC Operating Conditions (TA = -40°C to + 85°C, VDD = 2.7V to 3.6V unless otherwise specified)
Symbol
Parameter
Min
Typ
Max
Units
VDD
Power Supply Voltage
2.7
3.6
V
IDD
Power Supply Current
@ SCK = 1.0 MHz
0.25
mA
@ SCK = 5.0 MHz
1.2
@ SCK = 25.0 MHz
6.0
ISB
Standby Current
1
@ TA = 25°C
µA
2
@ TA = 55°C
µA
5
@ TA = 70°C
µA
10
@ TA = 85°C
µA
ILI
Input Leakage Current
µA
±1
ILO
Output Leakage Current
µA
±1
VIH
Input High Voltage
0.7 VDD
VDD + 0.5
V
VIL
Input Low Voltage
-0.3
0.3 VDD
V
VOH
Output High Voltage
V
VDD – 0.8
@ IOH = -2 mA
VOL
Output Low Voltage
0.4
V
@ IOL = 2 mA
VHYS
Input Hysteresis
0.05 VDD
V
Notes
1. SCK toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V.
2. SCK = SI = /CS=VDD. All inputs VSS or VDD.
3. VSS ≤ VIN ≤ VDD and VSS ≤ VOUT ≤ VDD.
4. This parameter is characterized but not 100% tested.
Rev. 2.0
Apr. 2005
Notes
1
2
3
3
4
Page 9 of 14
FM25L256
AC Parameters (CL = 30pF)
VDD 2.7 to 3.6V
VDD 3.0 to 3.6V
(-40°C to +85°C)
Symbol
fCK
tCH
tCL
tCSU
tCSH
tOD
tODV
tOH
tD
tR
tF
tSU
tH
tHS
tHH
tHZ
tLZ
Notes
1.
2.
3.
Parameter
SCK Clock Frequency
Clock High Time
Clock Low Time
Chip Select Setup
Chip Select Hold
Output Disable Time
Output Data Valid Time
Output Hold Time
Deselect Time
Data In Rise Time
Data In Fall Time
Data Setup Time
Data Hold Time
/Hold Setup Time
/Hold Hold Time
/Hold Low to Hi-Z
/Hold High to Data Active
Min
0
22
22
10
10
(0°C to +70°C)
Max
20
Min
0
18
18
10
10
20
22
Max
25
15
15
0
60
0
60
50
50
50
50
5
5
10
10
5
5
10
10
20
20
20
15
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1
1
2
1,3
1,3
2
2
tCH + tCL = 1/fCK.
This parameter is characterized but not 100% tested.
Rise and fall times measured between 10% and 90% of waveform.
Power Cycle Timing (TA = -40° C to + 85° C, VDD = 2.7V to 3.6V)
Symbol
Parameter
tPU
Power Up (VDD min) to First Access (/CS low)
tPD
Last Access (/CS high) to Power Down (VDD min)
tVR
VDD Rise Time
tVF
VDD Fall Time
Capacitance (TA = 25° C, f=1.0 MHz, VDD = 3.3V)
Symbol
Parameter
CO
Output capacitance (SO)
CI
Input capacitance
Notes
1. This parameter is characterized and not 100% tested.
2. Slope measured at any point on VDD waveform.
AC Test Conditions
Input Pulse Levels
Input rise and fall times
Input and output timing levels
Output Load Capacitance
Rev. 2.0
Apr. 2005
Min
10
0
50
100
Min
-
Max
-
Max
8
6
Units
ms
µs
µs/V
µs/V
Notes
Units
pF
pF
Notes
1
1
1,2
1,2
10% and 90% of VDD
5 ns
0.5 VDD
30 pF
Page 10 of 14
FM25L256
Serial Data Bus Timing
tD
CS
tCSU
SCK
tSU
tF
1/tCK
tCL
tR
tCSH
tCH
tH
SI
tOH
tODV
tOD
SO
/Hold Timing
tHS
CS
tHH
SCK
tHH
tHS
HOLD
SO
tHZ
tLZ
Power Cycle Timing
Data Retention (VDD = 2.7V to 3.6V)
Parameter
Data Retention
Rev. 2.0
Apr. 2005
Min
10
Max
-
Units
Years
Notes
Page 11 of 14
FM25L256
Mechanical Drawing
8-pin SOIC (JEDEC MS-012 variation AA)
Recommended PCB Footprint
7.70
3.90 ±0.10
3.70
6.00 ±0.20
2.00
Pin 1
0.65
1.27
4.90 ±0.10
1.27
0.33
0.51
0.25
0.50
1.35
1.75
0.10
0.25
0.10 mm
0°- 8°
0.19
0.25
45 °
0.40
1.27
Refer to JEDEC MS-012 for complete dimensions and notes.
All dimensions in millimeters.
SOIC Package Marking Scheme
XXXXXXX-P
LLLLLLL
RICYYWW
Legend:
XXXX= part number, P= package type
LLLLLLL= lot code
RIC=Ramtron Int’l Corp, YY=year, WW=work week
Example: FM25L256, Standard SOIC package, Year 2004, Work Week 39
FM25L256-S
A40003S
RIC0439
Rev. 2.0
Apr. 2005
Page 12 of 14
FM25L256
8-pin DFN (4.0mm x 4.5mm body, 0.65mm pitch)
4.00 ±0.1
4.50 ±0.1
3.60 ±0.10
2.60 ±0.10
Exposed metal pad.
Do not connect to
anything except Vss.
Pin 1 ID
Pin 1
2.85 REF
0.0 - 0.05
0.75 ±0.05
0.20 REF.
0.95
0.40 ±0.05
Note: All dimensions in millimeters.
DFN Package Marking Scheme for Body Size 4.0mm x 4.5mm
RICG
XXXX
LLLL
YYWW
Legend:
RIC=Ramtron Int’l Corp, G=”green” DFN package
XXXX=base part number
LLLL= lot code
YY=year, WW=work week
Example: “Green” DFN package, FM25L256, Lot 0003, Year 2004, Work Week 39
RICG
5L25
0003
0439
Rev. 2.0
Apr. 2005
Page 13 of 14
FM25L256
Revision History
Revision
0.1
0.11
0.12
Date
9/9/03
12/9/03
1/7/04
0.13
5/5/04
1.0
8/12/04
1.1
9/21/04
1.2
3/9/05
2.0
4/5/05
Rev. 2.0
Apr. 2005
Summary
Initial release.
Reduced IDD spec limits.
Added tVR and tVF specs, “green” package, and modified Power Cycling
diagram.
Changed tOD, tODV , and tLZ timing specs. Changed ISB spec limit. Changed tVR
and tVF conditions. Changed voltage/temperature conditions in AC Parameters
table.
Added DFN mechanical package drawing and ordering information. Added
ISB limits at various temperatures. Changed AC timing reference to 0.5 VDD.
Changed tODV spec. New rev. number to comply with new scheme.
Changed IDD limits. Added Power Down timing parameter and changed
diagram.
Removed “preliminary” from DFN package drawing. Added note about
powering down with /CS active (pg 3). Added ESD and package MSL
ratings.
Changed to Pre-Production status.
Page 14 of 14