CML CMX972 Small 32-lead vqfn package Datasheet

CMX972
CML Microcircuits
Quadrature Demodulator
with IF PLL/VCO
COMMUNICATION SEMICONDUCTORS
D/972/2 February 2015
Provisional Issue
Features
Applications











20 – 300MHz IF/RF Demodulator
10MHz Rx I/Q Bandwidth
< 1 degree I/Q Phase Matching
< 0.5 dB I/Q Gain Matching
Low Power, 3.0V – 3.6V Operation
Small 32-lead VQFN Package
n/c
RXLO
VCO
P2
VCO
P1
Wireless Data Terminals
HF/VHF and UHF Mobile Radio
Avionics Radio Systems
Software Defined Radio (SDR)
Satellite Terminals
VCO
N1
VCO
N2
OA1O
OA1N
n/c
OA1P
VCO
40-1000MHz
n/c
VSS
n/c
CSN
n/c
OA2O
Local oscillator
switching
IFIN
OA2N
VCC
OA2P
Quadrature
demodulator
RXIN
PLL
RXIP
RXQP
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RXQN
n/c
REFIN
DO
Serial bus
and
control
VCC
CDATA
SYNTH
VDD
RDATA
SCLK
Quadrature Demodulator with IF PLL/VCO
1
CMX972
Brief Description
The CMX972 features a low-power quadrature IF/RF demodulator with wide operating frequency range
and optimised power consumption. The demodulator is suitable for superheterodyne architectures with IF
frequencies up to 300MHz and the device may be used in low IF systems or in those converting down to
baseband. An on-chip PLL and VCO, together with uncommitted baseband differential amplifiers, provide
additional flexibility. Control of the CMX972 is by serial bus. The CMX972 is supplied in an RF-optimised
32-lead VQFN package.
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CMX972
CONTENTS
Section
1
1.1
Page
Brief Description .................................................................................................. 2
History .............................................................................................................. 5
2
Block Diagram ...................................................................................................... 6
3
Pin List .................................................................................................................. 7
4
4.1
4.2
4.3
4.4
4.5
5
External Components .......................................................................................... 8
Power Supply Decoupling ................................................................................ 8
Quadrature Demodulator ................................................................................. 9
Local Oscillator (LO) Input ............................................................................... 9
VCO and PLL ................................................................................................... 9
Differential Amplifiers ..................................................................................... 12
4.5.1 I/Q Output Amplifiers ............................................................................... 12
4.5.2 Low IF Output .......................................................................................... 13
General Description ........................................................................................... 14
Quadrature Demodulator ............................................................................... 14
5.1.1 I/Q Amplitude and Phase Correction ....................................................... 14
5.1.2 DC Offset Correction ............................................................................... 16
5.2
Differential Amplifiers ..................................................................................... 17
5.3
Local Oscillator (LO) ...................................................................................... 17
5.3.1 Demodulator LO Input ............................................................................. 17
5.3.2 VCO and PLL .......................................................................................... 17
5.1
6
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
7
7.1
C-BUS Interface and Register Description ...................................................... 20
General Reset Command .............................................................................. 21
6.1.1 General Reset Command - $1A: no data ................................................ 21
General Control Register ............................................................................... 22
6.2.1 General Control Register - $1B: 8-bit write ............................................. 22
6.2.2 General Control Register - $EB: 8-bit read ............................................. 22
Rx Control Register ....................................................................................... 22
6.3.1 Rx Control Register - $1C: 8-bit write...................................................... 22
6.3.2 Rx Control Register - $EC: 8-bit read ..................................................... 23
Rx Mode Register .......................................................................................... 23
6.4.1 Rx Mode Register - $1D: 8-bit write ........................................................ 23
6.4.2 Rx Mode Register - $ED: 8-bit read ........................................................ 24
Rx Offset Register ......................................................................................... 24
6.5.1 Rx Offset Register - $1F: 8-bit write ........................................................ 24
6.5.2 Rx Offset Register - $EF: 8-bit read ........................................................ 25
PLL M Divider Register .................................................................................. 25
6.6.1 PLL M Divider - $2C - $2A: 8-bit write ..................................................... 25
6.6.2 PLL M Divider - $DC - $DA: 8-bit read .................................................... 26
PLL R Divider Register .................................................................................. 26
6.7.1 PLL R Divider - $2E - $2D: 8-bit write ..................................................... 26
6.7.2 PLL R Divider - $DE - $DD: 8-bit read .................................................... 26
VCO Control Register .................................................................................... 26
6.8.1 VCO Control Register - $2F: 8-bit write................................................... 26
6.8.2 VCO Control Register - $DF: 8-bit read .................................................. 27
Application Notes ............................................................................................... 28
IF/RF Input Matching ..................................................................................... 28
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7.2
7.3
7.4
7.5
7.6
7.7
8
CMX972
Demodulator Intermodulation and Output Drive Capability ........................... 29
Variation with Temperature............................................................................ 29
Effect of Gain Control on Receiver Performance .......................................... 30
Measurement of CMX972 Demodulator Intermodulation Performance ........ 32
Operation with large input signals .................................................................. 33
VCO Phase Noise .......................................................................................... 34
Performance Specification ................................................................................ 35
Electrical Performance................................................................................... 35
8.1.1 Absolute Maximum Ratings .................................................................... 35
8.1.2 Operating Limits ...................................................................................... 35
8.1.3 Operating Characteristics ........................................................................ 36
8.2
Packaging ...................................................................................................... 41
8.1
Section
Page
Table 1 Pin List ................................................................................................................... 7
Table 2 Power Supply Component Values ......................................................................... 8
Table 3 Quadrature Demodulator Input Components ........................................................ 9
Table 4 Internal VCO Amplifier Tank Circuit for 180MHz Operation ................................ 11
rd
Table 5 3 Order Loop Filter Circuit for 180MHz Operation ............................................ 11
Table 6 Rx I/Q Differential to Single-ended Amplifier Components ................................. 12
Table 7 Rx Low IF (455kHz) Components ....................................................................... 13
Table 8 Typical Phase Balance, LO/2 Mode .................................................................... 15
Table 9 Recommended FREQ bit Settings in the Rx Mode Register .............................. 15
Table 10 Effect of FREQ bits ($1D, b3-b0) on I/Q Phase Balance at 250MHz ................ 16
Table 11 Effect of FREQ bits ($1D, b3-b0) on I/Q Phase Balance at 300MHz with Temperature
.......................................................................................................................................... 16
Table 12 DC Offset Correction Adjustments .................................................................... 16
Table 13 LO Connections................................................................................................. 17
Table 14 PLL Control ....................................................................................................... 19
Table 15 Quadrature Demodulator Input Impedances and Parallel Equivalent Circuit .... 28
Table 16 Typical Noise Figure and Gain of IF Amp, VGA and I/Q Mixer ......................... 29
Table 17 Typical Third Order Intercept Performance of demodulator at 45MHz (straight-in case)
.......................................................................................................................................... 29
Table 18 Effect of VCONR bits, fvco = 180 MHz, divide-by-2 ........................................... 34
Section
Page
Figure 1 Block Diagram ...................................................................................................... 6
Figure 2 Power Supply Connections and Decoupling ........................................................ 8
Figure 3 IF Input Match Circuit ........................................................................................... 9
Figure 4 RXLO Input Configuration .................................................................................... 9
Figure 5 Example External Components – VCO External Tank Circuit ........................... 10
Figure 6 Example External Components – PLL Loop Filter ............................................. 11
Figure 7 Example External Components – Receive I/Q Output ....................................... 12
Figure 8 Example External Components – Receive Low IF Output ................................. 13
Figure 9 Demodulator Gain Control ................................................................................. 14
Figure 10 Frequency Response, showing effect of COR bit ($1C, b6) and FREQ bits($1D, b3-b0)
.......................................................................................................................................... 15
Figure 11 Simplified Schematic DC Offset Correction Circuit .......................................... 16
Figure 12 PLL Architecture ............................................................................................... 18
Figure 13 C-BUS Transactions ........................................................................................ 21
Figure 14 Quadrature Demodulator Input Impedance (10MHz to 300MHz) .................... 28
Figure 15 Demodulator Gain Variation With Temperature ............................................... 30
Figure 16 Variation in Gain with Temperature (COR = ‘0’ $1D = 0x00) .......................... 30
Figure 17 Variation in CMX972 Demodulator Noise Figure with VGA/VGB Control ........ 31
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Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
1.1
1
Variation in Input Third Order Intercept Point with VGA/VGB Control ............. 31
Variations in Signal and IMD Product Levels ................................................... 32
Output Signal Level Variations with Large Input Signals .................................. 33
Effect of VCO Gain on Phase Noise ................................................................ 34
C-BUS Timing .................................................................................................. 40
Q5 Mechanical Outline: Order as part no. CMX972Q5 ................................... 41
History
Version
2
CMX972
Changes

 Corrected VCO range to 40 – 1000MHz and changed varactor diode to
Toshiba 1SV305
 Original document, first approved.
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Date
17/2/15
7/12/12
D/972/2
Quadrature Demodulator with IF PLL/VCO
2
CMX972
Block Diagram
VDD
Control Logic
VCCSYNTH
REFIN
DO
Integer-N
PLL
VSS
VCON2
External
Resonator
and
Varactors
VCON1
VCOP1
RDATA
SCLK
CDATA
CSN
VCC
RFGND
VCO
VCOP2
OA1O
Divide by
2 or 4
RXLO
sin
OA1N
OA1P
DC
Offset
Adjust
IFIN
cos
DC
Offset
Adjust
RXIP
RXIN
OA2O
OA2N
OA2P
RXQP
RXQN
Figure 1 Block Diagram
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CMX972
Pin List
Pin
1
2
3
4
5
6
7
Name
~
~
~
~
IFIN
VCC
RXIN
Type
~
~
~
~
IP
PWR
OP
8
RXIP
OP
9
RXQP
OP
10
RXQN
OP
11
~
12
REFIN
13
DO
14
VCCSYNTH
15
CDATA
16
VDD
17
SCLK
18
RDATA
19
OA2P
20
OA2N
21
OA2O
22
CSN
23
VSS
24
OA1P
25
OA1N
26
OA1O
27
VCON2
28
VCON1
29
VCOP1
30
VCOP2
31
RXLO
32
~
33*
RFGND
Notes: IP
=
OP
=
TSOP =
PWR =
NR
=
~
IP
OP
PWR
IP
PWR
IP
TSOP
IP
IP
OP
IP
PWR
IP
IP
OP
NR
NR
NR
NR
IP
~
PWR
Function
Do not connect to this pin
Do not connect to this pin
Do not connect to this pin
Do not connect to this pin
IF/RF input signal
Analogue and RF supply
Analogue output for baseband receive I signal
(negative)
Analogue output for baseband receive I signal
(positive)
Analogue output for baseband receive Q signal
(positive)
Analogue output for baseband receive Q signal
(negative)
Do not connect to this pin
PLL frequency reference input
PLL charge pump output
RF supply for synthesiser
C-BUS data input
C-BUS and digital supply
C-BUS clock input
C-BUS data output
Baseband amplifier 2 positive input
Baseband amplifier 2 negative input
Baseband amplifier 2 output
C-BUS chip select
C-BUS and digital ground
Baseband amplifier 1 positive input
Baseband amplifier 1 negative input
Baseband amplifier 1 output
VCO negative port 2
VCO negative port 1
VCO positive port 1
VCO positive port 2
Input for demodulator local oscillator
Do not connect to this pin
Analogue and RF ground
Input
Output
Three-state output
Power connection
Negative resistance VCO port
* Pin 33 is the exposed metal pad on the back of the package and should be connected to the RF
Ground Plane (VRFGND).
Table 1 Pin List
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CMX972
4
External Components
4.1
Power Supply Decoupling
This device has separate supply pins for the analogue and digital circuitry; a 3.3V nominal supply is
recommended.
R3
VCCSYNTH
R2
VSUPPLY
VCC
R1
VDD
C2
C1
C3
VRFGND
Ground
VSS
Figure 2 Power Supply Connections and Decoupling
C1
C2
C3
10nF
10nF
10nF
R1
R2
R3
10
3.3
10
Resistors 1%, capacitors 20%
Table 2 Power Supply Component Values
Note:
It is expected that low-frequency interference on the 3.3V supply will be removed by active regulation. A
large capacitor is an alternative but may require more board space and so may not be preferred. The
supply decoupling shown is intended for RF noise suppression. It is necessary to have a small series
impedance prior to the decoupling capacitor for the decoupling to work well. This may be achieved cost
effectively by using the resistor as shown. The use of resistors results in small dc voltage drops. Choosing
resistor values approximately inversely proportional to the dc current requirements of each supply pin
ensures the dc voltage drop on each supply is reasonably matched. In any case, the dc voltage change
that results are well within the design tolerance of the device. If higher impedance resistors are used then
greater care will be needed to ensure that the supply voltages are maintained within tolerance, including
when parts of the device are enabled or disabled.
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4.2
CMX972
Quadrature Demodulator
The input impedance of the quadrature demodulator section is shown in section 7.1. The input can be
driven from a 50 Ohm source or can be matched to 50 Ohms. A typical 50 Ohm matching circuit is shown
in Figure 3 for operation at 45MHz.
CMX972
L1
IF Input
IFIN
C1
Figure 3 IF Input Match Circuit
L1
910nH
C1
10pF
Table 3 Quadrature Demodulator Input Components
4.3
Local Oscillator (LO) Input
The CMX972 has a single-ended LO input. The demodulator LO can come from either the on-chip
VCO/PLL or from an external source (RXLO pin), see section 5.3.
Users should be aware that the presence of high levels of harmonics in the signals applied to the RXLO
input might degrade quadrature accuracy.
CMX972
RXLO Input
Buffer and
Divider
Figure 4 RXLO Input Configuration
4.4
VCO and PLL
A typical configuration for using the internal VCO negative resistance amplifier at 180MHz is shown in
Figure 5. The other external components required to complete the PLL are the loop filter components, see
rd
Figure 6 – which shows a 3 order loop filter; typical values for a 300Hz bandwidth are given in Table 5.
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CMX972
VCOP1 should be connected to VCOP2 and similarly VCON1 to VCON2 in order to form the negative
resistance loop. It is recommended that the parallel LC tank (L1/C1) is situated as close to the package as
possible, with the inductor closest to the device pins. Also the shorting of VCOP1 to VCOP2 and of
VCON1 to VCON2 occurs as close as possible to the tank circuit – this minimises the effects of series
inductance on the oscillator behaviour.
For further information see also section 7.7.
Enable
Enable
VCO
Negative
Resistance
(NR)
Amplifier
VCON2
VCON1
VCOP1
VCOP2
VCO
Output Buffer
Amplifier
L1 should have
a Q>30
L1
C1
C2
C3
CV2
CV1
R1
R2
Input from
Loop Filter
Figure 5 Example External Components – VCO External Tank Circuit
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L1
C1
C2
C3
CMX972
51nH (Note 1)
8.2pF (Note 2)
27pF
27pF
CV1
CV2
R1
R2
SMV1705-079LF
SMV1705-079LF
10kΩ
10kΩ
Note 1: Tolerance of 2% or better recommended
Note 2: Tolerance of 5% or better recommended
Table 4 Internal VCO Amplifier Tank Circuit for 180MHz Operation
Alternative diodes may be used for CV1,CV2, for example the Toshiba 1SV305 (for which no other value
changes should be necessary). For increased tuning range the Skyworks SMV1249-079LF can be used: in
this case changing the tank circuit values is recommended. For operation at 180MHz, make L1 = 56nH
and C1=6.8pF, then C2 and C3 can be adjusted to give the desired tuning range: with C2, C3 = 27pF the
VCO gain (Kv) = 15 MHz/V and with C2, C3 = 12pF, Kv = 8MHz/V. For C2,C3 = 12pF, the value of C1
should be changed to 8.2pF, to give a control voltage closer to the centre of the tuning range.
Output to
Tank Cct
DO
R2
C1
R1
C3
C2
Figure 6 Example External Components – PLL Loop Filter
C1
C2
C3
150nF
1µF
15nF
R1
R2
1.5kΩ
2.4kΩ
rd
Table 5 3 Order Loop Filter Circuit for 180MHz Operation
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4.5
CMX972
Differential Amplifiers
The CMX972 provides two uncommitted differential amplifiers which may be used for a range of purposes.
Two possible configurations are shown in the following sections, however other uses include buffering or
level shifting of the modulator I/Q signals.
4.5.1
I/Q Output Amplifiers
The uncommitted differential amplifiers may be used to convert the differential I/Q output signals to a
single-ended output. A typical configuration of the amplifier on the Q channel (the I channel is identical) is
shown in Figure 7. This circuit has a linear gain of 1.5. Although the circuit is not optimum for rejection of
common mode signals, in practice performance is generally still satisfactory if R4 is omitted (i.e. replaced
with a 0 Ohm link). Users should note that the gain and bandwidth of this stage can be adjusted by altering
the component values and should be configured to suit a particular application.
C1 and C2 may be fitted to provide filtering if required.
CMX972
C1
R1
OA2P
RXQN
R2
BBAmp2
R4
OA2O
OA2N
RXQP
R3
C2
Figure 7 Example External Components – Receive I/Q Output
C1
C2
R1
Note 1:
NF
NF
10kΩ
R2
R3
R4
10kΩ
10kΩ
5kΩ Note 1
The value of R4 should be calculated from the value of the other resistors using the
calculation R4 = R1 – ((R2*R3)/(R2+R3)).
Table 6 Rx I/Q Differential to Single-ended Amplifier Components
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4.5.2
CMX972
Low IF Output
The quadrature demodulator output bandwidth is at least 5MHz, (see section 8.1.3.3), so the output of
each quadrature demodulator mixer can be configured to mix down to a low IF and use one of the
differential amplifiers to provide gain. A possible configuration for the Q channel is shown in Figure 8.
CMX972
C2
RXQN
RXQP
F1
R2
Bias
Voltage
C1
R1
R3
OA2P
BBAmp2
OA2O
OA2N
12.5k or 6.25k
Ceramic Filter
R4
C3
Figure 8 Example External Components – Receive Low IF Output
C1
C2
C3
F1
100nF
47nF
33pF
CFWL455KEFA-B0
R1
R2
R3
R4
1.5kΩ
1.5kΩ
1.5kΩ
4.7kΩ
Table 7 Rx Low IF (455kHz) Components
The components above specify, as an example, a particular ceramic filter (F1) that would typically be used
in a 25kHz channel application in a system with an IF frequency of 455kHz. The other component values
specified (e.g. R1, R3) are determined by the input/output impedance of the filter used. The filter and other
components can be easily changed to allow for other bandwidths and IF frequencies.
A different external IF filter, e.g. of different bandwidth, could similarly be connected to the I channel output
to support a second modulation bandwidth mode, e.g. to receive a 6.25kHz channel signal. The channel to
be used is selectable via the Rx Mode register ($1D), section 6.4.1, the unused channel being powereddown.
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5
CMX972
General Description
The CMX972 is an RF integrated circuit providing a quadrature demodulator, integer-N synthesiser and an
IF VCO. Additional features include gain control and uncommitted differential amplifiers. A detailed block
diagram for the IC is shown in section 2. The device can support a wide range of modulation formats and
standards. The following sections describe the functionality of the CMX972.
5.1
Quadrature Demodulator
The quadrature demodulator is designed for IF/RF operation, having very low power consumption. Input
frequencies in the range 20MHz to 300MHz are allowed. The demodulator system has two gain-controlled
stages, one before and one after the I/Q down-converters, as shown in Figure 9. The two gain control
elements can be independently controlled (see section 6.3.1). This adjustability allows users to optimise
characteristics depending on their system requirements. Minimum noise figure can be maintained by
decreasing gain in VGA with VGB at maximum gain. Intermodulation performance can be optimised by
decreasing gain in VGA or VGB. A lower gain in VGA will tend to reduce dc offsets in the output I/Q signal.
For further information on the effects of control of VGA and VGB see section 7.4.
Divide by
2 or 4
LO
RXIP
sin
RXIN
IFIN
RXQP
cos
RXQN
Variable Gain
Stage B
(VGB)
Variable Gain
Stage A
(VGA)
Figure 9 Demodulator Gain Control
The output of the quadrature demodulator is provided as a differential signal (pins RXIP, RXIN, RXQP and
RXQN). The bandwidth of the I/Q signals depends on the OUTDRV bit (b7, $1C, Rx Control Register, see
section 6.3.1). The intermodulation performance of the CMX972 also depends on the OUTDRV bit, see
section 7.2 for further details.
The CMX972 provides for an optimisation of receiver intermodulation using the “IMD” bits in the VCO
control register, further details can be found in section 7.2.
5.1.1
I/Q Amplitude and Phase Correction
The LO path includes a correction circuit which may be enabled or disabled using the COR bit (b6 in the
Rx Control Register $1C), see section 6.3.1. This will improve the I/Q balance of the demodulator
particularly when using the local oscillator divide by two (LO/2) mode; enabling this mode (COR=’1’) will
give a small increase in current consumption of typically 0.5mA. The improvement is most noticeable with
higher frequency signals, e.g. circa 200 - 300MHz; at 45MHz the improvement is negligible.
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CMX972
250MHz
Condition
45MHz
RXIP/RXQP RXIN/RXQN RXIP/RXQP RXIN/RXQN
$1C, b6 = ‘0’
$1C, b6 = ‘1’
92.0°
89.8°
92.0°
89.8°
90.1°
89.9°
90.2°
89.9°
Table 8 Typical Phase Balance, LO/2 Mode
At 250MHz I/Q amplitude balance is typically 0.12dB with COR = ‘0’ and 0.04dB with COR = ‘1’. Enabling
the correction circuit also reduces the I/Q path gain, particularly at higher frequencies. This can be
compensated by setting the FREQ bits (b3-0 in the Rx Mode register $1D) to ‘1111’, instead of the default
value of ‘0000’. I/Q path gain is restored at the expense of a slight degradation in I/Q phase balance of
≈0.5°. For many applications, the ‘1111’ setting will be adequate.
At all frequencies, phase correction accuracy is improved by using a lower setting of the FREQ bits (b3-0
in the Rx Mode register $1D). However, care should be taken to avoid significant gain degradation, which
occurs if a setting near ‘0000’ is chosen for a high frequency. Table 9 is a guide for the appropriate setting
of the FREQ bits, so as to obtain the best phase balance (typically better than 0.06°) with only a small gain
reduction (typically less than 0.6dB). Where frequency ranges overlap, either setting of the FREQ bits can
be used.
Bit
b3
0
1
1
1
1
b2
1
0
1
1
1
b1
0
0
0
0
1
b0
0
0
0
1
0
Frequency
20MHz to 40MHz
40MHz to 80MHz
80MHz to 200MHz
200MHz to 240MHz
240MHz to 300MHz
Table 9 Recommended FREQ bit Settings in the Rx Mode Register
60
59
58
57
Gain / dB
56
55
54
53
52
51
Cor=ON, $1D=00
50
49
Cor=ON, $1D=0F
48
47
Cor=OFF, $1D=00
46
45
0
50
100
150
200
250
300
Frequency / MHz
Figure 10 Frequency Response, showing effect of COR bit ($1C, b6) and FREQ bits($1D, b3-b0)
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CMX972
Condition
COR = ‘0’ $1D = 0x00
COR = ‘1’ $1D = 0x00
COR = ‘1’ $1D = 0x0F
Typical I/Q Phase Balance
87.95
90.06
90.49
Table 10 Effect of FREQ bits ($1D, b3-b0) on I/Q Phase Balance at 250MHz
Condition
COR = ‘0’ $1D = 0x00, +20°C
COR = ‘1’ $1D = 0x0F, -20°C
COR = ‘1’ $1D = 0x0F, +20°C
COR = ‘1’ $1D = 0x0F, +55°C
Typical I/Q Phase Balance
87.3
90.6
90.6
90.5
Table 11 Effect of FREQ bits ($1D, b3-b0) on I/Q Phase Balance at 300MHz with Temperature
5.1.2
DC Offset Correction
Digitally-controlled dc offset correction is provided which is capable of reducing the offset to 60mV or less
for errors of up to +/-420mV. This represents a reduction in dynamic range of about 0.3dB for a typical
ADC input signal range (2Vp-p) and is therefore negligible. The required correction must be measured
externally as such measurements are application specific. The correction is applied close to the start of the
I/Q baseband chain and therefore maximises dynamic range in the analogue sections.
The correction is applied in a differential manner so positive and negative corrections are possible, see
Figure 11. This allows the dc to be corrected to the nominal dc bias level. The voltage sources are scaled
in a binary fashion so multiple sources can be added to provide the desired correction. The same
arrangement applies independently on both I and Q channels.
Positive
Terminal
Vdc3
+
+
Vdc5
+
Vdc2
+
Vdc6
+
Vdc1
Differential
Output
Signal
Vdc4
+
Negative
Terminal
Figure 11 Simplified Schematic DC Offset Correction Circuit
Source
Voltage Correction at Output for
Maximum Gain in Baseband Amplifiers
Vdc1
60mV
Vdc2
120mV
Vdc3
180mV
Vdc4
60mV
Vdc5
120mV
Vdc6
180mV
Correction Polarity
Positive terminal increase,
Negative terminal decrease
Positive terminal increase,
Negative terminal decrease
Positive terminal increase,
Negative terminal decrease
Negative terminal increase,
Positive terminal decrease
Negative terminal increase,
Positive terminal decrease
Negative terminal increase,
Positive terminal decrease
Table 12 DC Offset Correction Adjustments
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5.2
CMX972
Differential Amplifiers
A pair of differential amplifiers are provided which may be used to implement filtering or buffering. These
uncommitted amplifiers may be used to implement Sallen-Key or Multiple Feedback (MFB) style filters,
buffering or configured as needed.
The amplifiers are low power and are enabled using the General Control Register (see section 6.2.1). It is
also possible for the amplifiers to be enabled with individual I and Q paths, see section 6.4.1.
5.3
Local Oscillator (LO)
The device allows for a flexible choice of routing for the LO input to the demodulator, to suit a variety of
applications.
The options available, controlled by the General Control Register (see section 6.2.1), are as follows:


The demodulator LO may be derived from the external input (RXLO) or from the internal
VCO/PLL.
The selected LO source is fed back to an integer-N PLL circuit which may be used to control the
on-chip (or an external) VCO from its Charge Pump output (DO).
Three bits in the General Control Register are used to define the allowed states. The permitted
combinations are shown in Table 13.
VCOEN
PLLEN
$1B, b3
$1B, b2
RXEN
Function
$1B, b1
0
0
0
0
0
1
0
1
1
1
1
1
All features disabled for low power
Use of demodulator with signal from RXLO pin
Use of demodulator with external VCO connected to
RXLO using on-chip PLL
Use of demodulator with LO supplied by on-chip
VCO and PLL
Note: Other combinations of control bit are illegal states and should not be used.
Table 13 LO Connections
5.3.1
Demodulator LO Input
The RXLO pin is a single-ended input for the demodulator LO signal. Internal ac coupling is provided so an
external dc blocking capacitor is not required. Note that the LO should be at twice or four times the desired
input frequency.
5.3.2
VCO and PLL
The internal VCO may be connected to the internal PLL and the demodulator. If required, an external VCO
can be connected to the PLL using the RXLO input, in this case the on-chip VCO must be disabled using
bit 3 in the General Control Register (see section 6.2.1 and Table 13).
5.3.2.1
PLL
The PLL functions are shown in Figure 12. The output frequency of the PLL is set by the following
calculation:
fout = fref x ( M / R )
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where
fout = The desired output frequency in MHz
fref = The reference frequency supplied to the PLL on pin REFIN in MHz
M = Divider value programmed in the M divider register (see section 6.6.1)
R = Divider value programmed in the R divider register (see section 6.7.1)
also note that fcomparision = fref / R
The PLL only supports VCOs with a positive tuning slope, i.e. a high tuning voltage from DO results in a
higher oscillation frequency from the VCO.
RXLO Input Pin and
Demodulator LO drive
CMX972
VCO
NR
Amplifier
NR
Control
Switching
M Divider
(Feedback)
80 - 32767
REFIN
Lock
Detect
DO
Phase
Detector
VCON2
VCOP1
VCON1
VCOP2
VCO
Output
Buffer
R Divider
(Reference)
2 - 8191
VCO
Tank &
Varactors
Figure 12 PLL Architecture
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The PLL block has to be enabled from the General Control Register $1B, b2 (section 6.2.1) and the PLL R
Divider Register $2C, b7 (section 6.7.1), i.e. an AND function is performed on these two bits.
General Control
Register $1B, b2
0
0
1
1
PLL R Divider
Register $2C, b7
0
1
0
1
PLL Enable
No
No
No
Yes
Table 14 PLL Control
The PLL provides a lock detect function which can be read via C-BUS register $DC bit 6, see section
6.6.2. Register $2C provides the facility for the PLL charge pump to be placed in a high-impedance state,
this mode can be used, for example, to allow pre-steering of the VCO.
When using the CMX972 PLL, spurious products (spurs) in the receiver I/Q output may be observed. The
level of the spurs varies and is typically different in I and Q channels. The frequency of the spurs is linked
to the PLL M divider value, thus the comparison frequency and which of the divider modes (divide-by-2 or 4) is selected for the receiver LO circuits. Operation in divide-by-2 mode is most predictable: all even
division ratios are problem free and all odd division ratios will give a spurious product at:
fspur = flo / ( M * 2 )
In divide-by-4 mode odd divisions will produce a spur although at some low frequencies (e.g circa
100MHz) spur levels are much lower. At circa 300 MHz and above, even divisions are also problematic (in
divide-by-4 mode).
It is recommended that for safe operation of the CMX972 PLL, receiver LO divide-by-2 with even division
ratios, should be used.
5.3.2.2
VCO
The CMX972 VCO is a reflection oscillator that requires an external resonator circuit (see section 4.4) with
the negative resistance (NR) generator on the device. The VCO Control Register ($2F, section 6.8.1)
provides a control of the magnitude of the negative transconductance for optimum phase noise
performance. The NR minimum mode should be used with the low Q external tank circuit and NR
maximum with the higher Q circuits. For further information see section 7.7.
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6
CMX972
C-BUS Interface and Register Description
The C-BUS serial interface supports the transfer of control and status information between the CMX972’s
internal registers and an external host. Each C-BUS transaction consists of the host sending a single
Register Address byte, which may then be followed by zero or one data bytes that are written into the
corresponding CMX972 register, as illustrated in Figure 13.
Data sent from the host on the Command Data (CDATA) line is clocked into the CMX972 on the rising
edge of the Serial Clock (SCLK) input. The C-BUS interface is compatible with common µC/DSP serial
interfaces and may also be easily implemented with general-purpose I/O pins controlled by a simple
software routine. Section 8.1.3.5 gives the detailed C-BUS timing requirements.
Whether a C-BUS register is of read or write type is fixed for a given C-BUS register address, thus it is not
possible to read from and write to the same C-BUS register address.
In order to provide ease of addressing when using this device with other CML RF devices, the C-BUS
addresses below are arranged so as not to overlap those used on the other CML RF Devices. Thus, a
common chip select (CSN) signal can be used, as well as common CDATA, RDATA and SCLK signals.
Also note that the General Reset ($1A) command on the CMX972 differs from other CML devices (such as
CMX991/CMX992/CMX993/CMX998), which use $01 or $10 for this function.
The following C-BUS register addresses are used:
Write Only register:
General Reset Register (Address only, no data)
General Control Register, 8-bit write only
Rx Control Register, 8-bit write only
Rx Mode Register, 8-bit write only
Rx Offset Correction Register, 8-bit write only
IF PLL M Divider Register, 8-bit write only
IF PLL R Divider Register, 8-bit write only
VCO Control Register, 8-bit write only
Address $1A
Address $1B
Address $1C
Address $1D
Address $1F
Address $2A-$2C
Address $2D-$2E
Address $2F
Read Only register:
General Control Register, 8-bit read only
Rx Control Register, 8-bit read only
Rx Mode Register, 8-bit read only
Rx Offset Correction Register, 8-bit read only
IF PLL M Divider Register, 8-bit read only
IF PLL R Divider Register, 8-bit read only
VCO Control Register, 8-bit read only
Address $EB
Address $EC
Address $ED
Address $EF
Address $DA-$DC
Address $DD-$DE
Address $DF
Notes:



The 8-bit write-only register ($1E), which is reserved for future use, defaults to 0x00 on power-up.
For minimum current consumption, this register should not be written to.
All registers will retain data if VDD pin is held high, even if all other power supply pins are
disconnected.
If clock and data lines are shared with other devices VDD must be maintained in its normal
operating range otherwise ESD protection diodes may cause a problem with loading signals
connected to SCLK, RDATA and CDATA pins, preventing correct programming of other devices.
Other supplies may be turned off and all circuits on the device may be powered down without
causing this problem.
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Figure 13 C-BUS Transactions
6.1
General Reset Command
6.1.1
General Reset Command - $1A: no data
This command resets the device and clears all bits of all registers. The General Reset command places
the device into powersave mode.
Whenever power is applied to the VDD pin, a built in power-on-reset circuit ensures that the device powers
up into the same state as follows a General Reset command.
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6.2
General Control Register
6.2.1
General Control Register - $1B: 8-bit write
This register controls general features such as powersave.
All bits of this register are cleared to ‘0’ during a General Reset command.
Bit:
7
6
5
4
3
2
1
0
RXDIV
0
DIFAMP
ENBIAS
VCOEN
PLLEN
RXEN
0
General Control Register b7
Writing b7 = ’1’ the receiver LO is divided by 2; writing b7 = ’0’ the LO is divided by 4.
General Control Register b6
Reserved, set to ‘0’.
General Control Register b5 - b1
These bits control power up/power down of the various blocks of the IC.
In all cases ‘1’ = power up, ‘0’ = power down.
b5
b4
b3
b2
Enable differential amplifiers (see also section 6.4.1)
Enable bias
Enable VCO (this bit also disables the RXLO input)
PLL enable (see Table 14 and section 6.6.1)
Note: To enable the PLL b7 of the PLL M-Divider Register ($2C)
also needs to be set.
Enable quadrature demodulator
b1
Note: b1-b3 also control local oscillator signal routing, see section 5.3 and Table 13.
General Control Register b0
Reserved, set to ‘0’.
6.2.2
General Control Register - $EB: 8-bit read
This register reads the value in register $1B, see section 6.2.1 for details of bit functions.
6.3
Rx Control Register
6.3.1
Rx Control Register - $1C: 8-bit write
This register controls operational modes of the receiver such as gain setting.
All bits of this register are cleared to ‘0’ by a General Reset command.
Bit:
7
6
5
4
3
2
1
0
OUTDRV
COR
0
VGB2
VGB1
VGB0
VGA1
VGA0
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CMX972
Rx Control Register b7
Writing b7 = ’1’ the output drive capability of the demodulator I/Q output is increased, this mode
allows the CMX972 to support wider bandwidth modulation and/or driver lower impedance loads;
b7 = ’0’ is the default condition with best power efficiency.
Rx Control Register b6
Writing b6 = ‘1’ enables the correction circuit in the quadrature demodulator. This will improve the
I/Q phase balance of the demodulator particularly in LO/2 mode; enabling this mode increases the
current consumption slightly. For further information see section 5.1.1.
With b6 = ‘0’ this enhanced mode is disabled for optimum current consumption.
Rx Control Register b5
Reserved, must be cleared to ‘0’ for correct operation.
Rx Control Register b4 – b2
Variable Gain (VGB) Control; these bits control the gain of the IF/RF amplifier reducing the gain
from the maximum in 6dB steps.
Bit
b4
1
1
1
1
0
0
0
0
b3
1
1
0
0
1
1
0
0
b2
1
0
1
0
1
0
1
0
Reserved do not use
Reserved do not use
VG = -30dB
VG = -24dB
VG = -18dB
VG = -12dB
VG = -6dB
VG = 0dB (maximum gain)
Rx Control Register b1 – b0
Variable Gain (VGA) control; this bits control the gain of the post-I/Q mixer baseband amplifiers
reducing the gain from the maximum in 6dB steps.
Bit
6.3.2
b1
1
1
0
0
b0
1
0
1
0
VG = -18dB
VG = -12dB
VG = -6dB
VG = 0dB (maximum gain)
Rx Control Register - $EC: 8-bit read
This read-only register mirrors the value in register $1C; see section 6.3.1 for details of bit
functions.
6.4
Rx Mode Register
6.4.1
Rx Mode Register - $1D: 8-bit write
This register controls operational modes of the receiver.
All bits of this register are cleared to ‘0’ by a General Reset command.
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Bit:
CMX972
7
6
5
4
3
2
1
0
M1
M0
DIFAMPI
DIFAMPQ
FREQ3
FREQ2
FREQ1
FREQ0
Rx Mode Register b7 – b6
Bit
b7
0
0
1
1
b6
0
1
0
1
I and Q channels enabled
Only I channel enabled
Only Q channel enabled
Reserved do not use
Rx Mode Register b5 - b4
With b4, b5 = ‘0’ both differential amplifiers are enabled/disabled by the DIFAMP bit in the General
Control Register (section 6.2.1). With b4 = ‘1’ the Q channel differential amplifier control by the
DIFAMP bit will be inverted. With b5 = ‘1’ the I channel differential amplifier control by the DIFAMP
bit will be inverted. This aids the applications where the amplifiers are associated with either the I
or Q channels.
Bit
$1B, b5
0
0
0
0
1
1
1
1
b5
0
0
1
1
0
0
1
1
b4
0
1
0
1
0
1
0
1
Diff Amp 1 = ‘OFF’; Diff Amp 2 = ‘OFF’
Diff Amp 1 = ‘OFF’; Diff Amp 2 = ‘ON’
Diff Amp 1 = ‘ON’; Diff Amp 2 = ‘OFF’
Diff Amp 1 = ‘ON’; Diff Amp 2 = ‘ON’
Diff Amp 1 = ‘ON’; Diff Amp 2 = ‘ON’
Diff Amp 1 = ‘ON’; Diff Amp 2 = ‘OFF’
Diff Amp 1 = ‘OFF’; Diff Amp 2 = ‘ON’
Diff Amp 1 = ‘OFF’; Diff Amp 2 = ‘OFF’
Rx Mode Register b3 – b0
These bits optimise the operation of the receiver quadrature demodulator mixers by adjusting the
LO signal. The bits adjust LO amplitude, which has an impact on mixer gain, but the adjustment
also has an effect on quadrature accuracy. See also section 5.1.1. Note that if $1C b6 is set to 0,
so that phase correction is not used, the setting of these FREQ bits has no effect.
A setting of ‘0000’ represents the optimum value for phase accuracy.
6.4.2
Rx Mode Register - $ED: 8-bit read
This read-only register mirrors the value in register $1D; see section 6.4.1 for details of bit
functions.
6.5
Rx Offset Register
6.5.1
Rx Offset Register - $1F: 8-bit write
All bits of this register are cleared to ‘0’ by a General Reset command.
Bit:
7
6
5
4
3
2
1
0
QDC3
QDC2
QDC1
QDC0
IDC3
IDC2
IDC1
IDC0
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Rx Offset Register b7 – b0
I/Q DC offset correction, see section 5.1.2 for further details.
Bit
6.5.2
b3
b2
b1
b0
I Channel
b7
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
b6
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
b5
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
b4
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Q Channel
-420mV
-360mV
-300mV
-240mV
-180mV
-120mV
-60mV
No correction
+420mV
+360mV
+300mV
+240mV
+180mV
+120mV
+60mV
No correction
Rx Offset Register - $EF: 8-bit read
This read-only register mirrors the value in register $1F; see section 6.5.1 for details of bit
functions.
6.6
PLL M Divider Register
6.6.1
PLL M Divider - $2C - $2A: 8-bit write
These registers set the M divider value for the PLL (Feedback divider). The PLL dividers are only
updated when $2C has been written, so this register should be written to last. Bits 7 and 5 also
control the PLL and charge-pump blocks and these control bits are active as soon as $2C is written.
(Note: To enable the PLL, b2 of the General Control Register ($1B) also needs to be set).
$2C
Bit:
$2B
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
E
LD_Synth
CP
0
0
0
M17
M16
M15
M14
M13
M12
M11
M10
M9
M8
$2A
7
6
5
4
3
2
1
0
M7
M6
M5
M4
M3
M2
M1
M0
M17:M0
Phase Locked Loop M divider value.
CP
$2C, b5 = ’1’ enables the charge pump, $2C b5 = ’0’ puts the charge pump into high-impedance
mode.
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LD_Synth
Only write ‘0’ to b6 of $2C (when read, this shows the PLL lock status, see section 6.6.2).
E
$2C, b7 = ’1’ enables the PLL; b7 = ’0’ disables the PLL – in this mode an external local oscillator
may be supplied to the CMX972, see also section 5.3.2 and Table 14. (Note: To enable the PLL b2
of the General Control Register ($1B) also needs to be set).
$2C b4-b2
Reserved, set to ‘0’.
6.6.2
PLL M Divider - $DC - $DA: 8-bit read
These registers read the respective values in registers $2C, $2B and $2A ($DC reads back $2C
and $DB reads back $2B etc.); see section 6.6.1 for details of bit functions.
N.B. $DC b6 indicates the Synthesiser lock detect status.
6.7
PLL R Divider Register
6.7.1
PLL R Divider - $2E - $2D: 8-bit write
These registers set the R divider value for the PLL (Reference divider). The PLL dividers are only
updated when $2E has been written, so this register should be written to last.
$2E
Bit:
$2D
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
R15
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
R15:R0
Phase Locked Loop R divider value.
6.7.2
PLL R Divider - $DE - $DD: 8-bit read
These registers read the respective values in registers $2E and $2D ($DE reads back $2E and
$DD reads back $2D); see section 6.7.1 for details of bit functions.
6.8
VCO Control Register
6.8.1
VCO Control Register - $2F: 8-bit write
This register optimises the operation of the VCO. Note the VCO is enabled when b3 = ‘1’ in the
General Control register ($1B), as detailed in section 6.2.
All bits of this register are cleared to ‘0’ by a General Reset command.
Bit:
7
6
5
4
3
2
1
0
IMD5
IMD4
IMD3
IMD2
IMD1
IMD0
VCONR2
VCONR1
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VCO Control Register b7 – b2
These bits allow the user to adjust the intermodulation performance of the Rx I/Q mixers. The
default value is ‘0’ for all the bits. Improved intermodulation can be achieved with a particular value
in these bits. The recommended value for optimum performance is ‘111111’. This value does not
vary between devices or with frequency. For further details see section 7.2.
VCO Control Register b1 – b0
VCO amplifier Negative Resistance (NR) control for optimum phase noise performance, see
section 5.3.2.2.
Bit:
6.8.2
b2
0
0
1
1
b1
0
1
0
1
NR maximum (highest Q tank circuit)
NR Intermediate value
NR Intermediate value
NR minimum (lowest Q tank circuit)
VCO Control Register - $DF: 8-bit read
This register reads the value in register $2F, see section 6.8.1 for details of bit functions.
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7
Application Notes
7.1
IF/RF Input Matching
CH1
S 11
1 U FS
CMX972
1_: 990.69
-594.37
13.388 pF
20.000 000 MHz
PRm
Cor
2_: 455.72
-611.44
45 MHz
MARKER 1
20 MHz
3_: 159.09
-383.72
100 MHz
4_: 54.992
-210.29
200 MHz
5_: 40.453
-171.7
250 MHz
1
2
3
4
5
START 10.000 000 MHz
STOP 300.000 000 MHz
Figure 14 Quadrature Demodulator Input Impedance (10MHz to 300MHz)
Frequency
(MHz)
20
45
100
200
250
Typical
Impedance
(Ω-/+jΩ)
991 - j594
456 - j611
159 - j384
55 - j210
41 - j172
Parallel Equivalent
Circuit
(R//pF)
1.35kR // 3.5pF
1.28kR // 3.7pF
1.08kR // 3.5pF
860.5R // 3.5pF
768.4R // 3.5pF
Table 15 Quadrature Demodulator Input Impedances and Parallel Equivalent Circuit
The typical input impedance of the IFIN port is shown in Figure 14 and Table 15. The configuration of the
IF input has a significant effect on the measured performance. This is demonstrated in Table 16, where
the receiver is measured with a 50 Ohm source and three different input conditions. A matched network
(e.g. as shown in section 4.2) provides the best noise figure and maximum gain, however intermodulation
will be degraded in this condition due to the larger signal levels indicated by the extra gain. The ‘straight in’
condition means that the 50 Ohm signal source was connected directly at IFIN.
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Input Condition Noise Figure / dB
50R shunt resistor
matched network
straight in
16.3
7.8
10
Gain / dB
50.5
64
56
Table 16 Typical Noise Figure and Gain of IF Amp, VGA and I/Q Mixer
The gain in the ‘straight in’ case is based on direct conversion of the signal generator power to a voltage
and calculating the gain based on the output voltage. The output signal is the differential signal at RXIN
and RXIP (or RXQN and RXQP) so if the voltage is measured at a single pin the signal level must be
doubled to get the appropriate differential signal level. Also it should be noted that making a simple
conversion of the power in the ‘straight in’ case is erroneous as the voltage calculated will be a potential
difference. As the circuit is unmatched an e.m.f. would be more appropriate (i.e. twice the potential
difference value).
7.2
Demodulator Intermodulation and Output Drive Capability
The intermodulation performance of the demodulator may be optimised by use of the output drive bit
(register $1C b7, see section 6.3.1). Performance can be further optimised by setting the IMD bits in the
VCO register (register $2F b2 to b7) to ‘111111’ = 63 decimal.
IMD bits setting
(register $2F b2
to b7) decimal
value
0
63
$1C, b7=’0’
50kHz and
100kHz tones
$1C, b7=’1’
50kHz and
100kHz tones
$1C, b7=’0’
500kHz and
1MHz tones
$1C, b7=’1’
500kHz and
1MHz tones
-23 dBm
-19 dBm
-12 dBm
-11 dBm
-24 dBm
-24 dBm
-12 dBm
-11 dBm
Table 17 Typical Third Order Intercept Performance of demodulator at 45MHz (straight-in case)
7.3
Variation with Temperature
The CMX972 demodulator exhibits excellent temperature stability. Typical variation of the receive path
gain is shown in Figure 15. The I/Q gain/phase balance (see Table 10), dc level and attenuator steps also
show only small variations with temperature.
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CMX972
Demodulator Gain / dB
58
57.5
57
20MHz
100MHz
56.5
250MHz
56
55.5
55
-55
-35
-15
5
25
45
65
85
Temperature / deg. C
Figure 15 Demodulator Gain Variation With Temperature
59
58
57
Gain / dB
56
55
54
RT
53
-20degs
52
-40degs
51
+55degs
+85degs
50
49
50
100
150
200
Freqency / MHz
250
300
Figure 16 Variation in Gain with Temperature (COR = ‘0’ $1D = 0x00)
7.4
Effect of Gain Control on Receiver Performance
The CMX972 has two independent gain control elements: VGA is gain control applied in the I/Q sections
and VGB is gain control in the RF/IF sections. Further details can be found in section 5.1. The gain can be
controlled in 6dB steps via the Rx Control Register (see section 6.3).
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CMX972
The control of gain using VGA and VGB has an impact on the performance of the CMX972 demodulator
section. The variation in noise figure (NF) is straightforward, with the RF/IF gain control (VGB) having a
direct impact on NF but, due to the gain before the I/Q section, VGA has little impact on NF (see Figure
17). The variation of intermodulation (IMD) is more complex, as shown in Figure 18, where performance is
characterised by ‘Input Third Order Intercept Point’ (IIP3). At maximum gain IIP3 is at a minimum and as
would be expected, the IIP3 increases as the RF/IF gain is reduced (VGB). The improvement plateaus
beyond the –18dB gain setting as the input stages limit performance at this level. Reduction in gain with
VGA (I/Q gain control) also has a positive effect on IIP3. This is perhaps less intuitive but indicates that the
intermodulation performance of the CMX972 demodulator chain is dominated by the output stages rather
than RF/IF or mixer stages. Thus –6dB or even –12dB VGA gain control settings can be used to achieve
improved IMD performance for negligible change in noise figure (Figure 17), as long as the reduction in
gain can be tolerated.
40
Noise Figure / dB
35
30
25
VGA
20
VGB
15
10
5
0
-30
-25
-20
-15
-10
-5
0
VGA / VGB Attenuation
Figure 17 Variation in CMX972 Demodulator Noise Figure with VGA/VGB Control
10
5
IIP3 / dBm
0
VGA
-5
VGB
-10
-15
-20
-30
-25
-20
-15
-10
-5
0
Gain Control / dB
Figure 18 Variation in Input Third Order Intercept Point with VGA/VGB Control
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7.5
CMX972
Measurement of CMX972 Demodulator Intermodulation Performance
The measurement of the intermodulation (IMD) performance of the CMX972 demodulator requires great
care because generally the IMD products are at a very low level. As a result, it is important to ensure
products being measured are generated by the CMX972, not the measurement instrument or the test
system.
It is also important to ensure that measurements are taken before the onset of clipping in the I/Q output
stages – the effect is shown in Figure 19. Considering the graph, at signal levels below –51dBm per tone
(two tone signal, tones of equal amplitude) the measured IMD product rises at the classical rate of 2dB for
every 1dB increase in tone level. For input levels above –51dBm the rate of increase rises dramatically due
to the onset of clipping. The effect can be seen in the plots of the composite signal: the calculated line is
based on a calculation of the peak-to-peak swing of the output I/Q voltage from measured tone level at the
output of the CMX972, however the actual output level is also plotted and the two lines deviate at the onset of clipping.
It will be apparent that any calculation of IMD parameters, e.g. input third order intercept point, from
measurements taken after the onset of clipping will give erroneous results if trying to characterise receiver
operation at normal signal levels.
10
3.5
0
Output Signal Level / dBm
-10
2.5
-20
-30
2
-40
1.5
-50
1
-60
Composite Signal level / Vp-p
3
Signal
IMD Product
Calculated level of
composite signal
Composite Signal
(Measured)
0.5
-70
-80
-53
-52
-51
-50
-49
0
-48
Input Signal Level Per Tone / dBm
(Note: the two curves ‘Signal’ and ‘IMD Product’ are levels in dBm so should be referenced to the left hand
Y-axis; the other curves are output voltages and use the right hand Y-axis.)
Figure 19 Variations in Signal and IMD Product Levels
Typical IMD measurements for the CMX972 demodulator usually involve IMD products at least 75dB
below the wanted signal.
The input level where compression commences will vary somewhat from device to device, the value of
-44.5dBm1 (Figure 19) is typical but should only be used as an initial guide.
1
Note: -50.5 dBm per tone = -44.5 dBm PEP,
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7.6
CMX972
Operation with large input signals
The input 1dB gain compression point of the CMX972 will vary depending on the settings of the VGA and
VGB gain stages. Typical results with a 45 MHz signal, 50 ohm source, ‘straight in’ are as follows:
VGA = 0dB, VGB = 0dB
VGA = -18dB, VGB = 0dB
VGA = -18dB, VGB = -12dB
VGA = -18dB, VGB = -24dB
Input 1dB compression point = -42dBm
Input 1dB compression point = -25dBm
Input 1dB compression point = -12dBm
Input 1dB compression point = +5dBm
The above results are with the OUTDRV bit set to ‘1’ and the IMD5-IMD0 bits in register $2F=’000000’. For
optimum intermodulation performance the IMDn bits should be set to ‘111111’ which has the effect of
reducing the gain by about 1dB thus improving the input compression point by 1dB.
At high input signal levels the output of the CMX972 can start to reduce. Typical performance at maximum
and minimum gain settings is shown in Figure 20, measured at 45MHz, setting as above. The output level
is shown in dBm, this is measured by buffering the differential I/Q output signals (voltage), converting to
single-ended and then measuring as power based on 50 Ohms.
16
Minimum Gain
Maximum Gain
14
Output Level / dBm
12
10
8
6
4
2
0
-60
-50
-40
-30
-20
-10
0
10
Input Level / dBm
Figure 20 Output Signal Level Variations with Large Input Signals
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7.7
CMX972
VCO Phase Noise
The performance of the negative resistance VCO can be optimised by use of the VCONR bits in the VCO
control register ($2F, b1-b0, see section 6.8.1). For example, the typical change in phase noise and tuning
voltage with VCONR setting is shown in Table 18 for the 180 MHz VCO described in Figure 5 / Table 4.
VCONR setting ($2F, b1-b0)
Vtune
(V)
Phase Noise at 10kHz
offset, from fvco/2
(dBc/Hz)
Maximum
Intermediate 1
Intermediate 2
Minimum
2.425
2.335
2.235
2.183
-105.7
-107.1
-109.0
-110.0
Table 18 Effect of VCONR bits, fvco = 180 MHz, divide-by-2
The phase noise achieved by the CMX972 VCO depends on the VCO gain (Kv). The effect is shown in
Figure 21, which plots the phase noise measured at 90 MHz (180 MHz VCO as Figure 5 / Table 4, divideby-2 mode) as a function of the VCO gain.
Phase Noise (dBc/Hz)
-105
-106
-107
-108
-109
-110
6
8
10
12
14
VCO Gain Kv (MHz/V)
Figure 21 Effect of VCO Gain on Phase Noise
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8
Performance Specification
8.1
Electrical Performance
8.1.1
Absolute Maximum Ratings
CMX972
Exceeding these maximum ratings can result in damage to the device.
Supply (VDD - VSS) or (VCC - VRFGND) or
(VCCSYNTH - VRFGND)
Voltage on any pin to VSS or VRFGND
Voltage between pins RFGND and VSS
Voltage between pins VCC and VCCSYNTH
Current into or out of RFGND, VSS, VCC, VCCSYNTH or
VDD pins
Current into or out of any other pin
Q5 Package
Total Allowable Power Dissipation at TAMB = 25°C
... Derating (see Note below)
Storage Temperature
Operating Temperature
Min.
-0.3
Max.
+4.0
Units
V
-0.3
-50
-0.3
-75
VDD + 0.3
+50
+0.3
+75
V
mV
V
mA
-30
+30
mA
Min.
–
–
-55
-40
Max.
1410
14.1
+125
+85
Units
mW
mW/°C
°C
°C
Note: Junction-to-ambient thermal resistance is dependent on board layout and mounting
arrangements. The derating factor stated will be better than this with good connection between the
device and a ground plane or heat sink.
8.1.2
Operating Limits
Notes
Analogue Supply (VCC – VRFGND)
Digital Supply (VDD – VSS)
Operating Temperature (see Note above)
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Min.
3.0
3.0
-40
Max.
3.6
3.6
+85
Units
V
V
°C
D/972/2
Quadrature Demodulator with IF PLL/VCO
8.1.3
8.1.3.1
CMX972
Operating Characteristics
DC Parameters
For the following conditions unless otherwise specified:
VCC = VCCSYNTH = VDD = 3.3V; VRFGND = VSS = 0V. RXLO Level = -10dBm and TAMB = +25ºC.
DC Parameters
Total Current Consumption
Powersave Mode
Bias Only
Operating Currents
Rx Only
PLL and VCO
Additional Current with DIFFAMP=’1’
Logic '1' Input Level
Logic '0' Input Level
Logic Input Leakage Current (Vin = 0 to VDD)
Output Logic ‘1’ Level (lOH = 0.6 mA)
Output Logic ‘0’ Level (lOL = -1.0 mA)
Power Up Time
Voltage Reference
All Blocks Except Voltage Reference
Notes
1
2
Min.
Typ.
Max.
Units
–
–
7
1.7
70
2
µA
mA
4
5
6
–
–
–
15
9
0.85
20
11
1.5
mA
mA
mA
70%
–
-1.0
80%
–
–
–
–
–
–
–
30%
+1.0
–
+0.4
VDD
VDD
µA
VDD
V
–
–
–
–
0.5
10
ms
µs
7
7
Notes:
1.
2.
3.
4.
5.
6.
7.
Total current, VDD, VCC and VCCSYNTH.
Clock input (REFIN pin) not active; powersave mode includes the case after general reset with
all analogue and digital supplies applied and also the case with VDD applied but with VCC and
VCCSYNTH supplies disconnected (i.e. in this latter scenario power from VDD will not exceed the
specified value, whatever the state of the registers), not including any current drawn from
device pins by external circuitry.
Void
Only Rx and Bias sections active.
Only Bias, PLL and VCO sections active.
DIFFAMP bit in General Control Register, see section 6.2.1, combined current for both
differential amplifiers
Time from the rising edge of the last serial clock input following CSN being asserted for a write
to the appropriate control register.
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8.1.3.2
CMX972
AC Parameters
For the following conditions unless otherwise specified:
VCC = VCCSYNTH = VDD = 3.3V; VRFGND = VSS = 0V. and TAMB = +25ºC.
AC Parameters
Notes
Differential Amplifiers
Gain Bandwidth Product
Input Offset Voltage
Input Common Mode Range
Input Bias Current
Input Resistance
Slew Rate
Differential Input Voltage
Input Referred Noise at 1kHz
DC Output Range
Output Load
11
Min.
Typ.
Max.
Units
40
–
1.0
–
–
–
–
–
70
1
1.6
0.4
160
6
–
15
–
–
–
2.5
–
–
–
2
–
MHz
mV
V
µA
VRFGND+
0.1
–
1k
//100pF
VRFGND0.1
–
k
V/µs
Vp-p
nV/Hz
V
Notes:
10. Local oscillator input frequency twice or four times the required operating frequency.
11. Operating into a virtual earth (not ground).
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8.1.3.3
CMX972
AC Parameters – Demodulator
For the following conditions unless otherwise specified:
VCC = VCCSYNTH = VDD = 3.3V; VRFGND = VSS = 0V. RXLO Level = -10dBm and TAMB = +25ºC.
IF Amplifier and
Quadrature Demodulator
Gain
Noise Figure
Input Third Order Intercept Point
Input Frequency Range
RXLO Frequency Range
Input Impedance
Output Impedance
Output Load
Resistance (differential)
Capacitance per Pin
Differential Output Voltage
Output Common Mode Voltage
RXLO Leakage at Input
Input 1dB Compression Point
VGA Control Range
VGB Control Range
VGA and VGB Step Size
I/Q Gain Matching Error
I/Q Phase Matching Error
I/Q Output Bandwidth (-3dB)
Notes
Min.
Typ.
Max.
Units
30,31
30,31
30,34
–
–
–
20
40
–
–
56
10
-15
–
–
1000
200
–
–
–
300
600
–
–
dB(V/V)
dB
dBm
MHz
MHz
Ω
Ω
10
–
2
VCC – 1.9
–
–
–
–
4
–
–
5
–
–
–
VCC – 1.7
-80
-41
18
30
6
0.1
0.1
10
–
10
–
VCC – 1.5
-40
–
–
–
8
0.5
1
–
kΩ
pF
Vp-p
V
dBm
dBm
dB
dB
dB
dB
degree
MHz
31
33
33
33
30, 34,35
32
32
33
Notes:
30.
31.
32.
33.
34.
35.
Measured from an unmatched 50Ω input source to a differential I or Q output voltage; test
frequency = 45MHz. Note that values include combined response of IF amplifier, quadrature
demodulator and I/Q amplifier stages; at maximum VGA and VGB setting (0dB).
See also section 7.1.
Four VGA steps and six VGB steps, see Rx Control Register, section 6.3.1.
Differential Output Voltage is achieved with default output drive setting (register $1C, b7=’0’,
see section 6.3.1), for given output load and for at least the minimum I/Q output bandwidth;
typical I/Q output bandwidth is achieved with increased drive capability selected (register $1C,
b7=’1’, see section 6.3.1) and with the same output load specification.
With increased output drive setting (register $1C, b7=’1’).
With IMD5 – IMD0 (b7 – b2 of register $2F) set to ‘111111’
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D/972/2
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8.1.3.4
CMX972
AC Parameters – Integer N PLL and VCO
For the following conditions unless otherwise specified:
VCC = VCCSYNTH = VDD = 3.3V; VRFGND = VSS = 0V. RXLO Level = -10dBm and Tamb = +25ºC.
Phase Locked Loop
Reference Input
Frequency
Level
Divide Ratios (R Counter)
Synthesiser
Comparison Frequency (fcomparison)
Input Frequency Range
Input Level
Divide Ratios (M Counter)
Charge Pump Current
1Hz Normalised Phase Noise Floor
Negative Resistance VCO
Supply Current (Enabled)
Frequency Range
Phase Noise at 10kHz Offset
Phase Noise at 100kHz Offset
RXLO Input
Input Level
Frequency Range
Notes
Min.
Typ.
Max.
Unit
40
5
–
2
–
0.5
–
30
–
8191
MHz
Vp-p
–
–
–
–
2.5
-216
500
1000
-5
32767
–
–
kHz
MHz
dBm
43
1
40
-20
80
–
–
mA
dBc/Hz
41
42
42
–
40
–
–
3
–
-104
-118
–
1000
–
–
mA
MHz
dBc/Hz
dBc/Hz
–
40
-10
–
–
1000
dBm
MHz
Notes:
40.
41.
42.
43.
Sinewave or clipped sinewave.
Operation will depend on the choice and layout of external resonant components.
With external components from section 4.4 (Table 4) forming a 180MHz VCO; negative
resistance bits set to minimum ($2F, b1-b0 = ‘11’); phase noise quoted at VCO operating
frequency but will normally be improved by the divider circuits in the demodulator LO path.
1Hz Normalised Phase Noise Floor (PN1Hz) can be used to calculate the phase noise within
the PLL loop bandwidth by: Measured Phase Noise (in 1Hz) = PN1Hz + 20log10(M) +
10log10(fcomparison).
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8.1.3.5
CMX972
C-BUS
C-BUS Timings (See Figure 22)
tCSE
CSN-Enable to Clock-High Time
tCSH
Last Clock-High to CSN-High Time
tLOZ
Clock-low to reply output enable time
tHIZ
CSN-high to reply output 3-state time
tCSOFF
CSN-High Time between transactions
tNXT
Inter-Byte Time
tCK
Clock-Cycle Time
tCH
Serial Clock (SCLK) - High Time
tCL
Serial Clock (SCLK) - Low Time
tRDS
Reply Data (RDATA) - Set-Up Time
tRDH
Reply Data (RDATA) – Hold Time
tCDS
Command Data (CDATA) - Set-Up Time
tCDH
Command Data (CDATA) – Hold Time
Notes
Min.
100
100
0.0
–
1.0
200
200
100
100
50.0
0.0
75.0
25.0
Typ.
–
–
–
–
–
–
–
–
–
–
–
–
–
Max.
–
–
–
1.0
–
–
–
–
–
–
–
–
–
Units
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
Maximum 30pF load on each C-BUS interface line.
Note: Only 1 byte of data is used in CMX972 C-BUS transactions.
Figure 22 C-BUS Timing
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Quadrature Demodulator with IF PLL/VCO
8.2
CMX972
Packaging
DIM.
*
*
MIN.
TYP.
MAX.
5.00 BSC
A
B
C
F
G
H
J
K
L
L1
P
T
0.80
3.00
3.00
0.00
0.18
0.20
0.30
0
5.00 BSC
0.90
0.25
1.00
3.80
3.80
0.05
0.30
0.55
0.15
0.50
0.20
NOTE :
*
Exposed
Metal Pad
A & B are reference data and do
not include mold deflash or protrusions.
All dimensions in mm
Angles are in degrees
Index Area 1
Dot
Index Area 2
Dot
Chamfer
Index Area 1 is located directly above Index Area 2
Depending on the method of lead termination at the edge of the package, pull back (L1) may be present.
L minus L1 to be equal to, or greater than 0.3mm
The underside of the package has an exposed metal pad which should ideally be soldered to the pcb to enhance the thermal
conductivity and mechanical strength of the package fixing. Where advised, an electrical connection to this metal pad may also
be required
Figure 23 Q5 Mechanical Outline: Order as part no. CMX972Q5
Handling precautions: This product includes input protection, however, precautions should be taken to prevent device damage
from electro-static discharge. CML does not assume any responsibility for the use of any circuitry described. No IPR or circuit
patent licences are implied. CML reserves the right at any time without notice to change the said circuitry and this product
specification. CML has a policy of testing every product shipped using calibrated test equipment to ensure compliance with
this product specification. Specific testing of all circuit parameters is not necessarily performed.