TI1 LM48824TMX/NOPB Class g headphone amplifier with i2c volume control Datasheet

LM48824
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LM48824
Class G Headphone Amplifier
with I C Volume Control
2
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FEATURES
DESCRIPTION
•
•
The LM48824 is a Class G, ground-referenced stereo
headphone amplifier designed for portable devices.
The LM48824 features TI’s ground-referenced
architecture, which eliminates the large DC blocking
capacitors required by traditional headphone
amplifiers, saving board space and minimizing
system cost.
1
2
•
•
•
•
•
•
•
Class G Power Savings
Ground Referenced Headphone Outputs –
Eliminates Output Coupling Capacitors
Common-Mode Sense
I2C Volume and Mode Control
High Output Impedance in Shutdown
Differential Inputs
Advanced Click-and-Pop Suppression
Low Supply Current
Low THD Mode Option
The LM48824 takes advantage of TI’s patent-pending
Class G architecture offering power savings
compared to a traditional Class AB headphone
amplifier. Additionally, output noise is improved by
common-mode sensing that corrects for any
differences between the amplifier ground and the
potential at the headphone return terminal, minimizing
noise created by any ground mismatches.
APPLICATIONS
•
•
Mobile Phones, PDAs, MP3 Players
Portable Electronic Devices, Notebook PCs
A high output impedance mode allows the LM48824's
outputs to be driven by an external source without
degrading the signal. Other features include flexible
power supply requirements, differential inputs for
improved noise rejection, a low power (2.5μA)
shutdown mode, and a 32-step I2C volume control
with mute function.
KEY SPECIFICATIONS
•
•
•
•
•
Quiescent Power Supply Current at 3.6V:
0.9mA (typ)
Output Power/Channel at VDD = 3.6V (RL = 16Ω,
THD+N ≤ 1%): 37 mW (Typ)
Output Power/Channel at VDD = 3.6V (RL = 32Ω,
THD+N ≤ 1%): 29 mW (Typ)
PSRR at 217Hz: 100 dB (Typ)
Shutdown Current: 2.5 μA (Typ)
The LM48824's superior click and pop suppression
eliminates audible transients on power-up/down and
during shutdown. The LM48824 is available in an
ultra-small 16-bump, 0.4mm pitch DSBGA package
(1.69mm x 1.69mm)
Simplified Block Diagram
Left
VOLUME
CONTROL
GND
Right
V+
SCL
SDA
Digital
Interface
POWER
SUPPLY
V-
LM48824
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2013, Texas Instruments Incorporated
LM48824
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Typical Application
2.4V to 5.5V
C3
1 PF
VDD
2.3V to 5.5V
SW
REGULATOR
CONTROL
3.3 PH
C4
10 PF
5 k:
5 k:
HPVDD
C1P
SDA
SCL
I2C INTERFACE
C1
2.2 PF
CHARGE PUMP
C1N
HPVSS
C2
2.2 PF
1 PF
CIN
INL+
INLCIN
CIN
OUTL
1 PF
1 PF
INR+
OUTPUT LEVEL
DETECT
VOLUME
CONTROL
OUTR
INRCIN
1 PF
COM
GND
Figure 1. Typical Audio Amplifier Application Circuit
2
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Connection Diagram
Top View
A
SW
VDD
OUTL
INL-
B
GND
C1P
HPVDD
INL+
C
C1N
HPVSS
COM
INR+
D
SDA
SCL
OUTR
INR-
1
2
3
4
Figure 2.
DSBGA Package (1.7mm x 1.7mm x 0.6mm)
See Package Number YFQ0016DDA
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2) (3) (4)
Supply Voltage (1)
6V
−65°C to +150°C
Storage Temperature
Input Voltage
-0.3V to VDD + 0.3V
Power Dissipation (5)
Internally Limited
ESD Rating (6)
2000V
(7)
200V
ESD Rating
ESD Rating (8)
500V
Junction Temperature
Soldering Information
Thermal Resistance
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
150°C
Vapor Phase (60 sec.)
215°C
Infrared (15 sec.)
θJA (YFQ0016DDA)
220°C
60°C/W
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified
The Electrical Characteristics tables list specified specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Soldering Information: See AN-1112 “Micro SMD Wafer Level Chip Scale package”
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX , θJA, and the ambient temperature,
TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA) / θJA or the number given in Absolute Maximum Ratings,
whichever is lower.
Human body model, applicable std. JESD22-A114C.
Machine model, applicable std. JESD22-A115-A.
Charged Device Model, applicable std. JESD22-C101-C.
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Operating Ratings
Temperature Range (TMIN ≤ TA ≤ TMAX)
−40°C ≤ TA ≤ +85°C
2.4V ≤ VDD ≤ 5.5V
Supply Voltage (VDD)
Electrical Characteristics VDD = 3.6V (1) (2)
The following specifications apply for AV = 0dB, RL = 32Ω, f = 1kHz, unless otherwise specified. Limits apply to TA = 25°C.
Parameter
IDD
IDD(OP)
Quiescent Power Supply Current
Operating Power Supply Current
LM48824
Test Conditions
Typ
(3)
VIN = 0V, both channels active, RL = ∞
0.9
RL = ∞, Low THD mode
1.55
PO = 100µW, two channels in phase, 3dB
Crest Factor, RL = 32Ω + 15Ω
1.8
PO = 100µW, two channels in phase, 3dB
Crest Factor, RL = 32Ω + 15Ω,
Low THD mode
2.2
PO = 500µW, two channels in phase, 3dB
Crest Factor RL = 32Ω + 15Ω
3.1
PO = 500µW, two channels in phase, 3dB
Crest Factor RL = 32Ω + 15Ω,
Low THD mode
3.4
PO = 1mW, two channels in phase, 3dB
Crest Factor, RL = 32Ω + 15Ω
4.1
PO = 1mW, two channels in phase, 3dB
Crest Factor, RL = 32Ω + 15Ω,
Low THD mode
4.4
Limit (4)
Units
(Limits)
1.3
mA (max)
mA
2.5
mA (max)
mA
3.8
mA (max)
mA
4.9
mA (max)
mA
ISD
Shutdown Current
Shutdown Enabled, VSCL = VSDA = 1.8V
2.5
3.9
µA (max)
VOS
Output Offset Voltage
VIN = 0V
0.15
0.65
mV (max)
TWU
Wake Up Time
From Shutdown
AV
AV(MUTE)
2
Minimum Gain Setting
–59
–58
–60
dB (max)
dB (min)
Maximum Gain Setting
4
4.5
3.5
dB (max)
dB (min)
Gain
Mute Attenuation
RIN
Input Resistance
PO
Output Power
ms
–110
dB
AV = 4dB
AV = –59dB
24
64
20
80
kΩ (min)
kΩ (max)
f = 1kHz, THD+N = 1%
Two channels in phase, RL= 16Ω
37
30
mW (min)
f = 1kHz, THD+N = 1%
Two channels in phase, RL= 32Ω
29
23
mW (min)
RL = 16Ω
0.77
0.7
VRMS
(min)
RL = 32Ω
0.96
0.86
VRMS
(min)
RL = 32Ω + 15Ω
1.05
RL = 10kΩ
1.3
THD+N = 1%, Two Channels in Phase
VO
(1)
(2)
(3)
(4)
4
Output Swing
VRMS
1.1
VRMS
(min)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified
The Electrical Characteristics tables list specified specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at TA = +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not ensured.
Datasheet min/max specification limits are specified by test or statistical analysis.
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Electrical Characteristics VDD = 3.6V(1)(2) (continued)
The following specifications apply for AV = 0dB, RL = 32Ω, f = 1kHz, unless otherwise specified. Limits apply to TA = 25°C.
Parameter
Test Conditions
LM48824
Typ
(3)
Limit (4)
Units
(Limits)
f = 1kHz, Single Channel
THD+N
Total Harmonic Distortion + Noise
VO = 600mVRMS, RL = 16Ω
0.05
%
VO = 600mVRMS, RL = 16Ω,
Low THD Mode
0.03
%
VO = 800mVRMS, RL = 32Ω,
0.035
%
VO = 800mVRMS, RL = 32Ω,
Low THD Mode
0.02
%
VO = 900mVRMS, RL = 32Ω+ 15Ω
0.027
VO = 900mVRMS, RL = 32Ω+ 15Ω,
Low THD Mode
0.015
0.04
%(max)
%
VRIPPLE = 200mVP-P, Inputs AC GND, CIN = 1μF, input referred
PSRR
CMRR
XTALK
Power Supply Rejection Ratio
Common Mode Rejection Ratio
Crosstalk
SNR
Signal-to-Noise Ratio
∈OS
Output Noise
fRIPPLE = 217Hz
100
fRIPPLE = 1kHz
100
VRIPPLE = 1VP-P, fRIPPLE = 217Hz
60
RL ≥ 16Ω, PO = 5mW, f = 1kHz
80
70
dB (min)
RL ≥ 10kΩ, VOUT = 1VRMS, f = 1kHz
110
95
dB (min)
VOUT = 1VRMS, f = 1kHz
102
98
dB (min)
VOUT = 1VRMS, f = 1kHz,
Low THD Mode
105
AV = 4dB, A-Weighted Filter
8
AV = 4dB, A-weighted Filter, Low THD
Mode
7
94
dB (min)
dB
dB
dB
12
μV(max)
μV
Charge pump-only mode enabled
ROUT
Output Impedance
f < 40kHz
43
30
kΩ (min)
f = 6MHz
500
Ω (min)
f = 36MHz
75
Ω (min)
No Sustained Oscillations
CL
VOUT
Maximum Capacitive Load
Maximum Voltage Swing
with 5Ω series resistance
100
with no series resistance
100
pF
1.1
VRMS
(min)
Voltage applied to amplifier outputs in
charge pump-only mode
nF
1.0
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I2C Interface Characteristics VDD = 3.6V (1) (2)
The following specifications apply for AV = 0dB, RL = 16Ω, f = 1kHz, unless otherwise specified. Limits apply to TA = 25°C.
Parameter
(1)
(2)
(3)
(4)
6
Test Conditions
LM48824
Typ
(3)
Limit (4)
Units
(Limits)
t1
SCL Period
2.5
μs (min)
t2
SDA Setup Time
250
ns (min)
t3
SDA Stable Time
250
ns (min)
t4
Start Condition Time
250
ns (min)
t5
Stop Condition Time
250
ns (min)
VIH
Input High Voltage
1.2
V (min)
VIL
Input Low Voltage
0.6
V (max)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified
The Electrical Characteristics tables list specified specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at TA = +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not ensured.
Datasheet min/max specification limits are specified by test or statistical analysis.
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Typical Performance Characteristics
THD+N vs Frequency
VDD = 3.6V, RL = 16Ω, VO = 600VRMS
100
100
10
10
THD + N (%)
THD + N (%)
THD+N vs Frequency
VDD = 3.6V, RL = 16Ω, VO = 600VRMS
Low THD Mode
1
0.1
1
0.1
0.01
0.01
0.001
20
100
1k
0.001
20
10k 20k
100
10k 20k
Figure 3.
Figure 4.
THD+N vs Frequency
VDD = 3.6V, RL = 32Ω, VO = 800VRMS
Low THD Mode
THD+N vs Frequency
VDD = 3.6V, RL = 32Ω, VO = 800VRMS
100
100
10
10
1
0.1
0.01
1
0.1
0.01
0.001
20
100
1k
0.001
20
10k 20k
FREQUENCY (Hz)
100
1k
10k 20k
FREQUENCY (Hz)
Figure 5.
Figure 6.
THD+N vs Frequency
VDD = 3.6V, RL = 47Ω, VO = 900VRMS
Low THD Mode
THD+N vs Frequency
VDD = 3.6V, RL = 47Ω, VO = 900VRMS
100
100
10
10
THD + N (%)
THD + N (%)
1k
FREQUENCY (Hz)
THD + N (%)
THD + N (%)
FREQUENCY (Hz)
1
0.1
1
0.1
0.01
0.001
20
0.01
100
1k
10k 20k
0.001
20
FREQUENCY (Hz)
100
1k
10k 20k
FREQUENCY (Hz)
Figure 7.
Figure 8.
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Typical Performance Characteristics (continued)
THD+N vs Output Voltage
VDD = 3.6V, RL = 16Ω, f = 1kHz
Low THD Mode
THD+N vs Output Voltage
VDD = 3.6V, RL = 16Ω, f = 1kHz
10
10
THD + N (%)
100
THD + N (%)
100
1
1
0.1
0.1
200m
400m
0.01
100m
600m 800m 1
200m
Figure 9.
Figure 10.
THD+N vs Output Voltage
VDD = 3.6V, RL = 32Ω, f = 1kHz
Low THD Mode
THD+N vs Output Voltage
VDD = 3.6V, RL = 32Ω, f = 1kHz
100
100
10
10
1
1
0.1
0.01
100m
200m 300m 500m 700m 1
0.01
100m
2
200m 300m 500m 700m 1
Figure 11.
Figure 12.
THD+N vs Output Voltage
VDD = 3.6V, RL = 47Ω, f = 1kHz
Low THD Mode
THD+N vs Output Voltage
VDD = 3.6V, RL = 47Ω, f = 1kHz
100
10
10
THD + N (%)
100
1
0.1
0.01
100m
2
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
THD + N (%)
600m 800m 1
OUTPUT VOLTAGE (V)
0.1
1
0.1
200m 300m 500m 700m 1
2
OUTPUT VOLTAGE (V)
0.01
100m
200m 300m 500m 700m 1
2
OUTPUT VOLTAGE (V)
Figure 13.
8
400m
OUTPUT VOLTAGE(V)
THD + N (%)
THD + N (%)
0.01
100m
Figure 14.
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Typical Performance Characteristics (continued)
THD+N vs Output Power
VDD = 3.6V, RL = 16Ω, f = 1kHz
100
100
10
10
THD + N (%)
THD + N (%)
THD+N vs Output Power
VDD = 3.6V, RL = 16Ω, f = 1kHz
Low THD Mode
1
1
0.1
0.1
0.01
1m
2m
5m
10m
20m
0.01
1m
50m 100m
2m
OUTPUT POWER (W)
50m 100m
Figure 16.
THD+N vs Output Power
VDD = 3.6V, RL = 32Ω, f = 1kHz
Low THD Mode
THD+N vs Output Power
VDD = 3.6V, RL = 32Ω, f = 1kHz
100
100
10
10
1
1
0.1
0.1
0.01
1m
2m
5m
10m
20m
0.01
1m
50m 100m
2m
5m
20m
10m
50m 100m
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 17.
Figure 18.
Power Dissipation vs Output Power
VDD = 3.6V, RL = 16Ω, f = 1kHz
Power Dissipation vs Output Power
VDD = 3.6V, RL = 32Ω, f = 1kHz
80
140
TOTAL POWER DISSIPATION (mW)
Low THD Mode
TOTAL POWER DISSIPATION (mW)
20m
10m
Figure 15.
THD + N (%)
THD + N (%)
5m
OUTPUT POWER (W)
120
100
Normal Mode
80
60
40
20
Low THD Mode
70
60
50
Normal Mode
40
30
20
10
0
0
0
5
10
15 20
25 30
35
40
45
0
5
10
15
20
25
30
35
40
OUTPUT POWER/CHANNEL (mW)
OUTPUT POWER/CHANNEL (mW)
Figure 19.
Figure 20.
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Typical Performance Characteristics (continued)
Power Dissipation vs Output Power
VDD = 3.6V, RL = 47Ω, f = 1kHz
70
Low THD Mode
45
OUTPUT POWER/CHANNEL (mW)
TOTAL POWER DISSIPATION (mW)
50
40
Normal Mode
35
30
25
20
15
10
5
Output Power vs Supply Voltage
RL = 16Ω, f = 1kHz
60
50
THD+N = 10%
40
30
THD+N = 1%
20
10
0
0
5
10
15
20
25
30
2
35
2.5
4
4.5
5
5.5
Figure 21.
Figure 22.
Output Power vs Supply Voltage
RL = 32Ω, f = 1kHz
Output Power vs Supply Voltage
RL = 47Ω, f = 1kHz
6
40
OUTPUT POWER/CHANNEL (mW)
OUTPUT POWER/CHANNEL (mW)
3.5
SUPPLY VOLTAGE (V)
OUTPUT POWER/CHANNEL (mW)
50
3
45
40
THD+N = 10%
35
30
25
THD+N = 1%
20
15
35
THD+N = 10%
30
25
THD+N = 1%
20
15
2
2.5
3
3.5
4
4.5
5
5.5
6
2
SUPPLY VOLTAGE (V)
2.5
3
3.5
4
4.5
5
5.5
6
SUPPLY VOLTAGE (V)
Figure 23.
Figure 24.
Supply Current vs Supply Voltage No Load
CMRR vs Frequency
VDD = 3.6V, VRIPPLE = 1VP-P
RL = 32Ω
2
-56
-57
Low THD Mode
1.5
CMRR (dB)
SUPPLY CURRENT (mA)
1.75
1.25
Normal Mode
1
-59
-60
0.75
0.5
2
2.5
3
3.5
4
4.5
5
5.5
6
-61
10
100
1000
10000
100000
FREQUENCY (Hz)
SUPPLY VOLTAGE (V)
Figure 25.
10
-58
Figure 26.
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Typical Performance Characteristics (continued)
PSRR vs Frequency
VDD = 3.6V, VRIPPLE = 200VP-P
RL = 32Ω
Crosstalk vs Frequency
VDD = 3.6V, PO = 5mW
RL = 32Ω
-40
-20
-50
CROSSTALK (dB)
0
PSRR (dB)
-40
-60
-80
-60
-60
-80
-100
-120
10
-90
100
1000
10000
100000
-100
10
FREQUENCY (Hz)
100
1000
10000
100000
FREQUENCY (Hz)
Figure 27.
Figure 28.
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APPLICATION INFORMATION
I2C COMPATIBLE INTERFACE
The LM48824 is controlled through an I2C compatible serial interface that consists of a serial data line (SDA) and
a serial clock (SCL). The clock line is uni-directional. The data line is bi-directional (open drain). The LM48824
and the master can communicate at clock rates up to 400kHz. Figure 29 shows the I2C interface timing diagram.
Data on the SDA line must be stable during the HIGH period of SCL. The LM48824 is a transmit/receive slaveonly device, reliant upon the master to generate the SCL signal. Each transmission sequence is framed by a
START condition and a STOP condition (Figure 30). Each data word, device address and data, transmitted over
the bus is 8 bits long and is always followed by an acknowledge pulse (Figure 31). The LM48824 device address
is 1100000.
I2C BUS FORMAT
The I2C bus format is shown in Figure 31. The START signal, the transition of SDA from HIGH to LOW while
SCL is HIGH, is generated, alerting all devices on the bus that a device address is being written to the bus.
The 7-bit device address is written to the bus, most significant bit (MSB) first, followed by the R/W bit (R/W = 0
indicates the master is writing to the LM48824, R/W = 1 indicates the master wants to read data from the
LM48824). Data is latched into the device on the rising clock edge. Each address bit must be stable while SCL is
HIGH. After the last address bit is transmitted, the master device releases SDA, during which time, an
acknowledge clock pulse is generated by the slave device. If the LM48824 receives the correct address, the
device pulls the SDA line low, generating an acknowledge bit (ACK).
Once the master device registers the ACK bit, the 8-bit register address word is sent. Each data bit should be
stable while SCL is HIGH. After the 8-bit register address is sent, the LM48824 sends another ACK bit. Following
the acknowledgment of the register address, the 8-bit register data word is sent. Each data bit should be stable
while SCL is HIGH. After the 8-bit register data is sent, the LM48824 sends another ACK bit. Following the
acknowledgement of the register data word, the master issues a STOP bit, allowing SDA to go high while SCL is
high.
Figure 29. I2C Timing Diagram
SDA
SCL
S
P
START condition
STOP condition
Figure 30. Start and Stop Diagram
12
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SCL
SDA
START
MSB
DEVICE ADDRESS
LSB
ACK
R/W
MSB
REGISTER DATA
ACK
LSB
STOP
Figure 31. I2C Write Cycle
ack from slave repeated start
ack from slave
ack from slave data from slave ack from master
start MSB Chip Address LSB w ack MSB Register 0x00h LSB ack rs
MSB Chip Address LSB r ack MSB
start slave address = 1100000 w ack register address = 0x00h ack
slave address = 1100000 r ack
Data
LSB ack stop
SCL
SDA
rs
register 0x00h data
ack stop
Figure 32. Example I2C Read Cycle
Table 1. Device Address
Device
Address
B7
B6
B5
B4
B3
B2
B1
B0 (R/W)
1
1
0
0
0
0
0
X
Table 2. I2C Control Registers (1)
(1)
Register
Address
Register
Name
B7
B6
B5
B4
B3
B2
B1
B0
0x01h
MODE
CONTROL
HPL_EN
HPR_EN
0
0
0
0
THRM
SHDN
0x02h
VOLUME
CONTROL
MUTE_L
MUTE_R
VOL4
VOL3
VOL2
VOL1
VOL0
0
0x03h
OUTPUT
CONTROL
0
0
0
0
LOW_THD
0
HiZ_L
HiZ_R
0x04h
DEVICE
INFORMATIO
N (Read-Only)
0
1
0
0
0
0
0
0
All registers default to 0 on initial power-up except SHDN, MUTE_L, MUTE_R bits default to 1 at power-up.
Table 3. Mode Control Register
Bit
Name
B0
SHDN
B1
THRM
(Read Only)
B6
HPR_EN
B7
HPL_EN
Value
Description
0
Device enabled
1
Device disabled
0
Thermal-protection inactive
1
Thermal-protection active
0
Right channel amplifier disabled
1
Right channel amplifier enabled
0
Left channel amplifier disabled
1
Left channel amplifier enabled
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Table 4. Volume Control Register
Bit
Name
B5:B1
VOL4:VOL0
B6
MUTE_R
B7
Value
Description
These bits set the volume level. See Table 5.
MUTE_L
0
Right Channel Mute Disabled
1
Right Channel Mute Enabled
0
Left Channel Mute Disabled
1
Left Channel Mute Enabled
Table 5. Volume Control
14
Volume Step
VOL4
VOL3
VOL2
VOL1
VOL0
HP Gain (dB)
0
0
0
0
0
0
-59
1
0
0
0
0
1
-55
2
0
0
0
1
0
-51
3
0
0
0
1
1
-47
4
0
0
1
0
0
-43
5
0
0
1
0
1
-39
6
0
0
1
1
0
-35
7
0
0
1
1
1
-31
8
0
1
0
0
0
-27
9
0
1
0
0
1
-25
10
0
1
0
1
0
-23
11
0
1
0
1
1
-21
12
0
1
1
0
0
-19
13
0
1
1
0
1
-17
14
0
1
1
1
0
-15
15
0
1
1
1
1
-13
16
1
0
0
0
0
-11
17
1
0
0
0
1
-10
18
1
0
0
1
0
-9
19
1
0
0
1
1
-8
20
1
0
1
0
0
-7
21
1
0
1
0
1
-6
22
1
0
1
1
0
-5
23
1
0
1
1
1
-4
24
1
1
0
0
0
-3
25
1
1
0
0
1
-2
26
1
1
0
1
0
-1
27
1
1
0
1
1
0
28
1
1
1
0
0
1
29
1
1
1
0
1
2
30
1
1
1
1
0
3
31
1
1
1
1
1
4
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Table 6. Output Control Register
Bit
B0
B1
B3
Name
Value
HiZ_R
HiZ_L
LOW_THD
Description
0
Right channel high impedance mode disabled
1
Right channel high impedance mode enabled
0
Left channel high impedance mode disabled
1
Left channel high impedance mode enabled
0
LOW_THD mode disabled
1
LOW_THD mode enabled, improves overall THD
GENERAL DEVICE FUNCTION
The LM48824 integrates a high efficiency step down (buck) DC-DC switching regulator with a ground reference
headphone amplifier. The switching regulator delivers a constant voltage from an input voltage ranging from 2.4V
to 5.5V. The switching regulator uses a voltage-mode architecture with synchronous rectification, improving
efficiency and reducing component count.
The LM48824 headphone amplifier features TI’s ground referenced architecture that eliminates the large DCblocking capacitors required at the outputs of traditional single-ended headphone amplifiers. A low-noise
inverting charge pump creates a negative supply (HPVSS) from the positive supply voltage (VDD). The headphone
amplifiers operate from these bipolar supplies, with the amplifier outputs biased about GND. Because there is no
DC component on the output signals, the large DC-blocking, AC coupling capacitors (typically 220µF) are not
necessary, conserving board space, reducing system cost, and improving frequency response.
CLASS G OPERATION
Class G is a modification of some other class of amplifier (normally Class B or Class AB) to increase efficiency
and reduce power dissipation. Class G works off the fact that musical and voice signals have a high peak to
mean ratio with most of the signal content at low levels. To decrease power dissipation, Class G has multiple
voltage supplies. The LM48824 has two discrete voltage supplies at the output of the buck, 1.1V and 1.8V. When
the output reached the threshold to switch to the higher voltage rails, the rails will switch from 1.1V to 1.8V.
When the output falls below the required voltage rails for a set period of time, it will switch back to the lower rail
until the next time the threshold is reached. Power dissipation is greatly reduced for typical musical or voice
sources. The drawing below shows how a musical output may look. The green lines are the supply voltages at
the output of the buck converter.
HPVDD(HV)
HPVDD(LV)
0
HPVSS(LV)
HPVSS(HV)
Buck Converter Output
Power savings in Class G
+
Power dissipated in Class AB
Power dissipated in Class G
Figure 33. Class G Operation
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DIFFERENTIAL AMPLIFIER EXPLANATION
The LM48824 features a differential input stage, which offers improved noise rejection compared to a singleended input amplifier. Because a differential input amplifier amplifies the difference between the two input
signals, any component common to both signals is cancelled.
SYNCHRONOUS RECTIFIER
The buck converter in the LM48824 uses an internal NFET synchronous rectifier to reduce rectifier forward
voltage drop and associated power loss. Synchronous rectification provides a significant improvement in
efficiency whenever the output voltage is relative low compared to the voltage drop across an ordinary rectifier
diode and eliminating the need for the diode.
CURRENT LIMITING
A current limit of the buck converter in the LM48824 allows the device to protect itself and external components
during overload conditions.
PFM OPERATION
During PFM(Pulse-Frequency Modulation) operation, if the output voltage of the buck converter is below the
‘high’ PFM comparator threshold, the PMOS power switch is turned on. It remains on until the output voltage
reaches the ‘high’ PFM threshold or the peak current exceeds the IPFM level set for PFM mode. The typical peak
current in PFM mode is IPFM = 112mA + VDD/27Ω.
Once the PMOS power switch is turned off, the NMOS power switch is turned on until the inductor current ramps
to zero. When the NMOS zero-current condition is detected, the NMOS power switch is turned off. If the output
voltage is below the ‘high’ PFM comparator threshold, the PMOS switch is again turned on and the cycle is
repeated until the output reaches the desired level. Once the output reaches the ‘high’ PFM threshold, the NMOS
switch is turned on briefly to ramp the inductor current to zero and then both output switches are turned off and
the part enters an extremely low power mode.
Figure 34. PFM Operation
SOFT START
The buck converter has a soft-start circuit that limits in-rush current during start-up. During start-up the switch
current limit is increased in steps. Soft start is activated only if global SHDN goes from 1 to 0 after VDD reaches
2.7V. Soft start is implemented by increasing switch current limit in steps of 70mA, 140mA, 280mA, and 750mA
(typical switch current limit). The start-up time thereby depends on the output capacitor and load current of the
buck converter. Typical start-up times with a 10uF output capacitor and 150mA load is 280us and with 5mA load
is 240us.
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COMMON-MODE SENSE
The LM48824 features a ground (common mode) sensing feature. In noisy applications, or where the headphone
jack is used as a line out to other devices, noise pick up and ground imbalance can degrade audio quality. The
LM48824 COM input senses and corrects any noise at the headphone return, or any ground imbalance between
the headphone return and device ground, improving audio reproduction. Connect COM directly to the headphone
return terminal of the headphone jack (Figure 35). No additional external components are required. Connect
COM to GND if the common-mode sense feature is not in use.
AUDIO
INPUT
COM
COMMON MODE SENSE
EQUIVALENT CIRCUIT
Figure 35. COM Connection
SHUTDOWN FUNCTION
The LM48824 features individual amplifier shutdown control and a global device shutdown control.
Bit B0 (SHDN) of the MODE CONTROL register controls the global shutdown for the entire device. Set SHDN =
1 to put the device into current-saving shutdown mode, and set SHDN = 0 for normal operation. SHDN defaults
to 1 at power-up.
Bit B7 (HPL_EN) and Bit B6 (HPR_EN) of the MODE CONTROL register (register address 0x01h) controls the
left and right headphone amplifier shutdown respectively. Set HPL_EN = 0 to set the left channel headphone
amplifier to shutdown and set HPL_EN = 1 to enable left channel operation. Set HPR_EN = 0 to set the right
channel headphone amplifier to shutdown and set HPR_EN = 1 to enable right channel operation. The left and
right channel amplifier shutdowns operate individually.
The LM48824 has a shutdown time of 3ms to complete the internal shutdown sequence. After SHDN is set to 1,
any new I2C commands should only be sent after the 3ms shutdown time to ensure proper operation of the
device.
MUTE FUNCTION
The LM48824 features independent left and right channel mute functions.
Bit B7 (MUTE_L) and Bit B6 (MUTE_R) of the VOLUME CONTROL register (register address 0x02h) controls
the mute function of the left and right channels respectively. Set MUTE_L = 1 to mute the left channel and set
the MUTE_R = 1 to mute the right channel. Set MUTE_L = 0 and MUTE_R = 0 to disable mute on the respective
channels. MUTE_L and MUTE_R defaults to 1 at power-up.
LOW THD+N MODE
The LM48824 features a Low THD mode that reduces THD+N to improve audio qaulity. Set B3 (Low_THD) of
the OUTPUT CONTROL register (register address 0x03h) to 1 to enable the Low THD mode. There is a
quiescent and operating current increase in Low THD mode. See Electrical Characteristics and Typical
Performance Characteristics for reference.
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PROPER SELECTION OF EXTERNAL COMPONENTS
INDUCTOR SELECTION
There are two main considerations when choosing an inductor; the inductor saturation current and the inductor
current ripple should be small enough to achieve the desired output voltage ripple. Different saturation current
rating specifications are followed by different manufacturers so attention must be given to details. Saturation
current ratings are typically specified at 25°C, ratings at the maximum ambient temperature of application should
be requested from the manufacturer. Shielded capacitors are preferred since these capacitors radiate less noise.
Inductors with low DCR should also be considered to minimize the efficiency.
Inductor value involves trade-offs in performance. Larger inductors reduce inductor triple current, which typically
means less output voltage ripple (for a given size of output capacitor).
REGULATOR INPUT CAPACITOR SELECTION (C3)
A ceramic input capacitor of 1µF, 6.3V is sufficient for most applications. Place the input capacitor as close as
possible to the VDD pin of the device. A larger value may be used for improved input voltage filtering. Use X7R or
X5R types; do not use Y5V. DC bias characteristics of ceramic capacitors must be considered when selecting
case sizes like 0805 and 0603.
REGULATOR OUTPUT CAPACITOR SELECTION (C4)
A low ESR ceramic output capacitor of 10µF, 6.3V is sufficient for most applications. Use X7R or X5R types; do
not use Y5V. DC bias characteristics of ceramic capacitors must be considered when selecting case sizes like
0805 and 0603. DC bias characteristics vary from manufacturer to manufacturer and dc bias curves should be
requested from them as part of the capacitor selection process.
CHARGE PUMP CAPACITOR SELECTION
Use low ESR ceramic capacitors (less than 100mΩ) for optimum performance.
CHARGE PUMP FLYING CAPACITOR (C1)
The flying capacitor (C1) affects the load regulation and output impedance of the charge pump. A C1 value that
is too low results in a loss of current drive, leading to a loss of amplifier headroom. A higher valued C1 improves
load regulation and lowers charge pump output impedance to an extent. Above 2.2µF, the RDS(ON) of the charge
pump switches and the ESR of C1 and C2 dominate the output impedance. A lower value capacitor can be used
in systems with low maximum output power requirements.
CHARGE PUMP HOLD CAPACITOR (C2)
The value and ESR of the hold capacitor (C2) directly affects the ripple on CPVSS. Increasing the value of C2
reduces output ripple. Decreasing the ESR of C2 reduces both output ripple and charge pump output impedance.
A lower value capacitor can be used in systems with low maximum output power requirements.
Amplifier Input Capacitor Selection
Input capacitors may be required for some applications, or when the audio source is single-ended. Input
capacitors block the DC component of the audio signal, eliminating any conflict between the DC component of
the audio source and the bias voltage of the LM48824. The input capacitors create a high-pass filter with the
input resistors RIN. The -3dB point of the high-pass filter is found using the equation below.
f = 1 / 2πRINCIN
(Hz)
(1)
Where the value of RIN is given in the Electrical Characteristics VDD = 3.6V.
High-pass filtering the audio signal can be beneficial for some applications. When the LM48824 is using a singleended source, power supply noise on the ground is seen as an input signal. Setting the high-pass filter point
above the power supply noise frequencies, 217Hz in a GSM phone, for example, filters out the noise such that it
is not amplified and heard on the output. Capacitors with a tolerance of 10% or better are recommended for
impedance matching and improved CMRR and PSRR.
18
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SINGLE-ENDED AUDIO AMPLIFIER CONFIGURATION
The LM48824 is compatible with single-ended sources. Figure 36 shows the typical single-ended applications
circuit. Input coupling capacitors are required for single-ended configuration.
2.4V to 5.5V
C3
1 PF
VDD
3.3 PH
2.3V to 5.5V
SW
REGULATOR
CONTROL
C4
10 PF
5 k:
5 k:
HPVDD
C1P
SDA
I2C INTERFACE
SCL
C1
2.2 PF
CHARGE PUMP
C1N
HPVSS
C2
2.2 PF
CIN
Single-Ended
Audio Input
Single-Ended
Audio Input
1 PF
INL+
INL-
OUTL
CIN
1 PF
1 PF
CIN
INR+
OUTPUT LEVEL
DETECT
VOLUME
CONTROL
OUTR
INRCIN
1 PF
COM
GND
Figure 36. Single-Ended Input Configuration
PCB LAYOUT CONFIGURATION
Table 7. LM48824TM Demoboard Bill of Materials
Designator
Quantity
C1
1
10µF ±10% 16V 500Ω Tantalum Capacitor (B Case) AVX TPSB106K016R0500
Description
C2
1
1μF ±10% 16V X5R Ceramic Capacitor (603) Panasonic ECJ-1VB1C105K
C3, C8, C9
3
2.2μF ±10% 10V X5R Ceramic Capacitor (603) Panasonic ECJ-1VB1A225K
C4 – C7
4
1μF ±10% 16V X7R Ceramic Capacitor (1206) Panasonic ECJ-3YB1C105K
R1, R2
2
5kΩ ±5% 1/10W Thick Film Resistor (603) Vishay CRCW06035R1KJNEA
L1
1
3.3μH ± 30% 1.2A Inductor Murata LQM2MPN3R3NG0L
J1
1
Stereo Headphone Jack
J2
1
16-Pin Boardmount Socket 3M 8516-4500JL
JU1
1
3 Pin Header
JU2
1
2 Pin Header
LM4822TM
1
LM48824TM (16-Bump microSMD)
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Demoboard Schematic
Figure 37. LM48824 Demoboard Schematic
20
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Figure 38. Top Silkscreen
Figure 39. Top Layer
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Figure 40. Layer 2 (GND)
Figure 41. Layer 3 (VDD)
22
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Figure 42. Bottom Layer
Figure 43. Bottom Silkscreen
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Revision History
24
Rev
Date
Description
1.0
08/06/09
Initial released of the full datasheet.
1.01
08/31/09
Text edits.
D
05/02/2013
Changed layout of National Data Sheet to TI format.
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PACKAGE OPTION ADDENDUM
www.ti.com
2-May-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
LM48824TM/NOPB
ACTIVE
DSBGA
YFQ
16
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
GL6
LM48824TMX/NOPB
ACTIVE
DSBGA
YFQ
16
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
GL6
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
8-May-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
LM48824TM/NOPB
DSBGA
YFQ
16
250
178.0
8.4
LM48824TMX/NOPB
DSBGA
YFQ
16
3000
178.0
8.4
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1.85
2.01
0.76
4.0
8.0
Q1
1.85
2.01
0.76
4.0
8.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-May-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM48824TM/NOPB
DSBGA
YFQ
LM48824TMX/NOPB
DSBGA
YFQ
16
250
210.0
185.0
35.0
16
3000
210.0
185.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
YFQ0016xxx
D
0.600±0.075
E
TMD16XXX (Rev A)
D: Max = 1.715 mm, Min =1.655 mm
E: Max = 1.715 mm, Min =1.655 mm
4215081/A
NOTES:
A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
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12/12
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