ADC701 SHC702 ® 16-Bit 512kHz SAMPLING A/D CONVERTER SYSTEM FEATURES APPLICATIONS ● CONVERSION RATE: to 512kHz Over Temp ● NO MISSING CODES AT 16 BITS ● MEDICAL IMAGING ● SONAR ● PROFESSIONAL AUDIO RECORDING ● AUTOMATIC TEST EQUIPMENT ● HIGH PERFORMANCE FFT SPECTRUM ANALYSIS ● ULTRASOUND SIGNAL PROCESSING ● SPURIOUS-FREE DYNAMIC RANGE: 107dB ● LOW NONLINEARITY: ±0.0015% ● SELECTABLE INPUT RANGES: ±5V, ±10V, 0 to +10V, 0 to +5V, –10V to 0 ● HIGH SPEED DATA ACQUISITION ● REPLACES DISCRETE MODULAR ADCs ● LOW POWER DISSIPATION: 2.8W Typical Including Sample/Hold ● METAL AND CERAMIC DIP PACKAGES DESCRIPTION The ADC701 is a very high speed 16-bit analog-todigital converter based on a three-step subranging architecture. Outstanding dynamic performance is achieved with the SHC702 companion sample/hold amplifier. Both devices use hybrid construction for applications where reliability, small size, and low power consumption are especially important. Excellent linearity and stability are assured through use of a new ultra-precise monolithic D/A converter and a low-drift reference circuit. Custom monolithic op amps provide very high bandwidth and low noise in all sections of the analog signal path. Logic is CMOS/TTL compatible and is designed for maximum flexibility. 1kΩ Analog Input Flash Encoder PGA 1kΩ – DAC + Buffer Output Buffer Input Input Scaling Network – Timing and Control Logic Data Output Switch Drive + 10V Ref SHC702 Sample/Hold Command ADC701 Convert Command InternationalAirportIndustrialPark • MailingAddress:POBox11400,Tucson,AZ85734 • StreetAddress:6730S.TucsonBlvd.,Tucson,AZ 85706 • Tel:(520)746-1111 • Twx:910-952-1111 Internet:http://www.burr-brown.com/ • FAXLine:(800)548-6133(US/CanadaOnly) • Cable:BBRCORP • Telex:066-6491 • FAX:(520)889-1510 • ImmediateProductInfo:(800)548-6132 © 1988 Burr-Brown Corporation PDS-877D Printed in U.S.A. May, 1997 SPECIFICATIONS ELECTRICAL (ADC701 ONLY) At TA = +25°C, 500kHz sampling rate, ±VCC = ±15V, ±VDD1 = ±5V, +VDD2 = +5V, and five-minute warmup in a convection environment, unless otherwise noted. ADC701JH PARAMETER CONDITIONS MIN TYP ADC701KH MAX RESOLUTION MIN TYP 16 MAX UNITS * Bits INPUTS ANALOG Voltage Ranges Unipolar Bipolar 0 to +5V Range 0 to +10V, –10 to 0, ±5V Ranges ±10V Range All Ranges Resistance Capacitance DIGITAL Logic Family Convert Command Pulse Width 2.45 4.9 9.8 Start Conversion t = Conversion Period 0 to +5, 0 to +10, –10 to 0 ±5, ±10 2.5 2.55 * * 5 5.1 * * 10 10.2 * * 5 * TTL-Compatible CMOS Rising Edge t – 50 * 50 * * * V V kΩ kΩ kΩ pF * ns * * * * * * * * % % %/V mV mV %FSR/V %FSR(3) %FSR TRANSFER CHARACTERISTICS ACCURACY Gain Error(1) Power Supply Sensitivity of Gain Input Offset Error(1) Power Supply Sensitivity of Offset Integral Linearity Error(2) Differential Linearity Error(2) No Missing Codes Noise ±0.03 ±0.1 ±0.03 ±0.1 ±0.005 ±0.1 ±1 ±3 ±5 ±10 ±0.006 ±0.1 ±0.002 ±0.003 ±0.0006 ±0.0012 Guaranteed 0.6 0 to +10V Range ±10V Range All Ranges, All Supplies 0 to +10V Range ±10V Range All Ranges, All Supplies RSOURCE ≤ 50Ω * * * * * * ±0.0012 * Guaranteed * LSB rms CONVERSION CHARACTERISTICS Sample Rate Conversion Time(4) Unadjusted Unadjusted DC 512 1.5 1.45 * * * kHz µs * * * * V V ns * OUTPUTS DIGITAL Logic Family Data Coding Unipolar Ranges Bipolar Ranges IOL ≤ 3.2mA IOH ≤ 80µA Both Edges Logic “0” Levels (VOL) Logic “1” Levels (VOH) Data Valid Setup Time Before Strobe INTERNAL REFERENCE Voltage Current Available to External Loads TTL-Compatible CMOS Straight Binary Offset Binary 0.4 * * 4 28 0.1 4.9 37 RLOAD ≥ 5kΩ +9.995 2 +10.000 5 +10.005 * * * * * V mA Operating +14.25 –14.25 +4.75 –4.25 +4.25 +15 –15 +5 –5 +5 25 33 45 37 133 1.95 +15.75 –15.75 +5.25 –6 +5.25 30 45 55 50 150 2.3 * * * * * * * * * * * * * * * * * * * * * * * * * * * V V V V V mA mA mA mA mA W +55 ±15 ±5 ±5 0 +70 * * * ±0.5 ±0.3 °C ppm/°C ppm FSR/°C ppm FSR/°C ppm/°C ppm/°C * * ppm/°C ns/°C kHz POWER SUPPLY REQUIREMENTS Supply Voltages: +VCC –VCC +VDD1 –VDD1 +VDD2 Supply Currents: +ICC –ICC +IDD1 –IDD1 +IDD2 Power Dissipation Operating Nominal Voltages PERFORMANCE OVER TEMPERATURE Specification Temperature Range Gain Error Input Offset Error TA Min to TA Max All Ranges All Unipolar Ranges All Bipolar Ranges Integral Linearity Error(2) Differential Linearity Error(2) No Missing Codes Reference Output Drift Drift of Conversion Time Sample Rate Unadjusted Unadjusted +15 ±10 ±1 ±1 ±0.2 ±0.05 Typical ±3 +3 DC * Same specifications as ADC701JH. ® ADC701/SHC702 2 +4 512 * * * * * Guaranteed * * * SPECIFICATIONS ELECTRICAL (SHC702 ONLY) At TA = +25°C, 500kHz sampling rate, ±VCC = ±15V, +VDD1 = +5V, and five-minute warmup in a convection environment, unless otherwise noted. SHC702JM PARAMETER CONDITIONS MIN TYP MAX UNITS ±10.25 0.98 ±11 1 3 1.02 V kΩ pF INPUTS (Without Input Buffer) ANALOG Voltage Range Resistance Capacitance DIGITAL Logic Family Input Loading LSTTL 2 LSTTL Loads TRANSFER CHARACTERISTICS ACCURACY Gain Gain Error Linearity Error Offset Error Charge Offset (Pedestal) Error Droop Rate Dynamic Nonlinearity Power Supply Sensitivity RSOURCE = 0Ω RSOURCE = 0Ω Sample Mode Sample Mode Sample/Hold Mode, RSOURCE ≤ 50Ω Hold Mode Sample/Hold Mode Offset Plus Charge Offset, All Supplies –1 ±0.02 ±0.0003 ±0.5 ±0.5 ±0.2 ±0.0005 ±0.003 10V Step to ±150µV 5V Step to ±150µV to ±150µV 600 500 120 20 10 150 3.1 2 0.001 ±0.1 ±3 ±5 ±2 V/V % %FSR mV mV µV/µs %FSR %FSR/V DYNAMIC CHARACTERISTICS Acquisition Time Time(5) Sample-to-Hold Settling Aperture Delay Time Aperture Uncertainty (Jitter) Slew Rate Small Signal Bandwidth Full-Power Bandwidth Feedthrough Rejection VIN = ±1V VIN = ±10V Hold Mode, 10Vp-p Square Wave Input 25 ns ns ns ns ps rms V/µs MHz MHz % OUTPUT Voltage Range Output Current Short Circuit Protection Output Impedance RLOAD ≥ 1kΩ ±10.25 ±40 ±11 RLOAD = 0Ω DC Indefinite 0.01 VIN = ±10V RSOURCE ≤ 10kΩ 1013 3 ±2 ±0.3 ±11 V mA 0.1 Ω ±15 ±1.5 Ω pF pA mV V INPUT BUFFER CHARACTERISTICS INPUT Impedance Bias Current Offset Voltage Voltage Range DYNAMIC CHARACTERISTICS Slew Rate Full-Power Bandwidth Settling Time OUTPUT Output Current Short Circuit Protection ±10.25 20 35 570 1.7 V/µs kHz µs ±15 ±20 Indefinite mA +13.5 –13.5 +4.75 +15 –15 +5 33 18 5 790 VIN = ±10V 10V Step to ±150µV RLOAD = 0Ω POWER SUPPLY REQUIREMENTS Voltage: +VCC –VCC +VDD1 Current: +ICC –I CC +IDD1 Power Dissipation Operating Operating Nominal Voltages +16.5 –16.5 +5.25 40 25 10 950 V V V mA mA mA mW +70 ±5 ±30 ±80 ±50 ±15 °C ppm/°C µV/°C µV/°C µV/µs µV/°C PERFORMANCE OVER TEMPERATURE Specification Sample/Hold Sample/Hold Sample/Hold Droop Rate Buffer Offset Temperature Range Gain Error Offset Error Charge Offset Error TA Min to TA Max RSOURCE = 0Ω RSOURCE ≤ 50Ω RSOURCE ≤ 50Ω Error RSOURCE ≤ 10kΩ 0 ±1 ±10 ±10 ±3 NOTES: (1) Adjustable to zero. Tested and guaranteed for 0 to +10V and ±10V ranges only. (2) Peak-to-peak based on 99.9% of all codes. (3) FSR means fullscale range and depends on the input range selected. (4) ADC conversion time is defined as the time that the Sample/Hold must remain in the Hold mode; i.e., the duration of the Sample/Hold command. This time must be added to the Sample/Hold acqusition time to obtain the total system throughput time. (5) Given for reference only — this time overlaps with the ADC701 conversion time and does not affect system throughput rate. ® 3 ADC701/SHC702 SPECIFICATIONS ELECTRICAL (COMBINED ADC701/SHC702) At TA= +25°C, 500kHz sampling rate, ±VCC = ±15V, ±VDD1 = ±5V, +VDD2 = +5V, and five-minute warmup in a convection environment, ±5V input range, unless otherwise noted. PARAMETER Sample Rate Dynamic Nonlinearity Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) Two-Tone Intermodulation Distortion (IMD) Signal-to-Noise Ratio (SNR) Total Power Dissipation CONDITIONS MIN Unadjusted DC fIN = 20kHz (–0.3dB) fIN = 199kHz (–0.2dB) fIN = 20kHz (–0.3dB) fIN = 199kHz (–12dB) f1 = 195kHz (–6.5dB), f2 = 200kHz (–6.5dB) f1 = 195kHz (–12.5dB), fF2 = 200kHz (–12.5dB) fIN = 5kHz (–0.5dB) Operating ADC701 PIN ASSIGNMENTS TYP ±0.002 –103 –82 107 94 –81 –86 93 2.8 MAX UNITS 512 kHz %FSR dB dB dB dB dBC dBC dB W 3.25 ADC701 ORDERING INFORMATION PIN NO. DESCRIPTION PIN NO. DESCRIPTION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Bit 1/9 (Bit 1 = MSB) Bit 2/10 Bit 3/11 Bit 4/12 Bit 5/13 Bit 6/14 Bit 7/15 Bit 8/16 Clip Detect Output +VDD2 (+5V) Digital Common (Digital) Data Strobe High/Low Byte Select Convert Command Sample/Hold Control(3) Common (Digital) Common (Digital) Clock Adjust Common (Digital) +VDD2 (+5V) Digital 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 –VDD1 (–5V) Analog Common (Analog) +VDD1 (+5V) Analog Reference (Gain) Adjust +10V Reference Output(2) Common (Reference) DNC Common (Analog) +10V Reference Input(2) Input D (1) Input C (1) Common (Signal) Input B (1) Input A (1) –VCC (–15V) Analog Common (Power) +VCC (+15V) Analog DNC(4) Offset Adjust Offset Adjust ADC701 PACKAGE DRAWING NUMBER(1) ADC701JH ADC701KH Metal and Ceramic Metal and Ceramic 230 230 ±VCC .......................................................................................................................................... ±18V ±VDD1, +VDD2 ............................................................................... ±7V, +7V Analog Input ...................................................................................... ±VCC Logic Input .......................................................... –0.5V to (+VDD2 + 0.3V) Logic Output .................................................................................. ±25mA Case Temperature ........................................................................ +150°C Junction Temperature ................................................................... +165°C Storage Temperature ..................................................... –65°C to +165°C Power Dissipation ................................................................................. 3W Stresses above these ratings may permanently damage the device. NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ® ADC701/SHC702 H ADC701 ABSOLUTE MAXIMUM RATINGS PACKAGING INFORMATION PACKAGE ) Basic Model Number Performance Grade Code K: 0°C to +70°C Ambient Temperature J: +15°C to +55°C Ambient Temperature Package Code H: Metal and Ceramic NOTES: (1) Refer to Input Connection Table. (2) Reference Input is normally connected to Reference Output, unless an external 10V reference is used. (3) Sample/Hold Control goes high to activate Hold mode. (4) DNC = Do Not Connect. PRODUCT ( 4 ADC701 OUTPUT CODING NOMINAL INPUT VOLTAGE TO ADC701 (Multiply by –1 for SHC702 Input Voltage) (1LSB ≈05µV ±5V RANGE (1LSB ≈153µV) OUTPUT CODE (1 = Logic High) MSB LSB CLIP DETECT < –76µV 0V +153µV < –10.000153V –10V –9.999695V < –5.000076V –5V –4.999847V 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 1 0 0 –3/4FS –1/2FS –1/4FS +1.25V +2.5V +3.75V –7.5V –5V –2.5V –3.75V –2.5V –1.25V 0010 0000 0000 0000 0100 0000 0000 0000 0110 0000 0000 0000 0 0 0 –1LSB Mid-Scale +1LSB +4.999847V +5V +5.000153V –305µV 0V +305µV –153µV 0V +153µV 0111 1111 1111 1111 1000 0000 0000 0000 1000 0000 0000 0001 0 0 0 +1/4FS +1/2FS +3/4FS +6.25V +7.5V +8.75V +2.5V +5V +7.5V +1.25V +2.5V +3.75V 1010 0000 0000 0000 1100 0000 0000 0000 1110 0000 0000 0000 0 0 0 +FS –2LSB +FS – 1LSB Overrange +9.999695V +9.999847V > +9.999924V +9.99939V +9.999695V > +9.999847V +4.999695V +4.999847V > +4.999924V 1111 1111 1111 1110 1111 1111 1111 1111 1111 1111 1111 1111 0 0 1 INPUT LEVEL (Exact Center of Code) 0–10V RANGE (1LSB ≈153µV) ±10V RANGE Underrange –FS –FS + 1LSB SHC702 ORDERING INFORMATION SHC702 PIN ASSIGNMENTS PIN NO. DESCRIPTION PIN NO. DESCRIPTION 1 2 3 4 5 6 7 8 9 10 11 12 Sample/Hold Output NC(3) NC NC NC NC NC NC +VDD1 (+5V) Analog Common (Digital) Hold Input(1) Hold Input(1) 24 23 22 21 20 19 18 17 16 15 14 13 +VCC (+15V) Analog Common (Power) –VCC (–15V) Analog Common (Analog) NC NC NC Buffer Amp Input(2) NC Common (Signal) Buffer Amp Output Analog Input SHC702 SHC702 ABSOLUTE MAXIMUM RATINGS ±Vcc .................................................................................................... ±18V +VDD1 ................................................................................................... +7V Analog and Buffer Inputs ................................................................... ±VCC Outputs .......................................................... Indefinite Short to Common Logic Inputs ........................................................... –0.5V to (+VDD1 + 0.3V) Case Temperature ........................................................................ +150°C Junction Temperature ................................................................... +165°C Storage Temperature ...................................................... –65°C to +165°C Power Dissipation .............................................................................. 1.5W Stresses above these ratings may permanently damage the device. PACKAGING INFORMATION PACKAGE PACKAGE DRAWING NUMBER(1) SHC702JM 24-Pin 037 M Basic Model Number Performance Grade Code J: 0°C to +70°C Ambient Temperature Package Code M: Metal NOTES: (1) Hold mode is activated only when pin 12 is low and pin 11 is high. For normal use with ADC701, pin 12 is grounded and pin 11 is connected to ADC701 Sample/Hold control (ADC701 pin 15). (2) If the buffer amp is not used, pin 17 should be grounded. (3) NC = No Internal Connection. PRODUCT J NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 5 ADC701/SHC702 TYPICAL DYNAMIC PERFORMANCE (ADC701/SHC702)(1) FULL-SCALE SINEWAVE RESPONSE, f IN = 100kHz 0 –20 –20 –40 –40 Amplitude (dB) Amplitude (dB) FULL-SCALE SINEWAVE RESPONSE, f IN = 20kHz 0 –60 –80 2 V –100 3 V 4 V 5 V 7 V –60 –100 9 V –120 4 9V 6 V V 5 V –120 –140 –140 0 50 100 150 200 250 0 50 Frequency (kHz) Input Frequency Fundamental –0.3 dB 2nd Harmonic –107.5 dB 3rd Harmonic –111.5 dB 19.9890136719 kHz 4th Harmonic –115.6 dB 5th Harmonic –111.2 dB 6th Harmonic –124.5 dB Input Frequency Fundamental –0.5 dB 2nd Harmonic –89.1 dB 3rd Harmonic –90.5 dB –20 –40 –40 Amplitude (dB) –20 –60 2 3V V 7 V 200 250 100.982666016 kHz 4th Harmonic –102.5 dB 5th Harmonic –110.2 dB 6th Harmonic –106.8 dB –60 –80 1 43 V VV 2 V 6 5 V V –100 –120 –120 –140 –140 0 50 100 150 200 0 250 50 Input Frequency Fundamental –0.7dB 2nd Harmonic –81.4dB 3rd Harmonic –89.4dB 100 150 200 Frequency (kHz) Frequency (kHz) Frequency 1 Frequency 2 f1 –6.8dB f2 –6.3dB 1 > f1 +f2 –87.7dB 2 > f1 –f2 –88.8dB 199.005126953 kHz 4th Harmonic –111.5dB 5th Harmonic –97.0dB 6th Harmonic –112.5dB 194.976806641 kHz 199.981689453 kHz 3 > f1 +2f2 –96.0dB 4 > 2f 1 +f2 –96.8dB 5 > f1 –2f2 –104.9dB 6 > 2f 1 –f2 –109.0dB NOTE: (1) For figures above, sampling rate = 500.0000000000kHz. 16,384 point FFT, non-windowed. Noise floor limited by synthesized generators. DIFFERENTIAL NONLINEARITY OF ALL CODES, 19.6 MILLION SAMPLES 2 1 DNL (LSB) Amplitude (dB) 0 –100 150 TWO-TONE INTERMODULATION RESPONSE, f IN = 195kHz and 200kHz 0 5 V 100 Frequency (kHz) FULL-SCALE SINEWAVE RESPONSE, f IN = 200kHz –80 32 VV 8 7 V V –80 0 –1 –2 0 32767 Codes ® ADC701/SHC702 6 65535 250 THEORY OF OPERATION The ADC701 input voltage is converted to a current through the input scaling resistors (Figure 2), and this current is applied to the summing junction (virtual ground) of error amplifier A1. The current output of the DAC (0 to 2mA) is also applied to the summing point. If bipolar operation is selected, the 10V reference output is applied to input D, creating a 1mA offset current which sums with the input current. The ADC701 uses a three-step subranging architecture, meaning that the analog-to-digital conversion is performed in three passes which constitute coarse, medium and fine approximations of the input signal. Refer to Figures 1 and 2 for simplified block diagrams of the system. Before the input signal is presented to the ADC, it must be sampled with high linearity and low aperture error by the sample/hold amplifier. 1kΩ In the SHC702, the sampling switch is placed at the summing junction (virtual ground) of a high speed FET amplifier (Figure 1). This arrangement maintains constant charge injection independent of the signal amplitude, which is critically important for good linearity performance. The sampling switch itself is a high speed DMOS FET whose gate is driven from a fast-slewing control signal, thus minimizing the time aperture between the fully closed (sample mode) and the fully open (hold mode) states of the switch. The signal voltage is held across the feedback capacitor, forcing the op-amp to maintain a constant output voltage for the duration of the A/D conversion. Feedthrough from the input, already low due to the MOSFET’s low capacitance, is further reduced by clamping the summing point to ground with another FET. Ref Out Ref Input In C Input D 5kΩ 5kΩ Input A Input Scaling Network CHOLD Analog Input 1kΩ – + Hold Analog Output Switch and Clamp Drive Signal Conditioning Hold FIGURE 1. Simplified Block Diagram of the SHC702. Input B 5kΩ High Speed PGA 5kΩ Rf Attenuator – + DAC A1 Buffer X32 Error Amp X32 10V Reference DAC Register PGA Control Lines Adder (Digital Error Correction) ADC Output Register VIN 7 Bit Flash ADC Timing and Control Logic Flash ADC Reference Generator ADC Output Convert Command Hold Command Data Strobe FIGURE 2. Simplified Block Diagram of the ADC701. ® 7 ADC701/SHC702 INSTALLATION AND OPERATING INSTRUCTIONS At the beginning of each conversion, the DAC is reset to mid-scale so that its output current is exactly 1mA. This 1mA is subtracted from the input signal current. The difference current flows through Rf and appears as an error voltage at the output of A1. The ADC701/SHC702 combination is designed to be easy to use in a wide variety of applications, without sacrificing flexibility of the analog and digital interface. During the first pass, the programmable gain amplifier (PGA) is set to unity gain, which matches the error voltage range to the input range of the flash ADC. The error signal is digitized to 7-bit resolution by the flash ADC, creating a coarse approximation of the digital output value, which is then applied to the DAC. SHC702 INTERFACE The connection diagram (Figure 3) shows the basic hookup. At the SHC702 input, the user may opt to connect the builtin FET buffer amplifier. The buffer is most useful in multichannel applications where the signal bandwidth is less than 100kHz. In those applications, it serves to isolate the multiplexer output from the 1kΩ input impedance of the sample/ hold. For higher frequency applications and for any system that does not require the very high impedance, the best results (lowest noise and distortion) will be achieved by driving the SHC702’s analog input directly. If the buffer is not used, its input should be grounded to avoid random noise pickup and saturation of the buffer op amp. Since the DAC output is now approximately equal to the input signal current, the remaining difference current flowing through Rf is small—ideally less than 1/128 of full scale, which is due to the built-in quantizing uncertainty of the 7bit flash ADC. However, other sources of error (e.g., integral and differential nonlinearity of the flash ADC, gain and offset of the PGA, settling and noise errors throughout the signal path) cause the possible error range to be significantly greater. In fact, the ADC701 is designed to handle remainder signals up to 1/32 of full scale, which is four times the “ideal” value. Only two connections are required between the SHC702 and the ADC701: SHC702 analog output to ADC701 input(s) and the digital Hold Command from the ADC701 to the SHC702. As always, it is best to avoid routing these analog and digital lines along parallel traces. Although the placement of the SHC702 relative to the ADC is not extremely critical, one good approach is to mount the SHC along one end of the ADC package as shown in Figure 4. This minimizes the length of the interconnections and keeps the digital lines well away from sensitive analog signals. Therefore, the PGA is set during the second pass to a gain of 32, allowing the small remainder signal to match the full range of the flash ADC. This is again digitized to 7-bit resolution and added to the previous result to create the “medium” approximation of the input signal. Because the full-scale range of the flash represents 1/32 of the input signal’s full range, the 7-bit flash output is shifted right by 5 bits before being added to the original 7-bit “coarse” result, creating a 12-bit word. There is an overlap of two bits because the two least significant bits of the first-pass result correspond to the two most significant bits of the secondpass result. This overlap in the adder is called “digital error correction”—the mechanism that allows nonideal remainders from the first pass to be corrected in the second pass. ADC701 INPUT CONNECTIONS The ADC input network has four separate terminals, allowing many different input ranges. These should be connected as indicated in Table I. Most users will take advantage of the ADC701’s built-in reference circuit, which has very low noise and excellent temperature stability. To use the internal reference, it is only necessary to connect pin 36 (Reference Output) to pin 32 (Reference Input). To use an external 10V reference (to cause the ADC gain to track a system reference, for example), pin 36 is left unconnected and the external reference is applied to pin 32. If required, the ADC701 will typically accommodate a five to ten percent variation in the 10V reference. External references should have very low noise to avoid degrading the excellent signalto-noise ratio (SNR) of the ADC701. The 12-bit approximation is applied once again to the DAC, causing the remaining difference current to become yet smaller. For the third pass, the PGA’s gain is increased by another factor of 32, and the remainder is again digitized by the flash ADC. At this point in the conversion, all of the necessary data has been latched and it is no longer necessary to hold the analog signals from the sample/hold or the DAC. From a systems perspective, the conversion is now complete because the sample/hold is released to begin acquiring the next input sample and the DAC is reset to mid-scale for the next conversion. Meanwhile, the final result from the flash is added to the previous 12-bit result. Again there is a two-bit overlap to allow for error correction. The adder output is monitored to prevent a digital “rollover” condition, so that the ADC clips properly at the signal extremes. The upper sixteen bits of the final adder result are stored in the ADC’s output register, ready to be presented in byte-sequential form at the eight output data lines. The overrange or “clip” condition can also be detected externally by monitoring pin 9. Refer to the section on ADC701 Digital I/O for further detail. INPUT RANGE 0 to +10V ±10V ±5V –10V to 0 0 to +5V D B B C CONNECT Ref In TO — Input D Input D Input C and Input D — TABLE I. ADC701 Input Connection Table. ® ADC701/SHC702 CONNECT V IN TO Input A and Input Input A Input A and Input Input A and Input Input B and Input 8 +15V –15V +5V + + + 24 22 +15V Connect for Buffered Input 17 VIN (1) Connect for Direct Input 11 Hold 14 Buffer Output 13 Analog Input SHC702 Analog Output Hold 12 Optional Offset Adjust 500kΩ (6) +5V Buffer Input = Analog Ground Plane (5) Optional Gain Adjust 20kΩ 9 –15V Common 15 21 23 10 +15V –15V +5V + 30kΩ –5V + + + 31 32 Input Ref D In 36 Ref Out 37 Ref Adj 35 39 Ref Com 33 29 25 Analog Signal Power Commons Com Com 22 21 24 Offset Adjust Offset Adjust 26 +15V 38 –15V 40 +5V –5V Input A(2) Input B Start Convert 1 27 28 ADC701 Convert Command In Sample/Hold Command Out 15 14 Bit 1/9 Bit 2/10 Bit 3/11 Bit Bit 4/12 5/13 Bit 6/14 Bit 7/15 Bit Data 8/16 Strobe 1 2 3 4 6 7 8 5 12 Clip Detect Digital Common 9 11 16 17 19 High/Low Byte Clock Select Adj +5V 13 18 10 +5V 20 + 1k Ω Optional Clock Adjust +5V D 74HC574 Optional (4) 74HC574 Octal Flip-Flop (3) Q Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 9 Bit 8 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15 Bit 16 Clip Detect (Latched) NOTES: (1) For lowest distortion at high input frequencies the non-buffered option should be used. If the buffer is not used, its input should be grounded. (2) Shown connected for ±5V input range. Refer to Input Connection Table for other options. (3) If the Clip Detect feature is used, then the signal may be latched with a simple D type flip-flop as shown. See the section on ADC701 Digital I/O for additional applications information. (4) The second octal flip-flop is recommended but optional — it provides added digital signal isolation and buffering, and also permits three-state logic output compatibility. (5) All commons should be connected to the analog ground plane. Refer to the section on “Power and Ground Connections.” (6) The Offset Adjust circuit shown provides an adjustment range of approximately ±0.25% FSR. FIGURE 3. ADC701/SHC702 Connection Diagram. ® 9 ADC701/SHC702 OFFSET, GAIN AND CONVERSION SPEED ADJUSTMENTS (OPTIONAL) to the ground plane connections. For example, the ADC701 output data lines will sink current (statically and/or dynamically) when in the low state. This current comes from the power supply that runs the interface logic, and so must return to that supply’s ground. If the ground termination is placed such that this digital current will flow away from the ADC701, then the existing ground plane will suffice to carry the current. On the other hand, if the ground termination must be placed such that the digital current flows across the ADC or SHC layout, then it would be advisable to break the analog ground plane under the package (to stop the flow of current across the package) and to provide a separate trace (several centimeters wide) on another PC board layer to carry the digital return current from pins 11 and 19 to the termination point. If the ADC701 must interface into a fairly noisy digital environment, then another approach is to keep the first layer of latches and/or buffers connected to the ADC701 power and ground planes, so that the ADC itself is connected to “quiet” circuits with short return paths. This transfers the interface problem to the outputs of the latches, where it can be managed with less impact on the analog components. Adjustment of the reference voltage is the most straightforward way to adjust the ADC gain. For the internal reference, this is accomplished by connecting a 20kΩ potentiometer as shown in Figure 3. This will provide a gain trim range of about ±3%. It is also possible to use external series or parallel resistance in the input network, but that is more cumbersome and usually will degrade the gain stability over temperature due to tempco (temperature coefficient) mismatches among the resistors. ADC offset may be adjusted by connecting a 500kΩ potentiometer to pins 21 and 22, with the wiper connected through a series 30kΩ resistor to ground as shown in Figure 3. This will provide an offset trim range of approximately ±0.25% FSR. For a larger trim range of offset or gain, it is recommended that trims be accomplished elsewhere in the system. The Clock Adjust input (pin 18) is intended primarily for small adjustments of the conversion time. However, this will rarely be necessary because the ADC701 is guaranteed to convert up to 512kHz over the specified temperature range without external clock adjustment. PHYSICAL INSTALLATION The packages may be soldered directly into a PC board or mounted in low-profile machined pin sockets with good results. Use of tall (long lead length) sockets, adapters or headers is not recommended unless a local ground plane and bypass capacitors can be mounted directly under the packages. POWER AND GROUND CONNECTIONS Experience with testing and applying the ADC701 shows that it will perform well in most board layouts, provided that appropriate care is taken with grounding and bypassing. Power supplies may be shared between the ADC701, SHC702 and other analog circuitry without difficulty. It is recommended that each power pin be locally bypassed to the ground plane with a high quality tantalum capacitor of at least 1µF. If at all possible, power should be derived from well-regulated linear supplies—switching power supplies will require much more effort for proper decoupling and are not recommended for this or any high performance wideband analog system. In a room-temperature environment or inside an enclosure with moderate airflow, the ADC701 and SHC702 normally do not require heat-sinking. However, to keep the devices running as cool as possible, it is helpful to install a thin heattransfer plate under the packages to conduct heat into the ground plane. The plate may be made from metal (copper, aluminum or steel) or from a special heat-conductive material such as Sil-Pad(1). The Sil-Pad material has the advantage of being electrically insulating and somewhat pliable, so that it will tend to distribute pressure evenly and conform to the package—an advantage in systems where the board may be flexed or subjected to vibration. The +5V Digital supply pins, though not as sensitive to noise as the +5V Analog pin, should nonetheless be kept as quiet as possible. If the system digital supply is noisy, then it is best to use the system +5V analog supply for all of the +5V connections on the ADC701 and SHC702 rather than trying to separate them. If only one +5V supply is available and it is shared with other system logic, then extra bypassing and/or supply filtering may be required. PC BOARD LAYOUT An optimized layout has been designed for the DEMADC701-E demonstration fixture. For information concerning the demo board and the layout, contact your local sales representative. The –5V supply will operate with any voltage between – 4.75 and –6V. If –5V is not available from the system supplies, then an industry-standard 7905 regulator may be used to derive –5V from the –15V supply. All ground pins on both the ADC701 and the SHC702 should be connected directly to a common ground plane. This is true for both analog and digital grounds. However, it is also helpful to recognize where the digital ground currents flow in the system, and to provide PC board return paths for potentially troublesome digital currents in addition ® ADC701/SHC702 10 ADC701 Digital I/O OPTIONS FOR STROBED OUTPUT There are several ways in practice to implement the logic interface. Figure 3 shows the simplest configurations. In order to convert the ADC701’s byte-sequential data into 16bit parallel form, the minimum requirement is for one single octal flip-flop, such as a 74HC574 or equivalent. This will latch the first byte on the rising edge of the ADC701 Data Strobe. Then the second byte becomes valid, and all 16 bits may be strobed to the outside system on the falling edge of the Data Strobe. Refer to the timing diagram, Figure 4. The conversion process is initiated by a rising edge on the Convert Command input. This will immediately bring the sample/hold command output to a logic high state (Hold mode). After the ADC701 conversion is completed (approximately 1.5µs after the convert command edge), the Sample/Hold Command falls to a low state, enabling the sample/hold to begin acquisition of the next input sample. However, the ADC701 internal clock continues to run so that the output data may be processed. For better noise isolation of the ADC701 from the digital system, or if full three-state capability is required for the 16 output lines, a second octal flip-flop can be added as shown in the dashed lines of Figure 3. This will also require an inverter to convert the falling Data Strobe edge into a rising clock edge for the second flip-flop IC. There are two methods of reading data from the ADC: 1. Strobed Output—This will usually be the easiest and fastest method. The data are presented sequentially as high and low bytes of the total 16-bit word. The sequence High-Low or Low-High is controlled by the state of the High/Low Byte Select input. The first byte is valid on the rising edge of the Data Strobe output; the second byte is valid on the falling edge. If it is desirable to have all 16 output lines change simultaneously (for example when driving a D/A converter), then a third octal flip-flop (not shown in Figure 3) may be added to re-latch the output of the first byte. By driving that device’s clock also from the inverted Data Strobe, fully synchronous switching of the 16 output bits will be achieved. 2. Polled output—With this method, data strobes will occur as described above, but they are ignored by the user. Instead, the user waits until the Data Strobe output falls, and then manually selects high and low output data by means of the High/Low Byte Select input. This polling procedure may be carried out during the subsequent ADC conversion cycle, but two precautions must be observed: First, the user should avoid switching the High/Low Byte Select immediately before or after the next convert command. This will prevent digital switching noise from coupling into the system at the instant of analog sampling. Second, the polling sequence must be completed before the ADC begins to strobe out data from the subsequent conversion. USING THE CLIP DETECT OUTPUT The ADC701 provides a built-in Clip Detect signal on pin 9 which indicates an ADC overrange or underrange condition. The Clip Detect signal is only valid when the High Byte becomes valid as shown in Figure 4. Therefore, the simplest way to latch the Clip Detect signal is to provide an extra flipflop which is clocked on the same strobe edge as the High Byte flip-flop. Such a setup is illustrated in Figure 3. The Clip Detect signal remains at logic 0 under normal conditions, and indicates a clip condition by rising to a logic 1. Start Conversion N ADC701 Convert Command (CC) Start Conversion N+1 50ns min 50ns min CC to Hold delay 18ns typ Hold Command to SHC702 Hold Mode 1.45µs typ Sample Mode Data Outputs for Pin 13 = Low Low Byte, (4) Data N – 1 High Byte,(3) Data N Low Byte,(4) Data N Data Outputs for Pin 13 = High High Byte,(3) Data N – 1 Low Byte,(4) Data N High Byte,(3) Data N (2) (1) Data Strobe Output (1) 110ns typ 1.55µs typ NOTES: (1) Setup Time 28ns min, 37ns typ. (2) Hold Time 30ns min, 73ns typ. (3) High Byte refers to ADC bits 1 - 8, the most significant 8 bits. Also, the Clip Detect signal on pin 9 is valid simultaneously with High Byte. (4) Low Byte refers to ADC bits 9 - 16, the least significant bits. FIGURE 4. ADC701 Interface Timing Diagram. ® 11 ADC701/SHC702 TESTING THE ADC701/SHC702 The latched version of Clip Detect may be used to generate an interrupt to the user’s system computer, which would then launch a service routine to generate the appropriate alarms or corrective action. Another possible application would be to stretch the pulse using a monostable so that it would be easily visible when driving an LED warning lamp. The ADC701 and SHC702 together form a very high performance converter system and careful attention to test techniques is necessary to achieve accurate results. Spectral analysis by application of a Fast Fourier Transform (FFT) to the ADC digital output is the best method of examining total system performance. Attempts to evaluate the system by analog reconstruction through a D/A converter will usually prove unsatisfactory; assuming that the static and dynamic distortions of the D/A can be brought below the required level (–110dB), the performance will still be beyond the range of presently available spectrum analyzers. In some systems, it may be desirable to provide separate latched outputs for Underrange and Overrange. These conditions may be separately detected by using simple logic to implement the boolean equations: Underrange = Clip Detect AND Anybit Overrange = Clip Detect AND Anybit Even when the analysis is done using FFT techniques, several key issues must be addressed. First, the parameters of the FFT need to be adequate to perform the analysis and extract meaningful data. Second, the proper selection of test frequencies is critical for good results. Third, the limitations of commercial signal generators must be considered. These three points are addressed in later sections. Finally, the test board layout must follow the recommendations discussed on pages 8 through 10. where “Anybit” is any one of the data output bits. The Underrange and Overrange signals would then be latched into two separate flip-flops. A simple solution using a single ’74 dual flip-flop and a single ’00 quad NAND provides enough logic to implement the logic equations, with a spare NAND gate left over to use for creating the inverted Data Strobe signal. USING THE ADC701 AT MAXIMUM CONVERSION RATES The ADC701 is guaranteed to accept Convert commands at a rate of DC to 512kHz over the specified operating temperature range. At a conversion rate of 500kHz, the total throughput time of 2µs allows for the 1.5µs ADC conversion time plus 500ns for the digital output timing and sample/ hold acquisition time. DYNAMIC PERFORMANCE DEFINITIONS 1. Total Harmonic Distortion (THD): 10 log 2. Signal-to-Noise Ratio (SNR): If the user tries to exceed the maximum conversion rate by a large amount, the Convert Command of conversion N+1 will occur before the Data Strobe has fallen from conversion N. In such a situation, the ADC701 will simply ignore every other Convert command so the actual conversion rate will become half of the Convert command rate. Otherwise, the conversion will proceed normally. Note that the ADC timing slows down at high temperatures, so the frequency at which this occurs will vary with temperature—although it is still guaranteed to be greater than 512kHz over the specified temperature range. 10 log Sinewave Signal Power Noise Power 3. Intermodulation Distortion (IMD): 10 log IMD Product Power (RMS sum; to 3rd-order) Sinewave Signal Power 4. Spurious-Free Dynamic Range (SFDR): Another consideration for operation at very high rates is that the sample/hold acquisition time becomes shorter as the conversion rate is increased. Users will note that the available acquisition time becomes less than 550ns at rates above 500kHz, which is less than the typical SHC702 acquisition time for a 10V step to 150µV accuracy. However, the signal degradation is gradual as the acquisition time is shortened— even at 512kHz, there is enough time to acquire a 5V step to better than 500µV. Also, most signal processing environments do not contain full-power signals at the Nyquist frequency, but rather show a rolloff of signal power at high frequencies. If the ability to acquire extremely large input changes at extremely high conversion rates is of paramount importance, the user may elect to use a Burr-Brown model SHC803 sample/hold instead—it is pin compatible with the SHC702 and provides much faster acquisition time at the expense of some extra noise and higher distortion at low input frequencies. 10 log Power of Peak Spurious Component Sinewave Signal Power IMD is referred to the larger of the test signals f1 or f2—not to the total signal power, which would result in a number approximately 6dB “better.” The zero frequency bin (DC) is not included in these calculations—it represents total offset of the ADC, SHC and test equipment and is of little importance in dynamic signal processing applications. ® ADC701/SHC702 Harmonic Power (first 9 harmonics) Sinewave Signal Power 12 FFT Parameters Accurate FFT analysis of 16-bit systems requires adequate computing hardware and software. The FFT length (number of points) should be relatively large—at least 4K and preferably 16K or larger. There are several reasons for this: SELECTION OF TEST FREQUENCIES The FFT (and any similar DSP operation) treats the total time-domain record length as one cycle of an infinitely long periodic signal. Therefore, if the end of the sampled record does not match up smoothly with the beginning, the output spectrum will contain serious errors known as leakage or truncation error(2). This well-known problem is usually handled by applying a windowing function to the timedomain samples, suppressing the worst effects of the mismatch. However, the most often used windows such as Hanning, Hamming, raised cosine, etc., are completely inadequate for 16-bit ADC testing. More sophisticated functions such as the four-sample Blackman-Harris window(3) will provide much better results, although there still will be obvious spreading of the spectral lines. 1. The converter itself has 64K codes. Ideally, the test would guarantee that all codes are tested at least once. Practically speaking, however, that would require immensely long FFTs (>>64K points) or averaging of a large number of smaller FFTs. By using an FFT length of 4K or greater and proper selection of the test frequencies, a very good statistical picture of the ADC performance will be obtained which shows the effect of any defects in the transfer function. 2. The noise floor of the output spectrum is not low enough if less than 4K points are taken. Shorter FFTs have fewer bins to cover the output spectrum, so a larger fraction of the total system noise appears in each bin. Although the SNR of the ADC701/SCH702 system is in the range of –93dB, the noise level of the available generators may increase the total measured noise power to –80dB. Every doubling of the FFT length will spread the noise power among twice as many bins, resulting in a 3dB reduction of the spectral noise floor. In order to resolve spurious components that are at the level of –110dB, an average noise floor of less than –113dB would be barely adequate. This requires at least 2048 bins in the output half-spectrum, corresponding to a 4K-point FFT. Even at this level, it will be difficult or impossible to separate higher order harmonics in the ADC701 response from the average noise level, indicating that longer FFTs are desirable. The most successful approach is to eliminate the need for windowing by properly selecting the test signal frequency (or frequencies) in relation to the ADC sampling frequency(4). If the time sample contains exactly an integer number of cycles, then there is no mismatch or truncation error. Another point to consider is that the sampling frequency should not be an exact integer multiple of the signal frequency, which would tend to reduce the number of different ADC codes that are tested and also tend to artificially concentrate quantization error in the harmonics of the test signal. Both of these criteria are met by choosing an FFT length which is a power of two (the most standard and fastest to compute) and choosing a test frequency which causes an exact odd integer number of cycles to appear in the time record. In software, this selection can be accomplished very easily: 1. Determine the desired sampling frequency fS. 3. Following the guidelines for test frequency selection which are outlined in the next section, it becomes clear that longer FFTs allow a much wider choice of test frequencies without concern for sophisticated data windowing or code coverage problems. 2. Determine the desired input signal frequency fAPPROX. 3. Determine the FFT length N, which should be a power of 2 (e.g., 4096 or 16384). 4. Divide fAPPROX by fS, multiply the quotient by N, and round the result to the nearest odd integer. This is M, the number of cycles in the time record. Besides the consideration of FFT length, it is important to realize that the FFT calculations must be performed with high-precision arithmetic. The use of 32-bit fixed or floating point calculations will generally be inadequate because the noise floor due to calculation errors alone will interfere with the ADC performance data. Unfortunately, this consideration precludes the use of most DSP accelerator boards and similar hardware. In order to preserve the full dynamic range of the ADC output, it is best to use standard 64- or 80-bit arithmetic. To avoid excessively long calculation times, the FFT algorithm should be written in an efficiently compiled language and make use of techniques such as trigonometric look-up tables in software and dedicated floating-point coprocessors in hardware. There are several commercial software packages available from Burr-Brown and others that meet these requirements. 5. Multiply M by fS and divide by N to obtain the exact input signal frequency fACTUAL. SIGNAL GENERATOR CONSIDERATIONS To suppress leakage effects, the calculated ratio of fS to fACTUAL must be precisely maintained during the test. This requirement is met easily by the use of synthesized signal generators whose reference oscillators can be locked together. Other possible approaches include external phase locking of non-synthesized generators and direct digital synthesis techniques. If it is not possible to use phase-locked signals, then a Blackman-Harris window may be used as mentioned previously. ® 13 ADC701/SHC702 As noted previously, the combined noise contributions of the signal generator and sampling clock generator far exceed the SNR of the ADC701/SHC702 itself. The SNR has been measured separately by applying a highly filtered sinewave to the input, resulting in typical SNR performance of –93dB. However, the filters employed to achieve this low-noise test stimulus are found to cause reactive loading of the signal source which results in increased distortion. Therefore it is best to separate the tests for SNR from those for THD and IMD, unless a suitably pure and low-noise signal can be generated. Another key issue is the purity of both the signal and sampling frequency generators. The sampling clock’s phase noise (jitter) will act as another source of SNR degradation. This is not serious as long as the jitter is random and the noise sidebands contain no sharp peaks. The HP3325 synthesizer is suitable for this purpose. The input signal generator will require more attention because its distortion will usually be greater than that of the ADC701/SHC702. Presently, the lowest distortion synthesized generator is the Brüel & Kjær Model 1051 (or 1049). This is suitable for testing the system in the audio range. The upper frequency limit of the B&K synthesizer is 200kHz. Above 20kHz, the distortion becomes a limiting factor, and low-pass filters must be inserted into the signal path to reduce the harmonic and spurious content. Figures 5 and 6 show block diagrams of FFT test setups for the ADC701 and SHC702, summarizing the placement of the major components discussed above. The Typical Dynamic Performance section shows typical results obtained from testing the ADC701/SHC702 at a 500kHz conversion rate, using 16K samples for the FFT analysis. Start Conversion N Start Conversion N+1 ADC701 Convert Command (CC) 50ns min 50ns min CC to Hold delay 18ns typ Hold Mode 1.45µs typ Hold Command to SHC702 Sample Mode Data Outputs for Pin 13 = Low Low Byte, (4) Data N – 1 High Byte,(3) Data N Low Byte,(4) Data N Data Outputs for Pin 13 = High High Byte,(3) Data N – 1 Low Byte,(4) Data N High Byte,(3) Data N (2) (1) Data Strobe Output 1.55µs typ (1) 110ns typ NOTES: (1) Setup Time 28ns min, 37ns typ. (2) Hold Time 30ns min, 73ns typ. (3) High Byte refers to ADC bits 1 - 8, the most significant 8 bits. Also, the Clip Detect signal on pin 9 is valid simultaneously with High Byte. (4) Low Byte refers to ADC bits 9 - 16, the least significant bits. FIGURE 5. FFT Test Configuration for Single-Tone Testing. ® ADC701/SHC702 14 HISTOGRAM TESTING The FFT provides an excellent measure of harmonic and intermodulation distortion. Low-order spurious products are primarily caused by integral nonlinearity of the SHC and ADC. The influence of differential linearity errors is harder to distinguish in a spectral plot—it may show up as highorder harmonics or as very minor variations in the overall appearance of the noise floor. verter. In practice 10 to 20 million samples will demonstrate good results for a 16-bit system and expose any serious flaws in the DL performance. If the memory incrementing hardware can keep pace with the ADC701, then 20 million samples can be accumulated in well under one minute. The last figure on page six shows the results of a 19.6 million point histogram taken at an input frequency of 1kHz. A more direct method of examining the differential linearity (DL) performance is by using the popular histogram test method (5). Application of the histogram test to the ADC701/ SHC702 is relatively straightforward, though once again extra precision is required for a 16-bit system compared to 8- or 12-bit systems. Basically, this means that a very large number of samples are required to build an accurate statistical picture of each code width. If a histogram is taken using only one million points, then the average number of samples per code is less than fifteen. This is inadequate for good statistical confidence, and the resulting DL plot will look considerably worse than the actual performance of the con- HP3325A Frequency Synthesizer NOTES: 1. Available from Bergquist, 5300 Edina Industrial Blvd., Minneapolis, MN 55435 (612) 835-2322. 2. Brigham, E. Oran, The Fast Fourier Transform, Englewood Cliffs, N.J.: PrenticeHall, 1974. 3. Harris, Fredric J., “On the Use of Windows for Harmonic Analysis with the Discrete Fourier Transform”, Proceedings of the IEEE, Vol. 66, No. 1, January 1978, pp 5183. 4. Halbert, Joel M. and Belcher, R. Allan, “Selection of Test Signals for DSP-Based Testing of Digital Audio Systems”, Journal of the Audio Engineering Society, Vol. 34, No. 7/8, July/August, 1986, pp 546-555. 5. “Dynamic Tests for A/D Converter Performance”, Application Bulletin AB-133, Burr-Brown Corporation, Tucson, AZ, 1985. +2.8V +0.2V Convert Command Phase-Locked Brüel & Kjær Type 1051 Synthesizer Analog Input Low-Pass Filter ADC701 & SHC702 Under Test 600Ω TTL Latches 74HC574 – or – Crystal Filter High-Speed SRAM 64KB x 16 HP330 Series 9000 Computer FIGURE 6. FFT Test Configuration for Two-Tone (Intermodulation) Testing. ® 15 ADC701/SHC702