AKM AK7600VF 2/6-channel audio codec with digital eq Datasheet

[AK7600]
AK7600
2/6-Channel Audio CODEC with Digital EQ
GENERAL DESCRIPTION
AK7600 is a CODEC (2ch ADC, 6ch DAC) with a delay line memory and digital filters such as EQ. This
device operates in master mode and the internal sampling rate is 44.1kHz. It supports 5.0V single input
and the integrated regulator generates the internal voltage. The 2-channeled ADC achieves dynamic
rage of 97dB single end inputs, and 6-channeled DAC achieves 102dB single end outputs. The delay line
memory covers 36ms in total. Time alignment of 6m or less is possible since the delay line memory can
store for 18ms data for both left and right channels. A car audio system can be built easily 5-bands EQ
and time alignment functions.
FEATURES
1. 2ch 24bit ADC
- 64times Over Sampling
- Linear Phase Digital Anti-Alias Filter
- Single-ended input
- S/(N+D): 90dB
- DR, S/N: 97dB
- Digital HPF for AC coupling
2. 6ch 24bit DAC
- 128times Over Sampling
- 8times 24bit Digital filter
- Single-ended output
- S/(N+D): 90dB
- DR, S/N: 102dB
3. Digital Processing
- 5Band EQ×2ch (Second-order IIR-filter setting is also available)
- Delay line memory control
Maximum delay time:
Max 36ms / Lch 18ms, Rch 18ms (1input and 3outputs for each channel)
Adjustable output time (1/fs step)
- X’Over filter: 2step 2nd-order IIR Filter for Each channel of Delay line memory
- Spectrum analyzer: 7Band
68Hz, 160Hz, 400Hz, 1kHz, 2.5kHz, 6.3kHz,16kHz
- Soft Mute
- Zero Detect Function
4. Master Clock
- Master Mode: 256fs
5. μP Interface: I2C Bus (Ver 1.0, 400kHz mode)
6. Power Supply
- Analog: AVDD = 4.5 ∼ 5.5V
- Digital: DVDD = 4.5 ∼ 5.5V
7. Power Consumption: 52mA (fs=44.1kHz)
8. Ta = - 40 ∼ 85°C
9. Package: 30VSOP(0.65mm pitch)
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[AK7600]
■ Block Diagram
DZF
AINL
AINR
ADC
5Band EQ
nd
(2 IIR x 5)
Delay
2nd IIR x 2
Control
/ch
Function
2nd IIR x 2
VREFH
VCOM
DAC1
DAC2
/ch
2nd IIR x 2
DAC3
/ch
PDN
XTI
XTO
SpeAna
Filter
(2nd IIR x 1stIIR)
X7
SDA
SCL
AOUT1L
AOUT1R
SDTO1
AOUT2L
AOUT2R
SDTO2
AOUT3L
AOUT3R
SDTO3
CLKO
BICK
LRCK
TSTI
VSS1
AVDD
DVDD
VSS2
REF18
VSS4
VSS3
Figure 1. Block Diagram
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[AK7600]
■ Ordering Guide
-40 ∼ +85°C
30pin VSOP(0.65mm pitch)
Evaluation board for AK7600
AK7600VF
AKD7600
■ Pin Layout
TSTI
1
30
VSS2
REF18
2
29
XTO
VSS4
3
28
XTI
VCOM
4
27
SDTO3
AINL
5
26
SDTO2
AINR
6
25
SDTO1
AVDD
7
24
LRCK
VSS1
8
23
BICK
VREFH
9
22
DVDD
AOUT1L
10
21
CLKO
AOUT1R
11
20
SCL
AOUT2L
12
19
SDA
AOUT2R
13
18
VSS3
AOUT3L
14
17
PDN
AOUT3R
15
16
DZF
AK7600
Top
View
Figure 2. Pin Layout
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[AK7600]
PIN FUNCTION
No.
Pin Name
I/O
Function
Test Pin
1
TSTI
I
This pin should be connected to VSS1.
2
REF18
O
Internal regulator 1.8V Output pin
3
VSS4
Ground Pin, 0V
4
VCOM
O
VCOM pin
5
AINL
I
ADC Input pin Lch.
6
AINR
I
ADC Input pin Rch
7
AVDD
Analog Power Supply Pin 4.5~5.5V
8
VSS1
Ground Pin, 0V
9
VREFH
Positive Voltage Reference Input Pin, AVDD
10 AOUT1L
O
DAC1 Lch Output pin.
11 AOUT1R
O
DAC1 Rch Output pin
12 AOUT2L
O
DAC2 Lch Output pin
13 AOUT2R
O
DAC2 Rch Output pin
14 AOUT3L
O
DAC3 Lch Output pin
15 AOUT3R
O
DAC3 Rch Output pin
16 DZF
O
Zero detect pin
Power-Down & Reset Pin
17 PDN
I
When “L”, the AK7600 is powered-down and the control registers are reset to default
state.
18 VSS3
Ground Pin 0V
19 SDA
I/O Control Data Input Pin : SDA (I2C Bus) (Note 2)
20 SCL
I
Control Data Clock Pin : SCL (I2C Bus)
21 CLKO
O
Master Clock Output Pin
22 DVDD
Digital Power Supply 1 Pin, 4.5~5.5V
23 BICK
O
Output Audio Serial Data Clock Pin
24 LRCK
O
Output Channel Clock Pin
25 SDTO1
O
Audio Serial Data Output 1 Pin
26 SDTO2
O
Audio Serial Data Output 2 Pin
27 SDTO3
O
Audio Serial Data Output 3 Pin
28 XTI
I
X’tal Input Pin
29 XTO
O
X’tal Output Pin
30 VSS2
Ground Pin, 0V
Note 1. All digital input pins are never to be left float.
Note 2. Input mode when powered-down.
■Handling of Unused Pin
The unused I/O pins should be processed appropriately as below
Classification
Analog
Digital
Pin Name
AOUT1L, AOUT1R, AOUT2L, AOUT2R,
AOUT3L, AOUT3R, XTO
TSTI
BICK, LRCK, CLKO, SDTO1, SDTO2,
SDTO3
MS0999-E-00
Setting
These pins should be open.
This pin should be connected to VSS1.
These pins should be open.
2008/09
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[AK7600]
ABSOLUTE MAXMUM RATING
(VSS1=VSS2=VSS3=VSS4=0V; Note 3)
Parameter
Symbol
min
max
Units
Power Supplies
Analog
AVDD
-0.3
6.0
V
Digital
DVDD
-0.3
6.0
V
Input Current (any pins except for supplies)
IIN
mA
±10
Analog Input Voltage
VINA
-0.3
AVDD+0.3
V
Digital Input Voltage
VIND
-0.3
DVDD+0.3
V
Ambient Temperature (power applied)
Ta
-40
85
°C
Storage Temperature
Tstg
-65
150
°C
Note 3. All indicated voltages are with respect to ground VSS1, VSS2, VSS3 and VSS4 must be connected to the analog
ground plane.
Note 4. Analog input pins are AINL and AINR.
Note 5. Digital input pins are TSTI, SDA, SCL and XTI.
WARNING: Operating at or beyond these limits may result in permanent damage to the device. Normal operation is not
guaranteed at these critical conditions.
RECOMMENDED OPERATING CONDITIONS
(VSS1=VSS2=VSS3=VSS4 =0V; Note 3)
Parameter
Symbol
min
typ
AVDD
4.5
5.0
Power Supplies Analog
Digital
DVDD
4.5
5.0
(Note 6)
max
5.5
5.5
Units
V
V
Note 6. AVDD and DVDD must be the same voltage. The power up sequence between AVDD and DVDD is not critical
but the PDN pin must be “L” until all power supplies are ON, then put the PDN pin to “H”. All power supplies
of the AK7600 are must be ON. Do not turn any power supply off (means the same voltage as ground or
floating) independently. When using the AK7600 with I²C bus, the power supply of the AK7600 must not be
turned off unless the power supplies of the surrounding device are turned off.
* AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet.
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[AK7600]
ANALOG CHARACTERISTICS
(Ta=25°C; AVDD=5.0V, DVDD =5.0V; VSS1=VSS2=VSS3=VSS4=0V; VREFH=AVDD, fs=44.1kHz; BICK=64fs;
Signal Frequency=1kHz; 24bit Data; Measurement Frequency=20Hz∼20kHz at 44.1kHz, ; unless otherwise specified)
Parameter
min
typ
max
Units
ADC Analog Input Characteristics (single inputs)
Resolution
24
Bits
S/(N+D)
fs=44.1kHz
-1dBFS
83
90
dB
BW=20kHz
-60dBFS
35
DR
(-60dBFS with A-weighted)
90
97
dB
S/N
(A-weighted)
90
97
dB
Interchannel Isolation
90
110
dB
Interchannel Gain Mismatch
0
0.5
dB
Gain Drift
20
ppm/°C
Input Voltage
AIN=0.65xVREFH
3.09
3.25
3.41
Vpp
Input Resistance
22
45
kΩ
Power Supply Rejection
(Note 7)
50
dB
DAC Analog Output Characteristics (single outputs)
Resolution
24
Bits
S/(N+D)
fs=44.1kHz
-1dBFS
90
dB
BW=20kHz
-60dBFS
39
DR
(-60dBFS with A-weighted)
102
dB
S/N
(A-weighted)
102
dB
Interchannel Isolation
90
110
dB
Interchannel Gain Mismatch
0
0.5
dB
Gain Drift
20
ppm/°C
Output Voltage
AOUT=0.65xVREFH
3.09
3.25
3.41
Vpp
Load Resistance
(AC load)
5
kΩ
Load Capacitance
30
pF
Power Supply Rejection
(Note 7)
50
dB
ADC to DAC Characteristics (single outputs)
Resolution
24
Bits
S/(N+D)
fs=44.1kHz
-1dBFS
80
87
dB
BW=20kHz
-60dBFS
34
DR
(-60dBFS with A-weighted)
87
96
dB
S/N
(A-weighted)
87
96
dB
Note 7. PSR is applied to AVDD and DVDD with 1kHz, 50mVpp. This is the value of convoluted sinusoidal voltage of
1kHz and 50mVpp when the VREFH pin is held +5V.
Parameter
Power Supplies
Power Supply Current
Normal Operation (PDN pin = “H”)
AVDD
fs=44.1kHz
DVDD
fs=44.1kHz
Power-down mode (PDN pin = “L”)
AVDD+DVDD
(Note 8)
min
typ
max
Units
46
6
69
9
mA
mA
300
450
µA
Note 8. The AK7600 is not operating. This value is when all the digital input pins including clocks are held to VSS2.
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[AK7600]
FILTER CHARACTERISTICS
(Ta= -40 ∼ +85°C; AVDD=4.5∼ 5.5V, DVDD=4.5∼ 5.5V)
Parameter
Symbol
min
ADC Digital Filter (Decimation LPF):
Passband
(Note 9)
±0.1dB
PB
0
−0.2dB
−3.0dB
Stopband
(Note 9)
SB
25.7
Passband Ripple
PR
Stopband Attenuation
SA
68
Group Delay Distortion
ΔGD
Group Delay
(Note 10)
GD
ADC Digital Filter (HPF):
Frequency Response (Note 9) −3dB
FR
−0.1dB
DAC Digital Filter (LPF):
Passband
(Note 9) ±0.06dB
PB
0
−6.0dB
Stopband
(Note 9)
SB
24.1
Passband Ripple
PR
Stopband Attenuation
SA
54
Group Delay Distortion
ΔGD
Group Delay
(Note 10)
GD
DAC Digital Filter + Analog Filter:
Frequency Response (Note 11) 20~20kHz
FR
-
typ
max
Units
18.3
21.1
0
16
17.3
±0.04
-
kHz
kHz
kHz
kHz
dB
dB
μs
1/fs
0.86
5.9
-
Hz
Hz
22.05
0
20
20.0
±0.02
-
kHz
kHz
kHz
dB
dB
μs
1/fs
±0.1
-
dB
Note 9. The passband and stopband frequencies scale with fs (system sampling rate). For example, when fs= 44.1kHz,
DAC is PB=0.45412*fs (@±0.06dB).
Note 10. The calculated delay time induced by digital filtering. This time is from the input of an analog signal to the
setting of 24bit data both channels to the ADC output register for ADC. This time is from the set of 24bit data to
the input registers to the output of analog signal for DAC.
Note 11. The reference frequency of these responses is 1kHz.
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[AK7600]
DC CHARACTERISTICS
(Ta=-40°C∼+85°C; AVDD= DVDD=4.5∼5.5V)
Parameter
Symbol
Min
High-Level Input Voltage
( XTI, TSTI pins)
Low-Level Input Voltage
(XTI, TSTI pins)
High-Level Input Voltage
(PDN, SDA, SCL pins)
Low-Level Input Voltage
(PDN, SDA, SCL, pins)
High-Level Output Voltage
(SDTO1, SDTO2 ,SDTO3, LRCK, BICK, SDA
CLKO, DZF pins:
Iout=-100µA)
Low-Level Output Voltage
(SDTO1, SDTO2, SDTO3, LRCK, BICK,
CLKO, DZF pins:
Iout= 100µA)
(SDA pins:
Iout= 3mA)
Input Leakage Current
typ
max
Units
VIH
70%DVDD
-
-
V
VIL
-
-
30%DVDD
V
VIH
2.0
VIL
-
-
0.8
V
VOH
DVDD-0.5
-
-
V
VOL
VOL
Iin
-
-
0.5
0.4
±10
V
V
µA
MS0999-E-00
V
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[AK7600]
SWITCHING CHARACTERISTICS
(Ta=-40∼+85°C; AVDD=4.5~5.5V; DVDD=4.5∼5.5V; CL=20pF; unless otherwise specified)
Parameter
Symbol
Min
typ
Master Clock Timing
Crystal Resonator
Frequency
fXTAL
10
MCKO Output
Frequency
fMCK
10
dMCK
40
50
Duty cycle
External Clock
256fsn:
fCLK
10
Pulse Width Low
tCLKL
36
Pulse Width High
tCLKH
36
MCKO Output
Frequency
fMCK
10
Duty cycle
dMCK
40
50
Audio Interface Timing (Master mode)
BICK Frequency
fBCK
64fs
BICK Duty
dBCK
50
tMBLR
BICK “↓” to LRCK
−20
tBSD
BICK “↓” to SDTO
−20
max
Units
13
MHz
13
60
MHz
%
13
MHz
ns
ns
13
60
MHz
%
20
20
Hz
%
ns
ns
Note 12. “L” when using I2C format.
Note 13. BICK rising edge must not occur at the same time as LRCK edge.
Parameter
Control Interface Timing (I2C Bus mode):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
(Note 14)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed by Input Filter
Capacitive load on bus
Power-down & Reset Timing
PDN Pulse Width
(Note 15)
Symbol
min
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tSP
Cb
1.3
0.6
1.3
0.6
0.6
0
0.1
0.6
0
-
tPD
150
typ
max
Units
400
0.3
0.3
50
400
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
pF
ns
Note 14. Data must be held long enough to bridge the 300ns-transition time of SCL.
Note 15. The AK7600 can be reset by bringing the PDN pin = “L”.
Note 16. I2C is a registered trademark of Philips Semiconductors.
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[AK7600]
■ Timing Diagram
1/fCLK
VIH
XTI
VIL
tCLKH
tCLKL
1/fMCK
CLKO
50%DVDD
tdMCKH
tdMCKL
dMCK
= tdMCKH (or tdMCKL) x fMCK x 100
1/fs
LRCK
50%DVDD
tdLRKH
tdLRKL
dLRK
= tdLRKH (or tdLRKL) x fs x 100
1/fBCK
50%DVDD
BICK
tdBCKH
tdBCKL
dBCK
= tdBCKH (or tdBCKL) x fs x 100
Figure 3. Clock Timing
MS0999-E-00
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[AK7600]
50%DVDD
LRCK
tMBLR
50%DVDD
BICK
tBSD
50%DVDD
SDTO
Figure 4. Audio Interface Timing (Master mode)
VIH
SDA
VIL
tLOW
tBUF
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
Start
tSU:DAT
tSU:STA
Start
Figure 5. I2C Bus Mode Timing
tSU:STO
Stop
tPD
PDN
VIH
VIL
Figure 6. Power Down & Reset Timing
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[AK7600]
OPERATION OVERVIEW
■System Clock
The external clock input or X’tal input is available for MCLK clock source. (Figure 7, Figure 8) The required clock for
master mode is 256fs MCLK only.
In the normal operation, if the clock is stopped, click noise may occur when the clock supply is restarted. It can be prevent
by external mute.
LRCK
fs
44.1kHz
MCLK (MHz)
256fs
11.2896
BICK (MHz)
64fs
2.8224
Table 1. System Clock Example
■ Clock Source
The clock for the XTI pin can be generated by two methods:
1) External Clock
XTI
External Clock
AK7600
XTO
Figure 7. External Clock Mode
Note. Do not input the clock over DVDD.
2) X’tal
XTI
AK7600
XTO
Figure 8. X’tal Mode
Note: The capacitor is dependent on X’tal value. (Typ.15pF)
When using X’tal, DVDD=4.5~5.5V.
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[AK7600]
■ Digital High Pass Filter
The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 1.0Hz
(@fs=44.1kHz). The frequency response scales with fs.
■ Master Clock Output Pin
CLKO is the output pin for master clock.
■ Audio Interface Format
The DIF pin can select between two serial data modes as shown in Table 2. In all modes the serial data is MSB-first,
two’s complement format and it is latched on the rising edge of BICK.
DIF
Mode
I/O
24bit, Left
justified
24bit, I2S
0
1
BICK
LRCK
SDTO1-3
I/O
H/L
O
64fs
O
L/H
O
64fs
O
(default)
Table 2. Audio Data Format (Stereo mode)
LRCK
0
1
2
12
13
14
24
25
31
0
1
2
12
13
14
24
25
31
0
1
BICK(64fs)
23 22
SDTO(o)
12 11 10
0
23 22
12
11 10
0
23
SDTO-23:MSB, 0:LSB
Lch Data
Rch Data
Figure 9. Mode 0 Timing (Left justified mode)
LRCK
0
1
2
3
22
23
24
25
29
30
31
0
1
2
3
22
23
24
25
29
30
31
0
1
BICK(64fs)
SDTO(o)
23 22
2
1
0
23 22
2
1
0
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 10. Mode 1 Timing (I2S Mode)
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[AK7600]
■ Zero Detect Function
The AK7600 has independent zeros detect function for each DAC, which is always enabled. DZDD1-3 bits of CONT1
can select detection channel group and this function covers 6-channel outputs. Counting on “AND” for zero detected flags
of selected channels, when the input data is continuously zeros for 8192 LRCK cycles, the DZF pin goes to “H” at DZLH
bit (CONT1) is “0”, the DZF pin goes to “L” at DZLH bit (CONT1) is “1”. The DZF pin immediately returns to “L”
(DZLH bit “0”) or “H” (DZLH bit “1”) if the input data is not zero after the zero detection.
■ Soft Mute
Soft mute operation is performed in the digital domain. When the SMUTE bit is set “1”, the output signal is attenuated to
-∞ in 1024 LRCK cycles. When the SMUTE bit is returned to “0”, the mute is cancelled and the output attenuation
gradually changes to 0dB in 1024 LRCK cycles. If the soft mute is cancelled within the 1024 LRCK cycles after starting
this operation, the attenuation is discontinued and it is returned to 0dB by the same cycle. Soft mute is effective for
changing the signal source without stopping the signal transmission.
SMUTE bit
DAC Full Level
(1)
(2)
(4)
Attenuation
-∞
GD
(3)
GD
AOUT
DZF
(5)
8192/fs
Note:
(1) The transition time to attenuate input data to -∞ is 1024 LRCK cycles (1024/fs).
(2) The transition time to return to the full scale of the DAC input is 1024 LRCK cycles (1024/fs).
(3) Analog output corresponding to digital input has group delay (GD).
(4) If the soft mute is cancelled before attenuating -∞ after starting the operation, the attenuation is discontinued and
returned to ATT level by the same cycle.
(5) When the input data for both channels are continuously zero for 8192 LRCK cycles, the DZF pin goes to “H”. if the
DZLH bit is “0” (the DZF pin goes to “L” if the DZLH bit is “1”). The DZF pin immediately returns to “L” if the
input data are not zero after going to DZF “H” (DZLH bit =“0”).
Figure 11 Soft Mute and Zero Detect Function
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[AK7600]
■ System Reset
The AK7600 should be reset once by bringing the PDN pin = “L” upon power-up. The regulator will be powered-up by
inputting the master clock to the XTI pin directly or connect with a X’tal. The internal master clock starts by setting RSTN
bit to “1” after an interval of 10ms.
■ Power Down
The ADC and DAC parts of the AK7600 are placed in the power-down mode by bringing the PDN pin “L” and the digital
filter is also reset at the same time. The internal registers are initiated to their default value by the PDN pin = “L”. This
reset should always be made after power-up. In the power-down mode, SDTO1-3, BICK, LRCK and DZF pins go to “L”
and the analog output is VSS. When exiting the power-down mode, the AK7600 will be in reset state since the RSTN bit
= “0”. Figure 12 shows the power on/off sequence example.
PDN
Internal PDN
10ms(1)
RSTN
(2)
(3)
Regulator
Normal Operation
Internal ADC
State
Internal DAC
State
Normal Operation
Power Down
Normal Operation
Power Down
ADC In
(Analog)
Power Down
GD(4)
SDTO1~3
DAC Out
(Analog)
"0" data(5)
GD(4)
(7)
(6)
Clock In
XTI(external)
Clock In
X'tal
DZF
(8)
(9)
DZLH="1"
(10)
DZLH="0"
Note:
(1) After the PDN pin = “H”, the internal PDN is “L” until X’tal and regulator are powered-up. (Register writing is not
valid for 10ms of this period)
(2) During the RSTN bit is “0”, all circuits will be powered down except the regulator and X’tal even when the
internal PDN is “H”.
(3) Regulator will be powered-up after the PDN pin goes to “H”.
(4) The DAC and SDTO1-3 outputs corresponding to the ADC input has group delay (GD).
(5) The SDTP1-3 outputs are “0” when the AK7600 is powered-down.
(6) The DAC output is VSS voltage when the AK7600 is powered-down.
(7) Click noise occurs at the falling edge of PDN.
(8) In case of connecting a X’tal, the clock output is “L” when the PDN pin =“L”. The X’tal will be powered up after
the PDN pin =“H”.
(9) In power down mode(PDN pin = “L”), the DZF pin = “L”.
(10) The DZF pin output will reflects the DZLH bit setting when internal PDN is “H”.
Figure 12. Power Up/Down Sequence Example
MS0999-E-00
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- 15 -
[AK7600]
■ Reset Function
When the RSTN bit = “0”, ADC and DAC parts of the AK7600 is powered down, but the internal register values are not
initialized. The analog outputs settle to VCOM and the DZF pins for both channels go to “H” or “L” depending on the
DZLH bit setting. SDTO1-3 pins go to “L” and analog output is VCOM voltage. Click noise occurs at this timing, mute
the analog output externally if the click noise (8) influences system application. Figure 13 shows the example of reset by
RSTN bit.
RSTN bit
Internal
RSTN(ADC)
~1/fs(2)
4~5/fs(1)
Internal
RSTN(IIR)
Internal
RSTN(DAC)
ADC Internal
State
IIR Internal
State
DAC Internal
State
ADC In
(Analog)
Normal Operation
Normal Operation
Normal Operation
GD(6)
Clock In
XTI(external)
Normal Operation
7~8/fs (4)
Power Down
Normal Operation
Init
1.5~2.5/fs (5)
Power Down Init
Normal Operation
GD(6)
(8)
"0" data(7)
SDTO1~3
DAC Out
(Analog)
Power Down
8/fs (3
Init Cycle
)
GD(6)
(9)
(10)
(9)
Don't care(11)
Clock In
X'tal
DZF
GD(6)
(8)
9/fs
DZLH="0" (12)
Note:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Internal RSTN will be “L”, 4~5/fs after RSTN bit went to “0”.
ADC internal RSTN will be “H”, within 1/fs after RSTN bit = “1”.
The reset cycle is 8/fs after ADC internal RSTN goes to “H”.
Internal RSTN for IIR will be “H” after 7~8/fs from RSTN bit =“1”.
Internal RSTN for DAC will be “H” after 1.5~2.5/fs from RSTN bit = “1”.
The DAC and SDTO1-3 outputs corresponding to the ADC input has group delay (GD).
SDTO1-3 output is “0” data when the AK7600 is in powered down mode.
Click noise occurs when the initialization of ADC part is finished. Mute digital output if click noise adversely
affects system performance.
(9) Click noise occurs at the edge of internal RSTN.
(10) Analog output is VCOM voltage(AVDD/2) when RSTN bit = “0”.
(11) In case of inputting CLK from the XTI pin, the clock should be input before the RSTN bit is changed to “1” after
the RSTN bit is set to “0”.
(12) The DZF pin reflects the setting of DZLH bit. This pin changes to “L” or “H” 9/fs after the RSTN bit is set to “0”.
Figure 13. Reset Sequence Example
MS0999-E-00
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- 16 -
[AK7600]
■I2C BUS INTERFACE (Microcontroller Interface)
Access to the AK7600 registers and RAM is processed by I²C bus. The format of the I²C is complement with fast mode
(max: 400kHz). The AK7600 does not support Hs mode. (max: 3.4MHz).
■ Data Transfer
In order to access any IC devices on the I2C BUS, input a start condition first, followed by a single Slave address
which includes the Device Address. IC devices on the BUS compare this Slave address with their own addresses
and the IC device which has an identical address with the Slave-address generates an acknowledgement. An IC
device with the identical address then executes either a read or a write operation. After the command execution,
input a Stop condition.
1-1. Data Change
Change the data on the SDA line while SCL line is “L”. SDA line condition must be stable and fixed while the
clock is “H”. Change the Data line condition between “H” and “L” only when the clock signal on the SCL line is
“L”. Change the SDA line condition while SCL line is “H” only when the start condition or stop condition is input.
SCL
SDA
DATA LINE
STABLE :
DATA VALID
CHANGE
OF DATA
ALLOWED
Figure 14. Data Transition
1-2. Start condition and Stop condition
Start condition is generated by the transition of “H” to “L” on the SDA line while the SCL line is “H”. All
instructions are initiated by Start condition. Stop condition is generated by the transition of “L” to “H” on SDA
line while SCL line is “H”. All instructions end by Stop condition.
SCL
SDA
START CONDITION
STOP CONDITION
Figure 15. Start Condition and Stop Condition
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- 17 -
[AK7600]
1-3. Repeated Start Condition
When Start condition is received again instead of Stop condition, the bus changes to Repeated Start condition.
Repeated Start condition is functionally the same as Start condition.
SCL
SDA
START CONDITION
Repeated Start CONDITION
Figure 16. Repeated Start Condition
1-4. Acknowledge
An external device that is sending data to the AK7600 releases the SDA line (“H”) after receiving one-byte of
data. An external device that receives data from the AK7600 then sets the SDA line to “L” at the next clock. This
operation is called “acknowledgement” and it enables verification that the data transfer has been properly
executed. The AK7600 generates an acknowledgement upon receipt of Start condition and Slave address. For a
write instruction, an acknowledgement is generated whenever receipt of each byte is completed. For a read
instruction, succeeded by generation of an acknowledgement, the AK7600 releases the SDA line after outputting
data at the designated address, and it monitors the SDA line condition. When the Master side generates an
acknowledgement without sending Stop condition, the AK7600 outputs data at the next address location. When no
acknowledgement is generated, the AK7600 ends data output (not acknowledged).
Clock pulse
for acknowledge
SCL FROM
MASTER
1
8
DATA
OUTPUT BY
TRANSMITTER
DATA
OUTPUT BY
RECEIVER
9
not acknowledge
acknowledge
START
CONDITION
Figure 17. Acknowledge
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2008/09
- 18 -
[AK7600]
1-5. The First byte
The First Byte which includes the Slave-address is input after the Start condition is set, and a target IC device that
will be accessed on the bus is selected by the Slave-address. The Slave-address is configured with the upper 7-bits.
Data of the upper 7-bits is “0011000”. The address bits that select the desired IC are fixed. When the Slave-address
is inputted, an external device that has the identical device address generates an acknowledgement and
instructions are then executed. The 8th bit of the First Byte (lowest bit) is allocated as the R/W Bit. When the R/W
Bit is “1”, the read instruction is executed, and when it is “0”, the write instruction is executed.
Note 17. In this document, there is a case that describes a “Write Slave-address assignment” when both address
bits match and a Slave-address at R/W Bit = “0” is received. There is a case that describes “Read
Slave-address assignment” when both address bits matches and a Slave-address at R/W Bit = “1” is
received.
0
0
1
1
0
0
0
R/W
Slave Address is fixed 30H(write) or 31H(read).
Figure 18. The First Byte Structure
1-6. The Second and Succeeding Bytes
The data format of the second and succeeding bytes of the AK7600 Transfer / Receive Serial data (command code,
address and data in microcontroller interface format) on the I2C BUS are all configured with a multiple of 8-bits.
When transferring or receiving those data on the I2C BUS, they are divided into an 8-bit data stream segment and
they are transferred / received with the MSB side data first with an acknowledgement in-between.
When transferring / receiving A1B2C3 (hex) 24-bit serial data in microprocessor interface format:
2
(1)I C Foormat
A1
B2
C3
A
8BIT
A
8BIT
8BIT
A Acknowledge
Figure 19. Division of the Data
Note 18. In this document, there is a case that describes a write instruction command code which is received at the second
byte as “Write Command”. There is a case that describes a read instruction command code which is received at
the second byte as “Read Command”
MS0999-E-00
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- 19 -
[AK7600]
■ Command Code
BIT7
8/16/32 flag
BIT6
BIT5
BIT4
BIT3
BIT2
Area to be accessed
BIT1
BIT0
(1) 8/16/32 flag
When BIT[7:6] bits are “00”, the following data will be 8bit. The data will be 16bit 10byte of 1word x 5 transfer when
“01”, and 32bit 20byte of 1word x 5 transfer when “10”.
(2) Accompanying data to the access area
BIT5
BIT4
BIT3
BIT2
BIT1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
0
1
1
0
0
0
1
1
0
0
1
0
0
0
0
1
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
0
1
1
0
0
0
1
1
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
0
1
1
0
0
0
1
1
BIT0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
Command and Content
01H Control Register Cont0 Setting
02H Control Register Cont1 Setting
03H Control Register Cont2 Setting
40H Function2, Lch Coefficient Setting Preparation
41H Function2, Rch Coefficient Setting Preparation
42H Function2 Filter1 Coefficient Setting Preparation
43H Function2 Filter2 Coefficient Setting Preparation
44H Pre EQ ATT Coefficient Setting Preparation
45H EQ3 Filter Coefficient Setting Preparation
46H EQ4 Filter Coefficient Setting Preparation
47H X’Over ATT Coefficient Setting Preparation
48H X’Over Gain Coefficient Setting Preparation
49H Delay data Lch Setting Preparation
4AH Delay data Rch Setting Preparation
81H EQ0 Filter Coefficient Setting Preparation
82H EQ1 Filter Coefficient Setting Preparation
83H EQ2 Filter Coefficient Setting Preparation
84H X’Over HPF1-1 Coefficient Setting Preparation
85H X’Over HPF1-2 Coefficient Setting Preparation
86H X’Over HPF2-1 Coefficient Setting Preparation
87H X’Over HPF2-2 Coefficient Setting Preparation
88H X’Over LPF-1 Coefficient Setting Preparation
89H X’Over LPF-2 Coefficient Setting Preparation
C1H Read SpeAna 1Band (60Hz)
C2H Read SpeAna 2Band (160Hz)
C3H Read SpeAna 3Band (400Hz)
C4H Read SpeAna 3Band (1kHz)
C5H Read SpeAna 3Band (2.5kHz)
C6H Read SpeAna 3Band (6.3kHz)
C7H Read SpeAna 3Band (16kHz)
MS0999-E-00
2008/09
- 20 -
[AK7600]
■ Write Sequence
In the AK7600, when a “Write-Slave-address assignment” is received at the first byte, the write command at the second
byte and data at the third and succeeding bytes are received. At the data block, address and write data are received in a
single-byte unit each in accordance with a command code. The number of write data bytes (*1 in Figure 20)is fixed by the
received command code.
Usable command codes in write sequence are listed below as “Table 3. List of Usable Command Codes in Write
Sequence”.
S
SLAD
W
A
Cmd
A
Data
A
Stp
repeat N times (*1)
Figure 20. Write Sequence
Command Code
40H ~ 4AH
80H ~ 89H
01H,02H,03H
Data Length
10-byte
20-byte
1byte
Content
16bit coefficient data transferring in 5 coefficient unit or filter unit
28bit coefficient data transferring in 5 coefficient unit or filter unit
Control Register Writing
Table 3. List of Usable Command Codes in Write Sequence
MS0999-E-00
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- 21 -
[AK7600]
■ Data Format
Data Write
(1)Control Register Write
SDA
(1) COMMAND
01H, 02H, 03H
(2) DATA
D7~D0
Relationship between COMMAND and control register data.
1) Command 01H is write command for CONT0.
2) Command 02H is write command for CONT1.
3) Command 03H is write command for CONT2.
(2)16bit Coefficient or Delay Data Write
SDA
(1) COMMAND
40H,41H,42H,43H,44H,45H,46H,47H,48H,49H,4AH
(2) DATA1-1
D15~D8
(3) DATA1-2
D7~D0
(4) DATA2-1
D15~D8
(5) DATA2-2
D7~D0
(6)~(11)
(Continues in 2byte unit to DATA5. In total 10byte DATA)
(3)28bit Coefficient Data Write
SDA
(1) COMMAND
80H,81H,82H,83H,84H,85H,86H,87H,88H,89H
(2) DATA1-1
0 0 0 0 D27~D24
(3) DATA1-2
D23~D16
(4) DATA1-3
D15~D8
(5) DATA1-4
D7~D0
(6)~(21)
(Continues in 4byte unit to DATA5. In total 20byte DATA)
MS0999-E-00
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[AK7600]
■ Read Sequence
In the AK7600, when a “write- slave-address assignment” is received at the first byte, the command is send from micro
controller in the second byte. When the slave address is received after the start condition, the AK7600 starts outputting the
data regarding to command code.
When cancelling read operation before the AK7600 sends all data, assure that a “not acknowledged” signal is received by
the AK7600. If this “not acknowledged” signal is not received, the AK7600 continues to send data until specified number,
and since it did not release the BUS, the stop condition cannot be properly received.
Usable command codes in read sequence are listed in Table 4
S
SLAD
W
A
Cmd
A
rS
SLAD
R
A
Data
A
repeat N times
Data
Na
Stp
* Cancel
Figure 21. Read Sequence
Command Code
Data Length Content
40H ~ 4AH
16bit×5
16bit Coefficient; Delay Time Read
80H ~ 89H
32bit×5
28bit Coefficient; Data Read
01H, 02H, 03H
8bit
Control Register Read
C1H, C2H, C3H, C4H, C5H, C6H, C7H
16bit
Spectrum Analyzer Data Read
Table 4. List of Usable Read Command Codes in Read Sequence
MS0999-E-00
2008/09
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[AK7600]
Data Read
(1)Control Register Read
SDA
(1) COMMAND
01H,02H,03H
(2) DATA
D7~D0
Relationship between COMMAND and control register data.
4) Command 01H is read command for CONT0.
5) Command 02H is read command for CONT1.
6) Command 03H is read command for CONT2.
(2)16bit Coefficient or Delay Time Read
SDA
(1) COMMAND
40H,41H,42H,43H,44H,45H,46H,47H,48H,49H,4AH(Input)
(2) DATA1-1
D15~D8 (Output)
(3) DATA1-2
D7~D0
(4) DATA2-1
D15~D8
(5) DATA2-2
D7~D0
(6)~(11)
(Continues in 2byte unit to DATA5. In total 10byte DATA)
(3)28bit Coefficient Data Read
SDA
(1) COMMAND
80H,81H,82H,83H,84H,85H,86H,87H,88H,89H (Input )
(2) DATA1-1
0 0 0 0 D27~D24 ( Output )
(3) DATA1-2
D23~D16
(4) DATA1-3
D15~D8
(5) DATA1-4
D7~D0
(6)~(21)
(Continues in 4byte unit to DATA5. In total 20byte DATA)
(4) Spectrum Analyzer Data Read
SDA
(1) COMMAND
C1H, C2H, C3H, C4H, C5H, C6H, C7H (Input)
(2) DATA2
D15 D14 D13 D12 D11 D10 D9 D8 (Output)
(3) DATA1
D7 D6 D5 D4 D3 D2 D1 D0
MS0999-E-00
2008/09
- 24 -
[AK7600]
■ Register Definitions
Register Name: CONT0
COMMAND (01H)
Setting bit (1byte)
R/W
Default
D7
0
0
RD
0
D6
0
0
RD
0
D5
0
0
RD
0
D4
0
0
RD
0
D3
0
0
RD
0
D2
0
PMADC
R/W
1
D1
0
PMDAC
R/W
1
D0
1
RSTN
R/W
0
RSTN: Internal timing reset
0: Reset (The DZF pin goes to “H” but Register values are not initialized.)
1: Normal Operation
PMDAC: DAC1-3 power management
0: Power Down (All DAC’s)
1: Normal Operation
PMADC: ADC power management
0: Power Down
1: Normal Operation
MS0999-E-00
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- 25 -
[AK7600]
Register Name: CONT1
D7
0
DZD3
R/W
R/W
Default
0
Note) Writing to RD bits is ignored.
COMMAND (02H)
Setting bit (1byte)
D6
0
DZD2
R/W
0
D5
0
DZD1
R/W
0
D4
0
DZLH
R/W
0
D3
0
DIF
R/W
1
D2
0
0
RD
0
D1
1
0
RD
0
D0
0
SMUTE
R/W
0
DZD3: DZF setting
0: Indicate Zero detect of DAC3 at DZF
1: Ignore Zero detect
DZD2: DZF setting
0: Indicate Zero detect of DAC2 at DZF
1: Ignore Zero detect
DZD1: DZF setting
0: Indicate Zero detect of DAC1 at DZF
1: Ignore Zero detect
DZLH: DZF setting
0: Output “H” as a result of DZF zero detection
1: Output “L” as a result of DZF zero detection
D7
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D6
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D5
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
D4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
DAC3
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
-
DAC2
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
-
DAC1
Zero
Zero
Zero
Zero
Zero
Zero
Zero
Zero
-
DZF pin output Level
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
SMUTE: Soft Mute enable
0: Normal Operation
1: Soft Mute execute for all DAC’s
DIF: Digital output format (DIF mode setting)
0: Left justified mode
1: I2S mode (default)
MS0999-E-00
2008/09
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[AK7600]
Register Name: CONT2
COMMAND (03H)
Setting bit (1byte)
R/W
Default
D7
0
LRCK
R/W
0
D6
0
BICK
R/W
0
D5
0
MCKO
R/W
0
D4
0
Reserved
R/W
0
D3
0
DO3
R/W
0
D2
0
DO2
R/W
0
D1
1
DO1
R/W
0
D0
1
0
RD
0
LRCK: LRCK output enable
0: LRCK pin outputs “L”
1: Output LRCK(1fs) to the LRCK pin
BICK: BIT clock output enable
0: BICK pin outputs “L”
1: Output BIT clock (64fs) to the BICK pin
MCKO: Master clock output enable
0: CLKO pin outputs “L”
1: Output master clock (256fs) to the CLKO pin
Reserved: Write “0” into this bit.
DO3: SDTO3 output enable
0: SDTO3 pin outputs “L”
1: Output audio data to the SDTO3 pin
DO2: SDTO2 output enable
0: SDTO2 pin outputs “L”
1: Output audio data to the SDTO2 pin
DO1: SDTO1 output enable
0: SDTO1 pin outputs “L”
1: Output audio data to the SDTO1 pin
MS0999-E-00
2008/09
- 27 -
MS0999-E-00
- 28 -
HPF1-1
HPF1-2
F-Gain
HPF2-1
HPF2-2
R-Gain
Mute
DAC2
LPF1
LPF2
N-Gain
Mute
DAC3
DAC1
Mute
F-ATT
R-ATT
N-ATT
Delay Control
SpeAna
EQ4
EQ3
EQ2
EQ1
EQ0
ATT
Function
ADC
[AK7600]
■ Blocks and Circuits Construction of Command Setting
2008/09
[AK7600]
All 16bit 1bit Left
Function
LT
LO1
LI1
-n
D1
a10
Z
RI1
Z-1
Z-1
a11
b11
a12
b12
Z-1
RO1
Z-1
LO2
LI2
D2
a20
Z-n
RI2
Z-1
Z-1
a21
b21
a22
b22
Z-1
RO2
Z-1
RT
Command
Data 1 (2byte)
Data 2 (2byte)
Data 3 (2byte)
Data 4 (2byte)
Data 5 (2byte)
40H
LI1 Coefficient
RI1 Coefficient
LT Coefficient
LO1 Coefficient
LO2 Coefficient
Shift Setting
1bit left x2
1bit left x2
1bit left x2
1bit left x2
1bit left x2
R/W
R/W
R/W
R/W
R/W
R/W
Default Value
0x2000
0x2000
0x4000
0x0000
0x0000
Command
Data 1 (2byte)
Data 2 (2byte)
Data 3 (2byte)
Data 4 (2byte)
Data 5 (2byte)
41H
LI2 Coefficient
RI2 Coefficient
RT Coefficient
RO1 Coefficient
RO2 Coefficient
Shift Setting
1bit left x2
1bit left x2
1bit left x2
1bit left x2
1bit left x2
R/W
R/W
R/W
R/W
R/W
R/W
Default Value
0x2000
0x2000
0x4000
0x0000
0x0000
Command
Data 1 (2byte)
Data 2 (2byte)
Data 3 (2byte)
Data 4 (2byte)
Data 5 (2byte)
42H
A12 Coefficient
A11 Coefficient
A10 Coefficient
B12 Coefficient
B11 Coefficient
Shift Setting
1bit left x2
1bit left x2
1bit left x2
1bit left x2
1bit left x2
R/W
R/W
R/W
R/W
R/W
R/W
Default Value
0x0000
0x0000
0x4000
0x0000
0x0000
43H
A22 Coefficient
A21 Coefficient
A20 Coefficient
B22 Coefficient
B21 Coefficient
Shift Setting
1bit left x2
1bit left x2
1bit left x2
1bit left x2
1bit left x2
R/W
R/W
R/W
R/W
R/W
R/W
Default Value
0x0000
0x0000
0x4000
0x0000
0x0000
Command
Data 1 (2byte)
Data 2 (2byte)
Data 3 (2byte)
Data 4 (2byte)
Data 5 (2byte)
Note: All data are R/W.
MS0999-E-00
2008/09
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[AK7600]
ATT
Attenuate input data for both Left and Right channels.
<< 1
<< 1
Command
44H
Data 1 (2byte)
Pre EQ ATT setting coefficient
Data 2 (2byte)
Dummy
Data 3 (2byte)
Dummy
Data 4 (2byte)
Dummy
Data 5 (2byte)
Dummy
Note: All data are R/W.
Shift Setting
1bit left x2
1bit left x2
1bit left x2
1bit left x2
1bit left x2
R/W
R/W
R/W
R/W
R/W
R/W
Default Value
0x4000
0x0000
0x0000
0x0000
0x0000
EQ Setting
EQ0
A0
EQ1
A0
EQ2
A0
EQ3
A0
EQ4
A0
Lch
-1
Rch
Z
-1
A1
B1
-1
Z
-1
A1
B1
A2
B2
B2
B1
A2
B2
Z
-1
A1
B1
-1
Z
Z
A2
-1
A1
-1
-1
Z
Z
Z
A1
B1
A2
B2
-1
-1
Z
Z
Z
A2
B2
Command
Data 1 (4byte)
Data 2 (4byte)
Data 3 (4byte)
Data 4 (4byte)
Data 5 (4byte)
81H
EQ0 A2 Coefficient
EQ0 A1 Coefficient
EQ0 A0 Coefficient
EQ0 B2 Coefficient
EQ0 B1 Coefficient
Shift Setting
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
R/W
R/W
R/W
R/W
R/W
R/W
Default Value
0x00000000
0x00000000
0x04000000
0x00000000
0x00000000
Command
Data 1 (4byte)
Data 2 (4byte)
Data 3 (4byte)
Data 4 (4byte)
Data 5 (4byte)
82H
EQ1 A2 Coefficient
EQ1 A1 Coefficient
EQ1 A0 Coefficient
EQ1 B2 Coefficient
EQ1 B1 Coefficient
Shift Setting
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
R/W
R/W
R/W
R/W
R/W
R/W
Default Value
0x00000000
0x00000000
0x04000000
0x00000000
0x00000000
Command
83H
Data 1 (4byte)
EQ2 A2 Coefficient
Data 2 (4byte)
EQ2 A1 Coefficient
Data 3 (4byte)
EQ2 A0 Coefficient
Data 4 (4byte)
EQ2 B2 Coefficient
Data 5 (4byte)
EQ2 B1 Coefficient
Note: All data are R/W.
Shift Setting
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
R/W
R/W
R/W
R/W
R/W
R/W
Default Value
0x00000000
0x00000000
0x04000000
0x00000000
0x00000000
MS0999-E-00
2008/09
- 30 -
-1
Z
[AK7600]
Command
Data 1 (2byte)
Data 2 (2byte)
Data 3 (2byte)
Data 4 (2byte)
Data 5 (2byte)
45H
EQ3 A2 Coefficient
EQ3 A1 Coefficient
EQ3 A0 Coefficient
EQ3 B2 Coefficient
EQ3 B1 Coefficient
Shift Setting
1bit left x2
1bit left x2
1bit left x2
1bit left x2
1bit left x2
R/W
R/W
R/W
R/W
R/W
R/W
Default Value
0x0000
0x0000
0x4000
0x0000
0x0000
Command
46H
Data 1 (2byte)
EQ4 A2 Coefficient
Data 2 (2byte)
EQ4 A1 Coefficient
Data 3 (2byte)
EQ4 A0 Coefficient
Data 4 (2byte)
EQ4 B2 Coefficient
Data 5 (2byte)
EQ4 B1 Coefficient
Note: All data are R/W.
Shift Setting
1bit left x2
1bit left x2
2bit left x4
1bit left x2
1bit left x2
R/W
R/W
R/W
R/W
R/W
R/W
Default Value
0x0000
0x0000
0x2000
0x0000
0x0000
F-ATT, R-ATT, N-ATT
Amplify or regulate each Front (L1, R1), Rear (L2, R2) and SW (L3, R3) X’Over filter input data.
<< 1
<< 1
Command
47H
Data 1 (2byte) Front ATT setting coefficient
Data 2 (2byte) Rear ATT setting coefficient
Data 3 (2byte) SW(NF) ATT setting coefficient
Data 4 (2byte) Dummy
Data 5 (2byte) Dummy
Note: All data are R/W.
Shift Setting
1bit left x2
1bit left x2
1bit left x2
1bit left x2
1bit left x2
R/W
R/W
R/W
R/W
R/W
R/W
Default Value
0x4000
0x4000
0x4000
0x0000
0x0000
X’Over filter (HPF & LPF)
A0
HPF1-1
HPF1-2
First step HPF2-1
Second step HPF2-2
LPF-1
LPF-2
-1
-1
-1
Z
A0
A1
B1
Z
A1
B1
-1
-1
-1
Z
Z
A2
B2
Z
Z
A2
Command
84H
Data 1 (4byte)
HPF1-1 A2 Coefficient
Data 2 (4byte)
HPF1-1 A1 Coefficient
Data 3 (4byte)
HPF1-1 A0 Coefficient
Data 4 (4byte)
HPF1-1 B2 Coefficient
Data 5 (4byte)
HPF1-1 B1 Coefficient
Note: All data are R/W.
MS0999-E-00
B2
Shift Setting
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
R/W
R/W
R/W
R/W
R/W
R/W
Default Value
0x00000000
0x00000000
0x04000000
0x00000000
0x00000000
2008/09
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[AK7600]
Command
Data 1 (4byte)
Data 2 (4byte)
Data 3 (4byte)
Data 4 (4byte)
Data 5 (4byte)
85H
HPF1-2 A2 Coefficient
HPF1-2 A1 Coefficient
HPF1-2 A0 Coefficient
HPF1-2 B2 Coefficient
HPF1-2 B1 Coefficient
Shift Setting
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
R/W
R/W
R/W
R/W
R/W
R/W
Default Value
0x00000000
0x00000000
0x04000000
0x00000000
0x00000000
Command
Data 1 (4byte)
Data 2 (4byte)
Data 3 (4byte)
Data 4 (4byte)
Data 5 (4byte)
86H
HPF2-1 A2 Coefficient
HPF2-1 A1 Coefficient
HPF2-1 A0 Coefficient
HPF2-1 B2 Coefficient
HPF2-1 B1 Coefficient
Shift Setting
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
R/W
R/W
R/W
R/W
R/W
R/W
Default Value
0x00000000
0x00000000
0x04000000
0x00000000
0x00000000
Command
Data 1 (4byte)
Data 2 (4byte)
Data 3 (4byte)
Data 4 (4byte)
Data 5 (4byte)
87H
HPF2-2 A2 Coefficient
HPF2-2 A1 Coefficient
HPF2-2 A0 Coefficient
HPF2-2 B2 Coefficient
HPF2-2 B1 Coefficient
Shift Setting
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
R/W
R/W
R/W
R/W
R/W
R/W
Default Value
0x00000000
0x00000000
0x04000000
0x00000000
0x00000000
Command
Data 1 (4byte)
Data 2 (4byte)
Data 3 (4byte)
Data 4 (4byte)
Data 5 (4byte)
88H
LPF-1 A2 Coefficient
LPF-1 A1 Coefficient
LPF-1 A0 Coefficient
LPF-1 B2 Coefficient
LPF-1 B1 Coefficient
Shift Setting
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
R/W
R/W
R/W
R/W
R/W
R/W
Default Value
0x00000000
0x00000000
0x04000000
0x00000000
0x00000000
Command
89H
Data 1 (4byte)
LPF-2 A2 Coefficient
Data 2 (4byte)
LPF-2 A1 Coefficient
Data 3 (4byte)
LPF-2 A0 Coefficient
Data 4 (4byte)
LPF-2 B2 Coefficient
Data 5 (4byte)
LPF-2 B1 Coefficient
Note: All data are R/W.
Shift Setting
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
R/W
R/W
R/W
R/W
R/W
R/W
Default Value
0x00000000
0x00000000
0x04000000
0x00000000
0x00000000
F-Gain, R-Gain, N-Gain
Amplify or regulate each Front (L1, R1), Rear (L2, R2) and SW (L3, R3) X’Over filter output data.
<< 1
<< 1
Command
Data 1 (2byte)
Data 2 (2byte)
Data 3 (2byte)
Data 4 (2byte)
Data 5 (2byte)
48H
Front Gain setting coefficient
Rear Gain setting coefficient
SW(NF) Gain setting coefficient
Dummy
Dummy
MS0999-E-00
Shift Setting
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
1bit left x 2
R/W
R/W
R/W
R/W
R/W
R/W
Default Value
0x4000
0x4000
0x4000
0x0000
0x0000
2008/09
- 32 -
[AK7600]
■ Delay Time Setting (fs step)
1. D1 or D2 delay time setting of Function2
2. Delay time setting of each FL, FR, RR, RL, NL and NR channel
FL
RL
NL
Lch input
Delay Memory 1word=24bit
18ms Delay = 794word (44.1kHz x 0.018)
L1 out (Front)
L2 out (Rear)
L3 out (SW)
FR
RR
Rch input
NL
Delay Memory 1word=24bit
18ms Delay = 794word (44.1kHz x 0.018)
R1 out (Front)
R2 out (Rear)
R3 out (SW)
(1/fs = 1/44100 = approximately 0.0226ms)= one unit.
Command
Data 1 (2byte)
Data 2 (2byte)
Data 3 (2byte)
Data 4 (2byte)
Data 5 (2byte)
49H
Function2 D1 delay time
Set range (0x0000~0x002D)
Front L1 out delay time
Set range (0x0000~0x031A)
Rear L2 out delay time
Set range (0x0000~0x031A)
SW L3 out delay time
Set range (0x0000~0x031A)
Dummy
Command
Data 1 (2byte)
Setting Unit
Delay time: 1/fs unit
R/W
R/W
Default Value
0x0000
Delay time: 1/fs unit
R/W
0x0000
Delay time: 1/fs unit
R/W
0x0000
Delay time: 1/fs unit
R/W
0x0000
-
R/W
0x0000
4AH
Setting Unit
R/W
Function2 D2 delay time
Delay time: 1/fs unit
R/W
Set range (0x0000~0x002D)
Data 2 (2byte)
Front R1 out delay time
Delay time: 1/fs unit
R/W
Set range (0x0000~0x031A)
Data 3 (2byte)
Rear R2 out delay time
Delay time: 1/fs unit
R/W
Set range (0x0000~0x031A)
Data 4 (2byte)
SW R3 out delay time
Delay time: 1/fs unit
R/W
Set range (0x0000~0x031A)
Data 5 (2byte)
Dummy
R/W
Note: All data are R/W.
When the delay time is set over its limit, it will be set to the maximum value.
MS0999-E-00
Default Value
0x0000
0x0000
0x0000
0x0000
0x0000
2008/09
- 33 -
[AK7600]
Spectrum Analyzer
Each data level read of Spectrum Analyzer
Command
Data1 (2byte)
C1H
68Hz Level
R/W
RD
Command
Data1 (2byte)
C1H
160Hz Level
R/W
RD
Command
Data1 (2byte)
C1H
400Hz Level
R/W
RD
Command
Data1 (2byte)
C1H
1kHz Level
R/W
RD
Command
Data1 (2byte)
C1H
2.5kHz Level
R/W
RD
Command
Data1 (2byte)
C1H
6.3kHz Level
R/W
RD
Command
Data1 (2byte)
C1H
16kHz Level
R/W
RD
Measuring Frequency of Spectrum Analyzer
There are 7 bands of the detection frequency of spectrum analyzer level at Fs=44.1kHz.
Band
f0[Hz]
1
68
2
160
3
400
4
1000
MS0999-E-00
5
2500
6
6300
7
16000
2008/09
- 34 -
[AK7600]
SYSTEM DESIGN
Figure 22 shows the system connection diagram. An evaluation board (AKD7600) is available for fast evaluation as well
as suggestions for peripheral circuitry.
AK7600
0.1μF
VSS2 30
1 TSTI
2 REF18
10μF
XTI 28
3 VSS4
2.2μF
Analog 5.0V
0.1μF
10μF
0.1μ
0.1μ
4 VCOM
SDTO3 27
5 AINL
SDTO2 26
6 AINR
SDTO1 25
7 AVDD
LRCK 24
8 VSS1
BICK 23
9 VREFH
DVDD 22
Mute
10 AOUT1L
CLKO 21
11 AOUT1R
SCL 20
Mute
12 AOUT2L
SDA 19
Mute
13 AOUT2R
VSS3 18
14 AOUT3L
PDN 17
15 AOUT3R
DZF 16
10μF
Mute
15pF
XTO 29
15pF
DAC
CLKO
0.1μF
10μF
Digital 5.0V
μP
Mute
Mute
AGND
DGND
Figure 22. Typical Connection Diagram
Note: Do not take load current from the REF18 pin.
MS0999-E-00
2008/09
- 35 -
[AK7600]
1. Grounding and Power Supply Decoupling
The AK7600 requires careful attention to power supply and grounding arrangements. AVDD and DVDD are usually
supplied from the system’s analog supply. If AVDD and DVDD are supplied separately, the power-up sequence is not
critical. VSS1, VSS2, VSS3 and VSS4 of the AK7600 should be connected to the analog ground plane. System
analog ground and digital ground should be connected together near to where the supplies are brought onto the printed
circuit board. Decoupling capacitors should be as near to the AK7600 as possible, with the small value ceramic capacitor
being the nearest.
2. Voltage Reference Inputs
The input voltage to the VREFH pin sets the analog output range. Usually the VREFH pin is connected to AVDD and a
0.1μF ceramic capacitor is connected between AVDD and VSS1. VCOM is a signal ground of this chip (AVDD/2). The
electrolytic capacitor around 2.2µF attached between VCOM anVSS1 eliminates the effects of high frequency noise. The
ceramic capacitor in particular should be connected as close as possible to the pin. No load current may be taken from the
VCOM pin. All signals, especially clock, should be kept away from VREFH and VCOM in order to avoid unwanted
coupling into the AK7600.
3. Analog Inputs
The ADC inputs is single-ended and biased to VCOM voltage (AVDD/2) internally by 45kΩ(typ). The inputs signal
range scales with nominally at 0.65 x VREFH Vpp (typ)@fs=44.1kHz. The AK7600 can accept input voltage from VSS1
to AVDD. The output code format is 2's complement. Input DC offset is canceled by an integrated high-pass filter.
The AK7600 samples the analog input at 64fs(@fs=44.1kHz). A digital filter removes the noise over the stopband
attenuation level, except for a band of integral multiplication of 64fs. AK7600 has an integrated anti-alias RC filter in
order to reduce the noise at 64fs.
4. Analog output
The DAC output is single-ended and output range is 0.65xVREFH Vpp (typ) centered on VCOM. The bias voltage of the
external summing circuit is supplied externally. The input data format is two’s compliment. Positive full-scale output
corresponds to 7FFFFFH (@24bit) input code, Negative full scale is 800000H (@24bit) and VCOM voltage ideally is
000000H (@24bit). The Out-of-Band noise (shaping noise) generated by the internal delta-sigma modulator is attenuated
by an integrated switched capacitor filter (SCF) and a continuous time filter (CTF).
DC offsets on analog outputs are eliminated by AC coupling since analog outputs has DC offset of VCOM.
MS0999-E-00
2008/09
- 36 -
[AK7600]
PACKAGE
30pin VSOP (Unit: mm)
1.5MAX
*9.7±0.1
0.3
30
16
15
1
0.22±0.1
7.6±0.2
5.6±0.1
A
0.15 +0.10
-0.05
0.65
0.12 M
0.45±0.2
+0.10
0.08
0.10 -0.05
1.2±0.10
Detail A
NOTE: Dimension "*" does not include mold flash.
■ Materials and Lead Specification
Package: Epoxy
Lead frame: Copper
Lead-finish: Soldering plate (Pb free)
MS0999-E-00
2008/09
- 37 -
[AK7600]
MARKING
AKM
AK7600VF
XXXBYYYYC
XXXBYYYYC
Date code identifier
XXXB: Lot number (X: Digit number, B: Alpha character)
YYYYC: Assembly date (Y: Digit number, C: Alpha character)
REVISION HISTORY
Date (YY/MM/DD)
08/09/03
Revision
00
Reason
First Edition
Page
Contents
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
EMD Corporation (AKEMD) or authorized distributors as to current status of the products.
z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or
use of any information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKEMD. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or
for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform
may reasonably be expected to result in loss of life or in significant injury or damage to person or property.
z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise
places the product with a third party, to notify such third party in advance of the above content and conditions, and the
buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any
and all claims arising from the use of said product in the absence of such notification.
MS0999-E-00
2008/09
- 38 -
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