SHARC Processors ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 SUMMARY DEDICATED AUDIO COMPONENTS High performance 32-bit/40-bit floating point processor optimized for high performance audio processing Single-instruction, multiple-data (SIMD) computational architecture On-chip memory—3M bits of on-chip SRAM S/PDIF-compatible digital audio receiver/transmitter 8 channels of asynchronous sample rate converters (SRC) 16 PWM outputs configured as four groups of four outputs ROM-based security features include: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multiplier/divider ratios Available in 136-ball CSP_BGA and 144-lead LQFP_EP packages Code compatible with all other members of the SHARC family The ADSP-2136x processors are available with up to 333 MHz core instruction rate with unique audiocentric peripherals such as the digital applications interface, S/PDIF transceiver, DTCP (digital transmission content protection protocol), serial ports, precision clock generators, and more. For complete ordering information, see Ordering Guide on Page 54. Internal Memory SIMD Core Block 0 RAM/ROM Instruction Cache 5 stage Sequencer DAG1/2 Timer PEx PEy S FLAGx/IRQx/ TMREXP B0D 64-BIT Block 2 RAM B2D 64-BIT B1D 64-BIT Block 3 RAM B3D 64-BIT DMD 64-BIT DMD 64-BIT PMD 64-BIT Block 1 RAM/ROM Core Bus Cross Bar Internal Memory I/F PMD 64-BIT JTAG IOD 32-BIT PERIPHERAL BUS 32-BIT MTM/ DTCP IOD BUS PERIPHERAL BUS CORE TIMER FLAGS 2-0 ASRC 3-0 S/PDIF Tx/Rx PCG A-B SPI B PDAP/ SPORT IDP7-0 5-0 DAI Routing/Pins SPI Core Flags PWM 3-0 PP PP Pin MUX DAI Peripherals Peripherals Figure 1. Functional Block Diagram SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc. Rev. G Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2011 All rights reserved. ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 TABLE OF CONTENTS Summary ............................................................... 1 Package Information ............................................ 15 Dedicated Audio Components .................................... 1 ESD Caution ...................................................... 15 Revision History ...................................................... 2 Maximum Power Dissipation ................................. 15 General Description ................................................. 3 Absolute Maximum Ratings ................................... 15 SHARC Family Core Architecture ............................ 4 Timing Specifications ........................................... 15 Family Peripheral Architecture ................................ 6 Output Drive Currents ......................................... 44 I/O Processor Features ........................................... 8 Test Conditions .................................................. 44 System Design ...................................................... 8 Capacitive Loading .............................................. 44 Development Tools ............................................... 9 Thermal Characteristics ........................................ 45 Additional Information ........................................ 10 144-Lead LQFP_EP Pin Configurations ....................... 46 Related Signal Chains .......................................... 10 136-Ball BGA Pin Configurations ............................... 48 Pin Function Descriptions ....................................... 11 Package Dimensions ............................................... 51 Specifications ........................................................ 14 Surface-Mount Design .......................................... 52 Operating Conditions .......................................... 14 Automotive Products .............................................. 53 Electrical Characteristics ....................................... 14 Ordering Guide ..................................................... 54 REVISION HISTORY 3/11—Rev. F to Rev. G Revised S/PDIF Transmitter Input Data Timing ............. 38 Revised Table 45, added Figure 43 and Figure 44 in 144-Lead LQFP_EP Pin Configurations .................................... 46 Added an additional model to Automotive Products ....... 53 Rev. G | Page 2 of 56 | March 2011 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 GENERAL DESCRIPTION The ADSP-2136x SHARC® processor is a member of the SIMD SHARC family of DSPs that feature Analog Devices, Inc., Super Harvard Architecture. The processor is source code-compatible with the ADSP-2126x and ADSP-2116x DSPs, as well as with first generation ADSP-2106x SHARC processors in SISD (single-instruction, single-data) mode. The ADSP-2136x are 32-/40-bit floating-point processors optimized for high performance automotive audio applications. They contain a large on-chip SRAM and ROM, multiple internal buses to eliminate I/O bottlenecks, and an innovative digital audio interface (DAI). As shown in the functional block diagram on Page 1, the ADSP-2136x uses two computational units to deliver a significant performance increase over the previous SHARC processors on a range of signal processing algorithms. With its SIMD computational hardware, the ADSP-2136x can perform two GFLOPS running at 333 MHz. Table 1 shows performance benchmarks for these devices. Table 2 shows the features of the individual product offerings. Table 1. Benchmarks (at 333 MHz) Benchmark Algorithm 1024 Point Complex FFT (Radix 4, with reversal) FIR Filter (per tap)1 IIR Filter (per biquad)1 Matrix Multiply (pipelined) [3×3] × [3×1] [4×4] × [4×1] Divide (y/x) Inverse Square Root 1 Speed (at 333 MHz) 27.9 μs 1.5 ns 6.0 ns 13.5 ns 23.9 ns 10.5 ns 16.3 ns Assumes two files in multichannel SIMD mode. Table 2. ADSP-2136x Family Features Feature RAM ROM Audio Decoders in ROM1 Pulse-Width Modulation S/PDIF DTCP2 SRC SNR Performance ADSP-21362 3M bit 4M bit No Yes Yes Yes –128 dB ADSP-21363 3M bit 4M bit No Yes No No No SRC ADSP-21364 3M bit 4M bit No Yes Yes No –140 dB ADSP-21365 3M bit 4M bit Yes Yes Yes Yes –128 dB ADSP-21366 3M bit 4M bit Yes Yes Yes No –128 dB 1 Audio decoding algorithms include PCM, Dolby Digital EX, Dolby Pro Logic IIx, DTS 96/24, Neo:6, DTS ES, MPEG-2 AAC, MP3, and functions like bass management, delay, speaker equalization, graphic equalization, and more. Decoder/post-processor algorithm combination support varies depending upon the chip version and the system configurations. Please visit www.analog.com for complete information. 2 The ADSP-21362 and ADSP-21365 processors provide the Digital Transmission Content Protection protocol, a proprietary security protocol. Contact your Analog Devices sales office for more information. The diagram on Page 1 shows the two clock domains that make up the ADSP-2136x processors. The core clock domain contains the following features: The diagram on Page 1 also shows the following architectural features: • Two processing elements, each of which comprises an ALU, multiplier, shifter, and data register file • Six full duplex serial ports • Two SPI-compatible interface ports—primary on dedicated pins, secondary on DAI pins • Data address generators (DAG1, DAG2) • Program sequencer with instruction cache • PM and DM buses capable of supporting four 32-bit data transfers between memory and the core at every core processor cycle • One periodic interval timer with pinout • On-chip SRAM (3M bit) • On-chip mask-programmable ROM (4M bit) • JTAG test access port for emulation and boundary scan. The JTAG provides software debug through user breakpoints, which allow flexible exception handling. Rev. G • I/O processor that handles 32-bit DMA for the peripherals | Page 3 of 56 | • 8-bit or 16-bit parallel port that supports interfaces to offchip memory peripherals • Digital audio interface that includes two precision clock generators (PCG), an input data port (IDP), an S/PDIF receiver/transmitter, 8-channel asynchronous sample rate converter, DTCP cipher, six serial ports, eight serial interfaces, a 20-bit parallel input port, 10 interrupts, six flag outputs, six flag inputs, three timers, and a flexible signal routing unit (SRU) March 2011 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 SHARC FAMILY CORE ARCHITECTURE Entering SIMD mode also has an effect on the way data is transferred between memory and the processing elements. When in SIMD mode, twice the data bandwidth is required to sustain computational operation in the processing elements. Because of this requirement, entering SIMD mode also doubles the bandwidth between memory and the processing elements. When using the DAGs to transfer data in SIMD mode, two data values are transferred with each access of memory or the register file. The ADSP-2136x is code-compatible at the assembly level with the ADSP-2126x, ADSP-21160, and ADSP-21161, and with the first generation ADSP-2106x SHARC processors. The ADSP-2136x shares architectural features with the ADSP-2126x and ADSP-2116x SIMD SHARC processors, as shown in Figure 2 and detailed in the following sections. SIMD Computational Engine The processor contains two computational processing elements that operate as a single-instruction, multiple-data (SIMD) engine. The processing elements are referred to as PEX and PEY and each contains an ALU, multiplier, shifter, and register file. PEX is always active, and PEY can be enabled by setting the PEYEN mode bit in the MODE1 register. When this mode is enabled, the same instruction is executed in both processing elements, but each processing element operates on different data. This architecture is efficient at executing math intensive signal processing algorithms. S FLAG JTAG Independent, Parallel Computation Units Within each processing element is a set of computational units. The computational units consist of an arithmetic/logic unit (ALU), multiplier, and shifter. These units perform all operations in a single cycle. The three units within each processing element are arranged in parallel, maximizing computational throughput. Single multifunction instructions execute parallel ALU and multiplier operations. In SIMD mode, the parallel ALU and multiplier operations occur in both processing elements. These computation units support IEEE 32-bit, single-precision floating-point, 40-bit extended-precision floating-point, and 32-bit fixed-point data formats. TIMER INTERRUPT CACHE SIMD Core PM ADDRESS 24 DMD/PMD 64 5 STAGE PROGRAM SEQUENCER PM DATA 48 DAG1 16x32 DAG2 16x32 PM ADDRESS 32 SYSTEM I/F DM ADDRESS 32 USTAT 4x32-BIT PM DATA 64 PX 64-BIT DM DATA 64 MULTIPLIER MRF 80-BIT SHIFTER ALU MRB 80-BIT RF Rx/Fx PEx 16x40-BIT DATA SWAP RF Sx/SFx PEy 16x40-BIT ASTATx ASTATy STYKx STYKy ALU Figure 2. SHARC Core Block Diagram Rev. G | Page 4 of 56 | March 2011 SHIFTER MULTIPLIER MSB 80-BIT MSF 80-BIT ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Data Register File Each processing element contains a general-purpose data register file. The register files transfer data between the computation units and the data buses, and store intermediate results. These 10-port, 32-register (16 primary, 16 secondary) files, combined with the ADSP-2136x enhanced Harvard architecture, allow unconstrained data flow between computation units and internal memory. The registers in PEX are referred to as R0–R15 and in PEY as S0–S15. Context switch Many of the processor’s registers have secondary registers that can be activated during interrupt servicing for a fast context switch. The data registers in the register file, the DAG registers, and the multiplier result register all have secondary registers. The primary registers are active at reset, while the secondary registers are activated by control bits in a mode control register. Universal Registers The universal registers are general purpose registers. The USTAT (4) registers allow easy bit manipulations (Set, Clear, Toggle, Test, XOR) for all system registers (control/status) of the core. The data bus exchange register (PX) permits data to be passed between the 64-bit PM data bus and the 64-bit DM data bus, or between the 40-bit register file and the PM/DM data bus. These registers contain hardware to handle the data width difference. Timer A core timer that can generate periodic software interrupts. The core timer can be configured to use FLAG3 as a timer expired signal. Single-Cycle Fetch of Instruction and Four Operands The processor features an enhanced Harvard architecture in which the data memory (DM) bus transfers data and the program memory (PM) bus transfers both instructions and data (see Figure 2). With the its separate program and data memory buses and on-chip instruction cache, the processor can simultaneously fetch four operands (two over each data bus) and one instruction (from the cache), all in a single cycle. Instruction Cache The processor includes an on-chip instruction cache that enables three-bus operation for fetching an instruction and four data values. The cache is selective—only the instructions whose fetches conflict with PM bus data accesses are cached. This cache allows full-speed execution of core looped operations such as digital filter multiply-accumulates, and FFT butterfly processing. Data Address Generators with Zero-Overhead Hardware Circular Buffer Support The processor’s two data address generators (DAGs) are used for indirect addressing and implementing circular data buffers in hardware. Circular buffers allow efficient programming of delay lines and other data structures required in digital signal Rev. G | processing, and are commonly used in digital filters and Fourier transforms. The two DAGs contain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 secondary). The DAGs automatically handle address pointer wraparound, reduce overhead, increase performance, and simplify implementation. Circular buffers can start and end at any memory location. Flexible Instruction Set The 48-bit instruction word accommodates a variety of parallel operations for concise programming. For example, the processor can conditionally execute a multiply, an add, and a subtract in both processing elements while branching and fetching up to four 32-bit values from memory—all in a single instruction. On-Chip Memory The processor contains 3M bits of internal SRAM and 4M bits of internal ROM. Each block can be configured for different combinations of code and data storage (see Table 3). Each memory block supports single-cycle, independent accesses by the core processor and I/O processor. The processor’s memory architecture, in combination with its separate on-chip buses, allows two data transfers from the core and one from the I/O processor, in a single cycle. The SRAM can be configured as a maximum of 96K words of 32-bit data, 192K words of 16-bit data, 64K words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to 3M bits. All of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit floating-point storage format is supported that effectively doubles the amount of data that can be stored on-chip. Conversion between the 32-bit floating-point and 16-bit floating-point formats is performed in a single instruction. While each memory block can store combinations of code and data, accesses are most efficient when one block stores data using the DM bus for transfers, and the other block stores instructions and data using the PM bus for transfers. Using the DM bus and PM buses, with one bus dedicated to each memory block, assures single-cycle execution with two data transfers. In this case, the instruction must be available in the cache. On-Chip Memory Bandwidth The internal memory architecture allows three accesses at the same time to any of the four blocks, assuming no block conflicts. The total bandwidth is gained with DMD and PMD buses (2 × 64-bits, core CLK) and the IOD bus (32-bit, PCLK). ROM-Based Security The processor has a ROM security feature that provides hardware support for securing user software code by preventing unauthorized reading from the internal code. When using this feature, the processor does not boot-load any external code, executing exclusively from internal ROM. Additionally, the processor is not freely accessible via the JTAG port. Instead, a unique 64-bit key, which must be scanned in through the JTAG Page 5 of 56 | March 2011 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Table 3. ADSP-2136x Internal Memory Space IOP Registers 0x0000 0000–0003 FFFF Long Word (64 Bits) Extended Precision Normal or Instruction Word (48 Bits) Normal Word (32 Bits) Short Word (16 Bits) Block 0 ROM 0x0004 0000–0x0004 7FFF Block 0 ROM 0x0008 0000–0x0008 AAA9 Block 0 ROM 0x0008 0000–0x0008 FFFF Block 0 ROM 0x0010 0000–0x0011 FFFF Reserved 0x0009 0000–0x0009 7FFF Reserved 0x0012 0000–0x0012 FFFF Reserved 0x0004 8000–0x0004 BFFF Block 0 SRAM 0x0004 C000–0x0004 FFFF Block 0 SRAM 0x0009 0000–0x0009 5554 Block 0 SRAM 0x0009 8000–0x0009 FFFF Block 0 SRAM 0x0013 0000–0x0013 FFFF Block 1 ROM 0x0005 0000–0x0005 7FFF Block 1 ROM 0x000A 0000–0x000A AAA9 Block 1 ROM 0x000A 0000–0x000A FFFF Block 1 ROM 0x0014 0000–0x0015 FFFF Reserved 0x000B 0000–0x000B 7FFF Reserved 0x0016 0000–0x0016 FFFF Reserved 0x0005 8000–0x0005 BFFF Block 1 SRAM 0x0005 C000–0x0005 FFFF Block 1 SRAM 0x000B 0000–0x000B 5554 Block 1 SRAM 0x000B 8000–0x000B FFFF Block 1 SRAM 0x0017 0000–0x0017 FFFF Block 2 SRAM 0x0006 0000–0x0006 1FFF Block 2 SRAM 0x000C 0000–0x000C 2AA9 Block 2 SRAM 0x000C 0000–0x000C 3FFF Block 2 SRAM 0x0018 0000–0x0018 7FFF Reserved 0x000C 4000–0x000D FFFF Reserved 0x0018 8000–0x001B FFFF Block 3 SRAM 0x000E 0000–0x000E 3FFF Block 3 SRAM 0x001C 0000–0x001C 7FFF Reserved 0x000E 4000–0x000F FFFF Reserved 0x001C 8000–0x001F FFFF Reserved 0x0006 2000–0x0006 FFFF Block 3 SRAM 0x0007 0000–0x0007 1FFF Block 3 SRAM 0x000E 0000–0x000E 2AA9 Reserved 0x0007 2000–0x0007 FFFF Reserved 0x0020 0000–0xFFFF FFFF or test access port, will be assigned to each customer. The device will ignore a wrong key. Emulation features and external boot modes are only available after the correct key is scanned. FAMILY PERIPHERAL ARCHITECTURE The ADSP-2136x family contains a rich set of peripherals that support a wide variety of applications, including high quality audio, medical imaging, communications, military, test equipment, 3D graphics, speech recognition, monitor control, imaging, and other applications. Parallel Port The parallel port provides interfaces to SRAM and peripheral devices. The multiplexed address and data pins (AD15–0) can access 8-bit devices with up to 24 bits of address, or 16-bit devices with up to 16 bits of address. In either mode, 8-bit or 16-bit, the maximum data transfer rate is 55 Mbps. DMA transfers are used to move data to and from internal memory. Access to the core is also facilitated through the parallel port register read/write functions. The RD, WR, and ALE (address latch enable) pins are the control pins for the parallel port. Rev. G | Serial Peripheral (Compatible) Interface The processors contain two serial peripheral interface ports (SPIs). The SPI is an industry-standard synchronous serial link, enabling the processor’s SPI-compatible port to communicate with other SPI-compatible devices. The SPI consists of two data pins, one device select pin, and one clock pin. It is a full-duplex synchronous serial interface, supporting both master and slave modes and can operate at a maximum baud rate of fPCLK/4. The SPI port can operate in a multimaster environment by interfacing with up to four other SPI-compatible devices, either acting as a master or slave device. The ADSP-2136x SPIcompatible peripheral implementation also features programmable baud rate, clock phase, and polarities. The SPIcompatible port uses open drain drivers to support a multimaster configuration and to avoid data contention. Pulse-Width Modulation The entire PWM module has four groups of four PWM outputs each. Therefore, this module generates 16 PWM outputs in total. Each PWM group produces two pairs of PWM signals on the four PWM outputs. The PWM module is a flexible, programmable, PWM waveform generator that can be programmed to generate the required switching patterns for various applications related to motor and engine control or audio power control. The PWM generator can Page 6 of 56 | March 2011 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Serial ports operate in four modes: generate either center-aligned or edge-aligned PWM waveforms. In addition, it can generate complementary signals on two outputs in paired mode or independent signals in nonpaired mode (applicable to a single group of four PWM waveforms). • Standard DSP serial mode • Multichannel (TDM) mode • I2S mode The PWM generator is capable of operating in two distinct modes while generating center-aligned PWM waveforms: single update mode or double update mode. In single update mode, the duty cycle values are programmable only once per PWM period. This results in PWM patterns that are symmetrical about the midpoint of the PWM period. In double update mode, a second updating of the PWM registers is implemented at the midpoint of the PWM period. In this mode, it is possible to produce asymmetrical PWM patterns that produce lower harmonic distortion in 3-phase PWM inverters. Digital Audio Interface (DAI) The digital audio interface (DAI) provides the ability to connect various peripherals to any of the DSP’s DAI pins (DAI_P20–1). Programs make these connections using the signal routing unit (SRU, shown in Figure 1). The SRU is a matrix routing unit (or group of multiplexers) that enables the peripherals provided by the DAI to be interconnected under software control. This allows easy use of the DAI-associated peripherals for a wider variety of applications by using a larger set of algorithms than is possible with nonconfigurable signal paths. The DAI includes six serial ports, an S/PDIF receiver/transmitter, a DTCP cipher, a precision clock generator (PCG), eight channels of asynchronous sample rate converters, an input data port (IDP), an SPI port, six flag outputs and six flag inputs, and three timers. The IDP provides an additional input path to the ADSP-2136x core, configurable as either eight channels of I2S serial data or as seven channels plus a single 20-bit wide synchronous parallel data acquisition port. Each data channel has its own DMA channel that is independent from the processor’s serial ports. Serial Ports The processor features six synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixedsignal peripheral devices such as Analog Devices’ AD183x family of audio codecs, ADCs, and DACs. The serial ports are made up of two data lines, a clock, and a frame sync. The data lines can be programmed to either transmit or receive and each data line has a dedicated DMA channel. Serial ports are enabled via 12 programmable and simultaneous receive or transmit pins that support up to 24 transmit or 24 receive channels of audio data when all six SPORTs are enabled, or six full duplex TDM streams of 128 channels per frame. Serial port data can be automatically transferred to and from on-chip memory via dedicated DMA channels. Each of the serial ports can work in conjunction with another serial port to provide TDM support. One SPORT provides two transmit signals while the other SPORT provides the two receive signals. The frame sync and clock are shared. Rev. G | • Left-justified sample pair mode S/PDIF-Compatible Digital Audio Receiver/Transmitter The S/PDIF transmitter has no separate DMA channels. It receives audio data in serial format and converts it into a biphase encoded signal. The serial data input to the transmitter can be formatted as left-justified, I2S, or right-justified with word widths of 16, 18, 20, or 24 bits. The serial data, clock, and frame sync inputs to the S/PDIF transmitter are routed through the signal routing unit (SRU). They can come from a variety of sources such as the SPORTs, external pins, the precision clock generators (PCGs), or the sample rate converters (SRC) and are controlled by the SRU control registers. Digital Transmission Content Protection (DTCP) The DTCP specification defines a cryptographic protocol for protecting audio entertainment content from illegal copying, intercepting, and tampering as it traverses high performance digital buses, such as the IEEE 1394 standard. Only legitimate entertainment content delivered to a source device via another approved copy protection system (such as the DVD content scrambling system) is protected by this copy protection system. This feature is available on the ADSP-21362 and ADSP-21365 processors only. Licensing through DTLA is required for these products. Visit www.dtcp.com for more information. Memory-to-Memory (MTM) If the DTCP module is not used, the memory-to-memory DMA module allows internal memory copies for a standard DMA. Synchronous/Asynchronous Sample Rate Converter (SRC) The sample rate converter (SRC) contains four SRC blocks and is the same core as that used in the AD1896 192 kHz stereo asynchronous sample rate converter and provides up to 140 dB SNR. The SRC block is used to perform synchronous or asynchronous sample rate conversion across independent stereo channels, without using internal processor resources. The four SRC blocks can also be configured to operate together to convert multichannel audio data without phase mismatches. Finally, the SRC is used to clean up audio data from jittery clock sources such as the S/PDIF receiver. The S/PDIF and SRC are not available on the ADSP-21363 models. Input Data Port (IDP) The IDP provides up to eight serial input channels—each with its own clock, frame sync, and data inputs. The eight channels are automatically multiplexed into a single 32-bit by eight-deep FIFO. Data is always formatted as a 64-bit frame and divided into two 32-bit words. The serial protocol is designed to receive Page 7 of 56 | March 2011 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 audio channels in I2S, left-justified sample pair, or right-justified mode. One frame sync cycle indicates one 64-bit left/right pair, but data is sent to the FIFO as 32-bit words (that is, onehalf of a frame at a time). The processor supports 24- and 32-bit I2S, 24- and 32-bit left-justified, and 24-, 20-, 18- and 16-bit right-justified formats. Precision Clock Generator (PCG) The precision clock generators (PCG) consist of two units, each of which generates a pair of signals (clock and frame sync) derived from a clock input signal. The units, A and B, are identical in functionality and operate independently of each other. The two signals generated by each unit are normally used as a serial bit clock/frame sync pair. Peripheral Timers The following three general-purpose timers can generate periodic interrupts and be independently set to operate in one of three modes: • Pulse waveform generation mode SYSTEM DESIGN The following sections provide an introduction to system design options and power supply issues. Program Booting The internal memory of the processor boots at system power-up from an 8-bit EPROM via the parallel port, an SPI master, an SPI slave, or an internal boot. Booting is determined by the boot configuration (BOOT_CFG1–0) pins in Table 5. Selection of the boot source is controlled via the SPI as either a master or slave device, or it can immediately begin executing from ROM. Table 5. Boot Mode Selection BOOT_CFG1–0 00 01 10 11 • Pulse width count/capture mode • External event watchdog mode Phase-Locked Loop Each general-purpose timer has one bidirectional pin and four registers that implement its mode of operation: a 6-bit configuration register, a 32-bit count register, a 32-bit period register, and a 32-bit pulse width register. A single control and status register enables or disables all three general-purpose timers independently. I/O PROCESSOR FEATURES The processor’s I/O provides many channels of DMA and controls the extensive set of peripherals described in the previous sections. DMA Controller The processor’s on-chip DMA controllers allow data transfers without processor intervention. The DMA controller operates independently and invisibly to the processor core, allowing DMA operations to occur while the core is simultaneously executing its program instructions. DMA transfers can occur between the processor’s internal memory and its serial ports, the SPI-compatible (serial peripheral interface) ports, the IDP (input data port), the parallel data acquisition port (PDAP), or the parallel port (PP). See Table 4. Table 4. DMA Channels Peripheral SPORTs IDP/PDAP SPI MTM/DTCP Parallel Port Total DMA Channels Booting Mode SPI Slave Boot SPI Master Boot Parallel Port Boot via EPROM No booting occurs. Processor executes from internal ROM after reset. ADSP-2136x 12 8 2 2 1 25 Rev. G | The processors use an on-chip phase-locked loop (PLL) to generate the internal clock for the core. On power-up, the CLK_CFG1–0 pins are used to select ratios of 32:1, 16:1, and 6:1. After booting, numerous other ratios can be selected via software control. The ratios are made up of software configurable numerator values from 1 to 64 and software configurable divisor values of 1, 2, 4, and 8. Power Supplies The processor has a separate power supply connection for the internal (VDDINT), external (VDDEXT), and analog (AVDD/AVSS) power supplies. The internal and analog supplies must meet the 1.2 V requirement for K, B, and Y grade models, and the 1.0 V requirement for Y models. (For information on the temperature ranges offered for this product, see Operating Conditions on Page 14, Package Information on Page 15, and Ordering Guide on Page 54.) The external supply must meet the 3.3 V requirement. All external supply pins must be connected to the same power supply. Note that the analog supply pin (AVDD) powers the processor’s internal clock generator PLL. To produce a stable clock, it is recommended that PCB designs use an external filter circuit for the AVDD pin. Place the filter components as close as possible to the AVDD/AVSS pins. For an example circuit, see Figure 3. (A recommended ferrite chip is the muRata BLM18AG102SN1D.) To reduce noise coupling, the PCB should use a parallel pair of power and ground planes for VDDINT and GND. Use wide traces to connect the bypass capacitors to the analog power (AVDD) and ground (AVSS) pins. Note that the AVDD and AVSS pins specified in Figure 3 are inputs to the processor and not the analog ground plane on the board—the AVSS pin should connect directly to digital ground (GND) at the chip. Page 8 of 56 | March 2011 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 100nF 10nF 1nF the real-time characteristics of the program. Essentially, the developer can identify bottlenecks in software quickly and efficiently. By using the profiler, the programmer can focus on those areas in the program that impact performance and take corrective action. ADSP-213xx AVDD VDDINT HIGH-Z FERRITE BEAD CHIP AVSS Through debugging both C/C++ and assembly programs with the VisualDSP++ debugger, programmers can: LOCATE ALL COMPONENTS CLOSE TO AVDD AND AVSS PINS • View mixed C/C++ and assembly code (interleaved source and object information) Figure 3. Analog Power (AVDD) Filter Circuit • Insert breakpoints Target Board JTAG Emulator Connector Analog Devices’ DSP Tools product line of JTAG emulators uses the IEEE 1149.1 JTAG test access port of the processor to monitor and control the target board processor during emulation. Analog Devices’ DSP Tools product line of JTAG emulators provides emulation at full processor speed, allowing inspection and modification of memory, registers, and processor stacks. The processor’s JTAG interface ensures that the emulator does not affect target system loading or timing. For complete information on Analog Devices’ SHARC DSP Tools product line of JTAG emulator operation, refer to the appropriate emulator user’s guide. DEVELOPMENT TOOLS The processor is supported with a complete set of CROSSCORE®† software and hardware development tools, including Analog Devices emulators and VisualDSP++®‡ development environment. The same emulator hardware that supports other SHARC processors also fully emulates the ADSP-2136x processors. The VisualDSP++ project management environment lets programmers develop and debug an application. This environment includes an easy-to-use assembler (based on an algebraic syntax), an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instruction-level simulator, a C/C++ compiler, and a C/C++ runtime library that includes DSP and mathematical functions. A key point for these tools is C/C++ code efficiency. The compiler has been developed for efficient translation of C/C++ code to DSP assembly. The SHARC has architectural features that improve the efficiency of compiled C/C++ code. The VisualDSP++ debugger has a number of important features. Data visualization is enhanced by a plotting package that offers a significant level of flexibility. This graphical representation of user data enables the programmer to quickly determine the performance of an algorithm. As algorithms grow in complexity, this capability can have increasing significance on the designer’s development schedule, increasing productivity. Statistical profiling enables the programmer to nonintrusively poll the processor as it is running the program. This feature, unique to VisualDSP++, enables the software developer to passively gather important code execution metrics without interrupting † ‡ • Set conditional breakpoints on registers, memory, and stacks • Perform linear or statistical profiling of program execution • Fill, dump, and graphically plot the contents of memory • Perform source level debugging • Create custom debugger windows The VisualDSP++ integrated development and debugging environment (IDDE) lets programmers define and manage DSP software development. Its dialog boxes and property pages let programmers configure and manage all of the SHARC development tools, including the color syntax highlighting in the VisualDSP++ editor. This capability permits programmers to: • Control how the development tools process inputs and generate outputs • Maintain a one-to-one correspondence with the tool’s command line switches The VisualDSP++ Kernel (VDK) incorporates scheduling and resource management tailored specifically to address the memory and timing constraints of DSP programming. These capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning, when developing new application code. The VDK features include threads, critical and unscheduled regions, semaphores, events, and device flags. The VDK also supports priority-based, preemptive, cooperative, and time-sliced scheduling approaches. In addition, the VDK is designed to be scalable. If the application does not use a specific feature, the support code for that feature is excluded from the target system. Because the VDK is a library, a developer can decide whether to use it or not. The VDK is integrated into the VisualDSP++ development environment, but can also be used via standard command line tools. When the VDK is used, the development environment assists the developer with many error-prone tasks and assists in managing system resources, automating the generation of various VDK-based objects, and visualizing the system state, when debugging an application that uses the VDK. Use the expert linker to visually manipulate the placement of code and data on the embedded system. View memory utilization in a color-coded graphical form, easily move code and data to different areas of the processor or external memory with a drag of the mouse and examine runtime stack and heap usage. CROSSCORE is a registered trademark of Analog Devices, Inc. VisualDSP++ is a registered trademark of Analog Devices, Inc. Rev. G | Page 9 of 56 | March 2011 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 The expert linker is fully compatible with the existing linker definition file (LDF), allowing the developer to move between the graphical and textual environments. In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the SHARC processor family. Hardware tools include SHARC processor PC plug-in cards. Third party software tools include DSP libraries, real-time operating systems, and block diagram design tools. Designing an Emulator-Compatible DSP Board (Target) The Analog Devices family of emulators are tools that every DSP developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG test access port (TAP) on each JTAG processor. Nonintrusive incircuit emulation is assured by the use of the processor’s JTAG interface. (The emulator does not affect target system loading or timing.) The emulator uses the TAP to access the internal features of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The processor must be halted to send data and commands, but once an operation has been completed by the emulator, the DSP system is set running at full speed with no impact on system timing. To use these emulators, the target board must include a header that connects the DSP’s JTAG port to the emulator. For details on target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, refer to the Analog Devices JTAG Emulation Technical Reference (EE-68) on the Analog Devices website, www.analog.com. (Perform a site search on “EE-68.”) This document is updated regularly to keep pace with improvements to emulator support. With a full version of VisualDSP++ installed (sold separately), engineers can develop software for the EZ-KIT Lite or any custom defined system. Connecting one of Analog Devices’ JTAG emulators to the EZ-KIT Lite board enables high speed, nonintrusive emulation. ADDITIONAL INFORMATION This data sheet provides a general overview of the processor’s architecture and functionality. For detailed information on the ADSP-2136x family core architecture and instruction set, refer to the ADSP-2136x SHARC Processor Hardware Reference and the ADSP-2136x SHARC Processor Programming Reference. RELATED SIGNAL CHAINS A signal chain is a series of signal-conditioning electronic components that receive input (data acquired from sampling either real-time phenomena or from stored data) in tandem, with the output of one portion of the chain supplying input to the next. Signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena. For more information about this term and related topics, see the “signal chain” entry in the Glossary of EE Terms on the Analog Devices website. Analog Devices eases signal processing system development by providing signal processing components that are designed to work together well. A tool for viewing relationships between specific applications and related components is available on the www.analog.com website. The Circuits from the LabTM site (http://www.analog.com/signalchains) provides: Evaluation Kit Analog Devices offers a range of EZ-KIT Lite®† evaluation platforms to use as a cost-effective method to learn more about developing or prototyping applications with Analog Devices processors, platforms, and software tools. Each EZ-KIT Lite platform includes an evaluation board along with an evaluation suite of the VisualDSP++ development and debugging environment with the C/C++ compiler, assembler, and linker. Also included are sample application programs, a power supply, and a USB cable. All evaluation versions of the software tools are limited for use only with the EZ-KIT Lite product. • Graphical circuit block diagram presentation of signal chains for a variety of circuit types and applications • Drill down links for components in each chain to selection guides and application information • Reference designs applying best practice design techniques The USB controller on the EZ-KIT Lite board connects the board to the USB port of the user’s PC, enabling the VisualDSP++ evaluation suite to emulate the on-board processor in-circuit. This permits the customer to download, execute, and debug programs for the EZ-KIT Lite system. It also allows in-circuit programming of the on-board flash device to store user-specific boot code, enabling the board to run as a standalone unit without being connected to the PC. † EZ-KIT Lite is a registered trademark of Analog Devices, Inc. Rev. G | Page 10 of 56 | March 2011 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 PIN FUNCTION DESCRIPTIONS The processor’s pin definitions are listed below. Inputs identified as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for TMS and TDI). Inputs identified as asynchronous (A) can be asserted asynchronously to CLKIN (or to TCK for TRST). Tie or pull unused inputs to VDDEXT or GND, except for the following: DAI_Px, SPICLK, MISO, MOSI, EMU, TMS, TRST, TDI, and AD15–0. Note: These pins have pull-up resistors. Table 6. Pin Descriptions Pin AD15–0 Type I/O/T (pu) State During and After Reset Three-state with pull-up enabled RD O (pu) Three-state, driven high1 WR O (pu) Three-state, driven high1 ALE O (pd) Three-state, driven low1 FLAG[0]/IRQ0/SPI FLG[0] FLAG[1]/IRQ1/SPI FLG[1] FLAG[2]/IRQ2/SPI FLG[2] FLAG[3]/TMREXP/ SPIFLG[3] DAI_P20–1 I/O FLAG[0] INPUT Function Parallel Port Address/Data. The ADSP-2136x parallel port and its corresponding DMA unit output addresses and data for peripherals on these multiplexed pins. The multiplex state is determined by the ALE pin. The parallel port can operate in either 8-bit or 16-bit mode. Each AD pin has a 22.5 kΩ internal pull-up resistor. For details about the AD pin operation, refer to the ADSP-2136x SHARC Processor Hardware Reference . For 8-bit mode: ALE is automatically asserted whenever a change occurs in the upper 16 external address bits, ADDR23–8; ALE is used in conjunction with an external latch to retain the values of the ADDR23–8. For detailed information on I/O operations and pin multiplexing, refer to the ADSP-2136x SHARC Processor Hardware Reference. Parallel Port Read Enable. RD is asserted low whenever the processor reads 8-bit or 16bit data from an external memory device. When AD15–0 are flags, this pin remains deasserted. RD has a 22.5 kΩ internal pull-up resistor. Parallel Port Write Enable. WR is asserted low whenever the processor writes 8-bit or 16-bit data to an external memory device. When AD15–0 are flags, this pin remains deasserted. WR has a 22.5 kΩ internal pull-up resistor. Parallel Port Address Latch Enable. ALE is asserted whenever the processor drives a new address on the parallel port address pins. On reset, ALE is active high. However, it can be reconfigured using software to be active low. When AD15–0 are flags, this pin remains deasserted. ALE has a 20 kΩ internal pull-down resistor. FLAG0/Interrupt Request0/SPI0 Slave Select. I/O FLAG[1] INPUT FLAG1/Interrupt Request1/SPI1 Slave Select. I/O FLAG[2] INPUT FLAG2/Interrupt Request 2/SPI2 Slave Select. I/O FLAG[3] INPUT FLAG3/Timer Expired/SPI3 Slave Select. I/O/T (pu) Three-state with programmable pull-up Digital Audio Interface Pins. These pins provide the physical interface to the SRU. The SRU configuration registers define the combination of on-chip peripheral inputs or outputs connected to the pin and to the pin’s output enable. The configuration registers of these peripherals then determine the exact behavior of the pin. Any input or output signal present in the SRU can be routed to any of these pins. The SRU provides the connection from the serial ports, input data port, precision clock generators and timers, sample rate converters and SPI to the DAI_P20–1 pins. These pins have internal 22.5 kΩ pull-up resistors that are enabled on reset. These pull-ups can be disabled using the DAI_PIN_PULLUP register. The following symbols appear in the Type column of Table 6: A = asynchronous, G = ground, I = input, O = output, P = power supply, S = synchronous, (A/D) = active drive, (O/D) = open drain, and T = three-state, (pd) = pull-down resistor, (pu) = pull-up resistor. Rev. G | Page 11 of 56 | March 2011 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Table 6. Pin Descriptions (Continued) Pin SPICLK Type I/O (pu) State During and After Reset Three-state with pull-up enabled, driven high in SPImaster boot mode Function Serial Peripheral Interface Clock Signal. Driven by the master, this signal controls the rate at which data is transferred. The master can transmit data at a variety of baud rates. SPICLK cycles once for each bit transmitted. SPICLK is a gated clock active during data transfers, only for the length of the transferred word. Slave devices ignore the serial clock if the slave select input is driven inactive (high). SPICLK is used to shift out and shift in the data driven on the MISO and MOSI lines. The data is always shifted out on one clock edge and sampled on the opposite edge of the clock. Clock polarity and clock phase relative to data are programmable into the SPICTL control register and define the transfer format. SPICLK has a 22.5 kΩ internal pull-up resistor. I Input only Serial Peripheral Interface Slave Device Select. An active low signal used to select the SPIDS processor as an SPI slave device. This input signal behaves like a chip select, and is provided by the master device for the slave devices. In multimaster mode the processor’s SPIDS signal can be driven by a slave device to signal to the processor (as SPI master) that an error has occurred, as some other device is also trying to be the master device. If asserted low when the device is in master mode, it is considered a multimaster error. For a single-master, multiple-slave configuration where flag pins are used, this pin must be tied or pulled high to VDDEXT on the master device. For processor to processor SPI interaction, any of the master processor’s flag pins can be used to drive the SPIDS signal on the SPI slave device. MOSI I/O (O/D) Three-state with SPI Master Out Slave In. If the ADSP-2136x is configured as a master, the MOSI pin (pu) pull-up enabled, becomes a data transmit (output) pin, transmitting output data. If the processor is driven low in SPIconfigured as a slave, the MOSI pin becomes a data receive (input) pin, receiving input master boot mode data. In an SPI interconnection, the data is shifted out from the MOSI output pin of the master and shifted into the MOSI input(s) of the slave(s). MOSI has a 22.5 kΩ internal pullup resistor. MISO I/O (O/D) Three-state with SPI Master In Slave Out. If the ADSP-2136x is configured as a master, the MISO pin (pu) pull-up enabled becomes a data receive (input) pin, receiving input data. If the processor is configured as a slave, the MISO pin becomes a data transmit (output) pin, transmitting output data. In an SPI interconnection, the data is shifted out from the MISO output pin of the slave and shifted into the MISO input pin of the master. MISO has a 22.5 kΩ internal pull-up resistor. MISO can be configured as O/D by setting the OPD bit in the SPICTL register. Note: Only one slave is allowed to transmit data at any given time. To enable broadcast transmission to multiple SPI slaves, the processor’s MISO pin can be disabled by setting Bit 5 (DMISO) of the SPICTL register equal to 1. CLKIN I Input only Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-2136x clock input. It configures the ADSP-2136x to use either its internal clock generator or an external clock source. Connecting the necessary components to CLKIN and XTAL enables the internal clock generator. Connecting the external clock to CLKIN while leaving XTAL unconnected configures the processors to use the external clock source such as an external clock oscillator. The core is clocked either by the PLL output or this clock input depending on the CLK_CFG1–0 pin settings. CLKIN should not be halted, changed, or operated below the specified frequency. 2 Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external crystal. XTAL O Output only CLK_CFG1–0 I Input only Core to CLKIN Ratio Control. These pins set the start up clock frequency. Note that the operating frequency can be changed by programming the PLL multiplier and divider in the PMCTL register at any time after the core comes out of reset. The allowed values are: 00 = 6:1 01 = 32:1 10 = 16:1 11 = reserved. The following symbols appear in the Type column of Table 6: A = asynchronous, G = ground, I = input, O = output, P = power supply, S = synchronous, (A/D) = active drive, (O/D) = open drain, and T = three-state, (pd) = pull-down resistor, (pu) = pull-up resistor. Rev. G | Page 12 of 56 | March 2011 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Table 6. Pin Descriptions (Continued) Pin BOOT_CFG1–0 Type I State During and After Reset Input only Function Boot Configuration Select. This pin is used to select the boot mode for the processor. The BOOT_CFG pins must be valid before reset is asserted. For a description of the boot mode, refer to the ADSP-2136x SHARC Processor Hardware Reference . RESETOUT O Output only Reset Out. Drives out the core reset signal to an external device. RESET I/A Input only Processor Reset. Resets the ADSP-2136x to a known state. Upon deassertion, there is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program execution from the hardware reset vector address. The RESET input must be asserted (low) at power-up. Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted TCK I Input only3 (pulsed low) after power-up or held low for proper operation of the processors. TMS I/S Three-state with Test Mode Select (JTAG). Used to control the test state machine. TMS has a 22.5 kΩ (pu) pull-up enabled internal pull-up resistor. TDI I/S Three-state with Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 22.5 (pu) pull-up enabled kΩ internal pull-up resistor. TDO O Three-state4 Test Data Output (JTAG). Serial scan output of the boundary scan path. TRST I/A Three-state with Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) (pu) pull-up enabled after power-up or held low for proper operation of the ADSP-2136x. TRST has a 22.5 kΩ internal pull-up resistor. EMU O (O/D) Three-state with Emulation Status. Must be connected to the processor’s JTAG emulators target board (pu) pull-up enabled connector only. EMU has a 22.5 kΩ internal pull-up resistor. P Core Power Supply. Nominally +1.2 V dc for the K, B grade models, and 1.0 V dc for the VDDINT Y grade models, and supplies the processor’s core. VDDEXT P I/O Power Supply. Nominally +3.3 V dc. AVDD P Analog Power Supply. Nominally +1.2 V dc for the K, B grade models, and 1.0 V dc for the Y grade models, and supplies the processor’s internal PLL (clock generator). This pin has the same specifications as VDDINT, except that added filtering circuitry is required. For more information, see Power Supplies on Page 8. G Analog Power Supply Return. AVSS GND G Power Supply Return. The following symbols appear in the Type column of Table 6: A = asynchronous, G = ground, I = input, O = output, P = power supply, S = synchronous, (A/D) = active drive, (O/D) = open drain, and T = three-state, (pd) = pull-down resistor, (pu) = pull-up resistor. 1 RD, WR, and ALE are three-stated (and not driven) only when RESET is active. Output only is a three-state driver with its output path always enabled. 3 Input only is a three-state driver with both output path and pull-up disabled. 4 Three-state is a three-state driver with pull-up disabled. 2 Rev. G | Page 13 of 56 | March 2011 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 SPECIFICATIONS Specifications are subject to change without notice. OPERATING CONDITIONS K Grade B Grade Y Grade Parameter Description Min Max Min Max Min Max Unit VDDINT Internal (Core) Supply Voltage 1.14 1.26 1.14 1.26 0.95 1.05 V AVDD Analog (PLL) Supply Voltage 1.14 1.26 1.14 1.26 0.95 1.05 V VDDEXT External (I/O) Supply Voltage 3.13 3.47 3.13 3.47 3.13 3.47 V VIH1 High Level Input Voltage @ VDDEXT = Max 2.0 VDDEXT + 0.5 2.0 VDDEXT + 0.5 2.0 VDDEXT + 0.5 V Low Level Input Voltage @ VDDEXT = Min –0.5 +0.8 –0.5 +0.8 –0.5 +0.8 V High Level Input Voltage @ VDDEXT = Max 1.74 VDDEXT + 0.5 1.74 VDDEXT + 0.5 1.74 VDDEXT + 0.5 V VIL 1 VIH_CLKIN 2 VIL_CLKIN Low Level Input Voltage @ VDDEXT = Min –0.5 +1.19 –0.5 +1.19 –0.5 +1.19 V TJ3, 4 Junction Temperature 136-Ball CSP_BGA 0 +110 –40 +125 –40 +125 °C TJ3, 4 Junction Temperature 144-Lead LQFP_EP 0 +110 –40 +125 –40 +125 °C 1 Applies to input and bidirectional pins: AD15–0, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, SPIDS, BOOT_CFGx, CLK_CFGx, RESET, TCK, TMS, TDI, and TRST. Applies to input pin CLKIN. 3 See ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 for information on thermal specifications. 4 See Estimating Power for the ADSP-21362 SHARC Processors (EE-277) for further information. 2 ELECTRICAL CHARACTERISTICS Parameter Description Test Conditions VOH1 High Level Output Voltage @ VDDEXT = Min, IOH = –1.0 mA2 1 Min 2 Low Level Output Voltage @ VDDEXT = Min, IOL = 1.0 mA 3, 4 High Level Input Current @ VDDEXT = Max, VIN = VDDEXT Max 3 VOL IIH Max 2.4 Unit V 0.4 V 10 μA Low Level Input Current @ VDDEXT = Max, VIN = 0 V 10 μA IILPU4 Low Level Input Current Pull-Up @ VDDEXT = Max, VIN = 0 V 200 μA IOZH5, 6 Three-State Leakage Current @ VDDEXT = Max, VIN = VDDEXT Max 10 μA Three-State Leakage Current @ VDDEXT = Max, VIN = 0 V 10 μA IOZLPU Three-State Leakage Current Pull-Up @ VDDEXT = Max, VIN = 0 V 200 μA IDD-INTYP7, 8 Supply Current (Internal) tCCLK = Min, VDDINT = Nom 800 mA Supply Current (Analog) AVDD = Max 10 mA Input Capacitance fIN = 1 MHz, TCASE = 25°C, VIN = 1.2 V 4.7 pF IIL IOZL 5 6 9 IAVDD CIN 10, 11 1 Applies to output and bidirectional pins: AD15–0, RD, WR, ALE, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, EMU, TDO, and XTAL. See Output Drive Currents on Page 44 for typical drive current capabilities. 3 Applies to input pins: SPIDS, BOOT_CFGx, CLK_CFGx, TCK, RESET, and CLKIN. 4 Applies to input pins with 22.5 kΩ internal pull-ups: TRST, TMS, TDI. 5 Applies to three-stateable pins: FLAG3–0. 6 Applies to three-stateable pins with 22.5 kΩ pull-ups: AD15–0, DAI_Px, SPICLK, EMU, MISO, and MOSI. 7 Typical internal current data reflects nominal operating conditions. 8 See Estimating Power for the ADSP-21362 SHARC Processors (EE-277) for further information. 9 Characterized, but not tested. 10 Applies to all signal pins. 11 Guaranteed, but not tested. 2 Rev. G | Page 14 of 56 | March 2011 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 PACKAGE INFORMATION Table 8. Absolute Maximum Ratings The information presented in Figure 4 provides details about the package branding for the ADSP-2136x processor. For a complete listing of product availability, see Ordering Guide on Page 54. a ADSP-2136x tppZ-cc vvvvvv.x n.n #yyww country_of_origin Rating –0.3 V to +1.5 V –0.3 V to +1.5 V –0.3 V to +4.6 V –0.5 V to +3.8 V –0.5 V to VDDEXT + 0.5 V 200 pF –65°C to +150°C 125°C TIMING SPECIFICATIONS S Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, it is not meaningful to add parameters to derive longer times. For voltage reference levels, see Figure 39 on Page 44 under Test Conditions . Figure 4. Typical Package Brand Table 7. Package Brand Information Brand Key t pp Z cc vvvvvv.x n.n # yyww Parameter Internal (Core) Supply Voltage (VDDINT) Analog (PLL) Supply Voltage (AVDD) External (I/O) Supply Voltage (VDDEXT) Input Voltage Output Voltage Swing Load Capacitance Storage Temperature Range Junction Temperature While Biased Field Description Temperature Range Package Type RoHS Compliant Designation See Ordering Guide Assembly Lot Code Silicon Revision RoHS Compliant Designation Date Code Switching Characteristics specify how the processor changes its signals. Circuitry external to the processor must be designed for compatibility with these signal characteristics. Switching characteristics describe what the processor will do in a given circumstance. Use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. Timing Requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. Timing requirements guarantee that the processor operates correctly with other devices. ESD CAUTION ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. MAXIMUM POWER DISSIPATION See Estimating Power for the ADSP-21362 SHARC Processors (EE-277) for detailed thermal and power information regarding maximum power dissipation. For information on package thermal specifications, see Thermal Characteristics on Page 45. Core Clock Requirements The processor’s internal clock (a multiple of CLKIN) provides the clock signal for timing internal memory, processor core, and serial ports. During reset, program the ratio between the processor’s internal clock frequency and external (CLKIN) clock frequency with the CLK_CFG1–0 pins. The processor’s internal clock switches at higher frequencies than the system input clock (CLKIN). To generate the internal clock, the processor uses an internal phase-locked loop (PLL, see Figure 5). This PLL-based clocking minimizes the skew between the system clock (CLKIN) signal and the processor’s internal clock. Voltage Controlled Oscillator ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed in Table 8 may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. G | In application designs, the PLL multiplier value should be selected in such a way that the VCO frequency never exceeds fVCO specified in Table 11. Page 15 of 56 | • The product of CLKIN and PLLM must never exceed 1/2 fVCO (max) in Table 11 if the input divider is not enabled (INDIV = 0). March 2011 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 • The product of CLKIN and PLLM must never exceed fVCO (max) in Table 11 if the input divider is enabled (INDIV = 1). Note the definitions of the clock periods that are a function of CLKIN and the appropriate ratio control shown in Table 9. All of the timing specifications for the ADSP-2136x peripherals are defined in relation to tPCLK. Refer to the peripheral specific section for each peripheral’s timing information. The VCO frequency is calculated as follows: fVCO = 2 × PLLM × fINPUT fCCLK = (2 × PLLM × fINPUT) ÷ (2 × PLLN) Table 9. Clock Periods where: Timing Requirements tCK tCCLK tPCLK fVCO = VCO output PLLM = Multiplier value programmed in the PMCTL register. During reset, the PLLM value is derived from the ratio selected using the CLK_CFG pins in hardware. PLLN = 1, 2, 4, 8 based on the PLLD value programmed on the PMCTL register. During reset this value is 1. Description CLKIN Clock Period Processor Core Clock Period Peripheral Clock Period = 2 × tCCLK Figure 5 shows core to CLKIN relationships with external oscillator or crystal. The shaded divider/multiplier blocks denote where clock ratios can be set through hardware or software using the power management control register (PMCTL). For more information, refer to the ADSP-2136x SHARC Processor Hardware Reference. fINPUT = Input frequency to the PLL. fINPUT = CLKIN when the input divider is disabled or fINPUT = CLKIN ÷ 2 when the input divider is enabled PLL CLKIN DIVIDER LOOP FILTER fINPUT fVCO VCO PLL DIVIDER fCCLK BYPASS MUX CLKIN CCLK XTAL BUF CLK_CFGx/ PMCTL (2 × PLLM) PMCTL (INDIV) PMCTL (PLLD) PMCTL (PLLBP) DIVIDE BY 2 PCLK fVCO ÷ (2 × PLLM) PMCTL (CLKOUTEN) CLKOUT (TEST ONLY)* DELAY OF 4096 CLKIN CYCLES PIN MUX RESET RESETOUT RESETOUT BUF CORERST *CLKOUT (TEST ONLY) FREQUENCY IS THE SAME AS fINPUT. THIS SIGNAL IS NOT SPECIFIED OR SUPPORTED FOR ANY DESIGN. Figure 5. Core Clock and System Clock Relationship to CLKIN Rev. G | Page 16 of 56 | March 2011 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Power-Up Sequencing three-state leakage current pull-up, pull-down, may be observed on any pin, even if that is an input only (for example the RESET pin) until the VDDINT rail has powered up. The timing requirements for processor startup are given in Table 10. Note that during power-up, when the VDDINT power supply comes up after VDDEXT, a leakage current of the order of Table 10. Power-Up Sequencing Timing Requirements (Processor Startup) Parameter Timing Requirements RESET Low Before VDDINT/VDDEXT On tRSTVDD tIVDDEVDD VDDINT On Before VDDEXT tCLKVDD1 CLKIN Valid After VDDINT/VDDEXT Valid tCLKRST CLKIN Valid Before RESET Deasserted tPLLRST PLL Control Setup Before RESET Deasserted Switching Characteristic Core Reset Deasserted After RESET Deasserted tCORERST Min Max 0 –50 0 102 20 +200 200 Unit ns ms ms μs μs 4096tCK + 2 tCCLK 3, 4 1 Valid VDDINT/VDDEXT assumes that the supplies are fully ramped to their 1.2 V rails and 3.3 V rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds, depending on the design of the power supply subsystem. 2 Assumes a stable CLKIN signal, after meeting worst-case start-up timing of crystal oscillators. Refer to your crystal oscillator manufacturer’s data sheet for start-up time. Assume a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal. 3 Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low to properly initialize and propagate default states at all I/O pins. 4 The 4096 cycle count depends on tSRST specification in Table 12. If setup time is not met, 1 additional CLKIN cycle can be added to the core reset time, resulting in 4097 cycles maximum. RESET VDDINT tRSTVDD tIVDDEVDD VDDEXT tCLKVDD CLKIN tCLKRST CLK_CFG1–0 tPLLRST tCORERST RESETOUT Figure 6. Power-Up Sequencing Rev. G | Page 17 of 56 | March 2011 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Clock Input Table 11. Clock Input Parameter Min Timing Requirements tCK CLKIN Period tCKL CLKIN Width Low tCKH CLKIN Width High tCKRF CLKIN Rise/Fall (0.4 V to 2.0 V) tCCLK4 CCLK Period VCO Frequency tVCO5 tCKJ6,7 CLKIN Jitter Tolerance 200 MHz1 Max 303 12.51 12.51 Min 181 7.51 7.51 100 3 10 600 +250 5.01 200 –250 333 MHz2 Max Unit 100 ns ns ns ns ns MHz ps 3 10 800 +250 3.01 200 –250 1 Applies to all 200 MHz models. See Ordering Guide on Page 54. Applies to all 333 MHz models. See Ordering Guide on Page 54. 3 Applies only for CLK_CFG1–0 = 00 and default values for PLL control bits in the PMCTL register. 4 Any changes to PLL control bits in the PMCTL register must meet core clock timing specification tCCLK. 5 See Figure 5 on Page 16 for VCO diagram. 6 Actual input jitter should be combined with AC specifications for accurate timing analysis. 7 Jitter specification is maximum peak-to-peak time interval error (TIE) jitter. 2 tCKJ tCK CLKIN tCKH tCKL Figure 7. Clock Input Clock Signals The processor can use an external clock or a crystal. Refer to the CLKIN pin description in Table 6 on Page 11. The user application program can configure the processor to use its internal clock generator by connecting the necessary components to the CLKIN and XTAL pins. Figure 8 shows the component connections used for a fundamental frequency crystal operating in parallel mode. ADSP-2136x R1 1M Ω * CLKIN XTAL R2 47Ω * C1 22pF Note that the clock rate is achieved using a 16.67 MHz crystal and a PLL multiplier ratio 16:1. (CCLK:CLKIN achieves a clock speed of 266.72 MHz.) To achieve the full core clock rate, programs need to configure the multiplier bits in the PMCTL register. Y1 C2 22pF 24.576MHz R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL DRIVE POWER. REFER TO CRYSTAL MANUFACTURER’S SPECIFICATIONS. *TYPICAL VALUES Figure 8. Recommended Circuit for Fundamental Mode Crystal Operation Rev. G | Page 18 of 56 | March 2011 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Reset Table 12. Reset Parameter Timing Requirements tWRST1 tSRST 1 RESET Pulse Width Low RESET Setup Before CLKIN Low Min Unit 4 × tCK 8 ns ns Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator). CLKIN tWRST tSRST RESET Figure 9. Reset Interrupts The following timing specification applies to the FLAG0, FLAG1, and FLAG2 pins when they are configured as IRQ0, IRQ1, and IRQ2 interrupts. Table 13. Interrupts Parameter Timing Requirement tIPW IRQx Pulse Width DAI_P20–1 FLAG2–0 (IRQ2–0) tIPW Figure 10. Interrupts Rev. G | Page 19 of 56 | March 2011 Min Unit 2 × tPCLK +2 ns ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Core Timer The following timing specification applies to FLAG3 when it is configured as the core timer (TMREXP pin). Table 14. Core Timer Parameter Switching Characteristic tWCTIM TMREXP Pulse Width FLAG3 (TMREXP) Min Unit 2 × tPCLK – 1 ns tWCTIM Figure 11. Core Timer Timer PWM_OUT Cycle Timing The following timing specification applies to Timer0, Timer1, and Timer2 in PWM_OUT (pulse-width modulation) mode. Timer signals are routed to the DAI_P20–1 pins through the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 15. Timer PWM_OUT Timing Parameter Switching Characteristic tPWMO Timer Pulse Width Output Min Max Unit 2 tPCLK – 1 2(231 – 1) tPCLK ns tPWMO DAI_P20–1 (TIMER2–0) Figure 12. Timer PWM_OUT Timing Rev. G | Page 20 of 56 | March 2011 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Timer WDTH_CAP Timing The following timing specification applies to Timer0, Timer1, and Timer2 in WDTH_CAP (pulse width count and capture) mode. Timer signals are routed to the DAI_P20–1 pins through the SRU. Therefore, the timing specification provided below are valid at the DAI_P20–1 pins. Table 16. Timer Width Capture Timing Parameter Timing Requirement tPWI Timer Pulse Width Min Max Unit 2 tPCLK 2(231– 1) tPCLK ns tPWI DAI_P20–1 (TIMER2–0) Figure 13. Timer Width Capture Timing DAI Pin to Pin Direct Routing For direct pin connections only (for example, DAI_PB01_I to DAI_PB02_O). Table 17. DAI Pin to Pin Routing Parameter Timing Requirement tDPIO Delay DAI Pin Input Valid to DAI Output Valid Min Max Unit 1.5 10 ns DAI_Pn DAI_Pm tDPIO Figure 14. DAI Pin to Pin Direct Routing Rev. G | Page 21 of 56 | March 2011 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Precision Clock Generator (Direct Pin Routing) This timing is only valid when the SRU is configured such that the precision clock generator (PCG) takes its inputs directly from the DAI pins (via pin buffers) and sends its outputs directly to the DAI pins. For the other cases, where the PCG’s inputs and outputs are not directly routed to/from DAI pins (via pin buffers) there is no timing data available. All timing parameters and switching characteristics apply to external DAI pins (DAI_P01 through DAI_P20). Table 18. Precision Clock Generator (Direct Pin Routing) K and B Grade Y Grade Parameter Min Max Max Unit Timing Requirements tPCGIP Input Clock Period tPCLK × 4 ns PCG Trigger Setup Before Falling 4.5 ns tSTRIG Edge of PCG Input Clock tHTRIG PCG Trigger Hold After Falling 3 ns Edge of PCG Input Clock Switching Characteristics tDPCGIO PCG Output Clock and Frame Sync Active Edge Delay After PCG Input 2.5 10 10 ns Clock tDTRIGCLK PCG Output Clock Delay After PCG 2.5 + (2.5 × tPCGIP) 10 + (2.5 × tPCGIP) 12 + (2.5 × tPCGIP) ns Trigger tDTRIGFS PCG Frame Sync Delay After PCG 2.5 + ((2.5 + D – PH) × tPCGIP) 10 + ((2.5 + D – PH) × tPCGIP) 12 + ((2.5 + D – PH) × tPCGIP) ns Trigger tPCGOP1 Output Clock Period 2 × tPCGIP – 1 ns D = FSxDIV, PH = FSxPHASE. For more information, refer to the ADSP-2136x SHARC Processor Hardware Reference, “Precision Clock Generators” chapter. 1 In normal mode, tPCGOP (min) = 2 × tPCGIP. tSTRIG tHTRIG DAI_Pn PCG_TRIGx_I tPCGIP DAI_Pm PCG_EXTx_I (CLKIN) tDPCGIO DAI_Py PCG_CLKx_O tDTRIGCLK tDPCGIO DAI_Pz PCG_FSx_O tDTRIGFS Figure 15. Precision Clock Generator (Direct Pin Routing) Rev. G | Page 22 of 56 | March 2011 tPCGOP ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Flags The timing specifications provided below apply to the FLAG3–0 and DAI_P20–1 pins, the parallel port, and the serial peripheral interface (SPI). See Table 6 on Page 11 for more information on flag use. Table 19. Flags Parameter Timing Requirement tFIPW FLAG3–0 IN Pulse Width Switching Characteristic FLAG3–0 OUT Pulse Width tFOPW DAI_P20–1 (FLAG3–0IN) (AD15–0) tFIPW DAI_P20–1 (FLAG3–0OUT) (AD15–0) tFOPW Figure 16. Flags Rev. G | Page 23 of 56 | March 2011 Min Unit 2 × tPCLK + 3 ns 2 × tPCLK – 1 ns ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Memory Read—Parallel Port Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) when the processor is accessing external memory space. Table 20. 8-Bit Memory Read Cycle K and B Grade Parameter Min Max Timing Requirements tDRS AD7–0 Data Setup Before RD High 3.3 tDRH AD7–0 Data Hold After RD High 0 tDAD AD15–8 Address to AD7–0 Data Valid D + tPCLK – 5.0 Switching Characteristics tALEW ALE Pulse Width 2 × tPCLK – 2.0 1 AD15–0 Address Setup Before ALE Deasserted tPCLK – 2.5 tADAS tRRH Delay Between RD Rising Edge to Next H + tPCLK – 1.4 Falling Edge tALERW ALE Deasserted to Read Asserted 2 × tPCLK – 3.8 tRWALE Read Deasserted to ALE Asserted F + H + 0.5 tADAH1 AD15–0 Address Hold After ALE Deasserted tPCLK – 2.3 tALEHZ1 ALE Deasserted to AD7–0 Address in High-Z tPCLK tPCLK + 3.0 tRW RD Pulse Width D – 2.0 tRDDRV AD7–0 ALE Address Drive After Read High F + H + tPCLK – 2.3 AD15–8 Address Hold After RD High H tADRH tDAWH AD15–8 Address to RD High D + tPCLK – 4.0 D = (The value set by the PPDUR Bits (5–1) in the PPCTL register) × tPCLK H = tPCLK (if a hold cycle is specified, else H = 0) F = 7 × tPCLK (if FLASH_MODE is set, else F = 0) 1 Min Y Grade Max 4.5 0 ns ns D + tPCLK – 5.0 ns 2 × tPCLK – 2.0 tPCLK – 2.5 H + tPCLK – 1.4 ns ns ns 2 × tPCLK – 3.8 F + H + 0.5 tPCLK – 2.3 tPCLK tPCLK + 3.8 D – 2.0 F + H + tPCLK – 2.3 H D + tPCLK – 4.0 ns ns ns ns ns ns ns ns On reset, ALE is an active high cycle. However, it can be configured by software to be active low. ALE tALEW tRWALE tALERW tRRH tRW RD tRDDRV WR AD15–8 tADAS tDAWH tADAH tADRH VALID ADDRESS VALID ADDRESS VALID ADDRESS tDAD AD7–0 VALID DATA VALID ADDRESS tDRS VALID ADDRESS tDRH VALID DATA VALID ADDRESS tALEHZ NOTE: MEMORY READS ALWAYS OCCUR IN GROUPS OF FOUR BETWEEN ALE CYCLES. THIS FIGURE SHOWS ONLY TWO MEMORY READS TO PROVIDE THE NECESSARY TIMING INFORMATION. Figure 17. Read Cycle for 8-Bit Memory Timing Rev. G | Page 24 of 56 | March 2011 Unit ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Table 21. 16-Bit Memory Read Cycle K and B Grade Max Parameter Min Timing Requirements tDRS AD15–0 Data Setup Before RD High 3.3 tDRH AD15–0 Data Hold After RD High 0 Switching Characteristics tALEW ALE Pulse Width 2 × tPCLK – 2.0 tADAS1 AD15–0 Address Setup Before ALE Deasserted tPCLK – 2.5 tALERW ALE Deasserted to Read Asserted 2 × tPCLK – 3.8 tRRH2 Delay Between RD Rising Edge to Next Falling H + tPCLK – 1.4 Edge tRWALE Read Deasserted to ALE Asserted F + H + 0.5 tRDDRV ALE Address Drive After Read High F + H + tPCLK – 2.3 1 AD15–0 Address Hold After ALE Deasserted tPCLK – 2.3 tADAH tALEHZ1 ALE Deasserted to Address/Data15–0 in High-Z tPCLK tRW RD Pulse Width D – 2.0 D = (The value set by the PPDUR Bits (5–1) in the PPCTL register) × tPCLK H = tPCLK (if a hold cycle is specified, else H = 0) F = 7 × tPCLK (if FLASH_MODE is set, else F = 0) 1 2 Min Y Grade Max 4.5 0 ns ns 2 × tPCLK – 2.0 tPCLK – 2.5 2 × tPCLK – 3.8 H + tPCLK – 1.4 ns ns ns ns F + H + 0.5 F + H + tPCLK – 2.3 tPCLK – 2.3 tPCLK + 3.0 tPCLK tPCLK + 3.8 D – 2.0 On reset, ALE is an active high cycle. However, it can be configured by software to be active low. This parameter is only available when in EMPP = 0 mode. ALE tALEW tRWALE tALERW tRRH tRW RD WR tALEHZ tADAS AD15–0 tDRS tADAH VALID ADDRESS tRDDRV tDRH VALID DATA VALID DATA VALID ADDRESS NOTE: FOR 16-BIT MEMORY READS, WHEN EMPP ⬆ 0, ONLY ONE RD PULSE OCCURS BETWEEN ALE CYCLES. WHEN EMPP = 0, MULTIPLE RD PULSES OCCUR BETWEEN ALE CYCLES. FOR COMPLETE INFORMATION, SEE THE ADSP-2136x SHARC PROCESSOR HARDWARE REFERENCE. Figure 18. Read Cycle for 16-Bit Memory Timing Rev. G | Page 25 of 56 | March 2011 Unit ns ns ns ns ns ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Memory Write—Parallel Port Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) when the processor is accessing external memory space. Table 22. 8-Bit Memory Write Cycle K and B Grade Parameter Min Switching Characteristics tALEW ALE Pulse Width 2 × tPCLK – 2.0 tADAS1 AD15–0 Address Setup Before ALE Deasserted tPCLK – 2.8 tALERW ALE Deasserted to Write Asserted 2 × tPCLK – 3.8 tRWALE Write Deasserted to ALE Asserted H + 0.5 tWRH Delay Between WR Rising Edge to Next WR Falling Edge F + H + tPCLK – 2.3 1 AD15–0 Address Hold After ALE Deasserted tPCLK – 0.5 tADAH tWW WR Pulse Width D – F – 2.0 tADWL AD15–8 Address to WR Low tPCLK – 2.8 tADWH AD15–8 Address Hold After WR High H tDWS AD7–0 Data Setup Before WR High D – F + tPCLK – 4.0 tDWH AD7–0 Data Hold After WR High H AD15–8 Address to WR High D – F + tPCLK – 4.0 tDAWH D = (The value set by the PPDUR Bits (5–1) in the PPCTL register) × tPCLK. H = tPCLK (if a hold cycle is specified, else H = 0) F = 7 × tPCLK (if FLASH_MODE is set, else F = 0). If FLASH_MODE is set, D must be ≥ 9 × tPCLK. 1 Y Grade Min Unit 2 × tPCLK – 2.0 tPCLK – 2.8 2 × tPCLK – 3.8 H + 0.5 F + H + tPCLK – 2.3 tPCLK – 0.5 D – F – 2.0 tPCLK – 3.5 H D – F + tPCLK – 4.0 H D – F + tPCLK – 4.0 ns ns ns ns ns ns ns ns ns ns ns ns On reset, ALE is an active high cycle. However, it can be configured by software to be active low. ALE tALERW tALEW tRWALE tWW WR tWRH tADWL tDAWH RD tADAS tADAH tADWH AD15-8 VALID ADDRESS VALID ADDRESS VALID ADDRESS tDWH tDWS AD7-0 VALID ADDRESS VALID DATA VALID DATA NOTE: MEMORY WRITES ALWAYS OCCUR IN GROUPS OF FOUR BETWEEN ALE CYCLES. THIS FIGURE SHOWS ONLY TWO MEMORY WRITES TO PROVIDE THE NECESSARY TIMING INFORMATION. Figure 19. Write Cycle for 8-Bit Memory Timing Rev. G | Page 26 of 56 | March 2011 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Table 23. 16-Bit Memory Write Cycle K and B Grade Parameter Min Switching Characteristics tALEW ALE Pulse Width 2 × tPCLK – 2.0 tADAS1 AD15–0 Address Setup Before ALE Deasserted tPCLK – 2.5 tALERW ALE Deasserted to Write Asserted 2 × tPCLK – 3.8 tRWALE Write Deasserted to ALE Asserted H + 0.5 tWRH2 Delay Between WR Rising Edge to Next WR Falling Edge F + H + tPCLK – 2.3 1 tADAH AD15–0 Address Hold After ALE Deasserted tPCLK – 2.3 tWW WR Pulse Width D – F – 2.0 AD15–0 Data Setup Before WR High D – F + tPCLK – 4.0 tDWS tDWH AD15–0 Data Hold After WR High H D = (the value set by the PPDUR Bits (5–1) in the PPCTL register) × tPCLK. H = tPCLK (if a hold cycle is specified, else H = 0) F = 7 × tPCLK (if FLASH_MODE is set, else F = 0). If FLASH_MODE is set, D must be ≥ 9 × tPCLK. tPCLK = (peripheral) clock period = 2 × tCCLK 1 2 Y Grade Min Unit 2 × tPCLK – 2.0 tPCLK – 2.5 2 × tPCLK – 3.8 H + 0.5 F + H + tPCLK – 2.3 tPCLK – 2.3 D – F – 2.0 D – F + tPCLK – 4.0 H ns ns ns ns ns ns ns ns ns On reset, ALE is an active high cycle. However, it can be configured by software to be active low. This parameter is only available when in EMPP = 0 mode. ALE tALEW tRWALE tALERW tRRH tRW RD WR tALEHZ tADAS AD15–0 tDRS tADAH VALID ADDRESS tRDDRV tDRH VALID DATA VALID DATA VALID ADDRESS NOTE: FOR 16-BIT MEMORY READS, WHEN EMPP ⬆ 0, ONLY ONE RD PULSE OCCURS BETWEEN ALE CYCLES. WHEN EMPP = 0, MULTIPLE RD PULSES OCCUR BETWEEN ALE CYCLES. FOR COMPLETE INFORMATION, SEE THE ADSP-2136x SHARC PROCESSOR HARDWARE REFERENCE. Figure 20. Write Cycle for 16-Bit Memory Timing Rev. G | Page 27 of 56 | March 2011 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Serial Ports To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync (FS) delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) serial clock (SCLK) width. Serial port signals are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 24. Serial Ports—External Clock Parameter Timing Requirements tSFSE1 Frame Sync Setup Before SCLK (Externally Generated Frame Sync in Either Transmit or Receive Mode) 1 tHFSE Frame Sync Hold After SCLK (Externally Generated Frame Sync in Either Transmit or Receive Mode) 1 tSDRE Receive Data Setup Before Receive SCLK tHDRE1 Receive Data Hold After SCLK tSCLKW SCLK Width tSCLK SCLK Period Switching Characteristics tDFSE2 Frame Sync Delay After SCLK (Internally Generated Frame Sync in Either Transmit or Receive Mode) tHOFSE2 Frame Sync Hold After SCLK (Internally Generated Frame Sync in Either Transmit or Receive Mode) tDDTE2 Transmit Data Delay After Transmit SCLK 2 tHDTE Transmit Data Hold After Transmit SCLK Min K and B Grade Max Y Grade Max Unit 2.5 ns 2.5 2.5 2.5 (tPCLK × 4) ÷ 2 – 0.5 tPCLK × 4 ns ns ns ns ns 9.5 11 ns 9.5 11 ns ns ns 2 2 1 Referenced to sample edge. 2 Referenced to drive edge. Table 25. Serial Ports—Internal Clock Parameter Timing Requirements tSFSI1 Frame Sync Setup Before SCLK (Externally Generated Frame Sync in Either Transmit or Receive Mode) tHFSI1 Frame Sync Hold After SCLK (Externally Generated Frame Sync in Either Transmit or Receive Mode) Receive Data Setup Before SCLK tSDRI1 tHDRI1 Receive Data Hold After SCLK Switching Characteristics tDFSI2 Frame Sync Delay After SCLK (Internally Generated Frame Sync in Transmit Mode) tHOFSI2 Frame Sync Hold After SCLK (Internally Generated Frame Sync in Transmit Mode) tDFSIR2 Frame Sync Delay After SCLK (Internally Generated Frame Sync in Receive Mode) tHOFSIR2 Frame Sync Hold After SCLK (Internally Generated Frame Sync in Receive Mode) tDDTI2 Transmit Data Delay After SCLK 2 tHDTI Transmit Data Hold After SCLK tSCLKIW Transmit or Receive SCLK Width 1 2 Referenced to the sample edge. Referenced to drive edge. Rev. G | Page 28 of 56 | March 2011 Min K and B Grade Max Y Grade Max Unit 7 ns 2.5 7 2.5 ns ns ns 3 ns ns 8 9.5 ns –1.0 ns 3 4.0 ns –1.0 ns 2 × tPCLK – 2 2 × tPCLK + 2 2 × tPCLK + 2 ns –1.0 3.5 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 DATA RECEIVE—INTERNAL CLOCK DRIVE EDGE tSCLKIW DATA RECEIVE—EXTERNAL CLOCK SAMPLE EDGE DRIVE EDGE DAI_P20–1 (SCLK) SAMPLE EDGE tSCLKW DAI_P20–1 (SCLK) tDFSIR tDFSE tSFSI tHOFSIR tHFSI DAI_P20–1 (FRAME SYNC) tSFSE tHFSE tSDRE tHDRE tHOFSE DAI_P20–1 (FRAME SYNC) tSDRI tHDRI DAI_P20–1 (DATA CHANNEL A/B) DAI_P20–1 (DATA CHANNEL A/B) NOTE: EITHER THE RISING EDGE OR THE FALLING EDGE OF SCLK (EXTERNAL OR INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE. DATA TRANSMIT—INTERNAL CLOCK DRIVE EDGE tSCLKIW DATA TRANSMIT—EXTERNAL CLOCK SAMPLE EDGE DRIVE EDGE DAI_P20–1 (SCLK) tSCLKW SAMPLE EDGE DAI_P20–1 (SCLK) tDFSI tDFSE tHOFSI tSFSI tHFSI DAI_P20–1 (SCLK) tSFSE tHOFSE tHFSE DAI_P20–1 (FRAME SYNC) tHDTI tDDTI tHDTE DAI_P20–1 (DATA CHANNEL A/B) tDDTE DAI_P20–1 (DATA CHANNEL A/B) NOTE: EITHER THE RISING EDGE OR THE FALLING EDGE OF SCLK (EXTERNAL OR INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE. Figure 21. Serial Ports Rev. G | Page 29 of 56 | March 2011 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Table 26. Serial Ports—External Late Frame Sync Parameter Min Switching Characteristics tDDTLFSE1 Data Delay from Late External Transmit Frame Sync or External Receive FS with MCE = 1, MFD = 0 tDDTENFS1 Data Enable for MCE = 1, MFD = 0 0.5 1 K and B Grade Max Y Grade 9 Max Unit 10.5 ns ns The tDDTLFSE and tDDTENFS parameters apply to left-justified sample pair as well as serial mode, and MCE = 1, MFD = 0. EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0 DRIVE SAMPLE DRIVE DAI_P20–1 (SCLK) tHFSE/I tSFSE/I DAI_P20–1 (FRAME SYNC) tDDTE/I tDDTENFS tHDTE/I DAI_P20–1 (DATA CHANNEL A/B) 2ND BIT 1ST BIT tDDTLFSE LATE EXTERNAL TRANSMIT FS DRIVE SAMPLE DRIVE DAI_P20–1 (SCLK) tSFSE/I tHFSE/I DAI_P20–1 (FRAME SYNC) tDDTE/I tDDTENFS tHDTE/I DAI_P20–1 (DATA CHANNEL A/B) 2ND BIT 1ST BIT tDDTLFSE NOTES: THIS FIGURE REFLECTS CHANGES MADE TO SUPPORT LEFT-JUSTIFIED SAMPLE PAIR MODE. SERIAL PORT SIGNALS (SCLK, FS, DATA CHANNEL A/B) ARE ROUTED TO THE DAI_P20–1 PINS USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED ARE VALID AT THE DAI_P20–1 PINS. THE CHARACTERIZED SPORT AC TIMINGS ARE APPLICABLE WHEN INTERNAL CLOCKS AND FRAMES ARE LOOPED BACK FROM THE PIN, NOT ROUTED DIRECTLY THROUGH THE SRU. Figure 22. External Late Frame Sync Rev. G | Page 30 of 56 | March 2011 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Table 27. Serial Ports—Enable and Three-State Parameter Switching Characteristics tDDTEN1 Data Enable from External Transmit SCLK tDDTTE1 Data Disable from External Transmit SCLK 1 tDDTIN Data Enable from Internal Transmit SCLK 1 Min K and B Grade Max Y Grade Max Unit 8.5 ns ns ns 2 7 –1 Referenced to drive edge. DRIVE EDGE DRIVE EDGE DAI_P20–1 (SCLK, EXT) tDDTEN tDDTTE DAI_P20–1 (DATA CHANNEL A/B) DRIVE EDGE DAI_P20–1 (SCLK, INT) tDDTIN DAI_P20–1 (DATA CHANNEL A/B) Figure 23. Enable and Three-State Rev. G | Page 31 of 56 | March 2011 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Input Data Port (IDP) The timing requirements for the IDP are given in Table 28. IDP signals are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 28. IDP Parameter Timing Requirements tSISFS1 Frame Sync Setup Before Clock Rising Edge 1 tSIHFS Frame Sync Hold After Clock Rising Edge Data Setup Before Clock Rising Edge tSISD1 tSIHD1 Data Hold After Clock Rising Edge tIDPCLKW Clock Width tIDPCLK Clock Period 1 Min Unit 3 3 3 3 (tPCLK × 4) ÷ 2 – 1 tPCLK × 4 ns ns ns ns ns ns The data, clock, and frame sync signals can come from any of the DAI pins. Clock and frame sync can also come via the PCGs or SPORTs. The PCG’s input can be either CLKIN or any of the DAI pins. SAMPLE EDGE tIPDCLK tIPDCLKW DAI_P20–1 (SERIAL CLOCK) tSISFS tSIHFS DAI_P20–1 (FRAME SYNC) tSISD tSIHD DAI_P20–1 (DATA) Figure 24. IDP Master Timing Rev. G | Page 32 of 56 | March 2011 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Parallel Data Acquisition Port (PDAP) The timing requirements for the PDAP are provided in Table 29. PDAP is the parallel mode operation of Channel 0 of the IDP. For details on the operation of the IDP, refer to the ADSP-2136x SHARC Processor Hardware Reference, the chapter “Input Data Port.” Note that the most significant 16 bits of external 20-bit PDAP data can be provided through either the parallel port AD15–0 or the DAI_P20–5 pins. The remaining 4 bits can only be sourced through DAI_P4–1. The timing below is valid at the DAI_P20–1 pins or at the AD15–0 pins. Table 29. Parallel Data Acquisition Port (PDAP) Parameter Timing Requirements tSPCLKEN1 PDAP_CLKEN Setup Before PDAP_CLK Sample Edge tHPCLKEN1 PDAP_CLKEN Hold After PDAP_CLK Sample Edge tPDSD1 PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge tPDHD1 PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge Clock Width tPDCLKW tPDCLK Clock Period Switching Characteristics tPDHLDD Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word tPDSTRB PDAP Strobe Pulse Width 1 Data source pins are AD15–0 and DAI_P4–1, or DAI pins. Source pins for serial clock and frame sync are DAI pins. SAMPLE EDGE tPDCLK tPDCLKW DAI_P20–1 (PDAP_CLK) tSPCLKEN tHPCLKEN DAI_P20–1 (PDAP_CLKEN) tPDSD tPDHD DATA DAI_P20–1 (PDAP_STROBE) tPDHLDD Figure 25. PDAP Timing Rev. G | Page 33 of 56 | March 2011 tPDSTRB Min Unit 2.5 2.5 3.0 2.5 (tPCLK × 4) ÷ 2 – 3 tPCLK × 4 ns ns ns ns ns ns 2 × tPCLK – 1 2 × tPCLK – 1.5 ns ns ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Pulse-Width Modulation Generators Table 30. PWM Timing1 Parameter Switching Characteristics tPWMW PWM Output Pulse Width tPWMP PWM Output Period 1 Min Max Unit tPCLK – 2 2 × tPCLK – 1.5 (216 – 2) × tPCLK – 2 (216 – 1) × tPCLK ns ns Note that the PWM output signals are shared on the parallel port bus (AD15-0 pins). tPWMW PWM OUTPUTS tPWMP Figure 26. PWM Timing Sample Rate Converter—Serial Input Port The SRC input signals are routed from the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided in Table 31 are valid at the DAI_P20–1 pins. This feature is not available on the ADSP-21363 models. Table 31. SRC, Serial Input Port Parameter Timing Requirements tSRCSFS1 Frame Sync Setup Before Serial Clock Rising Edge tSRCHFS1 Frame Sync Hold After Serial Clock Rising Edge tSRCSD1 SDATA Setup Before Serial Clock Rising Edge tSRCHD1 SDATA Hold After Serial Clock Rising Edge tSRCCLKW Clock Width Clock Period tSRCCLK 1 Min Unit 3 3 3 3 36 80 ns ns ns ns ns ns The data, serial clock, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via the PCGs or SPORTs. The PCG’s input can be either CLKIN or any of the DAI pins. SAMPLE EDGE DAI_P20–1 (SCLK) tSRCCLK tSRCCLKW tSRCSFS tSRCHFS DAI_P20–1 (FS) tSRCSD tSRCHD DAI_P20–1 (SDATA) Figure 27. SRC Serial Input Port Timing Rev. G | Page 34 of 56 | March 2011 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Sample Rate Converter—Serial Output Port For the serial output port, the frame-sync is an input and should meet setup and hold times with regard to the serial clock on the output port. The serial data output has a hold time and delay specification with regard to serial clock. Note that the serial clock rising edge is the sampling edge and the falling edge is the drive edge. Table 32. SRC, Serial Output Port Parameter Timing Requirements tSRCSFS1 Frame Sync Setup Before Serial Clock Rising Edge tSRCHFS1 Frame Sync Hold After Serial Clock Rising Edge Switching Characteristics tSRCTDD1 Transmit Data Delay After Serial Clock Falling Edge tSRCTDH1 Transmit Data Hold After Serial Clock Falling Edge 1 K and B Grade Max Min Y Grade Max 3 3 Unit ns ns 10.5 2 12.5 ns ns The data, serial clock, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins. SAMPLE EDGE tSRCCLK tSRCCLKW DAI_P20–1 (SERIAL CLOCK) tSRCSFS tSRCHFS DAI_P20–1 (FRAME SYNC) tSRCTDD DAI_P20–1 (DATA) tSRCTDH Figure 28. SRC Serial Output Port Timing Rev. G | Page 35 of 56 | March 2011 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 S/PDIF Transmitter Serial data input to the S/PDIF transmitter can be formatted as left justified, I2S, or right justified with word widths of 16-, 18-, 20-, or 24-bits. The following sections provide timing for the transmitter. S/PDIF Transmitter-Serial Input Waveforms Figure 29 shows the right-justified mode. Frame sync is high for the left channel and low for the right channel. Data is valid on the rising edge of serial clock. The MSB is delayed the minimum in 24-bit output mode or the maximum in 16-bit output mode from a frame sync transition, so that when there are 64 serial clock periods per frame sync period, the LSB of the data is rightjustified to the next frame sync transition. Table 33. S/PDIF Transmitter Right-Justified Mode Parameter Timing Requirement tRJD FS to MSB Delay in Right-Justified Mode 16-Bit Word Mode 18-Bit Word Mode 20-Bit Word Mode 24-Bit Word Mode Unit 16 14 12 8 SCLK SCLK SCLK SCLK LEFT/RIGHT CHANNEL DAI_P20–1 FS DAI_P20–1 SCLK DAI_P20–1 SDATA Nominal tRJD LSB MSB MSB–1 MSB–2 Figure 29. Right-Justified Mode Rev. G | Page 36 of 56 | March 2011 LSB+2 LSB+1 LSB ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Figure 30 shows the default I2S-justified mode. The frame sync is low for the left channel and high for the right channel. Data is valid on the rising edge of serial clock. The MSB is left-justified to the frame sync transition but with a delay. Table 34. S/PDIF Transmitter I2S Mode Parameter Timing Requirement tI2SD FS to MSB Delay in I2S Mode DAI_P20–1 SDATA Unit 1 SCLK Nominal Unit 0 SCLK LEFT/RIGHT CHANNEL DAI_P20–1 FS DAI_P20–1 SCLK Nominal tI2SD MSB MSB–1 MSB–2 LSB+2 LSB+1 LSB Figure 30. I2S-Justified Mode Figure 31 shows the left-justified mode. The frame sync is high for the left channel and low for the right channel. Data is valid on the rising edge of serial clock. The MSB is left-justified to the frame sync transition with no delay. Table 35. S/PDIF Transmitter Left-Justified Mode Parameter Timing Requirement tLJD FS to MSB Delay in Left-Justified Mode DAI_P20–1 FS LEFT/RIGHT CHANNEL DAI_P20–1 SCLK tLJD DAI_P20–1 SDATA MSB MSB–1 MSB–2 LSB+2 LSB+1 Figure 31. Left-Justified Mode Rev. G | Page 37 of 56 | March 2011 LSB ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 S/PDIF Transmitter Input Data Timing The timing requirements for the S/PDIF transmitter are given in Table 36. Input signals are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 36. S/PDIF Transmitter Input Data Timing Parameter Timing Requirements tSISFS1 Frame Sync Setup Before Serial Clock Rising Edge tSIHFS1 Frame Sync Hold After Serial Clock Rising Edge tSISD1 Data Setup Before Serial Clock Rising Edge Data Hold After Serial Clock Rising Edge tSIHD1 tSITXCLKW Transmit Clock Width tSITXCLK Transmit Clock Period tSISCLKW Clock Width tSISCLK Clock Period 1 Min K Grade Max 3 3 3 3 9 20 36 80 Min Y Grade Max 3 3 3 3 9.5 20 36 80 Unit ns ns ns ns ns ns ns ns The serial clock, data and frame sync signals can come from any of the DAI pins.The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins. SAMPLE EDGE tSITXCLKW tSITXCLK DAI_P20–1 (TxCLK) tSISCLK tSISCLKW DAI_P20–1 (SCLK) tSISFS tSIHFS DAI_P20–1 (FS) tSISD tSIHD DAI_P20–1 (SDATA) Figure 32. S/PDIF Transmitter Input Timing Oversampling Clock (TxCLK) Switching Characteristics The S/PDIF transmitter requires an oversampling clock input. This high frequency clock (TxCLK) input is divided down to generate the internal biphase clock. Table 37. Oversampling Clock (TxCLK) Switching Characteristics Parameter Frequency for TxCLK = 384 × Frame Sync Frequency for TxCLK = 256 × Frame Sync Frame Rate (FS) Max Oversampling Ratio × Frame Sync <= 1/tSITXCLK 49.2 192.0 Rev. G | Page 38 of 56 | March 2011 Unit MHz MHz kHz ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 S/PDIF Receiver The following section describes timing as it relates to the S/PDIF receiver. This feature is not available on the ADSP-21363 processors. Internal Digital PLL Mode In the internal digital phase-locked loop mode the internal PLL (digital PLL) generates the 512 × FS clock. Table 38. S/PDIF Receiver Output Timing (Internal Digital PLL Mode) Parameter Switching Characteristics tDFSI tHOFSI tDDTI tHDTI tSCLKIW1 1 Min Frame Sync Delay After Serial Clock Frame Sync Hold After Serial Clock Transmit Data Delay After Serial Clock Transmit Data Hold After Serial Clock Transmit Serial Clock Width 5 ns ns ns ns ns 5 –2 38 SAMPLE EDGE DRIVE EDGE tSCLKIW DAI_P20–1 (SERIAL CLOCK) tDFSI tHOFSI DAI_P20–1 (FRAME SYNC) tDDTI tHDTI DAI_P20–1 (DATA CHANNEL A/B) Figure 33. S/PDIF Receiver Internal Digital PLL Mode Timing | Unit –2 Serial clock frequency is 64 ×FS where FS = the frequency of frame sync. Rev. G Max Page 39 of 56 | March 2011 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 SPI Interface—Master The processor contains two SPI ports. The primary has dedicated pins and the secondary is available through the DAI. The timing provided in Table 39 and Table 40 applies to both. Table 39. SPI Interface Protocol—Master Switching and Timing Specifications Parameter Timing Requirements tSSPIDM Data Input Valid to SPICLK Edge (Data Input Setup Time) tSSPIDM Data Input Valid to SPICLK Edge (Data Input Setup Time) (SPI2) tHSPIDM SPICLK Last Sampling Edge to Data Input Not Valid Switching Characteristics tSPICLKM Serial Clock Cycle Serial Clock High Period tSPICHM tSPICLM Serial Clock Low Period tDDSPIDM SPICLK Edge to Data Out Valid (Data Out Delay Time) tDDSPIDM SPICLK Edge to Data Out Valid (Data Out Delay Time) (SPI2) tHDSPIDM SPICLK Edge to Data Out Not Valid (Data Out Hold Time) tSDSCIM FLAG3–0IN (SPI Device Select) Low to First SPICLK Edge FLAG3–0IN (SPI Device Select) Low to First SPICLK Edge (SPI2) tSDSCIM tHDSM Last SPICLK Edge to FLAG3–0IN High tSPITDM Sequential Transfer Delay K and B Grade Min Max Min Y Grade Max 5.2 8.2 2 6.2 9.5 2 ns ns ns 8 × tPCLK – 2 4 × tPCLK – 2 4 × tPCLK – 2 8 × tPCLK – 2 4 × tPCLK – 2 4 × tPCLK – 2 ns ns ns ns ns ns ns ns ns ns 3.0 8.0 3.0 9.5 4 × tPCLK – 2 4 × tPCLK – 2.5 4 × tPCLK – 2.5 4 × tPCLK – 2 4 × tPCLK – 1 4 × tPCLK – 2 4 × tPCLK – 3.0 4 × tPCLK – 3.0 4 × tPCLK – 2 4 × tPCLK – 1 FLAG3–0 (OUTPUT) tSDSCIM tSPICHM tSPICLM tSPICLM tSPICHM tSPICLKM tSPITDM tHDSM SPICLK (CP = 0) (OUTPUT) SPICLK (CP = 1) (OUTPUT) tHDSPIDM tDDSPIDM MOSI (OUTPUT) LSB MSB tSSPIDM tSSPIDM tHSPIDM CPHASE = 1 MISO (INPUT) tHSPIDM MSB VALID LSB VALID tHDSPIDM tDDSPIDM MOSI (OUTPUT) CPHASE = 0 MISO (INPUT) MSB tSSPIDM LSB tHSPIDM MSB VALID LSB VALID Figure 34. SPI Master Timing Rev. G | Page 40 of 56 | March 2011 Unit ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 SPI Interface—Slave Table 40. SPI Interface Protocol—Slave Switching and Timing Specifications Parameter Timing Requirements tSPICLKS Serial Clock Cycle tSPICHS Serial Clock High Period tSPICLS Serial Clock Low Period tSDSCO SPIDS Assertion to First SPICLK Edge CPHASE = 0 CPHASE = 1 tHDS Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0 tSSPIDS Data Input Valid to SPICLK Edge (Data Input Setup Time) tHSPIDS SPICLK Last Sampling Edge to Data Input Not Valid tSDPPW SPIDS Deassertion Pulse Width (CPHASE = 0) Switching Characteristics tDSOE SPIDS Assertion to Data Out Active tDSOE1 SPIDS Assertion to Data Out Active (SPI2) tDSDHI SPIDS Deassertion to Data High Impedance tDSDHI1 SPIDS Deassertion to Data High Impedance (SPI2) tDDSPIDS SPICLK Edge to Data Out Valid (Data Out Delay Time) tHDSPIDS SPICLK Edge to Data Out Not Valid (Data Out Hold Time) SPIDS Assertion to Data Out Valid (CPHASE = 0) tDSOV 1 Min K and B Grade Max Y Grade Max Unit 4 × tPCLK – 2 2 × tPCLK – 2 2 × tPCLK – 2 ns ns ns 2 × tPCLK 2 × tPCLK 2 × tPCLK 2 2 2 × tPCLK ns ns ns ns ns ns 0 0 0 0 5 8 5 8.6 9.5 5 9 5.5 10 11.0 5 × tPCLK 5 × tPCLK 2 × tPCLK ns ns ns ns ns ns ns The timing for these parameters applies when the SPI is routed through the signal routing unit. For more information, refer to the ADSP-2136x SHARC Processor Hardware Reference, “Serial Peripheral Interface Port” chapter. Rev. G | Page 41 of 56 | March 2011 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 SPIDS (INPUT) tSPICHS tSPICLS tSPICLKS tHDS tSDPPW SPICLK (CP = 0) (INPUT) tSPICLS tSDSCO SPICLK (CP = 1) (INPUT) tSPICHS tDSDHI tDDSPIDS tDSOE tDDSPIDS MISO (OUTPUT) MSB LSB tSSPIDS tHSPIDS tSSPIDS CPHASE = 1 MOSI (INPUT) MSB VALID LSB VALID tHDSPIDS tDDSPIDS MISO (OUTPUT) MSB LSB tDSOV CPHASE = 0 MOSI (INPUT) tHDSPIDS tHSPIDS tSSPIDS MSB VALID LSB VALID Figure 35. SPI Slave Timing Rev. G | Page 42 of 56 | March 2011 tDSDHI ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 JTAG Test Access Port and Emulation Table 41. JTAG Test Access Port and Emulation Parameter Timing Requirements tTCK TCK Period tSTAP TDI, TMS Setup Before TCK High tHTAP TDI, TMS Hold After TCK High tSSYS1 System Inputs Setup Before TCK High 1 tHSYS System Inputs Hold After TCK High tTRSTW TRST Pulse Width Switching Characteristics tDTDO TDO Delay from TCK Low 2 tDSYS System Outputs Delay After TCK Low 1 2 Min tCK 5 6 7 18 4 × tCK tTCK TCK tSTAP tHTAP TMS TDI tDTDO TDO tSSYS tHSYS SYSTEM INPUTS tDSYS SYSTEM OUTPUTS Figure 36. IEEE 1149.1 JTAG Test Access Port | Page 43 of 56 | March 2011 Unit ns ns ns ns ns ns 7 tCK ÷ 2 + 7 System Inputs = ADDR15–0, SPIDS, CLK_CFG1–0, RESET, BOOT_CFG1–0, MISO, MOSI, SPICLK, DAI_Px, and FLAG3–0. System Outputs = MISO, MOSI, SPICLK, DAI_Px, ADDR15–0, RD, WR, FLAG3–0, EMU, and ALE. Rev. G Max ns ns ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 OUTPUT DRIVE CURRENTS CAPACITIVE LOADING Figure 37 shows typical I-V characteristics for the output drivers of the processor. The curves represent the current drive capability of the output drivers as a function of output voltage. Output delays and holds are based on standard capacitive loads: 30 pF on all pins (see Figure 38). Figure 42 shows graphically how output delays and holds vary with load capacitance. The graphs of Figure 40, Figure 41, and Figure 42 may not be linear outside the ranges shown for Typical Output Delay versus Load Capacitance and Typical Output Rise Time (20% to 80%, V = Min) versus Load Capacitance. 40 VOH 3.3V, +25°C 3.47V, - 45°C 20 12 10 3.11V, +125°C 10 0 -10 3.11V, +125°C -20 3.3V, +25°C VOL -30 3.47V, -45°C -40 0 0.5 1.0 2.0 1.5 2.5 SWEEP (VDDEXT ) VOLTAGE (V) 3.0 3.5 RISE AND FALL TIMES (ns) SOURCE (VDDEXT) CURRENT (mA) 30 y = 0.0467x + 1.6323 FALL 8 6 4 y = 0.045x + 1.524 2 Figure 37. ADSP-2136x Typical Drive 0 0 50 TEST CONDITIONS 100 150 200 250 200 250 LOAD CAPACITANCE (pF) The ac signal specifications (timing parameters) appear in Table 12 on Page 19 through Table 41 on Page 43. These include output disable time, output enable time, and capacitive loading. The timing specifications for the SHARC apply for the voltage reference levels in Figure 38. VLOAD 30pF Figure 38. Equivalent Device Loading for AC Measurements (Includes All Fixtures) Figure 40. Typical Output Rise/Fall Time (20% to 80%, VDDEXT = Max) 12 RISE 10 RISE AND FALL TIMES (ns) Timing is measured on signals when they cross the 1.5 V level as described in Figure 39. All delays (in nanoseconds) are measured between the point that the first signal reaches 1.5 V and the point that the second signal reaches 1.5 V. TO OUTPUT PIN RISE y = 0.049x + 1.5105 FALL 8 6 y = 0.0482x + 1.4604 4 2 0 0 INPUT OR OUTPUT 50 100 150 LOAD CAPACITANCE (pF) 1.5V 1.5V Figure 41. Typical Output Rise/Fall Time (20% to 80%, VDDEXT = Min) Figure 39. Voltage Reference Levels for AC Measurements Rev. G | Page 44 of 56 | March 2011 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Values of θJC are provided for package comparison and PCB design considerations when an exposed pad is required. Note that the thermal characteristics values provided in Table 42 through Table 44 are modeled values. 10 OUTPUT DELAY OR HOLD (ns) 8 y = 0.0488x - 1.5923 6 Table 42. Thermal Characteristics for BGA (No Thermal vias in PCB) 4 2 0 -2 -4 0 50 100 150 200 LOAD CAPACITANCE (pF) Figure 42. Typical Output Delay or Hold versus Load Capacitance (at Ambient Temperature) Parameter θJA θJMA θJMA θJC ΨJT ΨJMT ΨJMT The processor is rated for performance over the temperature range specified in Operating Conditions on Page 14. Table 42 through Table 44 airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6 and the junction-toboard measurement complies with JESD51-8. Test board and thermal via design comply with JEDEC standards JESD51-9 (BGA) and JESD51-5 (LQFP_EP). The junction-to-case measurement complies with MIL-STD-883. All measurements use a 2S2P JEDEC test board. Industrial applications using the BGA package require thermal vias, to an embedded ground plane, in the PCB. Refer to JEDEC standard JESD51-9 for printed circuit board thermal ball land and thermal via design information. Industrial applications using the LQFP_EP package require thermal trace squares and thermal vias, to an embedded ground plane, in the PCB. Refer to JEDEC standard JESD51-5 for more information. To determine the junction temperature of the device while on the application PCB, use: Parameter θJA θJMA θJMA θJC ΨJT ΨJMT ΨJMT Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W Condition Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Typical 23.40 20.00 19.20 5.00 0.130 0.300 0.360 Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W Table 44. Thermal Characteristics for LQFP_EP (with Exposed Pad Soldered to PCB) Parameter θJA θJMA θJMA θJC ΨJT ΨJMT ΨJMT T J = T T + ( Ψ JT × P D ) where: TJ = junction temperature (°C) TT = case temperature (°C) measured at the top center of the package ΨJT = junction-to-top (of package) characterization parameter is the typical value from Table 42 through Table 44. PD = power dissipation. See Estimating Power for the ADSP-21362 SHARC Processors (EE-277) for more information. Values of θJA are provided for package comparison and PCB design considerations. | Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Typical 25.40 21.90 20.90 5.07 0.140 0.330 0.410 Table 43. Thermal Characteristics for BGA (Thermal vias in PCB) THERMAL CHARACTERISTICS Rev. G Condition Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Page 45 of 56 | March 2011 Condition Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Typical 16.80 14.20 13.50 7.25 0.51 0.72 0.80 Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 144-LEAD LQFP_EP PIN CONFIGURATIONS The following table shows the processor’s pin names and, when applicable, their default function after reset in parentheses. Table 45. LQFP_EP Pin Assignments Pin Name VDDINT CLK_CFG0 CLK_CFG1 BOOT_CFG0 BOOT_CFG1 GND VDDEXT GND VDDINT GND VDDINT GND VDDINT GND FLAG0 FLAG1 AD7 GND VDDINT GND VDDEXT GND VDDINT AD6 AD5 AD4 VDDINT GND AD3 AD2 VDDEXT GND AD1 AD0 WR VDDINT Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pin Name VDDINT GND RD ALE AD15 AD14 AD13 GND VDDEXT AD12 VDDINT GND AD11 AD10 AD9 AD8 DAI_P1 (SD0A) VDDINT GND DAI_P2 (SD0B) DAI_P3 (SCLK0) GND VDDEXT VDDINT GND DAI_P4 (SFS0) DAI_P5 (SD1A) DAI_P6 (SD1B) DAI_P7 (SCLK1) VDDINT GND VDDINT GND DAI_P8 (SFS1) DAI_P9 (SD2A) VDDINT Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Pin Name Pin No. GND 109 110 VDDINT GND 111 VDDINT 112 GND 113 VDDINT 114 GND 115 116 VDDEXT GND 117 VDDINT 118 GND 119 VDDINT 120 RESET 121 122 SPIDS GND 123 VDDINT 124 SPICLK 125 MISO 126 MOSI 127 GND 128 VDDINT 129 VDDEXT 130 Avdd 131 Avss 132 GND 133 RESETOUT 134 EMU 135 TDO 136 TDI 137 TRST 138 TCK 139 TMS 140 GND 141 CLKIN 142 XTAL 143 VDDEXT 144 GND 145* *The ePAD is electrically connected to GND inside the chip (see Figure 43 and Figure 44), therefore connecting the pad to GND is optional. For better thermal performance the ePAD should be soldered to the board and thermally connected to the GND plane with vias. Rev. G | Pin Name VDDEXT GND VDDINT GND DAI_P10 (SD2B) DAI_P11 (SD3A) DAI_P12 (SD3B) DAI_P13 (SCLK3) DAI_P14 (SFS3) DAI_P15 (SD4A) VDDINT GND GND DAI_P16 (SD4B) DAI_P17 (SD5A) DAI_P18 (SD5B) DAI_P19 (SCLK5) VDDINT GND GND VDDEXT DAI_P20 (SFS5) GND VDDINT FLAG2 FLAG3 VDDINT GND VDDINT GND VDDINT GND VDDINT GND VDDINT VDDINT Page 46 of 56 | March 2011 Pin No. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Figure 43 shows the top view of the 144-lead LQFP_EP pin configuration. Figure 44 shows the bottom view of the 144-lead LQFP_EP lead configuration. LEAD 144 LEAD 109 LEAD 1 LEAD 108 LEAD 1 INDICATOR ADSP-2136x 144-LEAD LQFP_EP TOP VIEW LEAD 36 LEAD 73 LEAD 37 LEAD 72 Figure 43. 144-Lead LQFP_EP Lead Configuration (Top View) LEAD 109 LEAD 144 LEAD 108 LEAD 1 ADSP-2136x 144-LEAD LQFP_EP BOTTOM VIEW GND PAD (LEAD 145) LEAD 1 INDICATOR LEAD 73 LEAD 36 LEAD 72 LEAD 37 Figure 44. 144-Lead LQFP_EP Lead Configuration (Bottom View) Rev. G | Page 47 of 56 | March 2011 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 136-BALL BGA PIN CONFIGURATIONS The following table shows the processor’s ball names and, when applicable, their default function after reset in parentheses. Table 46. BGA Pin Assignments Ball Name CLK_CFG0 XTAL TMS TCK TDI RESETOUT TDO EMU MOSI MISO SPIDS VDDINT GND GND VDDINT GND GND GND GND GND GND GND GND FLAG3 Ball No. A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 E01 E02 E04 E05 E06 E09 E10 E11 E13 E14 Ball Name CLK_CFG1 GND VDDEXT CLKIN TRST AVSS AVDD VDDEXT SPICLK RESET VDDINT GND GND GND FLAG1 FLAG0 GND GND GND GND GND GND FLAG2 DAI_P20 (SFS5) Ball No. B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 F01 F02 F04 F05 F06 F09 F10 F11 F13 F14 Rev. G | Ball Name BOOT_CFG1 BOOT_CFG0 GND GND GND VDDINT Ball No. C01 C02 C03 C12 C13 C14 Ball Name VDDINT GND GND GND GND GND GND GND GND VDDINT Ball No. D01 D02 D04 D05 D06 D09 D10 D11 D13 D14 AD7 VDDINT VDDEXT DAI_P19 (SCLK5) G01 G02 G13 G14 AD6 VDDEXT DAI_P18 (SD5B) DAI_P17 (SD5A) H01 H02 H13 H14 Page 48 of 56 | March 2011 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Table 46. BGA Pin Assignments (Continued) Ball Name AD5 AD4 GND GND GND GND GND GND VDDINT DAI_P16 (SD4B) AD15 ALE RD VDDINT VDDEXT AD8 VDDINT DAI_P2 (SD0B) VDDEXT DAI_P4 (SFS0) VDDINT VDDINT GND DAI_P10 (SD2B) Ball No. J01 J02 J04 J05 J06 J09 J10 J11 J13 J14 N01 N02 N03 N04 N05 N06 N07 N08 N09 N10 N11 N12 N13 N14 Ball Name AD3 VDDINT GND GND GND GND GND GND GND DAI_P15 (SD4A) AD14 AD13 AD12 AD11 AD10 AD9 DAI_P1 (SD0A) DAI_P3 (SCLK0) DAI_P5 (SD1A) DAI_P6 (SD1B) DAI_P7 (SCLK1) DAI_P8 (SFS1) DAI_P9 (SD2A) DAI_P11 (SD3A) Ball No. K01 K02 K04 K05 K06 K09 K10 K11 K13 K14 P01 P02 P03 P04 P05 P06 P07 P08 P09 P10 P11 P12 P13 P14 Ball Name AD2 AD1 GND GND GND GND GND GND GND DAI_P14 (SFS3) Figure 45 and Figure 46 show BGA pin assignments from the bottom and top, respectively. Note: Use the center block of ground pins to provide thermal pathways to your printed circuit board’s ground plane. Rev. G | Page 49 of 56 | March 2011 Ball No. L01 L02 L04 L05 L06 L09 L10 L11 L13 L14 Ball Name AD0 WR GND GND DAI_P12 (SD3B) DAI_P13 (SCLK3) Ball No. M01 M02 M03 M12 M13 M14 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A A B B C C D D E E F F G G H H J J K K L L M M N N P P KEY KEY VDDINT VDDEXT GND AVSS AVDD VDDINT GND AVDD I/O SIGNALS VDDEXT AVSS I/O SIGNALS Figure 45. BGA Pin Assignments (Bottom View, Summary) Rev. G Figure 46. BGA Pin Assignments (Top View, Summary) | Page 50 of 56 | March 2011 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 PACKAGE DIMENSIONS The processor is available in 136-ball BGA and 144-lead exposed pad (LQFP_EP) packages. 0.75 0.60 0.45 22.20 22.00 SQ 21.80 1.60 MAX 20.20 20.00 SQ 19.80 109 144 109 108 1 SEATING PLANE 144 108 1 PIN 1 EXPOSED* PAD TOP VIEW (PINS DOWN) 1.45 1.40 1.35 8.80 SQ 0.20 0.09 0.15 0.05 0.08 COPLANARITY VIEW A 7° 3.5° 0° BOTTOM VIEW 73 36 37 72 (PINS UP) 73 VIEW A 0.50 BSC LEAD PITCH ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BFB-HD *EXPOSED PAD IS COINCIDENT WITH BOTTOM SURFACE AND DOES NOT PROTRUDE BEYOND IT. EXPOSED PAD IS CENTERED. Figure 47. 144-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP] (SW-144-1) Dimensions shown in millimeters Rev. G | Page 51 of 56 | March 2011 36 37 72 0.27 0.22 0.17 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 A1 CORNER INDEX AREA 12.10 12.00 SQ 11.90 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BALL A1 INDICATOR 10.40 BSC SQ TOP VIEW BOTTOM VIEW A B C D E F G H J K L M N P 0.80 BSC DETAIL A 1.70 MAX 1.31 1.21 1.10 DETAIL A 0.25 MIN *0.50 0.45 0.40 BALL DIAMETER SEATING PLANE 0.12 MAX COPLANARITY *COMPLIANT WITH JEDEC STANDARDS MO-205-AE WITH EXCEPTION TO BALL DIAMETER. Figure 48. 136-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-136) Dimensions shown in millimeters SURFACE-MOUNT DESIGN Table 47 is provided as an aid to PCB design. For industry standard design recommendations, refer to IPC-7351, Generic Requirements for Surface-Mount Design and Land Pattern Standard. Table 47. BGA Data for Use with Surface-Mount Design Package 136-Ball CSP_BGA (BC-136) Package Ball Attach Type Solder Mask Defined Rev. G | Page 52 of 56 | Package Solder Mask Opening 0.40 mm diameter March 2011 Package Ball Pad Size 0.53 mm diameter ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 AUTOMOTIVE PRODUCTS Some ADSP-2136x models are available for automotive applications with controlled manufacturing. Note that these special models may have specifications that differ from the general release models. The automotive grade products shown in Table 48 are available for use in automotive applications. Contact your local ADI account representative or authorized ADI product distributor for specific product ordering information. Note that all automotive products are RoHS compliant. Table 48. Automotive Products Temperature Range1 Instruction Rate On-Chip SRAM ROM Package Description Package Option 2 –40ºC to 85ºC 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136 AD21362WBSWZ1xx 2 –40ºC to 85ºC 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1 AD21362WYSWZ2xx 2 –40ºC to 105ºC 200 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1 AD21363WBBCZ1xx –40ºC to 85ºC 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136 AD21363WBSWZ1xx –40ºC to 85ºC 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1 AD21363WYSWZ2xx –40ºC to 105ºC 200 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1 AD21364WBBCZ1xx –40ºC to 85ºC 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136 AD21364WBSWZ1xx –40ºC to 85ºC 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1 Model Notes AD21362WBBCZ1xx AD21364WYSWZ2xx –40ºC to 105ºC 200 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1 AD21365WBSWZ1xxA 3, 4 –40ºC to 85ºC 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1 AD21365WBSWZ1xxF 3, 4 –40ºC to 85ºC 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1 AD21365WYSWZ2xxA 3, 4 –40ºC to 105ºC 200 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1 AD21366WBBCZ1xxA 3, 4 –40ºC to 85ºC 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136 AD21366WBSWZ1xxA 3, 4 –40ºC to 85ºC 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1 AD21366WYSWZ2xxA 3, 4 –40ºC to 105ºC 200 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1 1 Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 14 for junction temperature (TJ) specification which is the only temperature specification. 2 License from DTLA required for these products. 3 Available with a wide variety of audio algorithm combinations sold as part of a chipset and bundled with necessary software. For a complete list, visit our website at www.analog.com/SHARC. 4 License from Dolby Laboratories, Inc., and Digital Theater Systems (DTS) required for these products. Rev. G | Page 53 of 56 | March 2011 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 ORDERING GUIDE Model1 ADSP-21362BBCZ-1AA ADSP-21362BSWZ-1AA ADSP-21362YSWZ-2AA ADSP-21363KBC-1AA ADSP-21363KBCZ-1AA ADSP-21363KSWZ-1AA ADSP-21363BBC-1AA ADSP-21363BBCZ-1AA ADSP-21363BSWZ-1AA ADSP-21363YSWZ-2AA ADSP-21364KBC-1AA ADSP-21364KBCZ-1AA ADSP-21364KSWZ-1AA ADSP-21364BBC–1AA ADSP-21364BBCZ-1AA ADSP-21364BSWZ-1AA ADSP-21364YSWZ-2AA ADSP-21365BBCZ-1AA ADSP-21365BSWZ-1AA ADSP-21365YSWZ-2AA ADSP-21365YSWZ-2CA ADSP-21366KBC-1AA ADSP-21366KBCZ-1AR ADSP-21366KBCZ-1AA ADSP-21366KSWZ-1AA ADSP-21366BBC–1AA ADSP-21366BBCZ-1AA ADSP-21366BSWZ-1AA ADSP-21366YSWZ-2AA Notes 3 3 3 4 3, 4, 5 3, 4, 5 3, 4, 5 3, 4, 5 4, 5 4, 5, 6 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 Temperature Range2 –40°C to +85°C –40°C to +85°C –40°C to +105°C 0°C to +70°C 0°C to +70°C 0°C to +70°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +105°C 0°C to +70°C 0°C to +70°C 0°C to +70°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +105°C –40°C to +85°C –40°C to +85°C –40°C to +105°C –40°C to +105°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +105°C Instruction Rate 333 MHz 333 MHz 200 MHz 333 MHz 333 MHz 333 MHz 333 MHz 333 MHz 333 MHz 200 MHz 333 MHz 333 MHz 333 MHz 333 MHz 333 MHz 333 MHz 200 MHz 333 MHz 333 MHz 200 MHz 200 MHz 333 MHz 333 MHz 333 MHz 333 MHz 333 MHz 333 MHz 333 MHz 200 MHz On-Chip SRAM 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 3M Bit 1 ROM 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit 4M Bit Package Description 136-Ball CSP_BGA 144-Lead LQFP_EP 144-Lead LQFP_EP 136-Ball CSP_BGA 136-Ball CSP_BGA 144-Lead LQFP_EP 136-Ball CSP_BGA 136-Ball CSP_BGA 144-Lead LQFP_EP 144-Lead LQFP_EP 136-Ball CSP_BGA 136-Ball CSP_BGA 144-Lead LQFP_EP 136-Ball CSP_BGA 136-Ball CSP_BGA 144-Lead LQFP_EP 144-Lead LQFP_EP 136-Ball CSP_BGA 144-Lead LQFP_EP 144-Lead LQFP_EP 144-Lead LQFP_EP 136-Ball CSP_BGA 136-Ball CSP_BGA 136-Ball CSP_BGA 144-Lead LQFP_EP 136-Ball CSP_BGA 136-Ball CSP_BGA 144-Lead LQFP_EP 144-Lead LQFP_EP Package Option BC-136 SW-144-1 SW-144-1 BC-136 BC-136 SW-144-1 BC-136 BC-136 SW-144-1 SW-144-1 BC-136 BC-136 SW-144-1 BC-136 BC-136 SW-144-1 SW-144-1 BC-136 SW-144-1 SW-144-1 SW-144-1 BC-136 BC-136 BC-136 SW-144-1 BC-136 BC-136 SW-144-1 SW-144-1 Z = RoHS compliant part. Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 14 for junction temperature (TJ) specification which is the only temperature specification. 3 License from DTLA required for these products. 4 License from Dolby Laboratories, Inc., and Digital Theater Systems (DTS) required for these products. 5 Available with a wide variety of audio algorithm combinations sold as part of a chipset and bundled with necessary software. For a complete list, visit our website at www.analog.com/SHARC. 6 R = Tape and reel. 2 Rev. G | Page 54 of 56 | March 2011 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Rev. G | Page 55 of 56 | March 2011 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06359-0-3/11(G) Rev. G | Page 56 of 56 | March 2011