OKI ML9044A Dot matrix lcd controller driver Datasheet

OKI Semiconductor
ML9044A-xxA/xxB
PEDL9044A-04
Issue Date: Apr. 8, 2002
Preliminary
DOT MATRIX LCD CONTROLLER DRIVER
GENERAL DESCRIPTION
The ML9044A used in combination with an 8-bit or 4-bit microcontroller controls the operation of a character type
dot matrix LCD.
FEATURES
•
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Easy interfacing with 8-bit or 4-bit microcontroller
Switchable between serial and parallel interfaces
Dot-matrix LCD controller/driver for a small (5 × 7 dots) or large (5 × 10 dots) font
Built-in circuit allowing automatic resetting at power-on
Built-in 17 common signal drivers and 120 segment signal drivers
Built-in character generation ROM capable of generating 160 small characters (5 × 7 dots) or 32 large
characters (5 × 10 dots)
Creation of character patterns by programming: up to 8 small character patterns (5 × 8 dots) or up to 4 large
character patterns (5 × 11 dots)
Built-in RC oscillation circuit using external or internal resistors
Program-selectable duties: 1/9 duty (1 line: 5 × 7 dots + cursor + arbitrator), 1/12 duty (1 line: 5 × 10 dots +
cursor + arbitrator), or 1/17 duty (2 lines: 5 × 7 dots + cursor + arbitrator)
Built-in bias dividing resistors to drive the LCD
Bi-directional transfer of segment outputs
Bi-directional transfer of common outputs
120-dot arbitrator display
Line display shifting
Built-in contrast control circuit
Built-in voltage multiplier circuit
Gold Bump Chip
With dummy bumps on both sides of the chip: ML9044A-xxA CVWA
Without dummy bumps on both sides of the chip: ML9044A-xxB CVWA
*xx indicates a character generator ROM code number.
*51A and 51B indicate general character generator ROM code numbers.
1/64
5
Address
counter
(ADC)
8
VCC VC VIN
Voltage
multiplier
circuit
BE
Expansion
Expansion 8 instruction
decoder
instruction
(ED)
register (ER)
Busy flag
(BF)
Data
register
(DR)
8 Instruction
decoder
(ID)
Arbitrator
RAM
(AB RAM)
Display data
RAM
(DD RAM)
8
8
Character
generator
RAM
(CG RAM)
5
5
CSR SSR
Character
generator
ROM
(CG ROM)
5
17-bit
shift
register
120-bit shift register
V5IN
LCD bias
voltage
dividing
circuit
V1
V2
V3A
V3B
V4
V5
8
8
Instruction
register
(IR)
7
Cursor
blink
controller
Common
signal
driver
SEG120
SEG1
COM17
COM1
OKI Semiconductor
Contrast
control
circuit
Test
circuit
T1
T2
T3
4
4
I/O
buffer
8
Timing
generator
Parallelserial
converter
DB0 to DB3
DB4 to DB7
RS1
RS0
R/W
E
CS
S/P
SHT
SI
SO
OSC1
OSCR
OSC2
VDD
GND
PEDL9044A-04
ML9044A-xxA/xxB
BLOCK DIAGRAM
Segment Signal - driver
120-bit latch
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PEDL9044A-04
OKI Semiconductor
ML9044A-xxA/xxB
I/O CIRCUITS
VDD
VDD
VDD
VDD
P
P
P
N
N
Applied to pins SSR, CSR,
S/P, and BE
N
Applied to pins T1, T2, and T3
Applied to pins R/W, RS1, and RS0
: “0”
At serial I/F
At parallel I/F : “1”
At serial I/F
Applied to pin E
Applied to pin SI
: “1” (CS = “1”)
: “0” (CS = “0”)
: “1”
At serial I/F
Applied to pin SHT
VDD
At parallel I/F
At parallel I/F
: “1” (CS = “0”)
: “0” (CS = “1”)
: “0”
: “0”
At serial I/F
At parallel I/F : “1”
Applied to pin CS
VDD
P
P
VDD
N
P
N
Output Enable signal
Applied to pins DB0 to DB7
VDD
P
VDD
P
N
Output Enable signal
Applied to pin SO
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PEDL9044A-04
OKI Semiconductor
ML9044A-xxA/xxB
PIN DESCRIPTIONS
Symbol
Description
R/W
The input pin with a pull-up resistor to select Read (“H”) or Write (“L”) in the Parallel I/F
Mode.
This pin should be open in the Serial l/F Mode.
The input pins with a pull-up resistor to select a register in the Parallel l/F Mode.
RS0, RS1
RS1
RS0
Name of register
H
H
H
L
Instruction register
L
L
Expansion Instruction register
Data register
This pin should be open in the Serial I/F Mode.
E
The input pin for data input/output between the CPU and the ML9044A and for
activating instructions in the Parallel l/F Mode.
This pin should be open in the Serial l/F Mode.
DB0 to DB3
The input/output pins to transfer data of lower-order 4 bits between the CPU and the
ML9044A in the Parallel l/F Mode. The pins are not used for the 4-bit interface and
serial interface.
Each pin is equipped with a pull-up resistor, so this pin should be open when not used.
DB4 to DB7
The input/output pins to transfer data of upper 4 bits between the CPU and the
ML9044A in the Parallel l/F Mode. The pins are not used for the serial interface.
Each pin is equipped with a pull-up resistor, so this pin should be open in the Serial I/F
Mode when not used.
The clock oscillation pins required for LCD drive signals and the operation of the
ML9044A by instructions sent from the CPU.
OSC1
OSC2
OSCR
To input external clock, the OSC1 pin should be used. The OSCR and the OSC2 pins
should be open.
To start oscillation with an external resistor, the resistor should be connected between
the OSC1 and OSC2 pins. The OSCR pin should be open.
To start oscillation with an internal resistor, the OSC2 and OSCR pins should be
short-circuited outside the ML9044A. The OSC1 pin should be open.
The LCD common signal output pins.
COM1 to COM17
For 1/9 duty, non-selectable voltage waveforms are output via COM10 to COM17. For
1/12 duty, non-selectable voltage waveforms are output via COM13 to COM17.
SEG1 to SEG120
The LCD segment signal output pins.
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PEDL9044A-04
OKI Semiconductor
ML9044A-xxA/xxB
Symbol
Description
CSR
At 1/n duty, data is transferred from COM1 to COMn when “L” is applied to this pin and
transferred from COMn to COM1 when “H” is applied to this pin.
SSR
“L”: Data transfer from SEG1 to SEG120
The input pin to select the transfer direction of the common signal output data.
The input pin to select the transfer direction of the segment signal output data.
“H”: Data transfer from SEG120 to SEG1
The pins to output bias voltages to the LCD.
V1 , V2, V3A, V3B, V4
For 1/4 bias : The V2 and V3B pins are shorted.
For 1/5 bias : The V3A and V3B pins are shorted.
The input pin to enable or disable the voltage multiplier circuit.
"L" disables the voltage multiplier circuit. "H" enables the voltage multiplier circuit.
BE
VIN
The voltage multiplier circuit doubles the input voltage between VDD and VIN and the
multiplied voltage referenced to VDD is output to the V5IN pin. The voltage multiplier
circuit can be used only when generating a level lower than GND.
The pin to input voltage to the voltage multiplier.
The pins to supply the LCD drive voltage.
The LCD drive voltage is supplied to the V5 pin when the voltage multiplier is not used
(BE = “0”) and the internal contrast adjusting circuit is also not used. At this time, the
V5IN pin should be open.
V5, V5IN
The LCD drive voltage is supplied to the V5IN pin when the voltage multiplier is not used
(BE = “0”) but the internal contrast adjusting circuit is used. At this time, the V5 pin
should be open.
When the voltage multiplier is used (BE = “1”), the V5 pin should be open (the
multiplied voltage is output to the V5IN pin). In this case, the internal contrast adjusting
circuit must be used. Capacitors for the voltage multiplier should be connected
between the VDD pin and the V5IN pin.
VC
The pin to connect the positive pin of the capacitor for the voltage multiplier. Leave the
pin open when the voltage multiplier circuit is not used.
VCC
The pin to connect the negative pin of the capacitor used for the voltage multiplier.
Leave the pin open when the voltage multiplier circuit is not used.
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PEDL9044A-04
OKI Semiconductor
ML9044A-xxA/xxB
Symbol
Description
T 1, T 2, T 3
The input pins for test circuits (normally open). Each of these pins is equipped with a
pull-down resistor, so this pin should be left open.
VDD
The power supply pin.
GND
The ground level input pin.
The input pin to select the serial or parallel interface.
S/P
“L” selects the parallel interface.
“H” selects the serial interface.
The pin to enable this IC in the serial l/F mode.
CS
“L” enables this IC.
“H” disables this IC.
This pin should be open in the parallel l/F mode.
The pin to input shift clock in the serial l/F mode.
SHT
Data inputting to the SI pin is carried out synchronizing with the rising edge of this
clock signal.
Data outputting from the SO pin is carried out synchronizing with the falling edge of
this clock signal.
This pin should be open in the parallel l/F mode.
The pin to input DATA in the serial l/F mode.
Sl
Data inputting to this pin is carried out synchronizing with the rising edge of the SHT
signal.
This pin should be open in the parallel l/F mode.
The pin to output DATA in the serial l/F mode.
SO
Data inputting to this pin is carried out synchronizing with the falling edge of the SHT
signal.
This pin should be open in the parallel l/F mode.
DUMMY
NC pin.
Leave this pin open.
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PEDL9044A-04
OKI Semiconductor
ML9044A-xxA/xxB
ABSOLUTE MAXIMUM RATINGS
(GND = 0 V)
Parameter
Supply Voltage
LCD Driving Voltage
Input Voltage
Storage Temperature
Symbol
Condition
Rating
Unit
Applicable pins
VDD
Ta = 25°C
–0.3 to +6.5
V
VDD–GND
V1, V2, V3,
V4, V5
Ta = 25°C
VDD–7.5 to VDD+0.3
V
V1, V4, V5, V5IN, V2, V3A, V3B
VI
Ta = 25°C
–0.3 to VDD+0.3
V
R/W, E, SHT, CSR, S/P,
SSR, Sl, RS0, RS1, BE, CS,
T1 to T3, DB0 to DB7, VIN
TSTG
—
–55 to +150
°C
—
RECOMMENDED OPERATING CONDITIONS
(GND = 0 V)
Parameter
Supply Voltage
LCD Driving Voltage
Voltage Multipler
Operating Voltage
Operating Temperature
Symbol
Condition
Range
Unit
Applicable pins
VDD
—
2.7 to 5.5
V
VDD–GND
—
3.3 to 7.0
V
VDD–V5
(V5IN)
VMUL
BE = “1”
2.7 to 3.5
V
VDD–VIN
Top
—
–40 to +85
°C
—
VDD–V5
(See Note)
Note: This voltage should be applied across VDD and V5. The following voltages are output to the V1, V2,
V3A (V3B) and V4 pins:
• 1/4 bias
V1 = {VDD – (VDD – V5)/4} ±0.15 V
V2 = V3B = {VDD – (VDD – V5)/2} ±0.15 V
V4 = {VDD – 3 × (VDD – V5)/4 } ±0.15 V
• 1/5 bias
V1 = {VDD – (VDD – V5)/5} ±0.15 V
V2 = {VDD – 2 × (VDD – V5)/5} ±0.15 V
V3A = V3B = {VDD – 3 × (VDD – V5)/5} ±0.15 V
V4 = {VDD – 4 × (VDD – V5)/5} ±0.15 V
The voltages at the V1, V2, V3A (V3B), V4 and V5 pins should satisfy
VDD > V1 > V2 > V3A (V3B) > V4 > V5.
(Higher ←
→ Lower)
* If the chip is attached on a substrate using COG technology, the chip tends to be susceptible
to electrical characteristics of the chip due to trace resistance on the glass substrate. It is
recommended to use the chip by confirming that it operates on the glass substrate properly.
Trace resistance, especially, VDD and VSS trace resistance, between the chip on the LCD
panel and the flexible cable should be designed as low as possible. Trace resistance that
cannot be very well decreased, larger size of the LCD panel, or greater trace capacitance
between the microcontroller and the ML9044A device can cause device malfunction. In order
to avoid the device malfunction, power noise should be reduced by serial interfacing of the
microcontroller and the ML9044A device.
* Do not apply short-circuiting across output pins and across an output pin and an input/output
pin or the power supply pin in the output mode.
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PEDL9044A-04
OKI Semiconductor
ML9044A-xxA/xxB
ELECTRICAL CHARACTERISTICS
DC Characteristics
(GND = 0 V, VDD = 2.7 to 5.5 V, Ta = –40 to +85°C)
Parameter
“H” Input Voltage
Symbol
Condition
VIH
Min.
Typ.
Max.
0.8VDD
—
VDD
—
“L” Input Voltage
VIL
0
—
0.2VDD
—
—
—
0.2VDD
“H” Output Voltage 1
“L” Output Voltage 1
VOH1
VOL1
IOH = –0.1 mA
IOL = +0.1 mA
0.75VDD
—
“H” Output Voltage 2
VOH2
IOH = –13 µA
0.9VDD
—
—
“L” Output Voltage 2
VOL2
VCH
IOL = +13 µA
lOCH = –4 µA
—
VDD–0.3
—
—
0.1VDD
VDD
VCMH
VCML
lOCMH = ±4 µA VDD –V5 = 5 V
Note 1
lOCML = ±4 µA
lOCL = +4 µA
V1–0.3
V4–0.3
—
—
—
V1+0.3
V4+0.3
V5+0.3
COM Voltage Drop
VCL
VSH
SEG Voltage Drop
VSMH
VSML
VSL
Input Leakage Current
Input Current 1
| IIL |
| II1 |
Input Current 2
| II2 |
Supply Current
lDD
RLB
Oscillation Frequency
of External Resistor Rf
fosc1
Oscillation Frequency
of Internal Resistor Rf
fosc2
External Clock
LCD Bias Resistor
Clock Input
Frequency
Input Clock Duty
Input Clock Rise
Time
Input Clock Fall Time
fin
fduty
lOSH = –4 µA
V5
VDD–0.3
—
VDD
lOSMH = ±4 µA VDD –V5 = 5 V
Note 1
lOSML = ±4 µA
V2–0.3
V3–0.3
—
—
V2+0.3
V3+0.3
lOSL = +4 µA
V5
—
V5+0.3
VDD = 5 V, VI = 5 V or 0 V
—
—
1.0
VDD = 5 V, VI = GND
10
25
61
VDD = 5 V, VI = VDD,
Excluding current flowing
through the pull-up resistor
and the output driving MOS
—
—
2.0
VDD = 5 V, VI = VDD
15
45
105
—
—
2.0
—
—
1.2
VDD = 5 V, VI = GND,
Excluding current flowing
through the pull-down resistor
VDD = 5 V
Note 2
Rf = 180 kΩ±2%
Note 3
Note 4
OSC1: Open
OSC2 and OSCR: Shortcircuited
OSC2, OSCR: Open
Input from OSC1
Note 5
Unit
Applicable pin
V
R/W, RS0, RS1,
E, DB0 to DB7,
SHT, S/P, Sl,
CS, OSC1,
SSR, CSR, BE
V
DB0 to DB7, SO
V
OSC2
V
COM1 to
COM17
V
SEG1 to
SEG120
µA
E, SSR, CSR,
BE, SHT, S/P,
CS, Sl
µA
R/W, RS0, RS1,
DB0 to DB7, SO
µA
T 1, T 2, T 3
mA
VDD–GND
VDD, V1, V2,
V3A, V3B, V4, V5
2.5
4.0
6.0
kΩ
175
270
400
kHz OSC1, OSC2
140
270
480
kHz
125
—
480
kHz
45
50
55
%
frf
Note 6
—
—
0.2
µs
fff
Note 6
—
—
0.2
µs
OSC1, OSC2,
OSCR
OSC1
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PEDL9044A-04
OKI Semiconductor
ML9044A-xxA/xxB
(GND = 0 V, VDD = 2.7 to 5.5 V, Ta = –40 to +85°C)
Parameter
Symbol
Voltage Multiplier
Input Voltage
VMUL
Condition
Note 7
Min.
Typ.
Max.
Unit
Applicable
pins
2.7
—
3.5
V
VDD–VIN
4.1
—
(VDD–VIN)
×2
V
VDD–V5IN
VDD = 2.7 V, VIN = 0 V
1/5 bias
f = 125 kHz
Voltage Multiplier
Output Voltage
V5OUT
A capacitor for the voltage
multiplier =1 to 4.7 µF
3.9
—
(VDD–VIN)
×2
VDD = 5 V, V5IN = –2 V, 1/5 bias,
Contrast data: 1F, No load
6.6
—
—
VDD = 5 V, V5IN = –2 V, 1/4 bias,
Contrast data: 1F, No load
6.6
—
—
VDD = 4.1 V, V5IN = 0 V, 1/5 bias,
Contrast data: 1F, No load
3.8
—
—
VDD = 3.9 V, V5IN = 0 V, 1/4 bias,
Contrast data: 1F, No load
3.6
—
—
VDD = 5 V, V5IN = –2 V, 1/5 bias,
Contrast data: 00, No load
4.0
—
4.6
VDD = 5 V, V5IN = –2 V, 1/4 bias,
Contrast data: 00, No load
3.6
—
4.2
VDD = 4.1 V, V5IN = 0 V, 1/5 bias,
Contrast data: 00, No load
2.2
—
2.8
VDD = 3.9 V, V5IN = 0 V, 1/4 bias,
Contrast data: 00, No load
1.9
—
2.5
1/5 bias
3.3
—
7.0
1/4 bias
3.3
—
7.0
1/4 bias
No load
BE = “H”
VLCD
MAX
Maximum and
minimum LCD
drive voltages
when internal
variable resistors
are used. Note 8
VLCD
MIN
Bias Voltage for
Driving LCD
Note 1:
VLCD1
VDD–V5
V
VDD–V5
V
Note 9
VLCD2
V
V5
Applied to the voltage drop occurring between any of the VDD, V1, V4 and V5 pins and any of the
common pins (COM1 to COM17) when the current of 4 µA flows in or flows out at one common
pin.
Also applied to the voltage drop occurring between any of the VDD, V2, V3A (V3B) and V5 pins and
any of the segment pins (SEG1 to SEG120) when the current of 4 µA flows in or flows out at one
common pin.
The current of 4 µA flows out when the output level is VDD or flows in when the output level is
V5.
Note 2:
Applied to the current flowing into the VDD pin when the external clock (fOSC2 = fin = 270 kHz) is
fed to the internal Rf oscillation or OSC1 under the following conditions:
VDD = 5 V
GND = V5 = 0 V,
V1, V2, V3A (V3B) and V4: Open
E, SSR, CSR, and BE: “L” (fixed)
Other input pins: “L” or “H” (fixed)
Other output pins: No load
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Note 3:
ML9044A-xxA/xxB
Note 4:
OSC1
OSC1
OSCR
Rf = 180 kΩ±2%
OSCR
OSC2
OSC2
The wire between OSC1 and Rf and the wire between
OSC2 and Rf should be as short as possible.
Keep OSCR open.
The wire between OSC2 and OSCR should be as short
as possible. Keep OSC1 open.
Note 5:
tHW
tLW
VDD
VDD
VDD
2
2
2
fIN
waveform
Applied to the pulses entering from the OSC1 pin
fduty = tHW/(tHW + tLW) ×100 (%)
Note 6:
0.8VDD
0.8VDD
0.2VDD
0.2VDD
trf
tff
Applied to the pulses entering from the OSC1 pin
Note 7:
The maximum value of the voltage multiplier input voltage should be set at 3.5 V, and the
minimum value of the voltage multiplier input voltage should be set so that the voltage
multiplier output voltage meets the specification for the bias voltage for driving LCD after
contrast adjustment.
Note 8:
If using the built-in contrast control circuit, control the circuit so that the voltage of VDD-V5 is the
minimum value of the bias voltage for driving LCD or higher.
Note 9:
For 1/4 bias, V2 and V3B pins are short-circuited. V3A pin is open.
For 1/5 bias, V3A and V3B pins are short-circuited. V2 pin is open.
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ML9044A-xxA/xxB
Switching Characteristics (The following ratings are subject to change after ES evaluation.)
• Parallel Interface Mode
The timing for the input from the CPU (see 1) and the timing for the output to the CPU (see 2) are as shown below:
1) WRITE MODE (Timing for input from the CPU)
(VDD = 2.7 to 5.5 V, Ta = –40 to +85°C)
Parameter
Symbol
Min.
Typ.
Max.
Unit
R/W, RS0, RS1 Setup Time
tB
40
—
—
ns
E Pulse Width
tW
450
—
—
ns
R/W, RS0, RS1 Hold Time
tA
10
—
—
ns
E Rise Time
tr
—
—
25
ns
E Fall Time
tf
—
—
25
ns
E Pulse Width
tL
430
—
—
ns
E Cycle Time
tC
1000
—
—
ns
DB0 to DB7 Input Data Hold Time
tI
195
—
—
ns
DB0 to DB7 Input Data Setup Time
tH
10
—
—
ns
VIH
VIL
VIH
VIL
RS1, RS0
R/W
VIL
VIL
tr
tB
tL
E
VIL
tf
tW
VIH
tA
VIH
VIL
VIL
tI
VIH
VIL
DB0 to DB7
tH
Input
Data
VIH
VIL
tC
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ML9044A-xxA/xxB
2) READ MODE (Timing for output to the CPU)
(VDD = 2.7 to 5.5 V, Ta = –40 to +85°C)
Symbol
Min.
Typ.
Max.
Unit
R/W, RS1, RS0 Setup Time
Parameter
tB
40
—
—
ns
E Pulse Width
tW
450
—
—
ns
R/W, RS1, RS0 Hold Time
tA
10
—
—
ns
E Rise Time
tr
—
—
25
ns
E Fall Time
tf
—
—
25
ns
E Pulse Width
tL
430
—
—
ns
E Cycle Time
tC
1000
—
—
ns
DB0 to DB7 Output Data Delay Time
tD
—
—
350
ns
DB0 to DB7 Output Data Hold Time
tO
20
—
—
ns
Note: A load capacitance of each of DB0 to DB7 must be 50 pF or less.
RS1, RS0
VIH
VIL
R/W
VIH
VIH
VIL
VIH
tr
tB
tL
E
VIL
tW
VIH
tf
tA
VIH
VIL
VIL
tD
tO
VOH
VOL
DB0 to DB7
Output
Data
VOH
VOL
tC
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PEDL9044A-04
OKI Semiconductor
ML9044A-xxA/xxB
• Serial Interface Mode
(VDD = 2.7 to 5.5 V, Ta = –40 to +85°C)
Symbol
Min.
Typ.
Max.
Unit
SHT Cycle Time
Parameter
tSCY
500
—
—
ns
CS Setup Time
tCSU
100
—
—
ns
CS Hold Time
CS “H” Pulse Width
tCH
100
—
—
ns
tCSWH
200
—
—
ns
SHT Setup Time
tSSU
60
—
—
ns
SHT Hold Time
tSH
200
—
—
ns
SHT “H” Pulse Width
tSWH
200
—
—
ns
SHT “L” Pulse Width
tSWL
200
—
—
ns
SHT Rise Time
tSR
—
—
50
ns
SHT Fall Time
tSF
—
—
50
ns
Sl Setup Time
tDISU
100
—
—
ns
Sl Hold Time
tDIH
100
—
—
ns
Data Output Delay Time
tDOD
—
—
160
ns
Data Output Hold Time
tCDH
0
—
—
ns
tCSWH
tSCY
CS
VIH
tCSU
SHT
SI
VIL
VIL
tSSU
tSWL
VIH
VIL
tDISU
VIH
VIL
tDOD
SO
tSR
tSF
tSWH
VIH
tDIH
VIH
tSH
VIH
VIL
VIH
tCH
VIH
VIH
VIL
tDOD
VOL
VIH
tCDH
VOH
VOH
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PEDL9044A-04
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ML9044A-xxA/xxB
FUNCTIONAL DESCRIPTION
Instruction Register (IR), Data Register (DR), and Expansion Instruction Register (ER)
These registers are selected by setting the level of the Register Selection input pins RS0 and RS1. The DR is
selected when both RS0 and RS1 are “H”. The IR is selected when RS0 is “L” and RS1 is “H”. The ER is selected
when both RS0 and RS1 are “L”. (When RS0 is “H” and RS1 is “L”, the ML9044A is not selected.)
The IR stores an instruction code and sets the address code of the display data RAM (DDRAM) or the character
generator RAM (CGRAM).
The microcontroller (CPU) can write to the IR but cannot read from the IR.
The ER stores a contrast adjusting code and sets the address code of the arbitrator RAM (ABRAM).
The CPU can write to or read from the ER.
The DR stores data to be written in the DDRAM, ABRAM and CGRAM and also stores data read from the
DDRAM, ABRAM and CGRAM.
The data written in the DR by the CPU is automatically written in the DDRAM, ABRAM or CGRAM.
When an address code is written in the IR or ER, the data of the specified address is automatically transferred from
the DDRAM, ABRAM or CGRAM to the DR. The data of the DDRAM, ABRAM and CGRAM can be checked
by allowing the CPU to read the data stored in the DR.
After the CPU writes data in the DR, the data of the next address in the DDRAM, ABRAM or CGRAM is selected
to be ready for the next writing by the CPU. Similarly, after the CPU reads the data in the DR, the data of the next
address in the DDRAM, ABRAM or CGRAM is set in the DR to be ready for the next reading by the CPU.
Writing in or reading from these 3 registers is controlled by changing the status of the R/W (Read/Write) pin.
Table 1 R/W pin status and register operation
R/W
RS0
RS1
Operation
L
L
H
Writing in the IR
H
L
H
Reading the Busy flag (BF) and the address counter (ADC)
L
H
H
Writing in the DR
H
H
H
Reading from the DR
L
L
L
Writing in the ER
H
L
L
Reading the contrast code
L
H
L
Disabled (Not in a busy state, not performing the writes)
H
H
L
Disabled (Not in a busy state, not performing the reads.
Note data read by the CPU is undefined since the data bus
is high impedance.)
Busy Flag (BF)
The status “1” of the Busy Flag (BF) indicates that the ML9044A is carrying out internal operation.
When the BF is “1”, any new instruction is ignored.
When R/W = “H”, RS0 = “L” and RS1 = “H”, the data in the BF is output to the DB7.
New instructions should be input when the BF is “0”.
When the BF is “1”, the output code of the address counter (ADC) is undefined.
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ML9044A-xxA/xxB
Address Counter (ADC)
The address counter provides a read/write address for the DDRAM, ABRAM or CGRAM and also provides a
cursor display address.
When an instruction code specifying DDRAM, ABRAM or CGRAM address setting is input to the pre-defined
register, the register selects the specified DDRAM, ABRAM or CGRAM and transfers the address code to the
ADC. The address data in the ADC is automatically incremented (or decremented) by 1 after the display data is
written in or read from the DDRAM, ABRAM or CGRAM.
The data in the ADC is output to DB0 to DB6 when R/W = “H”, RS0 = “L”, RS1 = “H” and BF = “0”.
Timing Generator
The timing generator generates timing signals for the internal operation of the ML9044A activated by the
instruction sent from the CPU or for the operation of the internal circuits of the ML9044A such as DDRAM,
ABRAM, CGRAM and CGROM. Timing signals are generated so that the internal operation carried out for LCD
displaying will not be interfered by the internal operation initiated by accessing from the CPU. For example, when
the CPU writes data in the DDRAM, the display of the LCD not corresponding to the written data is not affected.
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ML9044A-xxA/xxB
Display Data RAM (DDRAM)
This RAM stores the 8-bit character codes (see Table 2).
The DDRAM addresses correspond to the display positions (digits) of the LCD as shown below. The DDRAM
addresses (to be set in the ADC) are represented in hexadecimal.
DB6 DB5 DB4 DB3 DB2 DB1 DB0
ADC
LSB
MSB
Hexadecimal
Hexadecimal
(Example) Representation of DDRAM address = 12
ADC
0
0
1
0
0
1
0
2
1
1) Relationship between DDRAM addresses and display positions (1-line display mode)
Digit
1 2
3 4
5
00 01 02 03 04
Left
end
23 24
Display position
16 17
DD RAM address (hexadecimal)
Right
end
In the 1-line display mode, the ML9044A can display up to 24 characters from digit 1 to digit 24. While the
DDRAM has addresses “00” to “4F” for up to 80 character codes, the area not used for display can be used as a
RAM area for general data. When the display is shifted by instruction, the relationship between the LCD
display and the DDRAM address changes as shown below:
Digit
1 2
3 4
23 24
(Display shifted to the right) 4F 00 01 02
Digit
1 2
3 4
5
(Display shifted to the left) 01 02 03 04 05
15 16
23 24
17 18
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PEDL9044A-04
OKI Semiconductor
ML9044A-xxA/xxB
2) Relationship between DDRAM addresses and display positions (2-line display mode)
In the 2-line mode, the ML9044A can display up to 48 characters (24 characters per line) from digit 1 to digit
24.
Digit
1 2 3 4 5
Line 1 00 01 02 03 04
23 24
16 17
Display position
Line 2 40 41 42 43 44
56 57
address (hexadecimal)
DD RAM
Note: The DDRAM address at digit 24 in the first line is not consecutive to the DDRAM address at
digit 1 in the second line.
When the display is shifted by instruction, the relationship between the LCD display and the DDRAM address
changes as shown below:
(Display shifted to the right)
(Display shifted to the left)
Digit
1 2 3 4 5
Line 1 27 00 01 02 03
23 24
15 16
Line 2 67 40 41 42 43
55 56
Digit
1 2 3 4 5
Line 1 01 02 03 04 05
23 24
17 18
Line 2 41 42 43 44 45
57 58
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PEDL9044A-04
OKI Semiconductor
ML9044A-xxA/xxB
Character Generator ROM (CGROM)
The CGROM generates small character patterns (5 × 7 dots, 160 patterns) or large character patterns (5 × 10 dots,
32 patterns) from the 8-bit character code signals in the DDRAM.
When the 8-bit character code corresponding to a character pattern in the CGROM is written in the DDRAM, the
character pattern is displayed in the display position specified by the DDRAM address.
Character codes 20 to 7F and A0 to FF are contained in the character code area in the CG ROM.
Character codes 20 to 7F and A0 to DF are contained in the character code area for the 5 × 7-dot character patterns.
Character codes E0 to FF are contained in the ROM area for 5 × 10-dot character patterns.
The general character generator ROM codes are 51A/51B.
The relationship between character codes and general purpose character patterns are indicated in Table 2.
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ML9044A-xxA/xxB
Character Generator RAM (CGRAM)
The CGRAM is used to generate user-specific character patterns that are not in the CGROM. CGRAM (64 bytes =
512 bits) can store up to 8 small character patterns (5 × 8 dots) or up to 4 large character patterns (5 × 11 dots).
When displaying a character pattern stored in the CGRAM, write an 8-bit character code (00 to 07 or 08 to 0F;
hex.) assigned in Table 2 to the DDRAM. This enables outputting the character pattern to the LCD display
position corresponding to the DDRAM address.
The cursor or blink is also displayed even when a CGRAM or ABRAM address is set in the ADC. Therefore, the
cursor or blink display should be inhibited while the ADC is holding a CGRAM or ABRAM address.
The following describes how character patterns are written in and read from the CGRAM.
1) Small character patterns (5 × 8 dots) (See Table 3-1.)
(1) A method of writing character patterns to the CGRAM from the CPU
The three CGRAM address bit weights 0 to 2 select one of the lines constituting a character pattern.
First, set the mode to increment or decrement from the CPU, and then input the CGRAM address.
Write each line of the character pattern in the CGRAM through DB0 to DB7.
The data lines DB0 to DB7 correspond to the CGRAM data bit weights 0 to 7, respectively (see Table 31). Input data “1” represents the ON status of an LCD dot and “0” represents the OFF status. Since the
ADC is automatically incremented or decremented by 1 after the data is written to the CGRAM, it is not
necessary to set the CGRAM address again.
The bottom line of a character pattern (the CGRAM address bit weights 0 to 2 are all “1”, which means 7
in hexadecimal) is the cursor line. The ON/OFF pattern of this line is ORed with the cursor pattern for
displaying on the LCD. Therefore, the pattern data for the cursor position should be all zeros to display
the cursor.
Whereas the data given by the CGRAM data bit weights 0 to 4 is output to the LCD as display data, the
data given by the CGRAM data bit weights 5 to 7 is not. Therefore, the CGRAM data bit weights 5 to 7
can be used as a RAM area.
(2) A method of displaying CGRAM character patterns on the LCD
The CGRAM is selected when the higher-order 4 bits of a character code are all zeros. Since bit weight 3
of a character code is not used, the character pattern “0” in Table 3-1 can be selected using the character
code “00” or “08” in hexadecimal.
When the 8-bit character code corresponding to a character pattern in the CGRAM is written to the
DDRAM, the character pattern is displayed in the display position specified by the DDRAM address.
(The DDRAM data bit weights 0 to 2 correspond to the CGRAM address bit weights 3 to 5, respectively.)
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PEDL9044A-04
OKI Semiconductor
ML9044A-xxA/xxB
2) Large character patterns (5 × 11 dots) (See Table 3-2.)
(1) A method of writing character patterns to the CGRAM from the CPU
The four CGRAM address bit weights 0 to 3 select one of the lines constituting a character pattern.
First, set the mode to increment or decrement from the CPU, and then input the CGRAM address.
Write each line of the character pattern code in the CGRAM through DB0 to DB7.
The data lines DB0 to DB7 correspond to the CGRAM data bit weights 0 to 7, respectively (see Table 32). Input data “1” represents the ON status of an LCD dot and “0” represents the OFF status. Since the
ADC is automatically incremented or decremented by 1 after the data is written to the CGRAM, it is not
necessary to set the CGRAM address again.
The bottom line of a character pattern (the CGRAM address bit weights 0 to 3 are all “1”, which means A
in hexadecimal) is a cursor line. The ON/OFF pattern of this line is ORed with the cursor pattern for
displaying on the LCD. Therefore, the pattern data for the cursor position should be all zeros to display
the cursor.
Whereas CGRAM data bit weights 0 to 4 are output as display data to the LCD when CGRAM address bit
weights 0 to 3 are “0” to “A” in hexadecimal, the data given by the CGRAM data bit weights 5 to 7 or the
CGRAM addresses B to F in hexadecimal is not. These bits can be written and read as a RAM area.
(2) A method of displaying CGRAM character patterns on the LCD
The CGRAM is selected when the higher-order 4 bits of a character code are all zeros. Since bit weights
0 and 3 of a character code are not used, the character pattern “g” in Table 3-2 can be selected with a
character code “02”, “03”, “0A” or “0B” in hexadecimal.
When the 8-bit character code corresponding to a character pattern in the CGRAM is written to the
DDRAM, the character pattern is displayed in the display position specified by the DDRAM address.
(The DDRAM data bit weights 1 and 2 correspond to the CGRAM address bit weights 4 and 5,
respectively.)
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PEDL9044A-04
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ML9044A-xxA/xxB
Arbitrator RAM (ABRAM)
The arbitrator RAM (ABRAM) stores arbitrator display data.
120 dots can be displayed in both 1-line and 2-line display modes. The arbitrator RAM has the addresses
(hexadecimal) from “00” to “1F” and the valid display address area is from 00 to 23 (0H to 17H). The area of 24 to
31 (18H to 1FH) not used for display can be used as a data RAM area for general data. Even if the display is
shifted by instruction, the arbitrator display is not shifted.
A capacity of 8 bits by 32 addresses (= 256 bits) is available for data write.
First set the mode to increment or decrement from the CPU, and then input the ABRAM address.
Write Display-ON data in the ABRAM through DB0 to DB7.
DB0 to DB7 correspond to the ABRAM data bit weights 0 to 7 respectively. Input data “1” represents the ON status
of an LCD dot and “0” represents the OFF status.
Since ADC is automatically incremented or decremented by 1 after the data is written to the ABRAM, it is not
necessary to set the ABRAM address again.
Whereas ABRAM data bit weights 0 to 4 are output as display data to the LCD, the ABRAM data bit weights 5 to
7 are not. These bits can be used as a RAM area.
The cursor or blink is also displayed even when a CGRAM or ABRAM address is set in the ADC. Therefore, the
cursor or blink display should be inhibited while the ADC is holding a CGRAM or ABRAM address.
DB6 DB5 DB4 DB3 DB2 DB1 DB0
ADC
MSB
LSB
Hexadecimal
Hexadecimal
The arbitrator RAM can store a maximum of 120 dots of the arbitrator Display-ON data in units of 5 dots.
The relationship with the LCD display positions is shown below.
Configuration of input display data
Input data
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
*
*
*
Relationship between display-ON
data and segment pins
5XSn+1
5XSn+5
E4 E3 E2 E1 E0
* Don’t Care
Display - ON data
E4
E0
Sn = ABRAM address (0 to 23)
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PEDL9044A-04
OKI Semiconductor
Table 2
ML9044A-xxA/xxB
Relationship between Character Codes and Character Patterns of the ML9044A51A/51B (General Character Codes)
The character code area in the CG ROM: Character codes 20H to 7FH, A0H to FFH.
5×7-dot ROM area: 20H to 7FH, A0H to DFH
5×10-dot ROM area: E0H to FFH
The CG RAM area
00H:
: Character codes 00H to FFH
08H:
20H:
28H: (
30H: 0
38H: 8
40H: @
48H: H
50H: P
21H: !
29H: )
31H: 1
39H: 9
41H: A
49H: I
51H: Q
22H: "
2AH: *
32H: 2
3AH: :
42H: B
4AH: J
52H: R
23H: #
2BH: +
33H: 3
3BH: ;
43H: C
4BH: K
53H: S
24H: $
2CH: ,
34H: 4
3CH: <
44H: D
4CH: L
54H: T
25H: %
2DH: -
35H: 5
3DH: =
45H: E
4DH: M
55H: U
26H: &
2EH: .
36H: 6
3EH: >
46H: F
4EH: N
56H: V
27H: '
2FH: /
37H: 7
3FH: ?
47H: G
4FH: O
57H: W
CG RAM(1) CG RAM(1)
01H:
09H:
CG RAM(2) CG RAM(2)
02H:
0AH:
CG RAM(3) CG RAM(3)
03H:
0BH:
CG RAM(4) CG RAM(4)
04H:
0CH:
CG RAM(5) CG RAM(5)
05H:
0DH:
CG RAM(6) CG RAM(6)
06H:
0EH:
CG RAM(7) CG RAM(7)
07H:
0FH:
CG RAM(8) CG RAM(8)
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Table 3-1
ML9044A-xxA/xxB
Relationship between CGRAM address bits, CGRAM data bits (character pattern)
and DDRAM data bits (character code) in 5 × 7 dot character mode. (Examples)
CG RAM CG RAM data
DD RAM data
address
(Character pattern) (Character code)
5 4 3 2 1 0 76543210 76543210
MSB
LSB MSB
LSB MSB
LSB
0 0 0 0 0 0 ××× 0 1 1 1 0
10001
0 0 1
10001
0 1 0
10001
0 1 1
1 0 0
10001
0000×000
10001
1 0 1
1 1 0
01110
1 1 1
00000
×××
10001
0 0 1 0 0 0
10010
0 0 1
10100
0 1 0
11000
0 1 1
10100
0000×001
1 0 0
10010
1 0 1
1 1 0
10001
1 1 1
0 0 0 0 0
1 1 1 0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 ×××
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
1
1
1
1
1
1
1
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0000×111
×: Don’t Care
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Table 3-2
ML9044A-xxA/xxB
Relationship between CGRAM address bits, CGRAM data bits (character pattern)
and DDRAM data bits (character code) in 5 × 10 dot character mode (Examples)
CG RAM
address
543210
MSB LSB
000 00 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
010 00 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
110
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
CG RAM data
DD RAM data
(Character pattern)
(Character code)
76543210
MSB
LSB
××× 0 1 0 0 0
01 1 1 1
10 0 1 0
01 1 1 1
01 0 1 0
11 1 1 1
00 0 1 0
00 0 0 0
00 0 0 0
00 0 0 0
00 0 0 0
×××××
76543210
MSB
LSB
××× 0 0 0 0 0
00 0 0 0
01 1 1 1
10 0 0 1
10 0 0 1
10 0 0 1
01 1 1 1
00 0 0 1
00 0 0 1
01 1 1 0
00 0 0 0
×××××
0 ×××
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0 0 0 0 0
0 0 0 0 0
1 1 0 1 1
0 1 0 1 0
1 0 0 0 1
1 0 0 0 1
0 1 1 1 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
×××××
0000×00×
0000×01×
0000×11×
×: Don’t Care
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ML9044A-xxA/xxB
Cursor/Blink Control Circuit
This circuit generates the cursor and blink of the LCD.
The operation of this circuit is controlled by the program of the CPU.
The cursor/blink display is carried out in the position corresponding to the DDRAM address set in the ADC
(Address Counter).
For example, when the ADC stores a value of “07” (hexadecimal), the cursor or blink is displayed as follows:
DB6
ADC
0
DB0
0 0
0
0
Digit
1 2
In 1-line display mode
1 1 1
7
3 4
5 6 7
8
9
23 24
00 01 02 03 04 05 06 07 08
16 17
Cursor/blink position
Digit
1 2
In 2-line display mode
9
23 24
00 01 02 03 04 05 06 07 08
16 17
Second line 40 41 42 43 44 45 46 47 48
56 57
First line
3 4
5 6 7
8
Cursor/blink position
Note:
The cursor or blink is also displayed even when a CGRAM or ABRAM address is set in
the ADC. Therefore, the cursor or blink display should be inhibited while the ADC is
holding a CGRAM or ABRAM address.
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LCD Display Circuit (COM1 to COM17, SEG1 to SEG120, SSR and CSR)
The ML9044A has 17 common signal outputs and 120 segment signal outputs to display 24 characters (in the 1line display mode) or 48 characters (in the 2-line display mode).
The character pattern is converted into serial data and transferred in series through the shift register.
The transfer direction of serial data is determined by the SSR pin. The shift direction of common signals is
determined by the CSR pin. The following tables show the transfer and shift directions:
SSR
Transfer direction
L
SEG1 → SEG120
H
SEG120 → SEG1
CSR
duty
AS bit
Shift Direction
Arbitrator’s common pin
L
1/9
L
COM1 → COM9
COM9
L
1/9
H
COM1 → COM9
COM1
L
1/12
L
COM1 → COM12
COM12
L
1/12
H
COM1 → COM12
COM1
L
1/17
L
COM1 → COM17
COM17
L
1/17
H
COM1 → COM17
COM1
H
1/9
L
COM9 → COM1
COM1
H
1/9
H
COM9 → COM1
COM9
H
1/12
L
COM12 → COM1
COM1
H
1/12
H
COM12 → COM1
COM12
H
1/17
L
COM17 → COM1
COM1
H
1/17
H
COM17 → COM1
COM17
* Refer to the Expansion Instruction Codes section about the AS bit.
Signals to be input to the SSR and CSR pins should be determined at power-on and be kept unchanged.
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Built-in Reset Circuit
The ML9044A is automatically initialized when the power is turned on.
During initialization, the Busy Flag (BF) is “1” and the ML9044A does not accept any instruction from the CPU
(other than the Read BF instruction).
The Busy Flag is “1” for about 15 ms after the VDD becomes 2.7 V or higher.
During this initialization, the ML9044A performs the following instructions:
1)
2)
3)
4)
5)
6)
7)
8)
9)
10)
11)
Display clearing
CPU interface data length = 8 bits
1-line LCD display
Font size = 5 × 7 dots
ADC counting = Increment
Display shifting = None
Display = Off
Cursor = Off
Blinking = Off
Arbitrator = Displayed in the lower line
Setting 1FH (hexadecimal) to the Contrast Data
(DL = “1”)
(N = “0”)
(F = “0”)
(I/D = “1”)
(S = “0”)
(D = “0”)
(C = “0”)
(B = “0”)
(AS = “0”)
To use the built-in reset circuit, the power supply conditions shown below should be satisfied. Otherwise, the
built-in reset circuit may not work properly. In such a case, initialize the ML9044A with the instructions from the
CPU. The use of a battery always requires such initialization from the CPU. (See “Initial Setting of Instructions”)
2.7 V
0.2 V
0.2 V
tON
0.2 V
tOFF
0.1 ms ≤ tON ≤100 ms
1 ms ≤ tOFF
Figure 1 Power-on and Power-off Waveform
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I/F with CPU
Parallel interface mode
The ML9044A can transfer either 8 bits once or 4 bits twice on the data bus for interfacing with any 8-bit or 4-bit
microcontroller (CPU).
1) 8-bit interface data length
The ML9044A uses all of the 8 data bus lines DB0 to DB7 at a time to transfer data to and from the CPU.
2) 4-bit interface data length
The ML9044A uses only the higher-order 4 data bus lines DB4 to DB7 twice to transfer 8-bit data to and from
the CPU.
The ML9044A first transfers the higher-order 4 bits of 8-bit data (DB4 to DB7 in the case of 8-bit interface data
length) and then the lower-order 4 bits of the data (DB0 to DB3 in the case of 8-bit interface data length).
The lower-order 4 bits of data should always be transferred even when only the transfer of the higher-order 4
bits of data is required. (Example: Reading the Busy Flag)
Two transfers of 4 bits of data complete the transfer of a set of 8-bit data. Therefore, when only one access is
made, the following data transfer cannot be completed properly.
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RS1
RS0
R/W
E
Busy
(Internal operation)
No
Busy
DR7
IR6
ADC6
DR6
DB5
IR5
ADC5
DR5
DB4
IR4
ADC4
DR4
DB3
IR3
ADC3
DR3
DB2
IR2
ADC2
DR2
DB1
IR1
ADC1
DR1
DB0
IR0
ADC0
DR0
DB7
IR7
DB6
Writing In IR
(Instruction
Register)
Busy
Reading BF (Busy Flag)
and ADC (Address Counter)
Writing In DR
(Data Register)
Figure 2 8-Bit Data Transfer
RS1
RS0
R/W
E
Busy
(Internal operation)
DB7
No
Busy
ADC3
DR7
DR3
IR2
ADC6
ADC2
DR6
DR2
IR5
IR1
ADC5
ADC1
DR5
DR1
IR4
IR0
ADC4
ADC0
DR4
DR0
IR7
IR3
DB6
IR6
DB5
DB4
Writing In IR
(Instruction
Register)
Busy
Reading BF (Busy Flag)
and ADC (Address Counter)
Writing In DR
(Data Register)
Figure 3 4-Bit Data Transfer
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Serial Interface Mode
In the Serial I/F Mode, the ML9044A interfaces with the CPU via the CS, SHT, SI and SO pins.
Writing and reading operations are executed in units of 16 bits after the CS signal falls down. If the CS signal rises
up before the completion of 16-bit unit access, this access is ignored.
When the BF bit is “1”, the ML9044A cannot accept any other instructions. Before inputting a new instruction,
check that the BF bit is “0”. Any access when the BF bit is “1” is ignored.
Data format is LSB-first.
Examples of Access in the Serial I/F Mode
1) WRITE MODE
CS
1
2
3
4
5
6
1
1
1
1
1
R/W
1
2
3
4
5
6
1
1
1
1
R/W
7
8
9
10
11
12
13
14
15
16
1
SHT
BUSY
(Internal operation)
SI
RS0 RS1
D0
7
9
D1
D2
D3
D4
D5
D6
D7
1
SO
2) READ MODE
CS
8
10
11
12
13
15
14
16
1
SHT
BUSY
(Internal operation)
SI
SO
1
RS0 RS1
1
D0
D1
D2
D3
D4
D5
D6
D7
Note 1: Higher 5 bits of each instruction must be input at a “H” level.
Note 2: Lower 8 bits are “don’t care” when the instructions in the READ MODE are set.
Note 3: After one instruction is input, the next instruction must be input after the CS pin is pulled at a “H” level.
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Instruction Codes
Table of Instruction Codes
Code
Instruction
RS1 RS0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Display Clear
1
0
0
0
0
0
0
0
0
0
1
Cursor Home
1
0
0
0
0
0
0
0
0
1
X
Entry Mode
Setting
1
0
0
0
0
0
0
0
1
I/D
S
Display
1
ON/OFF Control
0
0
0
0
0
0
1
D
C
B
Cursor/Display
Shift
1
0
0
0
0
0
1
X
X
Function Setting 1
0
0
0
0
1
DL
X
X
CGRAM
Address Setting
1
0
0
0
1
DDRAM
Address Setting
1
0
0
1
ADD
Busy Flag/
Address Read
1
0
1
BF
ADC
RAM Data Write
1
1
0
WRITE DATA
RAM Data Read 1
1
1
READ DATA
0
0
Arbitrator
0
Display Line Set
Contrast Control
0
Data Write
Contrast Control
0
Data Read
0
0
S/C R/L
N
F
ACG
0
0
0
0
1
Function
Execution
Time
f = 270 kHz
Clears all the displayed digits of the
LCD and sets the DDRAM address 0 in
1.52 ms
the address counter. The arbitrator
data is cleared.
Sets the DDRAM address 0 in the
address counter and shifts the display
1.52 ms
back to the original. The content of the
DDRAM remains unchanged.
Determines the direction of movement
of the cursor and whether or not to shift
37 µs
the display. This instruction is
executed when data is written or read.
Sets LCD display ON/OFF (D), cursor
ON/OFF or cursor-position character
37 µs
blinking ON/OFF.
Moves the cursor or shifts the display
37 µs
without changing the content of the
DDRAM.
Sets the interface data length (DL), the
37 µs
number of display lines (N) or the type
of character font (F).
Sets on CGRAM address. After that,
CGRAM data is transferred to and from
37 µs
the CPU.
Sets a DDRAM address. After that,
37 µs
DDRAM data is transferred to and from
the CPU.
Reads the Busy Flag (indicating that
0 µs
the ML9044A is operating) and the
content of the address counter.
Writes data in DDRAM, ABRAM or
37 µs
CGRAM.
Reads data from DDRAM, ABRAM or
37 µs
CGRAM.
AS Sets the arbitrator display line.
37 µs
Writes data to control the contrast of
37 µs
the LCD.
Reads data to control the contrast of
0
1
0
0
0
37 µs
the LCD.
Sets an ABRAM address. After that,
ABRAM
0
0
0
0
1
1
AAB
37 µs
ABRAM data is transferred to and from
Address Setting
the CPU.
I/D = “1” (Increment)
I/D = “0” (Decrement)
The
DD RAM: Display data RAM
S = “1” (Shifts the display.)
CG RAM: Character generator RAM execution
S/C = “1” (Shifts display.)
S/C = “0” (Moves the cursor.)
time is
ABRAM: Arbitrator data RAM
R/L = “1” (Right shift)
R/L = “0” (Left shift)
dependent
ACG:
CGRAM
address
D/L = “1” (8-bit data)
DL = “0” (4-bit data)
upon
ADD:
DDRAM address
N = “1” (2 lines)
N = “0” (1 line)
frequen(Corresponds to the cursor cies.
F = “1” (5 x 10 dots)
F = “0” (5 x 7 dots)
address)
—
BF = “1” (Busy)
BF = “0” (Ready to accept
an instruction)
AAB:
ABRAM address
B = “1” (Enables blinking)
ADC:
Address counter (Used by
C = “1” (Displays the cursor.)
DDRAM, ABRAM and
D = “1” (Displays a character pattern.)
CGRAM)
AS = “1” (Arbitrator Displays AS = “0” (Arbitrator Displays
arbitrator on the
arbitrator on the
upper line)
lower line)
×: Don't Care
0
0
0
0
1
WRITE (Contrast Data)
DATA
READ (Contrast Data)
DATA
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Instruction Codes
An instruction code is a signal sent from the CPU to access the ML9044A. The ML9044A starts operation as
instructed by the code received. The busy status of the ML9044A is rather longer than the cycle time of the CPU,
since the internal processing of the ML9044A starts at a timing which does not affect the display on the LCD. In
the busy status (Busy Flag is “1”), the ML9044A cannot input the Busy Flag Read instruction only. Therefore, the
CPU should ensure that the Busy Flag is “0” before sending an instruction code to the ML9044A.
1) Display Clear
Instruction Code:
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
0
0
0
0
0
0
1
When this instruction is executed, the LCD display including arbitrator display is cleared and the I/D entry
mode is set to “Increment”. The value of “S” (Display shifting) remains unchanged. The position of the cursor
or blink being displayed moves to the left end of the LCD (or the left end of the line 1 in the 2-line display
mode).
Note:
All DDRAM and ABRAM data turn to “20” and “00” in hexadecimal, respectively. The value of the
address counter (ADC) turns to the one corresponding to the address “00” (hexadecimal) of the
DDRAM.
The execution time of this instruction is 1.52 ms (maximum) at an oscillation frequency of 270 kHz.
2) Cursor Home
Instruction code:
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
0
0
0
0
0
1
×
×: Don’t Care
When this instruction is executed, the cursor or blink position moves to the left end of the LCD (or the left end
of line 1 in the 2-line display mode). If the display has been shifted, the display returns to the original display
position before shifting.
Note:
The value of the address counter (ADC) goes to the one corresponding to the address “00”
(hexadecimal) of the DDRAM).
The execution time of this instruction is 1.52 ms (maximum) at an oscillation frequency of 270 kHz.
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3) Entry Mode Setting
Instruction code:
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
0
0
0
0
1
I/D
S
(1) When the I/D is set, the cursor or blink shifts to the right by 1 character position (ID= “1”; increment) or to
the left by 1 character position (I/D= “0”; decrement) after an 8-bit character code is written to or read
from the DDRAM. At the same time, the address counter (ADC) is also incremented by 1 (when I/D =
“1”; increment) or decremented by 1 (when I/D = “0”; decrement). After a character pattern is written to
or read from the CGRAM, the address counter (ADC) is incremented by 1 (when I/D = “1”; increment) or
decremented by 1 (when I/D = “0”; decrement).
Also after data is written to or read from the ABRAM, the address counter (ADC) is incremented by 1
(when I/D = “1”; increment) or decremented by 1 (when I/D = “0”; decrement).
(2) When S = “1”, the cursor or blink stops and the entire display shifts to the left (I/D = “1”) or to the right
(I/D = “0”) by 1 character position after a character code is written to the DDRAM.
In the case of S = “1”, when a character code is read from the DDRAM, when a character pattern is
written to or read from the CGRAM or when data is written to or read from the ABRAM, normal
read/write is carried out without shifting of the entire display. (The entire display does not shift, but the
cursor or blink shifts to the right (I/D = “1”) or to the left (I/D = “0”) by 1 character position.)
When S = “0”, the display does not shift, but normal write/read is performed.
Note:
The execution time of this instruction is 37 µs (maximum) at an oscillation frequency of
270 kHz.
4) Display ON/OFF Control
Instruction code:
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
0
0
0
1
D
C
B
(1) The “D” bit (DB2) of this instruction determines whether or not to display character patterns on the LCD.
When the “D” bit is “1”, character patterns are displayed on the LCD.
When the “D” bit is “0”, character patterns are not displayed on the LCD and the cursor/blinking also
disappear.
Note:
Unlike the Display Clear instruction, this instruction does not change the character code in the
DDRAM and ABRAM.
(2) When the “C” bit (DB1) is “0”, the cursor turns off. When both the “C” and “D” bits are “1”, the cursor
turns on.
(3) When the “B” bit (DB0) is “0”, blinking is canceled. When both the “B” and “D” bits are “1”, blinking is
performed.
In the Blinking mode, all dots including those of the cursor, the character pattern and the cursor are
alternately displayed.
Note:
The execution time of this instruction is 37 µs (maximum) at an oscillation frequency of
270 kHz.
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5) Cursor/Display Shift
Instruction code:
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
0
0
1
S/C
R/L
×
×
×: Don’t Care
S/C = “0”, R/L = “0”
This instruction shifts left the cursor and blink positions by 1 (decrements the
content of the ADC by 1).
This instruction shifts right the cursor and blink positions by 1 (increments the
content of the ADC by 1).
This instruction shifts left the entire display by 1 character position. The cursor
and blink positions move to the left together with the entire display.
The Arbitrator display is not shifted.
(The content of the ADC remains unchanged.)
This instruction shifts right the entire display by 1 character position. The cursor
and blink positions move to the right together with the entire display.
The Arbitrator display is not shifted.
(The content of the ADC remains unchanged.)
S/C = “0”, R/L = “1”
S/C = “1”, R/L = “0”
S/C = “1”, R/L = “1”
In the 2-line mode, the cursor or blink moves from the first line to the second line when the cursor at digit 40
(27; hex) of the first line is shifted right.
When the entire display is shifted, the character pattern, cursor or blink will not move between the lines (from
line 1 to line 2 or vice versa).
The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of 270 kHz.
Note:
6) Function Setting
Instruction code:
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
0
1
DL
N
F
×
×
×: Don’t Care
(1) When the “DL” bit (DB4) of this instruction is “1”, the data transfer to and from the CPU is performed
once by the use of 8 bits DB7 to DB0.
When the “DL” bit (DB4) of this instruction is “0”, the data transfer to and from the CPU is performed
twice by the use of 4 bits DB7 to DB4.
(2) The 2-line display mode is selected when the “N” bit (DB3) of this instruction is “1”. The 1-line display
mode is selected when the “N” bit is “0”.
(3) The character font represented by 5 × 7 dots is selected when the “F” bit (DB2) of this instruction is “1”.
The character font represented by 5 × 10 dots is selected when the “F” bit is “1” and the “N” bit is “0”.
After the ML9044A is powered on, this function setting should be carried out before execution of any
instruction except the Busy Flag Read. After this function setting, no instructions other than the DL Set
instruction can be executed. In the Serial I/F Mode, DL setting is ignored.
N
F
Number of
display lines
0
0
1
5×7
1/9
4
9
0
1
1
5 × 10
1/12
4
12
1
0
2
5×7
1/17
5
17
1
1
2
5×7
1/17
5
17
Note:
Font size
Duty
Number of
biases
Number of
common signals
The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of
270 kHz.
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7) CGRAM Address Setting
Instruction code:
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
1
C5
C4
C3
C2
C1
C0
This instruction sets the CGRAM address to the data represented by the bits C5 to C0 (binary).
The CGRAM addresses are valid until DDRAM or ABRAM addresses are set.
The CPU writes or reads character patterns starting from the one represented by the CGRAM address bits C5 to
C0 set in the instruction code at that time.
Note: The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of 270 kHz.
8) DDRAM Address Setting
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
1
D6
D5
D4
D3
D2
D1
D0
Instruction code:
This instruction sets the DDRAM address to the data represented by the bits D6 to D0 (binary).
The DDRAM addresses are valid until CGRAM or ABRAM addresses are set.
The CPU writes or reads character codes starting from the one represented by the DDRAM address bits D6 to
D0 set in the instruction code at that time.
In the 1-line mode (the “N” bit is “0”), the DDRAM address represented by bits D6 to D0 (binary) should be in
the range “00” to “4F” in hexadecimal.
In the 2-line mode (the “N” bit is “1”), the DDRAM address represented by bits D6 to D0 (binary) should be in
the range “00” to “27” or “40” to “67” in hexadecimal.
If an address other than above is input, the ML9044A cannot properly write a character code in or read it from
the DDRAM.
Note: The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of 270 kHz.
9) DDRAM/ABRAM/CGRAM Data Write
Instruction code:
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
1
0
E7
E6
E5
E4
E3
E2
E1
E0
A character code (E7 to E0) is written to the DDRAM, Display-ON data (E7 to E0) to the ABRAM or a character
pattern (E7 to E0) to the CGRAM.
The DDRAM, ABRAM or CGRAM is selected at the preceding address setting.
After data is written, the address counter (ADC) is incremented or decremented as set by the Entry Mode
Setting instruction (see 3).
Note: The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of 270 kHz.
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10) Busy Flag/Address Counter Read (Execution time: 0 µs)
Instruction code:
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
1
BF
O6
O5
O4
O3
O2
O1
O0
The “BF” bit (DB7) of this instruction tells whether the ML9044A is busy in internal operation (BF = “1”) or
not (BF = “0”).
When the “BF” bit is “1”, the ML9044A cannot accept any other instructions. Before inputting a new
instruction, check that the “BF” bit is “0”.
When the “BF” bit is “0”, the ML9044A outputs the correct value of the address counter. The value of the
address counter is equal to the DDRAM, ABRAM or CGRAM address. Which of the DDRAM, ABRAM and
CGRAM addresses is set in the counter is determined by the preceding address setting.
When the “BF” bit is “1”, the value of the address counter is not always correct because it may have been
incremented or decremented by 1 during internal operation.
11) DDRAM/ABRAM/CGRAM Data Read
Instruction code:
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
1
1
P7
P6
P5
P4
P3
P2
P1
P0
A character code (P7 to P0) is read from the DDRAM, Display-ON data (P7 to P0) from the ABRAM or a
character pattern (P7 to P0) from the CGRAM.
The DDRAM, ABRAM or CGRAM is selected at the preceding address setting.
After data is read, the address counter (ADC) is incremented or decremented as set by the Entry Mode Setting
instruction (see 3).
Note: Conditions for reading correct data
(1) The DDRAM, ABRAM or CGRAM Setting instruction is input before this data read instruction is input.
(2) When reading a character code from the DDRAM, the Cursor/Display Shift instruction (see 5) is input
before this Data Read instruction is input.
(3) When two or more consecutive RAM Data Read instructions are executed, the following read data is
correct.
Correct data is not output under conditions other than the cases (1), (2) and (3) above.
Note:
The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of 270 kHz.
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Expansion Instruction Codes
The busy status of the ML9044A is rather longer than the cycle time of the CPU, since the internal processing of
the ML9044A starts at a timing which does not affect the display on the LCD. In the busy status (Busy Flag is “1”),
the ML9044A executes the Busy Flag Read instruction only. Therefore, the CPU should ensure that the Busy Flag
is “0” before sending an expansion instruction code to the ML9044A.
1) Arbitrator Display Line Set
Expansion instruction code:
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
0
0
1
AS
This expansion instruction code sets the Arbitrator display line. The relationship between the status of this bit
and the common outputs is as follows:
For display examples, refer to LCD Drive Waveforms section.
CSR
duty
AS bit
Shift direction
Arbitrator’s common pin
L
1/9
L
COM1→COM9
COM9
L
1/9
H
COM1→COM9
COM1
L
1/12
L
COM1→COM12
COM12
L
1/12
H
COM1→COM12
COM1
L
1/17
L
COM1→COM17
COM17
L
1/17
H
COM1→COM17
COM1
H
1/9
L
COM9→COM1
COM1
H
1/9
H
COM9→COM1
COM9
H
1/12
L
COM12→COM1
COM1
H
1/12
H
COM12→COM1
COM12
H
1/17
L
COM17→COM1
COM1
H
1/17
H
COM17→COM1
COM17
Note: The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of 270 kHz.
2) Contrast Adjusting Data Write
Expansion instruction code:
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
1
F4
F3
F2
F1
F0
This instruction writes contrast adjusting data (F4 to F0) to the contrast register.
After contrast adjusting data is written in the register, the potential (VLCD) output to the V5 pin varies
according to the data written.
The VLCD becomes maximum when the content of the contrast register is “1F” (hexadecimal) and becomes
minimum when it is “00” (hexadecimal).
Note: The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of 270 kHz.
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3) Contrast Adjusting Data Read
Expansion instruction code:
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
0
0
G4
G3
G2
G1
G0
This instruction reads contrast adjusting data (G4 to G0) from the contrast register.
Note: The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of 270 kHz.
4) ABRAM Address Setting
Expansion instruction code:
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
1
1
H4
H3
H2
H1
H0
This instruction sets the ABRAM address to the data represented by the bits H4 to H0 (binary).
The ABRAM addresses are valid until CGRAM or DDRAM addresses are set.
The CPU writes or reads the Display-ON data starting from the one represented by the ABRAM address bits H4
to H0 set in the instruction code at that time.
When the ABRAM address represented by bits H4 to H0 (binary) is in the range “00” to “17” in hexadecimal,
data is output to the LCD as the arbitrator.
Note: The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of 270 kHz.
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Examples of Combinations of ML9044A and LCD Panel
(1) Driving the LCD of one 24-character line under the conditions of the 1-line display mode and the character
font of 5 × 7 dots
(1/9 duty, AS = “0”, CSR = “L”, SSR = “H”)
COM1
Character
COM8
COM9
Cursor
Arbitrator
SEG120
SEG1
ML9044A
• COM10 to COM17 output Display-OFF common signals.
(1/9 duty, AS = “1”, CSR = “L”, SSR = “H”)
COM1
COM2
Arbitrator
Character
Cursor
COM9
SEG120
SEG1
ML9044A
• COM10 to COM17 output Display-OFF common signals.
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(1/9 duty, AS = “0”, CSR = “H”, SSR = “L”)
ML9044A
SEG1
SEG120
COM9
Character
COM2
COM1
Cursor
Arbitrator
• COM10 to COM17 output Display-OFF common signals.
(1/9 duty, AS = “1”, CSR = “H”, SSR = “L”)
ML9044A
SEG1
Arbitrator
SEG120
COM9
COM8
Character
Cursor
COM1
• COM10 to COM17 output Display-OFF common signals.
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(2) Driving the LCD of one 24-character line under the conditions of the 1-line display mode and the character
font of 5 × 10 dots
(1/12 duty, AS = “0”, CSR = “L”, SSR = “H”)
COM1
Character
COM11
COM12
Cursor
Arbitrator
SEG120
SEG1
ML9044A
• COM13 to COM17 output Display-OFF common signals.
(1/12 duty, AS = “1”, CSR = “L”, SSR = “H”)
COM1
COM2
Arbitrator
Character
Cursor
COM12
SEG120
SEG1
ML9044A
• COM13 to COM17 output Display-OFF common signals.
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PEDL9044A-04
OKI Semiconductor
ML9044A-xxA/xxB
(1/12 duty, AS = “0”, CSR = “H”, SSR = “L”)
ML9044A
SEG1
SEG120
COM12
Character
COM2
COM1
Cursor
Arbitrator
• COM13 to COM17 output Display-OFF common signals.
(1/12 duty, AS = “1”, CSR = “H”, SSR = “L”)
ML9044A
SEG1
Arbitrator
SEG120
COM12
COM11
Character
Cursor
COM1
• COM13 to COM17 output Display-OFF common signals.
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ML9044A-xxA/xxB
(3) Driving the LCD of two 24-character lines under the conditions of the 2-line display mode and the character
font of 5 × 7 dots
(1/17 duty, AS = “0”, CSR = “L”, SSR = “H”)
COM1
Character
COM8
Cursor
COM9
Character
COM16
COM17
Cursor
Arbitrator
SEG120
SEG1
ML9044A
(1/17 duty, AS = “1”, CSR = “L”, SSR = “H”)
COM1
COM2
Arbitrator
Character
COM9
Cursor
COM10
Character
COM17
Cursor
SEG120
SEG1
ML9044A
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PEDL9044A-04
OKI Semiconductor
ML9044A-xxA/xxB
(1/17 duty, AS = “0”, CSR = “H”, SSR = “L”)
ML9044A
SEG1
SEG120
COM17
Character
Cursor
COM10
COM9
Character
Cursor
Arbitrator
COM2
COM1
(1/17 duty, AS = “1”, CSR = “H”, SSR = “L”)
ML9044A
SEG1
Arbitrator
SEG120
COM17
COM16
Character
Cursor
COM9
COM8
Character
Cursor
COM1
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PEDL9044A-04
OKI Semiconductor
ML9044A-xxA/xxB
EXAMPLES OF VLCD GENERATION CIRCUITS
• With 1/4bias, a built-in contrast adjusting circuit and a voltage multiplier
VDD
V1
V2
V3A
V3B
V4
ML9044A
V5
V5IN
VC
VCC
VIN
BE
• With 1/4 bias, a built-in contrast adjusting circuit
and the V5 level input from an external circuit
ML9044A
Reference potential for
voltage multiplier
• With 1/4 bias, no built-in contrast adjusting circuit
and the V5 level input from an external circuit
VDD
V1
V2
V3A
VDD
V1
V2
V3A
V3B
V4
V5
V5IN
V3B
V4
V5
V5IN
ML9044A
V5 level
VC
VCC
VC
VCC
VIN
VIN
BE
BE
V5 level
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PEDL9044A-04
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ML9044A-xxA/xxB
• With 1/5 bias, a built-in contrast adjusting circuit and a voltage multiplier
VDD
V1
V2
V3A
V3B
V4
ML9044A
V5
V5IN
VC
VCC
VIN
BE
• With 1/5 bias, a built-in contrast adjusting circuit
and the V5 level input from an external circuit
ML9044A
Reference potential for
voltage multiplier
• With 1/5 bias, no built-in contrast adjusting circuit
and the V5 level input from an external circuit
VDD
V1
V2
V3A
VDD
V1
V2
V3A
V3B
V4
V5
V5IN
V3B
V4
V5
V5IN
ML9044A
V5 level
VC
VCC
VC
VCC
VIN
VIN
BE
BE
V5 level
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PEDL9044A-04
OKI Semiconductor
ML9044A-xxA/xxB
LCD Drive Waveforms
The COM and SEG waveforms (AC signal waveforms for display) vary according to the duty (1/9, 1/12 and 1/17
duties). See 1) to 3) below.
The relationship between the duty ratio and the frame frequency is as follows:
Note:
Duty ratio
Frame Frequency
1/9
75.0 Hz
1/12
56.3 Hz
1/17
79.4 Hz
At an oscillation frequency (OSC) of 270 kHz
1) COM and SEG Waveforms on 1/9 Duty
CSR = “H” 2 1 9 8 7 6 ··· 3 2 1 9 8 7 6 ··· 3 2 1 9 8
COM1 (CSR = “L”, AS = “L”)
COM2 (CSR = “L”, AS = “H”)
COM9 (CSR = “H”, AS = “L”)
COM8 (CSR = “H”, AS = “H”)
(first character line)
CSR = “L” 8 9 1 2 3 4 ··· 7 8 9 1 2 3 4 ··· 7 8 9 1 2
VDD
V1
V2, V3B
V4
V5
1 frame
COM2 (CSR = “L”, AS = “L”)
COM3 (CSR = “L”, AS = “H”)
COM8 (CSR = “H”, AS = “L”)
COM7 (CSR = “H”, AS = “H”)
(second character line)
VDD
V1
V2, V3B
V4
V5
COM8 (CSR = “L”, AS = “L”)
COM9 (CSR = “L”, AS = “H”)
COM2 (CSR = “H”, AS = “L”)
COM1 (CSR = “H”, AS = “H”)
(cursor line)
VDD
V1
V2, V3B
V4
V5
COM9 (CSR = “L”, AS = “L”)
COM1 (CSR = “L”, AS = “H”)
COM1 (CSR = “H”, AS = “L”)
COM9 (CSR = “H”, AS = “H”)
(arbitrator line)
VDD
V1
V2, V3B
V4
V5
COM10 to
COM17
VDD
V1
V2, V3B
V4
V5
Display
turning-off
waveform
SEG
VDD
V1
V2, V3B
V4
V5
Display
turning-on
waveform
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PEDL9044A-04
OKI Semiconductor
ML9044A-xxA/xxB
2) COM and SEG Waveforms on 1/12 Duty
CSR = “H” 2 1 12 11 10 9 8 7 ··· 4 3 2 1 12 11 10 9 8 7 ···
COM1 (CSR = “L”, AS = “L”)
COM2 (CSR = “L”, AS = “H”)
COM12 (CSR = “H”, AS = “L”)
COM11 (CSR = “H”, AS = “H”)
(first character line)
CSR = “L” 11 12 1 2 3 4 5 6 ··· 9 10 11 12 1 2 3 4 5 6 ···
VDD
V1
V2, V3B
V4
V5
1 frame
COM2 (CSR = “L”, AS = “L”)
COM3 (CSR = “L”, AS = “H”)
COM11 (CSR = “H”, AS = “L”)
COM10 (CSR = “H”, AS = “H”)
(second character line)
VDD
V1
V2, V3B
V4
V5
COM11 (CSR = “L”, AS = “L”)
COM12 (CSR = “L”, AS = “H”)
COM2 (CSR = “H”, AS = “L”)
COM1 (CSR = “H”, AS = “H”)
(cursor line)
VDD
V1
V2, V3B
V4
V5
COM12 (CSR = “L”, AS = “L”)
COM1 (CSR = “L”, AS = “H”)
COM1 (CSR = “H”, AS = “L”)
COM12 (CSR = “H”, AS = “H”)
(arbitrator line)
VDD
V1
V2, V3B
V4
V5
COM13 to
COM17
VDD
V1
V2, V3B
V4
V5
Display
turning-off
waveform
SEG
VDD
V1
V2, V3B
V4
V5
Display
turning-on
waveform
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PEDL9044A-04
OKI Semiconductor
ML9044A-xxA/xxB
3) COM and SEG Waveforms on 1/17 Duty
CSR = “H” 2 1 17 16 15 14 13 12 11 10 9 8 7 6 5 ··· 2 1 17 16 15 14
COM1 (CSR = “L”, AS = “L”)
COM2 (CSR = “L”, AS = “H”)
COM17 (CSR = “H”, AS = “L”)
COM16 (CSR = “H”, AS = “H”)
(first character line)
COM2 (CSR = “L”, AS = “L”)
COM3 (CSR = “L”, AS = “H”)
COM16 (CSR = “H”, AS = “L”)
COM15 (CSR = “H”, AS = “H”)
(second character line)
COM16 (CSR = “L”, AS = “L”)
COM17 (CSR = “L”, AS = “H”)
COM2 (CSR = “H”, AS = “L”)
COM1 (CSR = “H”, AS = “H”)
(cursor line)
COM17 (CSR = “L”, AS = “L”)
COM1 (CSR = “L”, AS = “H”)
COM1 (CSR = “H”, AS = “L”)
COM17 (CSR = “H”, AS = “H”)
(arbitrator line)
CSR = “L” 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 ··· 16 17 1 2 3 4
VDD
V1
V2
V3A (V3B)
V4
V5
1 frame
VDD
V1
V2
V3A (V3B)
V4
V5
VDD
V1
V2
V3A (V3B)
V4
V5
VDD
V1
V2
V3A (V3B)
V4
V5
Display
turning-off
waveform
SEG
VDD
V1
V2
V3A (V3B)
V4
V5
Display
turning-on
waveform
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PEDL9044A-04
OKI Semiconductor
ML9044A-xxA/xxB
Initial Setting of Instructions
(a)
Data transfer from and to the CPU using 8 bits of DB0 to DB7
1) Turn on the power.
2) Wait for 15 ms or more after VDD has reached 2.7 V or higher.
3) Set “8 bits” with the Function Setting instruction.
4) Wait for 4.1 ms or more.
5) Set “8 bits” with the Function Setting instruction.
6) Wait for 100 µs or more.
7) Set “8 bits” with the Function Setting instruction.
8) Check the Busy Flag for No Busy (or wait for 100 µs or more).
9) Set “8 bits”, “Number of LCD lines” and “Font size” with the Function Setting instruction.
(After this, the number of LCD lines and the font size cannot be changed.)
10) Check the Busy Flag for No Busy.
11) Execute the Display ON/OFF Control Instruction, Display Clear Instruction, Entry Mode Setting
instruction and Arbitrator Display Line Setting Instruction.
12) Check the Busy Flag for No Busy.
13) Initialization is completed.
An example of instruction code for 3), 5) and 7)
RS1
RS0
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
0
0
1
1
×
×
×
×
×: Don’t Care
(b) Data transfer from and to the CPU using 4 bits of DB4 to DB7
1) Turn on the power.
2) Wait for 15 ms or more after VDD has reached 2.7 V or higher.
3) Set “8 bits” with the Function Setting instruction.
4) Wait for 4.1 ms or more.
5) Set “8 bits” with the Function Setting instruction.
6) Wait for 100 µs or more.
7) Set “8 bits” with the Function Setting instruction.
8) Check the Busy Flag for No Busy (or wait for 100 µs or longer).
9) Set “4 bits” with the Function Setting instruction.
10) Wait for 100 µs or longer.
11) Set “4 bits”, “Number of LCD lines” and “Font size” with the Function Setting instruction. (After this,
the number of LCD lines and the font size cannot be changed.)
12) Check the Busy Flag for No Busy.
13) Execute the Display ON/OFF Control Instruction, Display Clear Instruction, Entry Mode Setting
instruction and Arbitrator Display Line Setting Instruction.
14) Check the Busy Flag for No Busy.
15) Initialization is completed.
An example of instruction code for 3), 5) and 7)
RS1
RS0
R/W
DB7
DB6
DB5
DB4
1
0
0
0
0
1
1
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PEDL9044A-04
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ML9044A-xxA/xxB
An example of instruction code for 9)
RS1
RS0
R/W
DB7
DB6
DB5
DB4
1
0
0
0
0
1
0
*: From 11), input data twice by the use of 4-bit data.
*: In 13), check the Busy Flag for No Busy before executing each instruction.
(c)
Data transfer from and to the CPU using the serial I/F
1) Turn on the power.
2) Wait for 15 ms or more after VDD has reached 2.7 V or higher.
3) Check the busy flag for No Busy.
4) Set “Number of LCD lines” and “Font size” with the Function Setting Instruction.(After this, the
number of LCD lines and the font size cannot be changed.)
5) Check the busy flag for No Busy.
6) Execute the Display ON/OFF Control Instruction, the Display Clear Instruction, the Entry Mode
Instruction and the Arbitrator Display Line Setting Instruction.
7) Check the busy flag for No Busy.
8) Initialization is completed.
*: In 6), check the Busy Flag for No Busy before executing each instruction.
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ML9044A-xxA/xxB
ML9044A-xxA CVWA PAD CONFIGURATION
Pad Layout
10.62 × 2.55 mm
625±20 µm
72 × 72 µm
(PAD No. 1-62, 183-189)
54 × 96 µm
(PAD No. 63-182)
Chip Size:
Chip Thickness:
Bump Size (1):
Bump Size (2):
Y
182
63
62
183
X
189
56
1
55
Pad Coordinates
Pad
Symbol
X (µm)
Y (µm)
Pad
Symbol
X (µm)
Y (µm)
1
V1
–5103
–1100
21
DB3
–1323
–1100
2
V2
–4914
–1100
22
DB2
–1134
–1100
3
V3A
–4725
–1100
23
DB1
–945
–1100
4
V3B
–4536
–1100
24
DB0
–756
–1100
5
V4
–4347
–1100
25
E
–567
–1100
6
V5
–4158
–1100
26
R/W
–378
–1100
7
V5IN
–3969
–1100
27
RS0
–189
–1100
8
VCC
–3780
–1100
28
RS1
0
–1100
9
VC
–3591
–1100
29
SO
189
–1100
10
VlN
–3402
–1100
30
Sl
378
–1100
11
BE
–3213
–1100
31
SHT
567
–1100
12
VDD
–3024
–1100
32
CS
756
–1100
13
CSR
–2835
–1100
33
OSC2
945
–1100
14
SSR
–2646
–1100
34
OSCR
1134
–1100
15
S/P
–2457
–1100
35
OSC1
1323
–1100
16
VSS
–2268
–1100
36
T3
1512
–1100
17
DB7
–2079
–1100
37
T2
1701
–1100
18
DB6
–1890
–1100
38
T1
1890
–1100
19
DB5
–1701
–1100
39
COM1
2079
–1100
20
DB4
–1512
–1100
40
COM2
2268
–1100
54/64
PEDL9044A-04
OKI Semiconductor
ML9044A-xxA/xxB
Pad
Symbol
X (µm)
Y (µm)
Pad
Symbol
X (µm)
Y (µm)
41
COM3
2457
–1100
81
SEG102
3486
1088
42
COM4
2646
–1100
82
SEG101
3402
1088
43
COM5
2835
–1100
83
SEG100
3318
1088
44
COM6
3024
–1100
84
SEG99
3234
1088
45
COM7
3213
–1100
85
SEG98
3150
1088
46
COM8
3402
–1100
86
SEG97
3066
1088
47
COM9
3591
–1100
87
SEG96
2982
1088
48
COM10
3780
–1100
88
SEG95
2898
1088
49
COM11
3969
–1100
89
SEG94
2814
1088
50
COM12
4158
–1100
90
SEG93
2730
1088
51
COM13
4347
–1100
91
SEG92
2646
1088
52
COM14
4536
–1100
92
SEG91
2562
1088
53
COM15
4725
–1100
93
SEG90
2478
1088
54
COM16
4914
–1100
94
SEG89
2394
1088
55
COM17
5103
–1100
95
SEG88
2310
1088
56
DUMMY
5184
–720
96
SEG87
2226
1088
57
DUMMY
5184
–480
97
SEG86
2142
1088
58
DUMMY
5184
–240
98
SEG85
2058
1088
59
DUMMY
5184
0
99
SEG84
1974
1088
60
DUMMY
5184
240
100
SEG83
1890
1088
61
DUMMY
5184
480
101
SEG82
1806
1088
62
DUMMY
5184
720
102
SEG81
1722
1088
63
SEG120
4998
1088
103
SEG80
1638
1088
64
SEG119
4914
1088
104
SEG79
1554
1088
65
SEG118
4830
1088
105
SEG78
1470
1088
66
SEG117
4746
1088
106
SEG77
1386
1088
67
SEG116
4662
1088
107
SEG76
1302
1088
68
SEG115
4578
1088
108
SEG75
1218
1088
69
SEG114
4494
1088
109
SEG74
1134
1088
70
SEG113
4410
1088
110
SEG73
1050
1088
71
SEG112
4326
1088
111
SEG72
966
1088
72
SEG111
4242
1088
112
SEG71
882
1088
73
SEG110
4158
1088
113
SEG70
798
1088
74
SEG109
4074
1088
114
SEG69
714
1088
75
SEG108
3990
1088
115
SEG68
630
1088
76
SEG107
3906
1088
116
SEG67
546
1088
77
SEG106
3822
1088
117
SEG66
462
1088
78
SEG105
3738
1088
118
SEG65
378
1088
79
SEG104
3654
1088
119
SEG64
294
1088
80
SEG103
3570
1088
120
SEG63
210
1088
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PEDL9044A-04
OKI Semiconductor
ML9044A-xxA/xxB
Pad
Symbol
X (µm)
Y (µm)
Pad
Symbol
X (µm)
Y (µm)
121
SEG62
122
SEG61
126
1088
156
SEG27
–2814
1088
42
1088
157
SEG26
–2898
1088
123
SEG60
–42
1088
158
SEG25
–2982
1088
124
SEG59
–126
1088
159
SEG24
–3066
1088
125
SEG58
–210
1088
160
SEG23
–3150
1088
126
SEG57
–294
1088
161
SEG22
–3234
1088
127
SEG56
–378
1088
162
SEG21
–3318
1088
128
SEG55
–462
1088
163
SEG20
–3402
1088
129
SEG54
–546
1088
164
SEG19
–3486
1088
130
SEG53
–630
1088
165
SEG18
–3570
1088
131
SEG52
–714
1088
166
SEG17
–3654
1088
132
SEG51
–798
1088
167
SEG16
–3738
1088
133
SEG50
–882
1088
168
SEG15
–3822
1088
134
SEG49
–966
1088
169
SEG14
–3906
1088
135
SEG48
–1050
1088
170
SEG13
–3990
1088
136
SEG47
–1134
1088
171
SEG12
–4074
1088
137
SEG46
–1218
1088
172
SEG11
–4158
1088
138
SEG45
–1302
1088
173
SEG10
–4242
1088
139
SEG44
–1386
1088
174
SEG9
–4326
1088
140
SEG43
–1470
1088
175
SEG8
–4410
1088
141
SEG42
–1554
1088
176
SEG7
–4494
1088
142
SEG41
–1638
1088
177
SEG6
–4578
1088
143
SEG40
–1722
1088
178
SEG5
–4662
1088
144
SEG39
–1806
1088
179
SEG4
–4746
1088
145
SEG38
–1890
1088
180
SEG3
–4830
1088
146
SEG37
–1974
1088
181
SEG2
–4914
1088
147
SEG36
–2058
1088
182
SEG1
–4998
1088
148
SEG35
–2142
1088
183
DUMMY
–5184
720
149
SEG34
–2226
1088
184
DUMMY
–5184
480
150
SEG33
–2310
1088
185
DUMMY
–5184
240
151
SEG32
–2394
1088
186
DUMMY
–5184
0
152
SEG31
–2478
1088
187
DUMMY
–5184
–240
153
SEG30
–2562
1088
188
DUMMY
–5184
–480
154
SEG29
–2646
1088
189
DUMMY
–5184
–720
155
SEG28
–2730
1088
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PEDL9044A-04
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ML9044A-xxA/xxB
ML9044A-xxACVWA ALIGNMENT MARK SPECIFICATION
Alignment Mark Coordinates
Y
A
B
.....................................................................................................
(0,0)
X
C
Alignment Mark
X (µm)
Y (µm)
A
–5100
960
B
5100
960
C
5100
–840
Alignment Mark Layer
Metal layers
Alignment Mark Specification
Symbol
Parameter
a
b
Alignment Mark Width
—
25.2
Alignment Mark Size
—
100.2
Mark A
26.8
c
d
e
Mark
Distance between Mark and Internal Pattern (MIN)
Distance between Mark and Adjacent Pad Metal Layer (MIN)
Distance between Mark and Adjacent Pad Bump (MIN)
Size (µm)
Mark B
17.1
Mark C
87.3
Mark A
57.3
Mark B
57.3
Mark C
36.3
Mark A
69.1
Mark B
69.1
Mark C
49.0
Metal
Bump
b
d
b
a
c
e
Internal Pattern
a
Metal
Bump
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PEDL9044A-04
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ML9044A-xxA/xxB
ML9044A-xxB CVWA PAD CONFIGURATION
Pad Layout
10.62 × 2.55 mm
625±20 µm
72 × 72 µm
(PAD No. 1-55)
54 × 96 µm
(PAD No. 56-175)
Chip Size:
Chip Thickness:
Bump Size (1):
Bump Size (2):
Y
175
56
X
1
55
Pad Coordinates
Note:
The ML9044A-xxB does not have the dummy pads corresponding to the pad numbers 56 to 62 and 183 to
189 for the ML9044A-xxA.
Pad
Symbol
X (µm)
Y (µm)
Pad
Symbol
X (µm)
Y (µm)
1
V1
–5103
–1100
21
DB3
–1323
–1100
2
V2
–4914
–1100
22
DB2
–1134
–1100
3
V3A
–4725
–1100
23
DB1
–945
–1100
4
V3B
–4536
–1100
24
DB0
–756
–1100
5
V4
–4347
–1100
25
E
–567
–1100
6
V5
–4158
–1100
26
R/W
–378
–1100
7
V5IN
–3969
–1100
27
RS0
–189
–1100
8
VCC
–3780
–1100
28
RS1
0
–1100
9
VC
–3591
–1100
29
SO
189
–1100
10
VlN
–3402
–1100
30
Sl
378
–1100
11
BE
–3213
–1100
31
SHT
567
–1100
12
VDD
–3024
–1100
32
CS
756
–1100
13
CSR
–2835
–1100
33
OSC2
945
–1100
14
SSR
–2646
–1100
34
OSCR
1134
–1100
15
S/P
–2457
–1100
35
OSC1
1323
–1100
16
VSS
–2268
–1100
36
T3
1512
–1100
17
DB7
–2079
–1100
37
T2
1701
–1100
18
DB6
–1890
–1100
38
T1
1890
–1100
19
DB5
–1701
–1100
39
COM1
2079
–1100
20
DB4
–1512
–1100
40
COM2
2268
–1100
58/64
PEDL9044A-04
OKI Semiconductor
ML9044A-xxA/xxB
Pad
Symbol
X (µm)
Y (µm)
Pad
Symbol
X (µm)
Y (µm)
41
COM3
2457
–1100
81
SEG95
2898
1088
42
COM4
2646
–1100
82
SEG94
2814
1088
43
COM5
2835
–1100
83
SEG93
2730
1088
44
COM6
3024
–1100
84
SEG92
2646
1088
45
COM7
3213
–1100
85
SEG91
2562
1088
46
COM8
3402
–1100
86
SEG90
2478
1088
47
COM9
3591
–1100
87
SEG89
2394
1088
48
COM10
3780
–1100
88
SEG88
2310
1088
49
COM11
3969
–1100
89
SEG87
2226
1088
50
COM12
4158
–1100
90
SEG86
2142
1088
51
COM13
4347
–1100
91
SEG85
2058
1088
52
COM14
4536
–1100
92
SEG84
1974
1088
53
COM15
4725
–1100
93
SEG83
1890
1088
54
COM16
4914
–1100
94
SEG82
1806
1088
55
COM17
5103
–1100
95
SEG81
1722
1088
56
SEG120
4998
1088
96
SEG80
1638
1088
57
SEG119
4914
1088
97
SEG79
1554
1088
58
SEG118
4830
1088
98
SEG78
1470
1088
59
SEG117
4746
1088
99
SEG77
1386
1088
60
SEG116
4662
1088
100
SEG76
1302
1088
61
SEG115
4578
1088
101
SEG75
1218
1088
62
SEG114
4494
1088
102
SEG74
1134
1088
63
SEG113
4410
1088
103
SEG73
1050
1088
64
SEG112
4326
1088
104
SEG72
966
1088
65
SEG111
4242
1088
105
SEG71
882
1088
66
SEG110
4158
1088
106
SEG70
798
1088
67
SEG109
4074
1088
107
SEG69
714
1088
68
SEG108
3990
1088
108
SEG68
630
1088
69
SEG107
3906
1088
109
SEG67
546
1088
70
SEG106
3822
1088
110
SEG66
462
1088
71
SEG105
3738
1088
111
SEG65
378
1088
72
SEG104
3654
1088
112
SEG64
294
1088
73
SEG103
3570
1088
113
SEG63
210
1088
74
SEG102
3486
1088
114
SEG62
126
1088
75
SEG101
3402
1088
115
SEG61
42
1088
76
SEG100
3318
1088
116
SEG60
–42
1088
77
SEG99
3234
1088
117
SEG59
–126
1088
78
SEG98
3150
1088
118
SEG58
–210
1088
79
SEG97
3066
1088
119
SEG57
–294
1088
80
SEG96
2982
1088
120
SEG56
–378
1088
59/64
PEDL9044A-04
OKI Semiconductor
ML9044A-xxA/xxB
Pad
Symbol
X (µm)
Y (µm)
Pad
Symbol
X (µm)
Y (µm)
121
SEG55
–462
1088
149
SEG27
–2814
1088
122
SEG54
–546
1088
150
SEG26
–2898
1088
123
SEG53
–630
1088
151
SEG25
–2982
1088
124
SEG52
–714
1088
152
SEG24
–3066
1088
125
SEG51
–798
1088
153
SEG23
–3150
1088
126
SEG50
–882
1088
154
SEG22
–3234
1088
127
SEG49
–966
1088
155
SEG21
–3318
1088
128
SEG48
–1050
1088
156
SEG20
–3402
1088
129
SEG47
–1134
1088
157
SEG19
–3486
1088
130
SEG46
–1218
1088
158
SEG18
–3570
1088
131
SEG45
–1302
1088
159
SEG17
–3654
1088
132
SEG44
–1386
1088
160
SEG16
–3738
1088
133
SEG43
–1470
1088
161
SEG15
–3822
1088
134
SEG42
–1554
1088
162
SEG14
–3906
1088
135
SEG41
–1638
1088
163
SEG13
–3990
1088
136
SEG40
–1722
1088
164
SEG12
–4074
1088
137
SEG39
–1806
1088
165
SEG11
–4158
1088
138
SEG38
–1890
1088
166
SEG10
–4242
1088
139
SEG37
–1974
1088
167
SEG9
–4326
1088
140
SEG36
–2058
1088
168
SEG8
–4410
1088
141
SEG35
–2142
1088
169
SEG7
–4494
1088
142
SEG34
–2226
1088
170
SEG6
–4578
1088
143
SEG33
–2310
1088
171
SEG5
–4662
1088
144
SEG32
–2394
1088
172
SEG4
–4746
1088
145
SEG31
–2478
1088
173
SEG3
–4830
1088
146
SEG30
–2562
1088
174
SEG2
–4914
1088
147
SEG29
–2646
1088
175
SEG1
–4998
1088
148
SEG28
–2730
1088
60/64
PEDL9044A-04
OKI Semiconductor
ML9044A-xxA/xxB
ML9044A-xxBCVWA ALIGNMENT MARK SPECIFICATION
Alignment Mark Coordinates
Y
B
A
..................................................................................................
(0,0)
X
C
Alignment Mark
X (µm)
Y (µm)
A
–5100
960
B
5100
960
C
5100
–840
Alignment Mark Layer
Metal layers
Alignment Mark Specification
Parameter
a
b
Alignment Mark Width
—
25.2
Alignment Mark Size
—
100.2
Mark A
26.8
c
d
e
Mark
Size (µm)
Symbol
Distance between Mark and Internal Pattern (MIN)
Distance between Mark and Adjacent Pad Metal Layer (MIN)
Distance between Mark and Adjacent Pad Bump (MIN)
Mark B
17.1
Mark C
87.3
Mark A
57.3
Mark B
57.3
Mark C
164.7
Mark A
69.1
Mark B
69.1
Mark C
173.7
Metal
Bump
b
d
b
a
c
e
Internal Pattern
a
Metal
Bump
61/64
PEDL9044A-04
OKI Semiconductor
ML9044A-xxA/xxB
ML9044A-xxA/xxBCVWA GOLD BUMP SPECIFICATION
Gold Bump Specification
Symbol
Parameter
A
Bump Pitch (Min Section: Output Section)
MIN
TYP
84
—
(Unit: µm)
MAX
—
B
Bump Size (Output Section: Pitch Direction)
49
54
59
C
Bump Size (Output Section: Depth Direction)
91
96
101
D
Bump-to-Bump Distance (Output Section: Pitch Direction)
25
30
35
E
Bump Size (Input Section: Pitch Direction)
67
72
77
F
Bump Size (Input Section: Depth Direction)
67
72
77
G
Bump-to-Bump Distance (Input Section: Pitch Direction)
112
117
122
H
Sliding of Total Bump Pitches
—
—
2
Bump Height
10
15
20
I
Bump Height Dispersion Inside Chip (Range)
—
—
4
J
Bump Edge Height
—
—
5
K
Shear Strength (g)
30
—
—
L
Bump Hardness (Hv: 25 g load)
50
90
130
■ Chip Size; 10.62 mm × 2.55 mm
■ Chip Thickness; 625 ±20 µm
Top View and Cross Section View
B•E
I
C•F
J
A
Top View
D•F
Cross Section View
62/64
PEDL9044A-04
OKI Semiconductor
ML9044A-xxA/xxB
REVISION HISTORY
Document
No.
PEDL9044A-01
PEDL9044A-02
PEDL9044A-03
PEDL9044A-04
Date
Dec. 2001
Feb. 1, 2002
Feb. 6, 2002
Apr. 8, 2002
Page
Previous Current
Edition
Edition
Description
–
–
5
5
6
6
8
8
10
10
Preliminary first edition
Changed descriptions of Symbol BE.
Changed descriptions of Symbols VC and VCC.
Changed description of Symbol S/P.
Added Symbol DUMMY and descriptions.
Integrated Parameters “ “H” Input Voltage 1”
and “ “H” Input Voltage 2”, and Parameters “ “L”
Input Voltage 1” and “ “L” Input Voltage 2”.
Changed Min. value of “ “L” input voltage” from
–0.3 to 0.
Changed condition of Parameter “Input Current
2” from V1 = VDD to V1 = GND.
Changed Note 6.
12
12
Added Note.
13
13
32
32
35
35
36
36
Added CS “H” pulse width.
Changed timing diagrams.
Added Note 3.
Changed caption 4) from “Display Mode
Setting” to “Display ON/OFF Control”.
Partially changed Section (1) of 4).
Partially changed Section (3) of 6).
37
37
Partially changed Section 8).
38
38
1
1
8
8
19
19
Partially changed Section 11).
Partially changed the content of Section
“FEATURES”.
Changed a symbol in column “Applicable pin”
from CS to CS.
Partially changed Section (1) of 1).
20
20
21
21
27
27
Partially changed Section (2).
Partially changed Section “Arbitrator
RAM (ABRAM)”.
Changed the figure for ADC.
35
35
Partially changed Section 3).
37
37
Partially changed Section 9).
40
40
Partially changed Section 4).
37
37
Partially changed Section 7) and Section 8).
40
40
Partially changed Section 4).
53
53
Partially added the content of Section 4) in (C).
63/64
PEDL9044A-04
OKI Semiconductor
ML9044A-xxA/xxB
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
2.
The outline of action and examples for application circuits described herein have been chosen as an
explanation for the standard action and performance of the product. When planning to use the product, please
ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.
3.
When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified
maximum ratings or operation outside the specified operating range.
5.
Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is
granted by us in connection with the use of the product and/or the information and drawings contained herein.
No responsibility is assumed by us for any infringement of a third party’s right which may result from the use
thereof.
6.
The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not authorized for use in any system or application that requires special
or enhanced quality and reliability characteristics nor in any system or application where the failure of such
system or application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7.
Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products
and will take appropriate and necessary steps at their own expense for these.
8.
No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2002 Oki Electric Industry Co., Ltd.
64/64