184pin Registered DDR SDRAM DIMMs based on 256Mb D ver. (TSOP)
This Hynix Registered Dual In-Line Memory Module (DIMM) series consists of 256Mb D ver. DDR SDRAMs in 400mil.
TSOP II packages on a 184pin glass-epoxy substrate. This Hynix 256Mb D ver. based Registered DIMM series provide
a high performance 8-byte interface in 5.25" width form factor of industry standard. It is suitable for easy interchange
and addition.
FEATURES
•
JEDEC Standard 184-pin dual in-line memory module
(DIMM)
•
Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
•
Two ranks 128M x 72, 64M x 72 and One rank 64M x
72, 32M x 72 organization
•
Edge-aligned DQS with data outs and Center-aligned
DQS with data inputs
•
Error Check Correction (ECC) Capability
•
Auto refresh and self refresh supported
•
2.5V ± 0.2V VDD and VDDQ Power supply for
DDR333 and below
•
8192refresh cycles / 64ms
•
Serial Presence Detect (SPD) with EEPROM
•
All inputs and outputs are compatible with SSTL_2
interface
•
Built with 256Mb DDR SDRAMs in 400 mil TSOP II
packages
•
Fully differential clock operations (CK & /CK) with
100/133MHz
•
Lead-free product listed for each configuration
(RoHS compliant)
•
DLL aligns DQ and DQS transition with CK transition
•
Programmable CAS Latency : DDR200(2 clock),
DDR266(2, 2.5 clock)
ADDRESS TABLE
Organization
Ranks
SDRAMs
# of
DRAMs
# of row/bank/column Address
Refresh
Method
256MB
32M x 72
1
32Mb x 8
9
13(A0~A12)/2(BA0,BA1)/10(A0~A9)
8K / 64ms
512MB
64M x 72
1
64Mb x 4
18
13(A0~A12)/2(BA0,BA1)/11(A0~A9,A11)
8K / 64ms
512MB
64M x 72
2
32Mb x 8
18
13(A0~A12)/2(BA0,BA1)/10(A0~A9)
8K / 64ms
1GB
128M x 72
2
128Mb x 4 (Stacked)
36
13(A0~A12)/2(BA0,BA1)/12(A0~A9,A11,A12)
8K / 64ms
PERFORMANCE RANGE
Part-Number Suffix
-K
-H
-L
Unit
Speed Bin
DDR266A
DDR266B
DDR200
-
2-3-3
2.5-3-3
2-2-2
CK
CL=3
-
-
-
MHz
CL=2.5
133
133
100
MHz
CL=2
133
133
100
MHz
CL - tRCD- tRP
Max Clock
Frequency
Rev. 1.1 / May. 2005
1
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
184pin Registered DDR SDRAM DIMMs
ORDERING INFORMATION
Part Number
HYMD232G726D8-K/H
Density
Organization
256MB
32M x 8
# of DRAMs Material
9
Normal
1
HYMD232G726DP8-K/H
256MB
32M x 8
9
Pb-free
HYMD232G726D8M-K/H
256MB
32M x 8
9
Normal
1
DIMM Dimension
133.35 x 43.18 x 3.99 [mm3]
↑
133.35 x 30.48 x 3.99 [mm3]
HYMD232G726DP8M-K/H
256MB
32M x 8
9
Pb-free
HYMD264G726D8-K/H
512MB
64M x 8
18
Normal
133.35 x 43.18 x 3.99 [mm3]
HYMD264G726DP8-K/H
512MB
64M x 8
18
Pb-free1
↑
HYMD264G726D8M-K/H
512MB
64M x 8
18
Normal
133.35 x 30.48 x 3.99 [mm3]
HYMD264G726DP8M-K/H
512MB
64M x 8
18
Pb-free1
↑
HYMD264G726D4-K/H
512MB
64M x 4
18
Normal
133.35 x 43.18 x 3.99 [mm3]
HYMD264G726DP4-K/H
512MB
64M x 4
18
Pb-free1
↑
HYMD264G726D4M-K/H
512MB
64M x 4
18
Normal
133.35 x 30.48 x 3.99 [mm3]
HYMD264G726DP4M-K/H
512MB
64M x 4
18
Pb-free1
↑
HYMD212G726DS4-K/H/L
1GB
128M x 4 (stacked)
36
Normal
133.35 x 43.18 x 6.81 [mm3]
HYMD212G726DSP4-K/H/L
1GB
128M x 4 (stacked)
36
Pb-free1
↑
HYMD212G726DS4M-K/H
1GB
128M x 4 (stacked)
36
Normal
133.35 x 30.48 x 6.81 [mm3]
HYMD212G726DSP4M-K/H
1GB
128M x 4 (stacked)
36
Pb-free1
↑
↑
Note:
1. The “Pb-free” products contain Lead less than 0.1% by weight and satisfy RoHS - please contact Hynix for product availability.
* These products are built with HY5DU564(8,16)22DT[P], the Hynix DDR SDRAM component.
Rev. 1.1 /May. 2005
2
184pin Registered DDR SDRAM DIMMs
PIN DESCRIPTION
Pin
CK0, /CK0
/CS0, /CS1
CKE0, CKE1
/RAS, /CAS, /WE
A0 ~ A13
A10/AP
BA0, BA1
DQ0~DQ63
CB0~CB7
DQS0~DQS8
DM0~8
Pin Description
Pin
Differential Clock Inputs
Chip Select Inputs
Clock Enable Inputs
Commend Sets Inputs
Address Inputs
Address Input/Autoprecharge
Bank Address
Data Inputs/Outputs
Data Check bits
Data Strobes
Data-in Masks
Pin Description
VDD
VDDQ
VSS
VREF
VDDSPD
VDDID
SA0~SA2
SCL
SDA
DU
NC
TEST
Power Supply for Core and I/O
Power Supply for DQs
Ground
Input/Output Reference
Power Supply for SPD
VDD, VDDQ Level Detection
SPD Address Inputs
SPD Clock Input
SPD Data Input/Output
Do not Use
No Connect
Reserved for test equipment use
PIN ASSIGNMENT
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Name
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VDD
DQ3
NC
NC
VSS
DQ8
DQ9
DQS1
VDDQ
NC,CK1
NC,/CK1
VSS
DQ10
DQ11
CKE0
VDDQ
DQ16
DQ17
DQS2
VSS
A9
DQ18
A7
VDDQ
DQ19
Pin
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
Name
A5
DQ24
VSS
DQ25
DQS3
A4
VDD
DQ26
DQ27
A2
VSS
A1
CB0
CB1
VDD
DQS8
A0
CB2
VSS
CB3
BA1
Key
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
BA0
DQ35
DQ40
Pin
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
Name
VDDQ
/WE
DQ41
/CAS
VSS
DQS5
DQ42
DQ43
VDD
NC,/CS2
DQ48
DQ49
VSS
NC,/CK2
NC,CK2
VDDQ
DQS6
DQ50
DQ51
VSS
VDDID
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
VSS
NC
SDA
SCL
Pin
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
Name
VSS
DQ4
DQ5
VDDQ
DM0,DQS9
DQ6
DQ7
VSS
NC
NC,TEST
NC,/FETEN
VDDQ
DQ12
DQ13
DM1,DQS10
VDD
DQ14
DQ15
CKE1
VDDQ
NC,BA2
DQ20
NC,A12
VSS
DQ21
A11
DM2,DQS11
VDD
DQ22
A8
DQ23
Pin
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
Name
VSS
A6
DQ28
DQ29
VDDQ
DM3,DQS12
A3
DQ30
VSS
DQ31
CB4
CB5
VDDQ
CK0
/CK0
VSS
DM8,DQS17
A10
CB6
VDDQ
CB7
Key
VSS
DQ36
DQ37
VDD
DM4,DQS13
DQ38
DQ39
VSS
DQ44
Pin
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
Name
/RAS
DQ45
VDDQ
/CS0
/CS1
DM5,DQS14
VSS
DQ46
DQ47
NC,/CS3
VDDQ
DQ52
DQ53
NC,A13
VDD
DM6
DQ54
DQ55
VDDQ
NC
DQ60
DQ61
VSS
DM7,DQS16
DQ62
DQ63
VDDQ
SA0
SA1
SA2
VDDSPD
note:
1. Pins 111, 158 are not used for single rank module.
2. Pin 167 is “NC” for 256MB, 512MB and 1GB or “A13” for 2GB module.
3. Pins 16, 17, 75, 71, 76, 102, 103, 113, 163 are not used on this module.
Rev. 1.1 /May. 2005
3
184pin Registered DDR SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
256MB, 32Mb x 72 ECC Registered DIMM: HYMD232G726D[P]8[M]
/RS0
DQS0
DM0
DQS4
DM4
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
DQ00
DQ01
DQ02
DQ03
DQ04
DQ05
DQ06
DQ07
/CS
DQS
D0
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS
D4
DQS5
DM5
DQS1
DM1
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
DQ08
DQ09
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
/CS
DQS
D1
DQS2
DM2
/CS
DQS
D5
DQS6
DM6
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
/CS
DQS
D2
DQS3
DM3
DQS
D6
DQS7
DM7
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
/CS
DM
I/O0
I/O1
I/O2
/CS
DQS
D3
DQS8
DM8
VDDSPD
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O3
I/O4
I/O5
I/O6
I/O7
R
E
G
I
S
T
E
R
/S0
BA0-BA1
A0-A13
/RAS
/CAS
CKE0
/WE
PCK
/PCK
Rev. 1.1 /May. 2005
/CS
Serial PD
DQS
SCL
D8
SDA
WP
A0
A1
A2
SA0 SA1 SA2
RBA0-RBA1-> : BA0->BA1 : SDRAMs D0-D8
RA0-RA13-> : A0->A13 : SDRAMs D0-D8
/RRAS->/RAS : SDRAMs D0-D8
/RCAS->/CAS : SDRAMs D0-D8
RCKEO->CKE : SDRAMs D0-D8
/RWE->/WE : SDRAMs D0-D8
/RESET
CKO, /CKO------PLL*
* Wire per Clock Loading Table/Wiring Diagram
D7
Serial PD
VDDQ
DO-D8
VDD
DO-D8
VREF
DO-D8
VSS
VDDID
/RS0->/CS : SDRAMs D0-D8
DQS
DO-D8
Strap:see Note 4
Note :
1. DQ-to-I/O wiring may be changed within a byte.
2. DQ/DQS/DM/CKE/S relationships must be maintained
as shown.
3. DQ/DQS resistors should be 22 Ohms.
4. VDDID strap connections (for memory device VDD, VDDQ) :
STRAP OUT (OPEN) : VDD = VDDQ
STRAP IN (VSS) : VDD ≠ VDDQ
5. SDRAM placement alternates between the back and
front sides of the DIMM.
6. Address and control resistors should be 22 Ohms.
4
184pin Registered DDR SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
512MB, 64Mb x 72 ECC Registered DIMM: HYMD264G726D[P]8[M]
/RS1
/RS0
DQS0
DM0
DQS4
DM4
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
/CS
DQS
D0
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
/CS
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D9
I/O7
/CS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
DQS
D4
/CS
DQS
D 1
D13
2
I/O7
I/O7
DQS5
DM5
DQS1
DM1
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
/CS
DQS
D1
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
/CS
DQS
D10
I/O7
I/O7
DQS2
DM2
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
/CS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
DQS
D5
I/O7
/CS
DQS
D14
I/O7
DQS6
DM6
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
/CS
DQS
D2
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
/CS
DQS
D11
I/O7
I/O7
DQS3
DM3
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
/CS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
DQS
D6
I/O7
/CS
DQS
D15
I/O7
DQS7
DM7
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
/CS
DQS
D3
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
/CS
DQS
D12
I/O7
I/O7
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
/CS
DQS
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
D7
/CS
DQS
D16
I/O7
I/O7
Serial PD
DQS8
DM8
SCL
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
/CS
DQS
D8
DM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
/CS
SDA
DQS
WP
D17
A0-A13
/RAS
/CAS
CKE0
CKE1
/WE
PCK
/PCK
VDDSPD
Serial PD
DO-17
/RCSO->/CSO : SDRAMs D0-D8
VDD
DO-D17
/RCS1->/CS1 : SDRAMs D9-D17
VREF
DO-D17
RBA0-RBA1-> : BA0->BA1 : SDRAMs D0-D17
RA0-RA13-> : A0->A13 : SDRAMs D0-D17
/RRAS->/RAS : SDRAMs D0-D17
/RCAS->/CAS : SDRAMs D0-D17
RCKEO->CKE : SDRAMs D0-D8
RCKE1->CKE : SDRAMs D9-D17
/RWE->WE : SDRAMs D0-D17
/RESET
CKO, /CKO------PLL*
* Wire per Clock Loading Table/Wiring Diagram
Rev. 1.1 /May. 2005
A2
I/O7
I/O7
R
E
G
I
S
T
E
R
/S1
BA0-BA1
A1
SA0 SA1 SA2
VDDQ
/S0
A0
VSS
VDDID
DO-D17
Strap:see Note 4
Note :
1. DQ-to-I/O wiring may be changed within a byte.
2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.
3. DQ/DQS resistors should be 22 Ohms.
4. VDDID strap connections (for memory device VDD, VDDQ) :
STRAP OUT (OPEN) : VDD = VDDQ
STRAP IN (VSS) : VDD ≠ VDDQ
5. RCS0 and RCS1 altermate between the back front sides of the DIMM.
6. Address and control resistors should be 22 Ohms.
5
184pin Registered DDR SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
512MB, 64Mb x 72 ECC Registered DIMM: HYMD264G726D[P]4[M]
VSS
/RS0
DQS0
DM0/DQS9
DQ0
DQ1
DQ2
DQ3
DQS /CS
I/O0
I/O1
I/O2
I/O3
DM
DQ8
DQ9
DQ10
DQ11
DQS /CS
I/O0
I/O1
I/O2
I/O3
DM
DQ16
DQ17
DQ18
DQ19
DQS /CS
I/O0
I/O1
I/O2
I/O3
DM
DQ24
DQ25
DQ26
DQ27
DQS /CS
I/O0
I/O1
I/O2
I/O3
DM
DQ32
DQ33
DQ34
DQ35
DQS /CS
I/O0
I/O1
I/O2
I/O3
DM
DQ40
DQ41
DQ42
DQ43
DQS /CS
I/O0
I/O1
I/O2
I/O3
DM
DQ48
DQ49
DQ50
DQ51
DQS /CS
I/O0
I/O1
I/O2
I/O3
DM
D0
DQS1
DQS /CS
I/O0
I/O1
D0
I/O2
I/O3
DM
DQ4
DQ5
DQ6
DQ7
DQS /CS
I/O0
I/O1
D0
I/O2
I/O3
DM
DQ12
DQ13
DQ14
DQ15
DQS /CS
I/O0
I/O1
D0
I/O2
I/O3
DM
DQ20
DQ21
DQ22
DQ23
DQS /CS
I/O0
I/O1
D0
I/O2
I/O3
DM
DQ28
DQ29
DQ30
DQ31
DQS /CS
I/O0
I/O1
D0
I/O2
I/O3
DM
DQ36
DQ37
DQ38
DQ39
DQS /CS
I/O0
I/O1
D0
I/O2
I/O3
DM
DQ44
DQ45
DQ46
DQ47
DQS /CS
I/O0
I/O1
D0
I/O2
I/O3
DM
DQ52
DQ53
DQ54
DQ55
D9
DM1/DQS10
D1
DQS2
D10
DM2/DQS11
D2
DQS3
D11
DM3/DQS12
D3
DQS4
D12
DM4/DQS13
D4
DQS5
D13
DM5/DQS14
D5
DQS6
D14
DM6/DQS15
D6
DQS7
VDDSPD
D15
Serial PD
VDDQ
DO-D8
VDD
DO-D8
VREF
DO-D8
VSS
DO-D8
DM7/DQS16
DQS /CS
I/O0
I/O1
I/O2
I/O3
DQ56
DQ57
DQ58
DQ59
DM
DQ60
DQ61
DQ62
DQ63
D7
DQS /CS
I/O0
I/O1
D0
I/O2
I/O3
DM
Strap:see Note 4
VDDID
D16
Serial PD
DQS8
DM8/DQS17
DQS /CS
I/O0
I/O1
I/O2
I/O3
CB0
CB1
CB2
D8
CB3
/S0
BA0-BA1
A0-A12
/RAS
/CAS
CKE
/WE
PCK
/PCK
DM
R
E
G
I
S
T
E
R
CB4
CB5
CB6
CB7
/RS->/CS : SDRAMs D0-D17
RBA0-RBA1-> : BA0->BA1 : SDRAMs D0-D17
RA0-RA12-> : A0->A12 : SDRAMs D0-D17
/RRAS->/RAS : SDRAMs D0-D17
/RCAS->/CAS : SDRAMs D0-D17
RCKEA->CKE : SDRAMs D0-D17
/RWE->WE : SDRAMs D0-D17
DQS /CS
I/O0
I/O1
D0
I/O2
I/O3
D17
DM
SCL
SDA
WP
A0
A1 A2
SA0 SA1SA2
Note :
1. DQ-to-I/O wiring may be changed within a byte.
2. DQ/DQS/DM/CKE/S relationships must be maintained
as shown.
3. DQ/DQS resistors should be 22 Ohms.
4. VDDID strap connections (for memory device VDD, VDDQ) :
STRAP OUT (OPEN) : VDD = VDDQ
STRAP IN (VSS) : VDD ≠ VDDQ
5. Address and control resistors should be 22 Ohms.
/RESET
CKO, /CKO------PLL*
* Wire per Clock Loading Table/Wiring Diagram
Rev. 1.1 /May. 2005
6
184pin Registered DDR SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
1GB, 128Mb x 72 ECC Registered DIMM : HYM212G726DS[P]4[M]
VSS
/RS1
/RS0
DQS0
DM0/DQS9
DQ00
DQ01
DQ02
DQ03
DQS /CS
I/O0
I/O1
I/O2
I/O3
DM
DQ08
DQ09
DQ10
DQ11
DQS /CS
I/O0
I/O1
I/O2
I/O3
DM
DQ16
DQ17
DQ18
DQ19
DQS /CS
I/O0
I/O1
I/O2
I/O3
DM
DQ24
DQ25
DQ26
DQ27
DQS /CS
I/O0
I/O1
I/O2
I/O3
DM
DQ32
DQ33
DQ34
DQ35
DQS /CS
I/O0
I/O1
I/O2
I/O3
DM
DQ40
DQ41
DQ42
DQ43
DQS /CS
I/O0
I/O1
I/O2
I/O3
DM
DQ48
DQ49
DQ50
DQ51
DQS /CS
I/O0
I/O1
I/O2
I/O3
DM
DQ56
DQ57
DQ58
DQ59
DQS /CS
I/O0
I/O1
I/O2
I/O3
DM
CB0
CB1
CB2
CB3
DQS /CS
I/O0
I/O1
I/O2
I/O3
DM
DQS /CS
I/O0
I/O1
I/O2
I/O3
DM
DQS /CS
I/O0
I/O1
I/O2
I/O3
DM
DQS /CS
I/O0
I/O1
I/O2
I/O3
DM
DQS /CS
I/O0
I/O1
I/O2
I/O3
DM
DQS /CS
I/O0
I/O1
I/O2
I/O3
DM
DQS /CS
I/O0
I/O1
I/O2
I/O3
DM
DQS /CS
I/O0
I/O1
I/O2
I/O3
DM
DQS /CS
I/O0
I/O1
I/O2
I/O3
DM
DQS /CS
I/O0
I/O1
I/O2
I/O3
DM
D18
D0
DQS1
DQ04
DQ05
DQ06
DQ07
DM
DQS /CS
I/O0
I/O1 D0
I/O2
I/O3
DM
DQS /CS
I/O0
I/O1 D0
I/O2
I/O3
DM
DQS /CS
I/O0
I/O1 D0
I/O2
I/O3
DM
DQS /CS
I/O0
I/O1 D0
I/O2
I/O3
DM
DQS /CS
I/O0
I/O1 D0
I/O2
I/O3
DM
DQS /CS
I/O0
I/O1 D0
I/O2
I/O3
DM
DQS /CS
I/O0
I/O1 D0
I/O2
I/O3
DM
DQS /CS
I/O0
I/O1 D0
I/O2
I/O3
DM
DQS /CS
I/O0
I/O1 D0
I/O2
I/O3
DM
DQS /CS
I/O0
I/O1 D0
I/O2
I/O3
DM
DQS /CS
I/O0
I/O1 D0
I/O2
I/O3
DM
DQS /CS
I/O0
I/O1 D0
I/O2
I/O3
DM
DQS /CS
I/O0
I/O1 D0
I/O2
I/O3
DM
DQS /CS
I/O0
I/O1 D0
I/O2
I/O3
DM
DQS /CS
I/O0
I/O1 D0
I/O2
I/O3
DM
DQS /CS
I/O0
I/O1 D0
I/O2
I/O3
DM
DQS /CS
I/O0
I/O1 D0
I/O2
I/O3
DM
D27
D9
DM1/DQS10
D19
D1
DQS2
DQ12
DQ13
DQ14
DQ15
D28
D10
DM2/DQS11
D20
D2
DQS3
DQ20
DQ21
DQ22
DQ23
D29
D11
DM3/DQS12
D21
D3
DQS4
DQ28
DQ29
DQ30
DQ31
D30
D12
DM4/DQS13
D22
D4
DQS5
DQ36
DQ37
DQ38
DQ39
D31
D13
DM5/DQS14
D23
D5
DQS6
DQ44
DQ45
DQ46
DQ47
D32
D14
DM6/DQS15
D24
D6
DQS7
DQ52
DQ53
DQ54
DQ55
D33
D15
DM7/DQS16
D25
D7
DQS8
DQ60
DQ61
DQ62
DQ63
D34
D16
DM8/DQS17
D8
D26
CB4
CB5
CB6
CB7
VDDSPD
/S0
/S1
BA0-BA1
A0-A12
/RAS
/CAS
CKE0
CKE1
/WE
PCK
/PCK
R
E
G
I
S
T
E
R
/RS0->/CS : SDRAMs D0-D17
/RS1->/CS : SDRAMs D18-D35
RBA0-RBA1-> : BA0->BA1 : SDRAMs D0-D35
D35
D17
Serial PD
VDDQ
DO-D35
VDD
DO-D35
Serial PD
SDA
SCL
WP
VREF
A0 A1 A2
DO-D35
RA0-RA12-> : A0->A12 : SDRAMs D0-D35
SA0 SA1SA2
DO-D35
VSS
/RRAS->/RAS : SDRAMs D0-D35
/RCAS->/CAS : SDRAMs D0-D35
Strap:see Note 4
VDDID
Note :
RCKE0->CKE : SDRAMs D0-D17
1. DQ-to-I/O wiring may be changed within a byte.
RCKE1->CKE : SDRAMs D18-D35
2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.
/RWE->WE : SDRAMs D0-D35
/RESET
CKO, /CKO------PLL*
* Wire per Clock Loading Table/Wiring Diagram
Rev. 1.1 /May. 2005
DQS /CS
I/O0
I/O1 D0
I/O2
I/O3
3. DQ/DQS resistors should be 22 Ohms.
4. VDDID strap connections (for memory device VDD, VDDQ) :
STRAP OUT (OPEN) : VDD = VDDQ
STRAP IN (VSS) : VDD ≠ VDDQ
5. Address and control resistors should be 22 Ohms.
6. Each Chip Select and CKE pair alternate between decks for thermal
enhancement.
7
184pin Registered DDR SDRAM DIMMs
ABSOLUTE MAXIMUM RATINGS1
Parameter
Operating Temperature (Ambient)
Storage Temperature
Voltage on VDD relative to VSS
Symbol
Rating
Unit
TA
0 ~ 70
oC
TSTG
-55 ~ 150
oC
VDD
-1.0 ~ 3.6
V
Voltage on VDDQ relative to VSS
VDDQ
-1.0 ~ 3.6
V
Voltage on inputs relative to Vss
VINPUT
-1.0 ~ 3.6
V
Voltage on I/O pins realtive to Vss
VIO
-0.5 ~3.6
V
Output Short Circuit Current
IOS
50
Soldering Temperature ⋅ Time
mA
oC
260 ⋅ 10
TSOLDER
⋅ Sec
Note:
1. Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Min
Typ.
Max
Unit
Power Supply Voltage
VDD
2.3
2.5
2.7
V
Power Supply Voltage
VDDQ
2.3
2.5
2.7
V
Input High Voltage
VIH
VREF + 0.15
-
VDDQ + 0.3
V
Input Low Voltage
VIL
-0.3
-
VREF - 0.15
V
Termination Voltage
VTT
VREF - 0.04
VREF
VREF + 0.04
V
Reference Voltage
VREF
0.49*VDDQ
0.5*VDDQ
0.51*VDDQ
V
Input Voltage Level, CK and CK inputs
VIN(DC)
-0.3
-
VDDQ+0.3
V
Input Differential Voltage, CK and CK inputs
VID(DC)
0.36
-
VDDQ+0.6
V
5
V-I Matching: Pullup to Pulldown Current Ratio
Note
1
3
4
VI(RATIO)
0.71
-
1.4
-
6
Input Leakage Current
ILI
-2
-
2
uA
7
Output Leakage Current
ILO
-5
-
5
uA
8
IOH
-16.8
-
-
mA
IOL
16.8
-
-
mA
Output High Current
(min VDDQ, min VREF, min VTT)
IOH
-13.6
-
-
mA
Output Low Current
(min VDDQ, max VREF, max VTT)
IOL
13.6
-
-
mA
Output High Current
(min VDDQ, min VREF, min VTT)
Normal Strength
Output Driver
Output Low Current
(VOUT=VTT ± 0.84)
(min VDDQ, max VREF, max VTT)
Half Strength
Output Driver
(VOUT=VTT ± 0.68)
Note:
1. VDDQ must not exceed the level of VDD.
2. VIL (min) is acceptable -1.5V AC pulse width with < 5ns of duration.
3. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of the same. Peak to
peak noise on VREF may not exceed ± 2% of the DC value.
4. VID is the magnitude of the difference between the input level on CK and the input level on /CK.
5. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the maximum to minimum
pullup and pulldown current will not exceed 1/7 for device drain to source voltages from 0.1 to 1.0.
6. VIN=0 to VDD, All other pins are not tested under VIN =0V.
7. DQs are disabled, VOUT=0 to VDDQ.
Rev. 1.1 /May. 2005
8
184pin Registered DDR SDRAM DIMMs
IDD SPECIFICATION AND CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)
256MB, 32Mb x 72 ECC Registered DIMM : HYMD232G726D[P]8[M]
Symbol
Speed
Test Condition
Unit
-K
-H
-L
IDD0
One bank; Active - Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs changing twice
per clock cycle; address and control inputs changing
once per clock cycle
1280
1280
1235
mA
IDD1
One bank; Active - Read - Precharge; Burst Length=2;
tRC=tRC(min); tCK=tCK(min); address and control
inputs changing once per clock cycle
1460
1460
1370
mA
IDD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
740
740
740
mA
IDD2F
/CS=High, All banks idle; tCK=tCK(min); CKE= High;
address and control inputs changing once per clock
cycle. VIN=VREF for DQ, DQS and DM
1010
1010
920
mA
IDD3P
One bank active ; Power down mode; CKE=Low,
tCK=tCK(min)
785
785
785
mA
IDD3N
/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;
tRC=tRAS(max); tCK=tCK(min); DQ, DM and DQS
inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle
1010
1010
965
mA
IDD4R
Burst=2; Reads; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); IOUT=0mA
2000
2000
1820
mA
IDD4W
Burst=2; Writes; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); DQ, DM and DQS inputs changing
twice per clock cycle
2000
2000
1820
mA
IDD5
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK
for DDR266A & DDR266B at 133Mhz; distributed refresh
1610
1610
1520
mA
CKE=<0.2V; External clock on; tCK
=tCK(min)
Normal
377
377
377
mA
Low Power
364
364
364
mA
2450
2450
2270
mA
IDD6
IDD7
Four bank interleaving with BL=4 Refer to the following
page for detailed test condition
Note
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.1 /May. 2005
9
184pin Registered DDR SDRAM DIMMs
IDD SPECIFICATION AND CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)
512MB, 64Mb x 72 ECC Registered DIMM : HYMD264G726D[P]8[M]
Symbol
Speed
Test Condition
Unit
-K
-H
-L
IDD0
One bank; Active - Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs changing twice
per clock cycle; address and control inputs changing
once per clock cycle
1640
1640
1550
mA
IDD1
One bank; Active - Read - Precharge; Burst Length=2;
tRC=tRC(min); tCK=tCK(min); address and control
inputs changing once per clock cycle
1820
1820
1685
mA
IDD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
830
830
830
mA
IDD2F
/CS=High, All banks idle; tCK=tCK(min); CKE= High;
address and control inputs changing once per clock
cycle. VIN=VREF for DQ, DQS and DM
1370
1370
1235
mA
IDD3P
One bank active ; Power down mode; CKE=Low,
tCK=tCK(min)
920
920
920
mA
IDD3N
/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;
tRC=tRAS(max); tCK=tCK(min); DQ, DM and DQS
inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle
1370
1370
1280
mA
IDD4R
Burst=2; Reads; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); IOUT=0mA
2360
2360
2135
mA
IDD4W
Burst=2; Writes; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); DQ, DM and DQS inputs changing
twice per clock cycle
2360
2360
2135
mA
IDD5
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK
for DDR266A & DDR266B at 133Mhz; distributed refresh
1970
1970
1835
mA
CKE=<0.2V; External clock on; tCK
=tCK(min)
Normal
404
404
404
mA
Low Power
377
377
377
mA
2810
2810
2585
mA
IDD6
IDD7
Four bank interleaving with BL=4 Refer to the following
page for detailed test condition
Note
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.1 /May. 2005
10
184pin Registered DDR SDRAM DIMMs
IDD SPECIFICATION AND CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)
512MB, 64Mb x 72 ECC Registered DIMM : HYMD264G726D[P]4[M]
Symbol
Speed
Test Condition
Unit
-K
-H
-L
IDD0
One bank; Active - Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs changing twice
per clock cycle; address and control inputs changing
once per clock cycle
1910
1910
1820
mA
IDD1
One bank; Active - Read - Precharge; Burst Length=2;
tRC=tRC(min); tCK=tCK(min); address and control
inputs changing once per clock cycle
2270
2270
2090
mA
IDD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
830
830
830
mA
IDD2F
/CS=High, All banks idle; tCK=tCK(min); CKE= High;
address and control inputs changing once per clock
cycle. VIN=VREF for DQ, DQS and DM
1370
1370
1190
mA
IDD3P
One bank active ; Power down mode; CKE=Low,
tCK=tCK(min)
920
920
920
mA
IDD3N
/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;
tRC=tRAS(max); tCK=tCK(min); DQ, DM and DQS
inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle
1370
1370
1280
mA
IDD4R
Burst=2; Reads; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); IOUT=0mA
3170
3170
2810
mA
IDD4W
Burst=2; Writes; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); DQ, DM and DQS inputs changing
twice per clock cycle
3170
3170
2810
mA
IDD5
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK
for DDR266A & DDR266B at 133Mhz; distributed refresh
2870
2870
2690
mA
CKE=<0.2V; External clock on; tCK
=tCK(min)
Normal
404
404
404
mA
Low Power
377
377
377
mA
4610
4610
4250
mA
IDD6
IDD7
Four bank interleaving with BL=4 Refer to the following
page for detailed test condition
Note
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.1 /May. 2005
11
184pin Registered DDR SDRAM DIMMs
IDD SPECIFICATION AND CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)
1GB, 128Mb x 72 ECC Registered DIMM : HYMD212G726DS[P]4[M]
Symbol
Speed
Test Condition
Unit
-K
-H
-L
IDD0
One bank; Active - Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs changing twice
per clock cycle; address and control inputs changing
once per clock cycle
2630
2630
2450
mA
IDD1
One bank; Active - Read - Precharge; Burst Length=2;
tRC=tRC(min); tCK=tCK(min); address and control
inputs changing once per clock cycle
2990
2990
2720
mA
IDD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
1010
1010
1010
mA
IDD2F
/CS=High, All banks idle; tCK=tCK(min); CKE= High;
address and control inputs changing once per clock
cycle. VIN=VREF for DQ, DQS and DM
2090
2090
1820
mA
IDD3P
One bank active ; Power down mode; CKE=Low,
tCK=tCK(min)
1190
1190
1190
mA
IDD3N
/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;
tRC=tRAS(max); tCK=tCK(min); DQ, DM and DQS
inputs changing twice per clock cycle; Address and other
control inputs changing once per clock cycle
2090
2090
1910
mA
IDD4R
Burst=2; Reads; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); IOUT=0mA
3890
3890
3440
mA
IDD4W
Burst=2; Writes; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); DQ, DM and DQS inputs changing
twice per clock cycle
3890
3890
3440
mA
IDD5
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK
for DDR266A & DDR266B at 133Mhz; distributed refresh
3590
3590
3320
mA
CKE=<0.2V; External clock on; tCK
=tCK(min)
Normal
458
458
458
mA
Low Power
404
404
404
mA
5330
5330
4880
mA
IDD6
IDD7
Four bank interleaving with BL=4 Refer to the following
page for detailed test condition
Note
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.1 /May. 2005
12
184pin Registered DDR SDRAM DIMMs
AC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V)
Parameter
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Symbol
Min
Max
Unit
VIH(AC)
VREF + 0.31
-
V
Note
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
VIL(AC)
-
VREF - 0.31
V
Input Differential Voltage, CK and /CK inputs
VID(AC)
0.7
VDDQ + 0.6
V
1
Input Crossing Point Voltage, CK and /CK inputs
VIX(AC)
0.5*VDDQ-0.2
0.5*VDDQ+0.2
V
2
Note :
1. VID is the magnitude of the difference between the input level on CK and the input on /CK.
2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.
AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)
Value
Unit
Reference Voltage
Parameter
VDDQ x 0.5
V
Termination Voltage
VDDQ x 0.5
V
AC Input High Level Voltage (VIH, min)
VREF + 0.31
V
AC Input Low Level Voltage (VIL, max)
VREF - 0.31
V
Input Timing Measurement Reference Level Voltage
VREF
V
Output Timing Measurement Reference Level Voltage
VTT
V
Input Signal maximum peak swing
1.5
V
1
V/ns
Input minimum Signal Slew Rate
Termination Resistor (RT)
50
Ω
Series Resistor (RS)
25
Ω
Output Load Capacitance for Access Time Measurement (CL)
30
pF
OUTPUT LOAD CIRCUIT
VTT
RT=50Ω
Output
Zo=50Ω
VREF
CL=30pF
Rev. 1.1 /May. 2005
13
184pin Registered DDR SDRAM DIMMs
CAPACITANCE (TA=25oC, f=100MHz )
256MB : HYMD232G726D[P]8[M]
Symbol
Min
Max
Unit
A0 ~ A12, BA0, BA1
Input/output Pins
CIN1
8
12
pF
/RAS, /CAS, /WE
CIN2
8
12
pF
CKE0
CIN3
8
12
pF
/CS0
CIN4
8
12
pF
CK0, /CK0
CIN5
8
14
pF
DM0 ~ DM8
CIN6
8
14
pF
DQ0 ~ DQ63, DQS0 ~ DQS8
CIO1
8
14
pF
CB0 ~ CB7
CIO2
8
14
pF
512MB : HYMD264G726D[P]8[M]
Symbol
Min
Max
Unit
A0 ~ A12, BA0, BA1
Input/output Pins
CIN1
8
12
pF
/RAS, /CAS, /WE
CIN2
8
12
pF
CKE0, CKE1
CIN3
8
12
pF
/CS0, /CS1
CIN4
8
12
pF
CK0, /CK0
CIN5
8
14
pF
DM0 ~ DM8
CIN6
12
18
pF
DQ0 ~ DQ63, DQS0 ~ DQS8
CIO1
12
18
pF
CB0 ~ CB7
CIO2
12
18
pF
512MB : HYMD264G726D[P]4[M]
Symbol
Min
Max
Unit
A0 ~ A12, BA0, BA1
Input/output Pins
CIN1
8
12
pF
/RAS, /CAS, /WE
CIN2
8
12
pF
CKE0
CIN3
8
12
pF
/CS0
CIN4
8
12
pF
CK0, /CK0
CIN5
8
14
pF
DM0 ~ DM8
CIN6
7
12
pF
DQ0 ~ DQ63, DQS0 ~ DQS8
CIO1
7
12
pF
CB0 ~ CB7
CIO2
7
12
pF
1GB : HYMD212G726DS[P]4[M]
Symbol
Min
Max
Unit
A0 ~ A12, BA0, BA1
Input/output Pins
CIN1
8
14
pF
/RAS, /CAS, /WE
CIN2
8
14
pF
CKE0, CKE1
CIN3
8
14
pF
/CS0, /CS1
CIN4
8
14
pF
CK0, /CK0
CIN5
8
14
pF
DM0 ~ DM8
CIN6
12
18
pF
DQ0 ~ DQ63, DQS0 ~ DQS8
CIO1
12
18
pF
CB0 ~ CB7
CIO2
12
18
pF
Rev. 1.1 /May. 2005
14
184pin Registered DDR SDRAM DIMMs
AC CHARACTERISTICS (note: 1 - 9 / AC operating conditions unless otherwise noted)
Parameter
Symbol
DDR400B
DDR333
DDR266A
DDR266B
DDR200
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
UNIT
Row Cycle Time
tRC
55
-
60
-
65
-
65
-
70
-
ns
Auto Refresh Row
Cycle Time
tRFC
70
-
72
-
75
-
75
-
80
-
ns
Row Active Time
tRAS
40
70K
42
70K
45
120K
45
120K
50
120K
ns
tRAP
tRCD or
tRASmin
-
tRCD or
tRASmin
-
tRCD or
tRASmin
-
tRCD or
tRASmin
-
tRCD or
tRASmin
-
ns
Row Address to
Column Address Delay
tRCD
15
-
18
-
20
-
20
-
20
-
ns
Row Active to Row
Active Delay
tRRD
10
-
12
-
15
-
15
-
15
-
ns
Column Address to
Column Address Delay
tCCD
1
-
1
-
1
-
1
-
1
-
tCK
Row Precharge Time
tRP
15
-
18
-
20
-
20
-
20
-
ns
Write Recovery Time
tWR
15
-
15
-
15
-
15
-
15
-
ns
Internal Write to Read
Command Delay
tWTR
2
-
1
-
1
-
1
-
1
-
tCK
tDAL
(tWR/
tCK)
+
(tRP/tCK)
-
(tWR/
tCK)
+
(tRP/tCK)
-
(tWR/
tCK)
+
(tRP/tCK)
-
(tWR/
tCK)
+
(tRP/tCK)
-
(tWR/
tCK)
+
(tRP/tCK)
-
tCK
5
10
-
-
-
-
-
-
-
-
-
-
6
12
7.5
12
7.5
12
8.0
12
ns
-
-
7.5
12
7.5
12
10
12
10
12
ns
Active to Read with
Auto Precharge Delay
Auto Precharge Write
Recovery + Precharge
Time22
CL = 3
System
Clock Cycle CL = 2.5
Time24
CL = 2
tCK
Clock High Level Width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Clock Low Level Width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Data-Out edge to Clock
edge Skew
tAC
-0.7
0.7
-0.7
0.7
-0.75
0.75
-0.75
0.75
-0.75
0.75
ns
-0.55
0.55
-0.6
0.6
-0.75
0.75
-0.75
0.75
-0.75
0.75
ns
tDQSQ
-
0.4
-
0.45
-
0.5
-
0.5
-
0.6
ns
tQH
tHP
-tQHS
-
tHP
-tQHS
-
tHP
-tQHS
-
tHP
-tQHS
-
tHP
-tQHS
-
ns
tHP
min
(tCL,tCH)
-
min
(tCL,tCH)
-
min
(tCL,tCH)
-
min
(tCL,tCH)
-
min
(tCL,tCH)
-
ns
tQHS
-
0.5
-
0.55
-
0.75
-
0.75
-
0.75
ns
DQS-Out edge to Clock
tDQSCK
edge Skew
DQS-Out edge to DataOut edge Skew21
Data-Out hold time
from DQS20
Clock Half Period19,20
Data Hold Skew
Factor20
Valid Data Output
Window
Rev. 1.1 /May. 2005
tDV
tQH-tDQSQ
tQH-tDQSQ
tQH-tDQSQ
tQH-tDQSQ
tQH-tDQSQ
ns
15
184pin Registered DDR SDRAM DIMMs
- Continue
Parameter
Symbol
DDR400B
DDR333
DDR266A
DDR266B
DDR200
UNIT
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
tHZ
-0.7
0.7
-0.7
0.7
-0.75
0.75
-0.75
0.75
-0.8
0.8
ns
tLZ
-0.7
0.7
-0.7
0.7
-0.75
0.75
-0.75
0.75
-0.8
0.8
ns
tIS
0.6
-
0.75
-
0.9
-
0.9
-
1.1
-
ns
tIH
0.6
-
0.75
-
0.9
-
0.9
-
1.1
-
ns
tIS
0.7
-
0.8
-
1.0
-
1.0
-
1.1
-
ns
tIH
0.7
-
0.8
-
1.0
-
1.0
-
1.1
-
ns
tIPW
2.2
-
2.2
-
2.2
-
2.2
-
2.5
-
ns
Write DQS High Level Width
tDQSH
0.35
-
0.35
-
0.35
-
0.35
-
0.35
-
tCK
Write DQS Low Level Width
tDQSL
0.35
-
0.35
-
0.35
-
0.35
-
0.35
-
tCK
Clock to First Rising edge of DQSIn
tDQSS
0.72
1.25
0.75
1.25
0.75
1.25
0.75
1.25
0.75
1.25
tCK
DQS falling edge to CK setup time
tDSS
0.2
-
0.2
-
0.2
-
0.2
-
0.2
-
tCK
DQS falling edge hold time from
CK
tDSH
0.2
-
0.2
-
0.2
-
0.2
-
0.2
-
tCK
DQ & DM input setup time25
tDS
0.4
-
0.45
-
0.5
-
0.5
-
0.6
-
ns
DQ & DM input hold time25
tDH
0.4
-
0.45
-
0.5
-
0.5
-
0.6
-
ns
DQ & DM Input Pulse Width17
tDIPW
1.75
-
1.75
-
1.75
-
1.75
-
2
-
ns
Read DQS Preamble Time
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
tCK
Read DQS Postamble Time
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
0
-
0
-
0
-
0
-
0
-
ns
-
0.25
-
0.25
-
0.25
-
0.25
-
tCK
Data-out high-impedance window
from CK,/CK10
Data-out low-impedance window
from CK, /CK10
Input Setup Time (fast slew
rate)14,16-18
Input Hold Time (fast slew
rate)14,16-18
Input Setup Time (slow slew
rate)15-18
Input Hold Time (slow slew
rate)15-18
Input Pulse Width17
Write DQS Preamble Setup Time12 tWPRES
Write DQS Preamble Hold Time
11
tWPREH 0.25
Write DQS Postamble Time
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
Mode Register Set Delay
tMRD
2
-
2
-
2
-
2
-
2
-
tCK
tXSNR
75
-
75
-
75
-
75
-
80
-
ns
tXSRD
200
-
200
-
200
-
200
-
200
-
tCK
tREFI
-
7.8
-
7.8
-
7.8
-
7.8
-
7.8
us
Exit Self Refresh to non-Read
command23
Exit Self Refresh to Read
command
Average Periodic Refresh
Interval13,25
Rev. 1.1 /May. 2005
16
184pin Registered DDR SDRAM DIMMs
Note:
1. All voltages referenced to Vss.
2. Tests for ac timing, IDD, and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels,
but the related specifications and device operation are guaranteed for the full voltage range specified.
3. Below figure represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to
be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production
tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment.
Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics).
VDDQ
Output
(VOUT)
50 Ω
30 pF
Figure: Timing Reference Load
4. AC timing and IDD tests may use a VIL to VIHswing of up to 1.5 V in the test environment, but input timing is still referenced to
VREF (or to the crossing point for CK, /CK), and parameter specifications are guaranteed for the specified ac input levels under
normal use conditions. The minimum slew rate for the input signals is 1 V/ns in the range between VIL(ac) and VIH(ac).
5. The ac and dc input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result
of the signal crossing the ac input level and will remain in that state as long as the signal does not ring back above (below) the
dc input LOW (HIGH) level.
6. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE < 0.2VDDQ is
recognized as LOW.
7. The CK, /CK input reference level (for timing referenced to CK, /CK) is the point at which CK and /CK cross; the input reference
level for signals other than CK, /CK is VREF.
8. The output timing reference voltage level is VTT.
9. Operation or timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must
be powered down and then restarted through the specified initialization sequence before normal operation can continue.
10. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to
a specific voltage level but specify when the device output is no longer driving (HZ), or begins driving (LZ).
11. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but
system performance (bus turnaround) will degrade accordingly.
12. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A
valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from High-Z to logic LOW. If a previous write was in progress, DQS could
be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
13. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
14. For command/address input slew rate ≥ 1.0 V/ns.
15. For command/address input slew rate ≥ 0.5 V/ns and ＜ 1.0 V/ns
16. For CK & /CK slew rate ≥ 1.0 V/ns (single-ended)
17. These parameters guarantee device timing, but they are not necessarily tested on each device.
They may be guaranteed by device design or tester correlation.
18. Slew Rate is measured between VOH(ac) and VOL(ac).
19. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
value can be greater than the minimum specification limits for tCL and tCH).
For example, tCL and tCH are = 50% of the period, less the half period jitter (tJIT(HP)) of the clock source, and less the half
period jitter due to crosstalk (tJIT(crosstalk)) into the clock traces.
Rev. 1.1 /May. 2005
17
184pin Registered DDR SDRAM DIMMs
20.tQH = tHP - tQHS, where:
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The
pulse duration distortion of on-chip clock circuits; and 2) The worst case push--out of DQS on one transition followed by the
worst case pull--in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects,
and p-channel to n-channel variation of the output drivers.
21. tDQSQ:
Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given
cycle.
22. tDAL = (tWR/tCK) + (tRP/tCK)
For each of the terms above, if not already an integer, round to the next highest integer.
Example: For DDR266B at CL=2.5 and tCK=7.5 ns
tDAL = ((15 ns / 7.5 ns) + (20 ns / 7.5 ns)) clocks
= ((2) + (3)) clocks
= 5 clocks
23. In all circumstances, tXSNR can be satisfied using
tXSNR = tRFCmin + 1*tCK
24. The only time that the clock frequency is allowed to change is during self-refresh mode.
25. If refresh timing or tDS/tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid
READ can be executed.
Rev. 1.1 /May. 2005
18
184pin Registered DDR SDRAM DIMMs
SYSTEM CHARACTERISTICS CONDITIONS for DDR SDRAMS
The following tables are described specification parameters that required in systems using DDR devices to ensure
proper performannce. These characteristics are for system simulation purposes and are guaranteed by design.
Input Slew Rate for DQ/DM/DQS
AC CHARACTERISTICS
(Table a.)
DDR400
DDR333
DDR266
DDR200
PARAMETER
Symbol
min
max
min
max
min
max
min
max
DQ/DM/DQS input slew rate
measured between VIH(DC),
VIL(DC) and VIL(DC), VIH(DC)
DCSLEW
0.5
4.0
0.5
4.0
0.5
4.0
0.5
4.0
UNIT
Note
V/ns
1,12
Address & Control Input Setup & Hold Time Derating (Table b.)
Input Slew Rate
Delta tIS
Delta tIH
UNIT
Note
0.5 V/ns
0
0
ps
9
0.4 V/ns
+50
0
ps
9
0.3 V/ns
+100
0
ps
9
DQ & DM Input Setup & Hold Time Derating
(Table c.)
Input Slew Rate
Delta tDS
Delta tDH
UNIT
Note
0.5 V/ns
0
0
ps
11
0.4 V/ns
+75
0
ps
11
0.3 V/ns
+150
0
ps
11
DQ & DM Input Setup & Hold Time Derating for Rise/Fall Delta Slew Rate
Input Slew Rate
Delta tDS
Delta tDH
UNIT
Note
± 0.0 ns/V
0
0
ps
10
± 0.25 ns/V
+50
+50
ps
10
± 0.5 ns/V
+100
+100
ps
10
Output Slew Rate Characteristics (for x4, x8 Devices)
Slew Rate
Characteristic
Typical Range
(V/ns)
Minimum
(V/ns)
Maximum
(V/ns)
(Table d.)
(Table e.)
Note
Pullup Slew Rate
1.2 - 2.5
1.0
4.5
1,3,4,6,7,8
Pulldown Slew Rate
1.2 - 2.5
1.0
4.5
2,3,4,6,7,8
Output Slew Rate Characteristics (for x16 Device) (Table f.)
Slew Rate
Characteristic
Typical Range
(V/ns)
Minimum
(V/ns)
Maximum
(V/ns)
Note
Pullup Slew Rate
1.2 - 2.5
1.0
4.5
1,3,4,6,7,8
Pulldown Slew Rate
1.2 - 2.5
1.0
4.5
2,3,4,6,7,8
Output Slew Rate Matching Ratio Characteristics
Slew Rate Characteristic
DDR266A
(Table g.)
DDR266B
DDR200
Parameter
min
max
min
max
min
max
Output Slew Rate Matching Ratio
(Pullup to Pulldown)
-
-
-
-
0.71
1.4
Rev. 1.1 /May. 2005
Note
5,12
19
184pin Registered DDR SDRAM DIMMs
Note:
1. Pullup slew rate is characterized under the test conditions as shown in below Figure.
Test Point
Output
(VOUT)
50
Ω
VSSQ
Figure: Pullup Slew rate
2. Pulldown slew rate is measured under the test conditions shown in below Figure.
VDDQ
Output
(VOUT)
50Ω
Test Point
Figure: Pulldown Slew rate
3. Pullup slew rate is measured between (VDDQ/2 - 320 mV ± 250mV)
Pulldown slew rate is measured between (VDDQ/2 + 320mV ± 250mV)
Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output
switching.
Example: For typical slew, DQ0 is switching
For minimum slew rate, all DQ bits are switching worst case pattern
For maximum slew rate, only one DQ is switching from either high to low, or low to high.
The remaining DQ bits remain the same as for previous state.
4. Evaluation conditions
Typical: 25 oC (Ambient), VDDQ = nominal, typical process
Minimum: 70 oC (Ambient), VDDQ = minimum, slow-slow process
Maximum: 0 oC (Ambient), VDDQ = Maximum, fast-fast process
5. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature
and voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process
variation.
6. Verified under typical conditions for qualification purposes.
7. TSOP-II package devices only.
8. Only intended for operation up to 256 Mbps per pin.
9. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5 V/ns as shown in Table b.
The Input slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions.
10. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables c
& d. Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, fall rate. Input slew rate is based on
the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. The
delta rise/fall rate is calculated as:
{1/(Slew Rate1)} - {1/(slew Rate2)}
For example:
If Slew Rate 1 is 0.5 V/ns and Slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is -0.5 ns/V. Using the table given, this would
result in the need for an increase in tDS and tDH of 100ps.
11. Table c is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the
lesser of the AC-AC slew rate and the DC-DC slew rate. The input slew rate is based on the lesser of the slew rates determined by
either VIH(ac) to VIL(AC) or VIH(DC) to VIL(DC), and similarly for rising transitions.
12. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions through the DC region must be monotonic.
Rev. 1.1 /May. 2005
20
184pin Registered DDR SDRAM DIMMs
SIMPLIFIED COMMAND TRUTH TABLE
Command
CKEn-1
CKEn
/CS
/RAS
/CAS
/WE
ADDR
A10/AP
BA
Note
Extended Mode Register Set
H
X
L
L
L
L
OP code
1,2
Mode Register Set
H
X
L
L
L
L
OP code
1,2
H
X
X
1
H
X
Device Deselect
No Operation
Bank Active
Read
Read with Autoprecharge
Write
Write with Autoprecharge
Precharge All Banks
Precharge selected Bank
Read Burst Stop
Auto Refresh
Entry
Self Refresh
Precharge Power
Down Mode
Active Power Down
Mode
H
X
H
X
X
X
L
H
H
H
L
L
H
H
L
H
L
H
RA
CA
V
L
H
L
V
1,3
1
H
X
L
H
L
L
CA
H
X
L
L
H
L
X
H
X
L
H
H
L
X
1
H
H
L
L
L
H
X
1
H
L
L
L
L
H
H
X
X
X
L
H
H
H
Exit
L
H
Entry
H
L
Exit
L
H
Entry
H
L
Exit
L
H
H
V
1
1
H
X
L
V
1,4
1,5
1
1
X
1
H
X
X
X
1
L
H
H
H
1
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
X
1
1
1
X
1
X
1
( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )
Note :
1. DM states are Don’t Care. Refer to below Write Mask Truth Table.
2. OP Code(Operand Code) consists of A0~A12 and BA0~BA1 used for Mode Registering duing Extended MRS or MRS.
Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP
period from Prechagre command.
3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+tRP).
4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+1+tWR+tRP). Write Recovery Time(tWR) is needed to guarantee that the last data has been
completely written.
5. If A10/AP is High when Row Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be precharged.
WRITE MASK TRUTH TABLE
Function
CKEn-1
CKEn
/CS, /RAS, /CAS, /WE
DM
ADDR
A10/AP
BA
Note
Data Write
H
X
X
L
X
1
Data-In Mask
H
X
X
H
X
1
Note:
1. Write Mask command masks burst write data with reference to LDQS/UDQS(Data Strobes) and it is not related with read data.
In case of x16 data I/O, LDM and UDM control lower byte(DQ0~7) and Upper byte(DQ8~15) respectively.
Rev. 1.1 /May. 2005
21
184pin Registered DDR SDRAM DIMMs
PACKAGE DIMENSIONS
256MB, 64Mb x 72 ECC Registered DIMM: HYMD232G726D[P]8
Unit:
Millimeters
Inches
Front
133.35
5.25
43.18
1.7
Register
PLL
Register
Back
Side
(Front)
3.99
.157max
1.27+/-0.10
0.05+/-0.004
Rev. 1.1 /May. 2005
22
184pin Registered DDR SDRAM DIMMs
PACKAGE DIMENSIONS
256MB, 64Mb x 72 ECC Registered DIMM: HYMD232G726D[P]8M
Unit:
Millimeters
Inches
Front
133.35
5.25
Register
30.48
1.2
PLL
Back
Side
3.99
Register
.157max
(Front)
1.27+/-0.10
0.05+/-0.004
Rev. 1.1 /May. 2005
23
184pin Registered DDR SDRAM DIMMs
PACKAGE DIMENSIONS
512MB, 64Mb x 72 ECC Registered DIMM: HYMD264G726D[P]8
Unit:
Millimeters
Inches
Front
133.35
5.25
43.18
1.7
Register
PLL
Register
Back
Side
(Front)
3.99
.157max
1.27+/-0.10
0.05+/-0.004
Rev. 1.1 /May. 2005
24
184pin Registered DDR SDRAM DIMMs
PACKAGE DIMENSIONS
512MB, 64Mb x 72 ECC Registered DIMM: HYMD264G726D[P]8M
Unit:
Millimeters
Inches
Front
133.35
5.25
Register
30.48
1.2
PLL
Back
Side
3.99
Register
.157max
(Front)
1.27+/-0.10
0.05+/-0.004
Rev. 1.1 /May. 2005
25
184pin Registered DDR SDRAM DIMMs
PACKAGE DIMENSIONS
512MB, 64Mb x 72 ECC Registered DIMM: HYMD264G726D[P]4
Unit:
Millimeters
Inches
Front
133.35
(2X)4.00
.157
5.25
Register
PLL
43.18
1.7
Register
Back
Side
(Front)
3.99
.157max
1.27+/-0.10
0.05+/-0.004
Rev. 1.1 /May. 2005
26
184pin Registered DDR SDRAM DIMMs
PACKAGE DIMENSIONS
512MB, 64Mb x 72 ECC Registered DIMM: HYMD264G726D[P]4M
Unit:
Millimeters
Inches
Front
133.35
5.25
Register
30.48
1.2
PLL
Back
Side
3.99
Register
.157max
(Front)
1.27+/-0.10
0.05+/-0.004
Rev. 1.1 /May. 2005
27
184pin Registered DDR SDRAM DIMMs
PACKAGE DIMENSIONS
1GB, 128Mb x 72 ECC Registered DIMM: HYMD212G726DS[P]4
Unit:
Millimeters
Inches
Front
133.35
(2X)4.00
.157
5.25
Register
PLL
43.18
1.7
Register
Back
Side
(Front)
6.81
.268max
1.27+/-0.10
0.05+/-0.004
Rev. 1.1 /May. 2005
28
184pin Registered DDR SDRAM DIMMs
PACKAGE DIMENSIONS
1GB, 128Mb x 72 ECC Registered DIMM: HYMD212G726DS[P]4M
Front
Unit:
Millimeters
Inches
133.35
5.25
Register
30.48
1.2
PLL
Back
Side
6.81 TSOP
0.268max
Register
(Front)
1.27
0.050
Rev. 1.1 /May. 2005
29
184pin Registered DDR SDRAM DIMMs
REVISION HISTORY
Revision
1.0
1.1
History
First Version Release - Datasheet coverage is changed from an individual module part to a
component based module family
Corrected PIN DESCRIPTION and PIN ASSIGNMENT Tables
Rev. 1.1 /May. 2005
Date
Remark
Feb. 2005
May. 2005
30