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Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. FAN6290QF/FAN6290QH Compact Secondary-Side Adaptive Charging Controller Synchronous Rectifier Control FAN6290QF/FAN6290QH are highly integrated, secondary-side power adaptor controllers compatible with the Quick Charge 3.0 (QC3.0) protocol. Internally adopted synchronous rectifier control helps for less BOM counts as well as for easy design. www.onsemi.com The internal two operational amplifiers control adaptive constant output voltage and adaptive constant output current. The outputs of the two amplifiers are tied together in open-drain configuration. 10 FAN6290QF/FAN6290QH enables adaptor output voltage and current adjustment when Quick Charge 3.0 protocol is acknowledged. According to request from a battery charger of a Portable Device, output voltage is adjusted up to 12 V. When a portable device that implements noncompliant protocols is attached, it just maintains the default output, (5 V) for safety of the portable device. 1 SOP-10 MARKING DIAGRAM FAN6290QF/FAN6290QH incorporates adaptive output over-voltage and under-voltage protections to improve system reliability. ZXYTT 6290QX MF Features Compatible with Quick Charge 3.0 (QC3.0) Protocol Auto-detection supporting 2.4 A Apple products Internal Synchronous Rectifier Control Circuit Secondary-Side Constant Voltage (CV) and Constant Current (CC) Regulation with Two Operational Amplifiers Small Current Sensing Resistor (30 mΩ) for High Efficiency Protections for Safe Operation ; Output Over-Voltage-Protection, Output Under-Voltage-Protection for QC2.0, Data line (D+/D-) Over-Voltage-Protection Built-in output capacitor bleeding function for fast discharging during change of output mode Built-in Cable-Drop Compensation Typical Applications Battery Chargers for Smart Phones, Feature Phones, and Tablet PCs AC-DC Adapters for Portable Devices that Require CV/CC Control 1st Line: 2nd Line: 3rd Line: F: Corporate Logo Z: Assembly Plant Code X: Year Code Y: Week Code TT: Die Run Code 6290Q: IC Part Name X: Series Line-up Name MF PIN CONNECTIONS DP 1 10 CS DN 2 9 LPC VREF 3 8 GND IREF 4 7 GATE SFB 5 6 VIN (TOP View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 17 of this data sheet. © Semiconductor Components Industries, LLC, 2016 December 2016- Rev. 1.0 1 Publication Order Number: FAN6290QF/D FAN6290QF/FAN6290QH Std-A L Transformer RSNU CSNU TH SR MOSFET Lm BD CIN1 CIN2 D- DN COUT RSENSE GND DSNU RHV Fuse CS RGATE GND Q1 GATE Gate 4 2 NC CS 3 RF 9 FB VREF DP DP SFB DN DN IREF VS 6 CVDD 8 IMIN FAN6290 RVSH DVDD VDD 5 VIN RCS LPC 10 GND USB Cable D+ DP AC IN 1 HV Micro-B VBUS FMAX 7 RVSL CVS FAN602 Figure 1 FAN6290QF and FAN6290QH Typical Application Schematic VIN DP Protocol Communication (auto-detection) DN Data line OVP Internal Bias (VDD) Mode Mode Change Mode Change Cable Fault OVP Cable Fault VDD-ON / VDD-OFF OVP Protection UVP Protection Mode UVP Mode Cable Fault Calculate VLPC-EN VLPC-EN IREF Green Mode GATE Driver S LPC Q VDD CS XAVCCR PWM Block GND R VLPC-TH VCCR RESET Line Detection Function Mode Cable Drop Compensation VDD VREF VIN SR Off-time Decision Σ VCVR GATE Mode SFB Figure 2. FAN6290QF and FAN6290QH Function Block Diagram www.onsemi.com 2 FAN6290QF/FAN6290QH PIN FUNCTION DESCRIPTION Pin No. Pin Name 1 DP Communication Interface Positive Terminal. This pin is tied to the USB D+ data line input. Description 2 DN Communication Interface Negative Terminal. This pin is tied to the USB D- data line input. 3 VREF Output Voltage Sensing Terminal. Non-inverting terminal of the internal CV loop amplifier. This pin is used for constant voltage regulation. 4 IREF Constant Current Amplifying Signal. The voltage on this pin represents the amplified current sense signal, also used for constant current regulation. It is tied to the internal CC loop amplifier's noninverting terminal. 5 SFB Secondary Feedback. Common output of the open-drain operation amplifiers. Typically an optocoupler is connected to this pin to provide feedback signal to the primary-side PWM controller. 6 VIN Input Voltage. This pin is tied to the output of the adaptor not only to monitor output voltage but also to supply internal bias. IC operating current, and MOSFET gate-drive current are supplied through this pin. 7 GATE Gate Drive Output. Totem-pole output to drive an external SR MOSFET. 8 GND Ground. 9 LPC SR MOSFET Drain Voltage Detection. This pin detects the voltage on the secondary winding for Synchronous Rectifier control. 10 CS Current Sensing Amplifier Negative Terminal. Output current is sensed through this terminal for green mode control, cable drop compensation, and constant current control. Series Line-up Table Name Output Voltage and its Nominal Output Current UVP Operation VO = 3.6 ~ 6 V VO = 6.2 ~ 9 V VO = 9.2 ~ 12 V FAN6290QF 3.0 A 2.0 A 1.5 A Pull-down SFB FAN6290QH 3.0 A 3.0 A 2.0 A Reduce CC www.onsemi.com 3 FAN6290QF/FAN6290QH MAXIMUM RATINGS (Note 1,2,3) Rating VIN Pin Input Voltage Symbol Value Unit VIN 20 V SFB Pin Input Voltage VSFB 20 V IREF Pin Input Voltage VIREF -0.3 to 6 V VREF Pin Input Voltage VVREF -0.3 to 6 V VCS -0.3 to 6 V DP Pin Input Voltage VDP -0.3 to 14 V DN Pin Input Voltage VDN -0.3 to 14 V LPC Pin Input Voltage VLPC -0.3 to 6.5 V GATE Pin Input Voltage VGATE -0.3 to 6 V PD 0.68 W CS Pin Input Voltage Power Dissipation (TA=25C) Operating Junction Temperature Storage Temperature Range Lead Temperature, (Soldering, 10 Seconds) Human Body Model, ANSI/ESDA/JEDEC JS-001-2012 (Note 4) TJ -40 to 150 C TSTG -40 to 150 C TL 260 C ESDHBM 3 kV Charged Device Model, JESD22-C101 (Note 4) ESDCDM 1.75 kV 1. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 2. All voltage values, except differential voltages, are given with respect to the GND pin. 3. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. 4. Meets JEDEC standards JS-001-2012 and JESD 22-C101. THERMAL CHARACTERISTICS (Note 5) Rating Thermal Characteristics, Thermal Resistance, Junction-to-Air Thermal Reference, Junction-to-Top 5. TA=25°C unless otherwise specified. Symbol Value Unit RθJA RψJT 142 21 °C/W RECOMMENDED OPERATING RANGES (Note 6) Rating Symbol Min Max Unit VIN Pin Input Voltage VIN 0 16 V SFB Pin Input Voltage VSFB 0 16 V IREF Pin Input Voltage VIREF 0 1 V VREF Pin Input Voltage VVREF 0 3.5 V CS Pin Input Voltage VCS -0.1 0 V DP Pin Input Voltage VDP 0 6 V DN Pin Input Voltage VDN 0 6 V LPC Pin Input Voltage VLPC 0 5 V GATE Pin input Voltage VGATE 0 5.5 V 6. Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. www.onsemi.com 4 FAN6290QF/FAN6290QH ELECTRICAL CHARACTERISTICS VIN=5 V, LPC=1.5 V, LPC width=2 µs at TJ= -40~125 C, FLPC=100 kHz, unless otherwise specified. Parameter Test Conditions Symbol Min Typ Max Unit 16 V VIN Section Continuous Operating Voltage(7) VIN-OP Operating Supply Current VIN=5 V, VCS= -60 mV IIN-OP-5V 8 mA Operating Supply Current VIN=12 V, VCS= -60 mV IIN-OP-12V 8 mA 5 V Green Mode Operating Supply Current VIN=5 V, VCS=0 mV IIN-Green 1.2 1.6 mA Voltage difference between GND and CS for fixed UVP current (IO-UVP.typ=217 mA) Only for FAN6290QH VCS- UVP 3.0 6.5 10.0 mV VIN Under-Voltage-Protection Enable, 9 V For QC2.0 9 V Mode VIN-UVP-L-9V 5.00 5.50 6.00 V VIN Under-Voltage-Protection Enable, 12 V For QC2.0 12 V Mode VIN-UVP-L-12V 7.50 8.00 8.50 V VIN Under-Voltage-Protection Disable, 9 V For QC2.0 9 V Mode VIN-UVP-H-9V 5.50 6.00 6.50 V VIN Under-Voltage-Protection Disable, 12 V For QC2.0 12 V Mode VIN-UVP-H-12V 8.00 8.50 9.00 V tD-VIN-UVP 45 60 75 ms Output Over-Voltage Protection through VIN Pin at VO=3.6 ~ 5 V VIN-OVP-5V 5.5 6.0 6.5 V Output Over-Voltage Protection through VIN Pin at VO=5.2 ~ 6 V VIN-OVP-6V 8.1 8.4 8.7 V Output Over-Voltage Protection through VIN Pin at VO=6.2 ~ 9 V VIN-OVP-9V 10.3 10.8 11.3 V Output Over-Voltage Protection through VIN Pin at VO=9.2 ~ 12 V VIN-OVP-12V 13.6 14.4 15.0 V tD-OVP 22 33 44 μs VIN-UVP Section CC Mode UVP Debounce Time VIN-OVP Section OVP Debounce Time Internal Bias Section Turn-On Threshold Voltage VIN Increases VIN-ON 2.9 3.2 3.4 V Turn-Off Threshold Voltage VIN Decreases after VIN=VIN-ON VIN-OFF 2.8 2.9 3.0 V Hysteresis of Turn-Off Threshold Voltage VIN Decreases after VIN=VIN-ON tVIN-on-debounce 50 µs tVIN-off-debounce 200 µs 2.5 V Turn-On Debounce Time Turn-Off Debounce Time Output Voltage Releasing Latch Mode (8) VIN-OFF-HYS VLATCH-OFF 0.3 1.5 2.0 V Constant Current Sensing Section Current-Sense Amplifier Gain(7) VIN=5 V, VCS= -60 mV AV-CCR 10 V/V Voltage difference between GND and CS at IO=3.0~3.4 A, IOTYP=3.2 A (3 mV Offset) IO-NOMINAL=3.0 A of FAN6290QF(8) VCS-3.0A-QF 90.0 93.0 96.0 mV Voltage difference between GND and CS at IO=2.0~2.3 A, IOTYP=2.15 A (3 mV Offset) IO-NOMINAL=2.0 A of FAN6290QF(8) VCS-2.0A-QF 59.5 62.0 64.5 mV Voltage difference between GND and CS at IO=1.5~1.8 A, IOTYP=1.65 A (3 mV Offset) IO-NOMINAL=1.5 A of FAN6290QF(8) VCS-1.5A-QF 43.5 46.0 48.5 mV Voltage difference between GND and CS at IO=3.0~3.4 A, IOTYP=3.2 A (3 mV Offset) IO-NOMINAL=3.0 A of FAN6290QH(8) VCS-3.0A-QH 90.0 93.0 96.0 mV Voltage difference between GND and CS at IO=2.0~2.4 A, IOTYP=2.2 A (3 mV Offset) IO-NOMINAL=2.0 A of FAN6290QH(8) VCS-2.0A-QH 62.5 65.0 67.5 mV ZCS 4 VCS-Green 2 Current-Sensing Input Impedance(8) Voltage difference between GND and CS for Green Mode RCS=30 mΩ www.onsemi.com 5 MΩ 5 8 mV FAN6290QF/FAN6290QH ELECTRICAL CHARACTERISTICS (CONTINUED) VIN=5 V, LPC=1.5 V, LPC width=2 µs at TJ= -40~125 C, FLPC=100 kHz, unless otherwise specified. Parameter Test Conditions Symbol Min Typ Max Unit 34 39 44 mV 100 µs Constant Current Sensing Section (continued) Voltage difference between GND and CS for Green Mode Only for under 4.8 V Mode of QC3.0, RCS=30 mΩ Green Mode Enable Debounce Time After VCS<VCS-Green Green Mode Disable Debounce Time After VCS>VCS-Green VCS-GreenLowQC3.0 TGreen-ENDebounce TGreen-DIS- 8 12 16 ms Debounce Constant Voltage Sensing Section Reference Voltage at 5 V VIN=5 V, VCS=0 V, VDP=0.6 V, VDN=0 V VCVR-5V 0.98 1.00 1.02 V Reference Voltage at 9 V VIN=9 V, VCS=0 V, VDP=0.6 V, VDN=0 V VCVR-9V 1.76 1.80 1.84 V Reference Voltage at 12 V VIN=12 V, VCS=0 V, VDP=0.6 V, VDN=0 V VCVR-12V 2.335 2.400 2.465 V Reference Voltage of Increment Step via continuous mode of QC3.0 protocol VIN=12 V, VCS=0 V, VDP=0.6 V, VDN=3.3 V VCVR-STEP-INC 35 40 45 mV Reference Voltage of Decrement Step via Continuous Mode of QC3.0 Protocol VIN=12 V, VCS=0 V, VDP=0.6 V, VDN=3.3 V VCVR-STEP-DEC 35 40 45 mV Reference Voltage Soft-drop Time(7) During Mode change from VIN to Low VIN tCVR-Soft-drop VCS=-60 mV VCOMR-CDC 64.5 68.0 71.5 mV VCS=-60 mV VCOMR-OVP 360 510 660 mV After VIN>VIN-ON tStart-Dis-CC 1.3 2.5 6.0 ms 40 ms Cable Drop Compensation Section Cable Compensation Voltage(8) OVP Cable Compensation Voltage (8) Constant Current Amplifier Section Disable Constant Current Amplifier Time during Startup Internal Amplifier Transconductance(7) Internal Amplifier Dominant Pole (7) Internal CC Amplifier Input Resistor GmCC 3.5 Ʊ fP-CC 10 kHz RCC-IN 8.50 13.75 19.00 kΩ Constant Voltage Amplifier Section Internal Amplifier Dominant Pole(7) fP-CV (7) IBias-CV CV Bias Current 10 kHz 30 nA 12 16 mV 0.6 1.0 ms Bleeder Section Voltage difference between GND and CS to Decreasing VCS, RCS=30 mΩ enable Bleeding (IO-EN-BLD.typ=0.42 A)(7) (7) Debounce time to decide enable Bleeding Decreasing VCS, RCS=30 mΩ VIN Pin Sink Current through when Bleeding(7) VIN=9 V 8 tCS-EN-BLD IVIN -Sink VIN Pin Internal MOSFET Parasitical Resistor(7) Maximum Discharging Time when Bleeding(7) VCS-EN-BLD 200 mA RDS_on_BLD Disabling OVP & SR Gate tBLD-MAX 275 ISFB-Sink-MAX 2 320 40 Ω 365 ms Feedback Section Feedback Pin Maximum Sink Current www.onsemi.com 6 mA FAN6290QF/FAN6290QH ELECTRICAL CHARACTERISTICS (CONTINUED) VIN=5 V, LPC=1.5 V, LPC width=2 µs at TJ= -40~125 C, FLPC=100 kHz, unless otherwise specified. Parameter Test Conditions Symbol Min Typ Max Unit DP Low Threshold Voltage VDPL 0.24 0.25 0.28 V DP High Threshold Voltage VDPH 1.95 2.05 2.15 V DN Low Threshold Voltage VDNL 0.30 0.35 0.40 V DN High Threshold Voltage VDNH 1.95 2.05 2.15 V DP and DN High Debounce Time tBC1.2 1.0 1.2 1.4 s tDISCONNECT 5 10 Protocol Section_Quick Charge 2.0 Interface DP Disconnect Debounce Time DN Low Debounce Time, VDN < VDNL tTOGGLE 40 15 ms 1.0 ms 60 ms 100 ms Mode-Change Debounce Time tV_CHANGE 20 Blanking Time after Mode Change tV_REQUEST 60 DP Pull Low Resistance RDP 300 1120 1500 kΩ DN Pull Low Resistance RDN 14.25 19.53 24.80 kΩ tV_CHANGE 20 40 60 ms tCONT_CHANGE 100 150 200 µs 12 V Protocol Section_Quick Charge 3.0 Interface Mode-Change Debounce Time VDP=0.6, VDN=3.3 V Mode-Change Debounce Time for Continuous Mode For TACTIVE and TINACTIVE VIN_CONT_ VIN Voltage Range for Continuous Mode(7) 3.6 RANGE Table 1. Quick Charge 3.0 & 2.0 Output Modes Mode VDP (Typ.) Mode 1 Mode 2 VDN (Typ.) VOUT 0.6 V 0V 5V 3.3 V 0.6 V 9V Mode 3 0.6 V 0.6 V 12 V Mode 4 0.6 V 3.3 V Continuous Mode Mode 5 3.3 V 3.3 V Reserved www.onsemi.com 7 FAN6290QF/FAN6290QH ELECTRICAL CHARACTERISTICS (CONTINUED) VIN=5 V, LPC=1.5 V, LPC width=2 µs at TJ= -40~125 C, FLPC=100 kHz, unless otherwise specified. Parameter Test Conditions Symbol Min Typ Max Unit Protocol Section_Auto Detection Default DP Voltage when floating 2.75 V Supply Mode VDP_2.75V 2.65 2.75 2.85 V Default DN Voltage when floating 2.75 V Supply Mode VDN_2.75V 2.65 2.75 2.85 V DP Pin Output Impedance in Default Mode 2.75 V Supply Mode RDP_2.75V 23 28 33 kΩ DN Pin Output Impedance in Default Mode 2.75 V Supply Mode RDN_2.75V 23 28 33 kΩ Increment of VDP for exiting 2.75 V Supply Mode Increment from VDP_2.75V VDP_INC 115 170 225 mV Debounce time for exiting 2.75 V Supply Mode tEXIT_MODE1 3 4 5 ms Delay time to recover to 2.75 V Supply Mode VDP< VDPL in BC1.2 Mode tREC_MODE1 3 4 5 sec 0.16 0.25 V Output Driver Section Output Voltage Low VIN=5 V, IGATE=100 mA VOL Output Voltage High VIN=5 V VOH Rising Time(7) VIN=5 V, CL=3300 pF, GATE=1 V ~ 4 V tR 20 Falling Time(7) VIN=5 V, CL=3300 pF, GATE=4 V~ 1 V tF 9 Propagation Delay to OUT High (LPC Trigger) VIN=5 V, GATE=1 V tPD-HIGH-LPC 44 Propagation Delay to OUT Low (LPC Trigger)(7) VIN=5 V, GATE=4 V tPD-LOW-LPC 30 ns tINHIBIT 1.4 µs KRES 0.150 V/V Gate Inhibit Time(7) 4.5 V 35 ns ns 80 ns Internal RES Section Internal RES Ratio(7) VIN=5~12 V VIN Dropping Protection Ratio with Two Cycle LPC Width=5 µs, VIN=5 V to 3.5 V Debounce Time for Disable SR when VIN Dropping Protection KVIN-DROP 70 tSR_OFF 3.8 VLPC 0.5 5.5 90 % 7.2 ms VIN -1 V LPC Section Linear Operation Range of LPC Pin Voltage(7) VIN -OFF < VIN ≤ 5 V LPC Sink Current VLPC=1 V 100 ILPC-SINK SR Enabled Threshold Voltage @High-Line nA 1.58 VLPC-HIGH-H V Threshold Voltage on LPC Rising Edge @High-Line(7) VLPC-HIGH-H *0.875=VLPC-TH-H SR Enabled Threshold Voltage @ Low-Line VLPC-HIGH-L-5.5V=VLPC-TH-L-5.5V / 0.875 VLPC-HIGH-L-5.5V Threshold Voltage on LPC Rising Edge @ Low-Line(7) Spec.=0.45+0.05*VIN, VIN=5.5 V VLPC-TH-L-5.5V SR Enabled Threshold Voltage @ Low-Line VLPC-HIGH-L-9V=VLPC-TH-L-9V / 0.875 VLPC-HIGH-L-9V Threshold Voltage on LPC Rising Edge @ Low-Line(7) Spec.=0.45+0.05*VIN, VIN=9 V VLPC-TH-L-9V SR Enabled Threshold Voltage @ Low-Line VLPC-HIGH-L-12V=VLPC-TH-L-12V / 0.875 VLPC-HIGH-L-12V Threshold Voltage on LPC Rising Edge @ Low-Line(7) Spec.=0.45+0.05*VIN, VIN=12 V VLPC-TH-L-12V 1.05 V VLPC-TH-TRIG 70 mV Falling Edge Threshold Voltage to Trigger SR(7) Low-to-High Line Threshold Voltage on LPC Pin VIN=5.5 V VLPC-TH-H VLINE-H-5.5V www.onsemi.com 8 1.31 V 0.86 0.725 V 1.06 0.90 1.93 V V 1.23 1.84 V 2.02 V V FAN6290QF/FAN6290QH ELECTRICAL CHARACTERISTICS (CONTINUED) VIN=5 V, LPC=1.5 V, LPC width=2 µs at TJ= -40~125 C, FLPC=100 kHz, unless otherwise specified. Parameter Test Conditions Symbol Min Typ Max Unit VLINE-L-5.5V 1.75 1.83 1.91 V LPC Section (continued) High-to-Low Line Threshold Voltage on LPC Pin VIN=5.5 V Line Change Threshold Hysteresis VLINE-HYS-5.5V=VLINE-H-5.5V - VLINE-L-5.5V Low-to-High Line Threshold Voltage on LPC Pin VIN=9 V VLINE-H-9V 2.05 2.14 2.23 V High-to-Low Line Threshold Voltage on LPC Pin VIN=9 V VLINE-L-9V 1.96 2.04 2.12 V Line Change Threshold Hysteresis VLINE-HYS-9V=VLINE-H-9V - VLINE-L-9V VLINE-HYS-9V Low -to-High Line Threshold Voltage on LPC Pin VIN=12 V VLINE-H-12V 2.23 2.32 2.41 V High-to-Low Line Threshold Voltage on LPC Pin VIN=12 V VLINE-L-12V 2.14 2.22 2.30 V Line Change Threshold Hysteresis VLINE-HYS-12V=VLINE-H-12V - VLINE-L-12V Higher Clamp Voltage LPC Threshold Voltage to Disable SR Gate VIN=5 V. LPC=3 V↑ Switching VLINE-HYS-5.5V 0.1 V 0.1 VLINE-HYS-12V V 0.1 VLPC-CLAMP-H 5.4 VLPC-DIS VIN - 0.6 6.2 V 7.0 V V Enable VLPC-DIS Increasing VIN VEN-LPC-DIS 4.30 4.45 4.60 V Disable VLPC-DIS Decreasing VIN VDIS-LPC-DIS 4.10 4.25 4.40 V Line Change Debounce from Low-Line to High-Line tLPC-LH-debounce 15 23 31 ms Line Change Debounce from High-Line to Low-Line(7) tLPC-HL-debounce 15 µs Internal Timing Section Ratio between VLPC & VRES VIN=5.5 V, FLPC=50 kHz, KRES=0.15 Minimum LPC Time to Enable the SR Gate @ High-Line Minimum LPC Time to Enable the SR Gate @ Low-Line RatioLPC-RES 3.88 4.09 4.30 VLPC=3 V tLPC-EN-H 150 250 350 ns VLPC=1.5 V tLPC-EN-L 520 620 720 ns tMIN 0.35 0.50 0.65 µs Minimum Gate Limit On-time tgate-limit-min 0.6 1.0 1.4 µs ton-SR(n+1)- ton-SR(n) < tgate-limit tgate-limit Minimum Gate Width(7) Limitation between LPC Rising Edge to next LPC Rising Edge Max. Period Forced internal CT Reset Time tMAX-PERIOD (7) 500 28 tCT-RESET 40 ns 52 10 µs ns Reverse Current Mode Section Reverse Current Mode Entry Debounce Time VIN=5 V, VLPC=0 V Treverse-debounce Operating Current during Reverse Current Mode VIN=5 V, VLPC=0 V IOP.reverse DP Pin Over-Voltage Protection Excepting 2.75 V Supply Mode VDP-OVP 4.10 DN Pin Over-Voltage Protection Excepting 2.75 V Supply Mode VDN-OVP 350 500 650 ms 1.7 mA 4.35 4.60 V 4.10 4.35 4.60 V 1.5 3.0 4.5 ms Data Line Over-Voltage Protection DP/DN Pin OVP Debounce Time tDN-DP-OVP- VDN > VDN-SD Debounce 7. 8. Guaranteed by Design. Guaranteed at -5° ~ 85°C. www.onsemi.com 9 FAN6290QF/FAN6290QH TYPICAL CHARACTERISTICS Figure 3 Turn-On Threshold Voltage (VIN-ON) Figure 4 Turn-Off Threshold Voltage (VIN-OFF) vs. Temperature vs. Temperature Figure 5 Reference Voltage at 5 V (VCVR-5V) Figure 6 Reference Voltage at 9 V (VCVR-9V) vs. Temperature vs. Temperature Figure 7 Reference Voltage at 12 V (VCVR-12V) Figure 8 VIN Under-Voltage-Protection Enable, vs. Temperature 9 V (VIN-UVP-L-9V) vs. Temperature www.onsemi.com 10 FAN6290QF/FAN6290QH TYPICAL CHARACTERISTICS Figure 9 VIN Under-Voltage-Protection Enable, Figure 10 Minimum LPC Time to Enable the SR 12 V (VIN-UVP-L-12V) vs. Temperature Gate @ Low-Line (tLPC-EN-L) vs. Temperature Figure 11 Minimum LPC Time to Enable the SR Figure 12 Ratio between VLPC & VRES (RatioLPC-RES) Gate @ High-Line (tLPC-EN-H) vs. Temperature vs. Temperature Figure 13 Reference Voltage of Increment Step Figure 14 Reference Voltage of Decrement Step via Continuous Mode of QC3.0 Protocol via Continuous Mode of QC3.0 Protocol (VCVR-STEP-INC) vs. Temperature (VCVR-STEP-DEC) vs. Temperature www.onsemi.com 11 FAN6290QF/FAN6290QH APPLICATIONS INFORMATION Table 2. Device Line-up Table Output Voltage and its Nominal Output Load Series Name FAN6290QF FAN6290QH UVP Operation 3.6~6.0 V 6.2~9.0 V 9.2~12.0 V 3.0 A 2.0 A 1.5 A Pull-down SFB 2.0 A Reduce CC 3.0 A 3.0 A FAN6290QF and FAN6290QH implement different operation methods when the UVP is triggered. FAN6290QH reduces constant current level after triggering UVP. When a foldback level is performed on the system, resistive load is normally used. Since this reduced constant current is lower than the resistive load in the UVP, the output voltage is collapsed and foldback can be achieved. FAN6290QF pulls-down the SFB pin after UVP is triggered. And then, it enters Latch Mode Operation (Refer to Figure 22 and Figure 23). According to Latch Mode Operation, the output voltage is collapsed and foldback can be achieved. Protocols (Auto-detection) 2.75 V Supply Mode Some Apple products charge higher current when a dedicated charging port sources specific voltage on D+ and D- lines. FAN6290Q supports 2.75 V on D+ and Dlines, respectively. Apple products regard it as the attached charging port supports 2.4A, and it charges with maximum 2.4 A. Once FAN6290Q is enabled, D+ and D- supplies 2.75 V as default. Fairchild intelligent autodetection acknowledges BC1.2. As soon as BC1.2 gets started, FAN6290Q leaves 2.75 V supply mode immediately. After acknowledging QC3.0 or QC2.0, FAN6290Q does not return 2.75 V supply mode as long as a portable device is not detached. Quick Charge 3.0 (QC3.0) and Quick Charge 2.0 (QC2.0) Protocols As described on Table 3, FAN6290Q supports up to 12 V (Class A) through QC3.0 protocol. Table 3. Output Mode of FAN6290Q according to Quick Charge 3.0 VDP VDN HVDCP Output Mode 0.6 V 0V 5 V Mode (Backward compatible with QC2.0) 3.3 V 0.6 V 9 V Mode (Backward compatible with QC2.0) 0.6 V 0.6 V 12 V Mode (Backward compatible with QC2.0) 0.6 V 3.3 V Continuous Mode 3.3 V 3.3 V Reserve (Keep previous status) Within continuous mode, output-voltage can be increased or decreased with 200 mV step per an increment or decrement protocol, respectively. (Refer to Figure 16 and Figure 17 which are examples of increment and decrement). FAN6290Q can enter continuous mode from any of 5 V, 9 V and 12 V modes. However, it can return to 5 V mode from continuous mode. TGLITCH_CONT_CHANGE DP 3.3V 0.6V 4 high/low pulses = 0.2V*4 = 0.8V DN 3.3V 0.6V BUS 5.8V 5V Start of communication End of communication Figure 16 Example of Increment Timing Diagram (800 mV Increment from 5 V) Power on Reset DP Acknowledge QC3.0 or QC2.0 2.75V supply mode (DPà2.75V, DNà2.75V) TGLITCH_CONT_CHANGE 3.3V 0.6V ∆VDP > VDP_INC for tEXIT_MODE1 OR VDP < VDPH for tEXIT_MODE1 OR VDN < VDNH for tEXIT_MODE1 VDPL > VDP for tREC_MODE1 De tac 3 high/low pulses = 0.2V*3 = 0.6V VDP < VDPH for tDISCONNECT DN 3.3V h 0.6V BC1.2 mode (DP & DN short) HVDCP mode VDPL < VDP < VDPH for tBC1.2 BUS (DPàRDP, DNàRDN) 5.8V 5.2V Figure 15 Sequence of Auto-detection Start of communication End of communication Figure 17 Example of Decrement Timing Diagram (600 mV Decrement from 5.8 V) www.onsemi.com 12 FAN6290QF/FAN6290QH Communication Function Description Vo Constant Voltage Control VO VCVR RF 1 RF 2 RF 2 (1) Constant Current Control In order to support adaptive constant output current, FAN6290Q incorporates the constant-current control circuit internally. Output current is sensed via a currentsense resistor, RCS, which is connected between the CS pin and GND pin. The sensed signal is internally amplified, and this amplified voltage is connected to the non-inverting input of the internal operation amplifier. Likewise the constant voltage amplifier circuit, it also plays a role as a shunt regulator to regulate the constant output current. In order to compensate output current regulation, one capacitor and one resistor are connected between IREF and SFB pins typically as the Figure 18. The constant output current is decided by the equation (2). 30 mΩ is typically used for the sense resistor. GND CS AV-CCR FB IREF SFB VCCR I O _ CC RF1 VREF RF2 VCVR Figure 18 Constant Voltage and Constant Current Circuit Green Mode Operation In order to reduce power consumption at light-load conditions, FAN6290Q enters the green mode. When VCS which is the voltage between CS and GND pins is smaller than VCS-Green with longer duration than tGreen-ENDebounce, FAN6290Q enters the green mode. Typical output current entering the green mode is 170 mA. While it operates in the green mode, some internal blocks are disabled such as Synchronous Rectifier control block. Therefore, the operating current can be reduced to 1.2 mA (typ.). It leaves green mode when VCS is larger than VCS-Green with longer duration that tGreen-DIS-Debounce. Cable Drop Compensation To regulate the output voltage constantly at the end of a cable regardless of output current, the cable drop compensation function is implemented. The weight of compensation is internally fixed. The compensated output voltage is described in equation (3). VOUT -COMPENSATION VCOMR-CDC V CCR AV -CCR RCS - RCS The internal constant voltage control block regulates adaptive output voltages. Output voltage is sensed through an external resistor divider. The sensed output voltage is connected to the VREF which is the noninverting input terminal of the internal operational amplifier. The inverting input terminal is connected to the internal voltage reference (VCVR) which can be adjusted according to the requested output voltage via Quick Charge 3.0 protocol. The amplifier and an internal switch operate as a shunt regulator. The output of the shunt regulator is connected to the external opto-coupler, and this pin is named as Secondary Feedback (SFB). To compensate output voltage regulation being stable, one capacitor and one resistor are connected typically between the SFB and VREF pins as shown in Figure 18. The output voltage can be derived as shown in equation (1) and the recommended ratio of the resistor divider is 5. 1 RF1 RF 2 I OUT RF 2 2 (3) (2) Since CS pin senses small amounts of voltage, the sensing resistor should be positioned as close as possible to CS pin. Shown in Figure 18, an RC low pass filter can be added on the CS pin to be immunized from noise. Output OVP also implements cable drop compensation. Ratio of cable drop compensation for output OVP is different with cable drop compensation for constant voltage regulation shown in equation (4). VOVP VIN -OVP VCOMR-OVP www.onsemi.com 13 I OUT 2 (4) FAN6290QF/FAN6290QH UVP-L longer RCable-BUS VBUS @PCB End COUT RCS VIN IO USB GND USB XAVCCR CS VBUS @Cable End RCable-GND OVP Σ Cable Drop Compensation Mode Table 3. Under-Voltage Protection Threshold Level RF1 VREF Symbol VIN-UVP-L-9V RF2 Σ Mode VCVR than tD-VIN-UVP, the constant current level is reduced to 220 mA (typ.). FAN6290Q leaves UVP when VIN voltage is higher than VIN-UVP-H. While the UVP is operated, the synchronous rectifier control is disabled to avoid shoot-through. Some option versions enter the latch mode instead of reducing output current after triggering UVP. The UVP function is only enabled when QC2.0 protocol is accepted. For QC3.0 mode, UVP function is disabled. VIN-UVP-H-9V VIN-UVP-L-12V Figure 19 Cable-Drop Compensation Block VIN-UVP-H-12V VOUT Range UVP Level (Typ.) 5.50 V 9 V of QC2.0 6.00 V 8.00 V 12 V of QC2.0 8.50 V Output Over-Voltage Protection Figure 20 shows the output Over-Voltage Protection (OVP) block, which is adaptive according to output voltage status. Once the sensed output voltage via VIN pin is larger than VIN-OVP longer than tD-OVP, the internal OVP switch is enabled with latch mode. And the latch mode of FAN6290Q is reset when VIN < VLATCH-OFF. When FAN6290Q is compatible with FAN602, VS-UVP of FAN602 can be triggered after releasing latch mode of FAN6290Q. According to protection mode of VS-UVP of FAN602, VIN-OVP of FAN6290Q is operated as Extended Auto-Restart mode or latch mode. COUT VOUT Range OVP Level (Typ.) VIN-OVP-5 V 3.6 V ~ 5.0 V 6.0 V VIN-OVP-6 V 5.2 V ~ 6.0 V 8.4 V VIN-OVP-9 V 6.2 V ~ 9.0 V 10.8 V VIN-OVP-12 V 9.2 V ~ 12.0 V 14.4 V CS IO GND VIN XAVCCR IREF SFB Table 2. Over-Voltage Protection Threshold Level Symbol VBUS RCS UVP Protection VCCR Mode Figure 21 Output Under-Voltage Protection Block D+/D- Data Line Over-Voltage Protection COUT VBUS RCS VIN OVP D OVP Latch-OFF Mode Q RST VIN-OVP Figure 20 Output Over-Voltage Protection Block Even though severe fault is occurred between BUS and Ground, monitoring data line status also can protect USB fault condition indirectly because data lines (D+/D-) may be polluted at the same time with BUS line pollution. Therefore, FAN6290Q implements data line OverVoltage-Protection. It can protect when the BUS and D+/D- are short-circuited with small impedance. When voltage on D+ line and/or D- line is higher than VDP-OVP and/or VDP-OVP longer than VDN-DP-OVP-Debounce, OverVoltage Protection is triggered. After detecting fault condition, FAN6290Q enters latch mode. When FAN6290Q releases the latch mode, FAN602 enters VSUVP. Latch Mode Operation Output Under-Voltage Protection In order to support foldback level of each output mode, the output Under-Voltage Protection (UVP) function is incorporated. The UVP function can reduce power delivery during output soft-short fault. Figure 21 shows its implementation. Once VIN voltage is lower than VIN- FAN6290Q implements latch mode operation to deliver fault conditions which are detected on secondary-side to primary-side. When one fault condition is triggered among cable fault Protections, over-voltage protection and under-voltage protection, SFB is started to be www.onsemi.com 14 FAN6290QF/FAN6290QH pulled-down with latch mode. This latch mode is released when VIN voltage is lower than VLatch-off which is lower than VIN-OFF. As shown on Figure 23, after the Latch Mode is released, the primary-side controller leaves burst mode and starts switching again. Since the VLatch-off is much lower than output voltage level which triggers VS-UVP of the primary-side controller, after releasing latch mode, the primary-side controller triggers VS-UVP. Therefore, throughout implementing the latch mode operation, the primary-side controller can trigger VS-UVP, and the system can enter latch mode. When not only VIN-OVP and cable fault protection are triggered, but also VIN voltage is lower than VIN-OFF, the latch mode is enabled, either. The latch mode operation for VIN-OFF avoids that system becomes open-loop when VIN < VINOFF. CO1 CO2 VBUS RCS Reset Circuit on VREF and IREF VREF and IREF pins are connected to VIN through compensation circuits. When CV and CC amplifiers are not enabled, VREF and IREF pin voltages are also increased according to increased VIN voltage (dot lines on Figure 24). The voltages on VREF and IREF are higher than target threshold levels. The Reset circuit on VREF and IREF are implemented as each pin is connected to ground through internal switches. The IREF pin is additionally reset during t Start-Dis-CC. Reset circuit pulls-down current, and these currents (IRESET_VREF and IRESET_IREF) can flow through compensation circuits. If current flowing through the opto-coupler is large enough, the primary controller enters burst mode and triggers VS-UVP-H, because of this startup may fail. Rbias helps to decrease current flowing through the opto-coupler, to avoid startup failure. The Rbias design depends on compensation design, typically 2~6 kΩ is recommended. VIN Primary FB VIN-ON tStart-Dis-CC Enable Reset circuit VIN time Cable Faults SFB Q D Without reset circuit VREF VIN-OVP VIN-UVP VIN-OFF VCVR-5V RST time Without reset circuit IREF VIREF@CC VLatch-off time Figure 24 Reset Circuit Operation Figure 22 Conceptual Latch Mode Block VOUT VSFB VBUS VOUT @VS-UVP - RCS VLatch-off GND CS FB AV-CCR VDD.pri Latch Mode Rbias IREF VFB IDS VBURST SFB VCCR Fault RF1 Reset VREF VS-UVP RF2 Figure 23 Waveform of Latch Mode Operation VCVR IRESET_IREF Figure 25 Reset Circuit and Rbias www.onsemi.com 15 IRESET_VREF FAN6290QF/FAN6290QH PCB Layout Guidelines Printed Circuit Board (PCB) layout and design are very important for switching mode power supplies where the voltage and current change with high speed. Good PCB layout minimizes Electro-Magnetic Interference (EMI) and prevents excessive noise from surge or Electro-Static Discharging (ESD). As shown in Figure 27 COUT1 and COUT2 are the output capacitors; Q2 is the secondary-side SR MOSFET. The following guidelines are recommended for layout designs. The main power flows through Q2, COUT1, COUT2 and RCS. This power path should be separated with signal grounds which are connected to FAN6290Q. In addition, it is recommended that power ground is directly connected to Y-cap. Refer to Figure 26. COUT1 COUT2 VO RSENSE CS GND Good connection COUT1 COUT2 VO RSENSE Rpattern Rpattern CS GND Bad connection; CS & GND should be closed to Rcs The sensed voltage via RCS is very small value. In order to avoid offset voltage or avoid inducing switching noise on the sensed voltage, RCS should be connected between ground of COUT2 and power ground. And RCS should be positioned as close as possible to CS pin and GND pin. Refer to Figure 27. COUT1 COUT2 VO RSENSE CS To avoid switching noise interference to Synchronous Rectifier operation, RLPC-H and RLPC-L should be close to FAN6290Q. And power path should be apart from LPC path. GND Bad connection; Rcs should not be connected before Cout2 COUT1 COUT2 VO VBUS SR MOSFET RSENSE COUT RSENSE CS GND Wrong connection; Rcs must not connected between Cout1 and Cout2 Signal GND Power GND CS GND GATE LPC Signal GND VIN FAN6290Q Figure 27 Examples of Sensing Resistor Connection VREF DP DP IREF DN DN SFB Figure 26 Power and Signal Ground on the Secondary-Side www.onsemi.com 16 FAN6290QF/FAN6290QH ORDERING INFORMATION Part Number Operating Temperature Range Package Packing Method FAN6290QFMX -40C to +125C 10-Lead, SOP Tape & Reel FAN6290QHMX -40C to +125C 10-Lead, SOP Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D www.onsemi.com 17 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. 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