M29DW323DT M29DW323DB 32 Mbit (4Mb x8 or 2Mb x16, Dual Bank 8:24, Boot Block) 3V Supply Flash Memory FEATURES SUMMARY ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ SUPPLY VOLTAGE – VCC = 2.7V to 3.6V for Program, Erase and Read – VPP =12V for Fast Program (optional) ACCESS TIME: 70ns PROGRAMMING TIME – 10µs per Byte/Word typical – Double Word/ Quadruple Byte Program MEMORY BLOCKS – Dual Bank Memory Array: 8Mbit+24Mbit – Parameter Blocks (Top or Bottom Location) DUAL OPERATIONS – Read in one bank while Program or Erase in other ERASE SUSPEND and RESUME MODES – Read and Program another Block during Erase Suspend UNLOCK BYPASS PROGRAM COMMAND – Faster Production/Batch Programming VPP/WP PIN for FAST PROGRAM and WRITE PROTECT TEMPORARY BLOCK UNPROTECTION MODE COMMON FLASH INTERFACE – 64 bit Security Code EXTENDED MEMORY BLOCK – Extra block used as security block or to store additional information LOW POWER CONSUMPTION – Standby and Automatic Standby 100,000 PROGRAM/ERASE CYCLES per BLOCK ELECTRONIC SIGNATURE – Manufacturer Code: 0020h – Top Device Code M29DW323DT: 225Eh – Bottom Device Code M29DW323DB: 225Fh March 2008 Figure 1. Packages TSOP48 (N) 12 x 20mm FBGA TFBGA48 (ZE) 6 x 8mm 1/51 M29DW323DT, M29DW323DB TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 TABLE OF CONTENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Table 1. Figure 3. Figure 4. Table 2. Figure 5. Figure 6. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 TFBGA48 Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Block Addresses (x8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Block Addresses (x16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Address Inputs (A0-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Data Inputs/Outputs (DQ8-DQ14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Data Input/Output or Address Input (DQ15A–1).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 VPP/Write Protect (VPP/WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Reset/Block Temporary Unprotect (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Byte/Word Organization Select (BYTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 VCC Supply Voltage (2.7V to 3.6V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Block Protect and Chip Unprotect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 3. Bus Operations, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 4. Bus Operations, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Read/Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Auto Select Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2/51 M29DW323DT, M29DW323DB Read CFI Query Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Fast Program Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Quadruple Byte Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Double Word Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Unlock Bypass Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Unlock Bypass Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Unlock Bypass Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Chip Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Enter Extended Block Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Exit Extended Block Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Block Protect and Chip Unprotect Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 5. Commands, 16-bit mode, BYTE = VIH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 6. Commands, 8-bit mode, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 7. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 19 STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 8. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 7. Data Polling Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 8. Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 9. Dual Operations Allowed In the Other Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 10. Dual Operations Allowed In Same Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 11. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 12. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 9. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 10.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 13. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 14. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 11.Read Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 15. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 12.Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 16. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3/51 M29DW323DT, M29DW323DB Figure 13.Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 17. Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 14.Toggle and Alternative Toggle Bits Mechanism, Chip Enable Controlled . . . . . . . . . . . . 29 Figure 15.Toggle and Alternative Toggle Bits Mechanism, Output Enable Controlled . . . . . . . . . . 29 Table 18. Toggle and Alternative Toggle Bits AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 16.Reset/Block Temporary Unprotect AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 19. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 17.Accelerated Program Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 18.TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Bottom View Package Outline . . 31 Table 20. TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Package Mechanical Data . . . . . 31 Figure 19.TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Bottom View Package Outline. . . . . . 32 Table 21. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Package Mechanical Data. . . . . . . . . 32 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 22. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 APPENDIX A.BLOCK ADDRESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 23. Top Boot Block Addresses, M29DW323DT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 24. Bottom Boot Block Addresses, M29DW323DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 APPENDIX B.COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 25. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 26. CFI Query Identification String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 27. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 28. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 29. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 30. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 APPENDIX C.EXTENDED MEMORY BLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Factory Locked Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Customer Lockable Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 31. Extended Block Address and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 APPENDIX D.BLOCK PROTECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 32. Programmer Technique Bus Operations, BYTE = VIH or VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 20.Programmer Equipment Group Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 21.Programmer Equipment Chip Unprotect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 22.In-System Equipment Group Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 23.In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4/51 M29DW323DT, M29DW323DB Table 33. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5/51 M29DW323DT, M29DW323DB SUMMARY DESCRIPTION The M29DW323D is a 32 Mbit (4Mb x8 or 2Mb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6V) supply. On power-up the memory defaults to its Read mode. The device features an asymmetrical block architecture. The M29DW323D has an array of 8 parameter and 63 main blocks and is divided into two Banks, A and B, providing Dual Bank operations. While programming or erasing in Bank A, read operations are possible in Bank B and vice versa. Only one bank at a time is allowed to be in program or erase mode. The bank architecture is summarized in Table 2. M29DW323DT locates the Parameter Blocks at the top of the memory address space while the M29DW323DB locates the Parameter Blocks starting from the bottom. M29DW323D has an extra 32 KWord (x16 mode) or 64 KByte (x8 mode) block, the Extended Block, that can be accessed using a dedicated command. The Extended Block can be protected and so is useful for storing security information. How- ever the protection is irreversible, once protected the protection cannot be undone. Each block can be erased independently so it is possible to preserve valid data while old data is erased. The blocks can be protected to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic. The memory is offered in TSOP48 (12x20mm), and TFBGA48 (6x8mm, 0.8mm pitch) packages. The memory is supplied with all the bits erased (set to ’1’). Figure 2. Logic Diagram Table 1. Signal Names VCC VPP/WP 21 Address Inputs DQ0-DQ7 Data Inputs/Outputs DQ8-DQ14 Data Inputs/Outputs DQ15A–1 Data Input/Output or Address Input E Chip Enable G Output Enable W Write Enable RP Reset/Block Temporary Unprotect RB Ready/Busy Output BYTE Byte/Word Organization Select VCC Supply Voltage VPP/WP VPP/Write Protect VSS Ground NC Not Connected Internally 15 A0-A20 DQ0-DQ14 DQ15A–1 W E A0-A20 M29DW323DT M29DW323DB G BYTE RB RP VSS AI05523 6/51 M29DW323DT, M29DW323DB Figure 3. TSOP Connections A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 W RP NC VPP/WP RB A18 A17 A7 A6 A5 A4 A3 A2 A1 1 48 M29DW323DT M29DW323DB 12 13 37 36 24 25 A16 BYTE VSS DQ15A–1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS E A0 AI05524 7/51 M29DW323DT, M29DW323DB Figure 4. TFBGA48 Connections (Top view through package) 1 2 3 4 5 6 A A3 A7 RB W A9 A13 B A4 A17 VPP/WP RP A8 A12 C A2 A6 A18 NC A10 A14 D A1 A5 A20 A19 A11 A15 E A0 DQ0 DQ2 DQ5 DQ7 A16 F E DQ8 DQ10 DQ12 DQ14 BYTE G G DQ9 DQ11 VCC DQ13 DQ15 A–1 H VSS DQ1 DQ3 DQ4 DQ6 VSS AI08084 Table 2. Bank Architecture Parameter Blocks 8/51 Main Blocks Bank Bank Size No. of Blocks Block Size No. of Blocks Block Size A 8 Mbit 8 8KByte/ 4 KWord 15 64KByte/ 32 KWord B 24 Mbit - 48 64KByte/ 32 KWord M29DW323DT, M29DW323DB Figure 5. Block Addresses (x8) Top Boot Block (x8) Address lines A20-A0, DQ15A-1 000000h 00FFFFh Bottom Boot Block (x8) Address lines A20-A0, DQ15A-1 000000h 64 KByte or 32 KWord 001FFFh 8 KByte or 4 KWord Total of 48 Main Blocks Bank B 2F0000h 2FFFFFh 300000h 30FFFFh Total of 8 Parameter Blocks (1) 00E000h 64 KByte or 32 KWord Bank A 64 KByte or 32 KWord 00FFFFh 010000h 01FFFFh 8 KByte or 4 KWord 64 KByte or 32 KWord Total of 15 Main Blocks 3E0000h Bank A 3EFFFFh 3F0000h 3F1FFFh 0F0000h 64 KByte or 32 KWord 0FFFFFh 100000h 8 KByte or 4 KWord 10FFFFh Total of 8 Parameter Blocks (1) 3FE000h 3FFFFFh Total of 15 Main Blocks 64 KByte or 32 KWord 64 KByte or 32 KWord Total of 48 Main Blocks Bank B 8 KByte or 4 KWord 3F0000h 3FFFFFh Note 1. Used as Extended Block Addresses in Extended Block mode. 64 KByte or 32 KWord AI05556 Note: Also see APPENDIX A., Table 23. and Table 24. for a full listing of the Block Addresses. 9/51 M29DW323DT, M29DW323DB Figure 6. Block Addresses (x16) Top Boot Block (x16) Address lines A20-A0 000000h 007FFFh Bottom Boot Block (x16) Address lines A20-A0 000000h 64 KByte or 32 KWord 000FFFh 8 KByte or 4 KWord Total of 48 Main Blocks Bank B 178000h 17FFFFh 180000h 187FFFh Total of 8 Parameter Blocks (1) 007000h 64 KByte or 32 KWord Bank A 64 KByte or 32 KWord 007FFFh 008000h 00FFFFh 8 KByte or 4 KWord 64 KByte or 32 KWord Total of 15 Main Blocks 1F0000h Bank A 1F7FFFh 1F8000h 1F8FFFh 078000h 64 KByte or 32 KWord 07FFFFh 080000h 8 KByte or 4 KWord 087FFFh Total of 8 Parameter Blocks (1) 1FF000h 1FFFFFh Total of 15 Main Blocks 64 KByte or 32 KWord Total of 48 Main Blocks Bank B 8 KByte or 4 KWord 1F8000h 1FFFFFh Note 1. Used as Extended Block Addresses in Extended Block mode. Note: Also see APPENDIX A., Table 23. and Table 24. for a full listing of the Block Addresses. 10/51 64 KByte or 32 KWord 64 KByte or 32 KWord AI05555 M29DW323DT, M29DW323DB SIGNAL DESCRIPTIONS See Figure 2., Logic Diagram, and Table 1., Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A20). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the Program/Erase Controller. Data Inputs/Outputs (DQ0-DQ7). The Data I/O outputs the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the Program/Erase Controller. Data Inputs/Outputs (DQ8-DQ14). The Data I/O outputs the data stored at the selected address during a Bus Read operation when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are high impedance. During Bus Write operations the Command Register does not use these bits. When reading the Status Register these bits should be ignored. Data Input/Output or Address Input (DQ15A–1). When BYTE is High, VIH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14). When BYTE is Low, VIL, this pin behaves as an address pin; DQ15A–1 Low will select the LSB of the addressed Word, DQ15A–1 High will select the MSB. Throughout the text consider references to the Data Input/Output to include this pin when BYTE is High and references to the Address Inputs to include this pin when BYTE is Low except when stated explicitly otherwise. Chip Enable (E). The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is High, VIH, all other pins are ignored. Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory. Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memory’s Command Interface. VPP/Write VPP/Write Protect (VPP/WP). The Protect pin provides two functions. The VPP function allows the memory to use an external high voltage power supply to reduce the time required for Program operations. This is achieved by bypassing the unlock cycles and/or using the Double Word or Quadruple Byte Program commands. The Write Protect function provides a hardware method of protecting the two outermost boot blocks. When VPP/Write Protect is Low, VIL, the memory protects the two outermost boot blocks; Program and Erase operations in these blocks are ignored while VPP/Write Protect is Low, even when RP is at VID. When VPP/Write Protect is High, VIH, the memory reverts to the previous protection status of the two outermost boot blocks. Program and Erase operations can now modify the data in these blocks unless the blocks are protected using Block Protection. When VPP/Write Protect is raised to VPP the memory automatically enters the Unlock Bypass mode. When VPP/Write Protect returns to VIH or VIL normal operation resumes. During Unlock Bypass Program operations the memory draws IPP from the pin to supply the programming circuits. See the description of the Unlock Bypass command in the Command Interface section. The transitions from VIH to VPP and from VPP to VIH must be slower than tVHVPP, see Figure 17. Never raise VPP/Write Protect to VPP from any mode except Read mode, otherwise the memory may be left in an indeterminate state. The VPP/Write Protect pin must not be left floating or unconnected or the device may become unreliable. A 0.1µF capacitor should be connected between the VPP/Write Protect pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during Unlock Bypass Program, IPP. Reset/Block Temporary Unprotect (RP). The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all Blocks that have been protected. Note that if VPP/WP is at VIL, then the two outermost boot blocks will remain protected even if RP is at VID. A Hardware Reset is achieved by holding Reset/ Block Temporary Unprotect Low, VIL, for at least tPLPX. After Reset/Block Temporary Unprotect goes High, VIH, the memory will be ready for Bus Read and Bus Write operations after tPHEL or tRHEL, whichever occurs last. See the Ready/Busy Output section, Table 19. and Figure 16., Reset/ Block Temporary Unprotect AC Waveforms, for more details. Holding RP at VID will temporarily unprotect the protected Blocks in the memory. Program and Erase operations on all blocks will be possible. The transition from VIH to VID must be slower than tPHPHH. Ready/Busy Output (RB). The Ready/Busy pin is an open-drain output that can be used to identify when the device is performing a Program or Erase 11/51 M29DW323DT, M29DW323DB operation. During Program or Erase operations Ready/Busy is Low, VOL. Ready/Busy is high-impedance during Read mode, Auto Select mode and Erase Suspend mode. After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy becomes high-impedance. See Table 19. and Figure 16., Reset/Block Temporary Unprotect AC Waveforms. The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy. Byte/Word Organization Select (BYTE). The Byte/Word Organization Select pin is used to switch between the x8 and x16 Bus modes of the memory. When Byte/Word Organization Select is Low, VIL, the memory is in x8 mode, when it is High, VIH, the memory is in x16 mode. 12/51 VCC Supply Voltage (2.7V to 3.6V). VCC provides the power supply for all operations (Read, Program and Erase). The Command Interface is disabled when the VCC Supply Voltage is less than the Lockout Voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. A 0.1µF capacitor should be connected between the VCC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during Program and Erase operations, ICC3. VSS Ground. VSS is the reference for all voltage measurements. The device features two VSS pins which must be both connected to the system ground. M29DW323DT, M29DW323DB BUS OPERATIONS There are five standard bus operations that control the device. These are Bus Read, Bus Write, Output Disable, Standby and Automatic Standby. The Dual Bank architecture of the M29DW323 allows read/write operations in Bank A, while read operations are being executed in Bank B or vice versa. Write operations are only allowed in one bank at a time. See Tables 3 and 4, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations. Bus Read. Bus Read operations read from the memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address Inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 11., Read Mode AC Waveforms, and Table 15., Read AC Characteristics, for details of when the output becomes valid. Bus Write. Bus Write operations write to the Command Interface. A valid Bus Write operation begins by setting the desired address on the Address Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH, during the whole Bus Write operation. See Figures 12 and 13, Write AC Waveforms, and Tables 16 and 17, Write AC Characteristics, for details of the timing requirements. Output Disable. The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH. Standby. When Chip Enable is High, VIH, the memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high-imped- ance state. To reduce the Supply Current to the Standby Supply Current, ICC2, Chip Enable should be held within VCC ± 0.2V. For the Standby current level see Table 14., DC Characteristics. During program or erase operations the memory will continue to use the Program/Erase Supply Current, ICC3, for Program or Erase operations until the operation completes. Automatic Standby. If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 300ns or more the memory enters Automatic Standby where the internal Supply Current is reduced to the Standby Supply Current, ICC2. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress. Special Bus Operations Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block Protection. These bus operations are intended for use by programming equipment and are not usually used in applications. They require VID to be applied to some pins. Electronic Signature. The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in Tables 3 and 4, Bus Operations. Block Protect and Chip Unprotect. Groups of blocks can be protected against accidental Program or Erase. The Protection Groups are shown in APPENDIX A., Tables 23 and 24, Block Addresses. The whole chip can be unprotected to allow the data inside the blocks to be changed. The VPP/Write Protect pin can be used to protect the two outermost boot blocks. When VPP/Write Protect is at VIL the two outermost boot blocks are protected and remain protected regardless of the Block Protection Status or the Reset/Block Temporary Unprotect pin status. Block Protect and Chip Unprotect operations are described in APPENDIX D. 13/51 M29DW323DT, M29DW323DB Table 3. Bus Operations, BYTE = VIL Operation E G Address Inputs DQ15A–1, A0-A20 W Data Inputs/Outputs DQ14-DQ8 DQ7-DQ0 Bus Read VIL VIL VIH Cell Address Hi-Z Data Output Bus Write VIL VIH VIL Command Address Hi-Z Data Input X VIH VIH X Hi-Z Hi-Z Standby VIH X X X Hi-Z Hi-Z Read Manufacturer Code VIL VIL VIH A0 = VIL, A1 = VIL, A9 = VID, Others VIL or VIH Hi-Z 20h Read Device Code VIL VIL VIH A0 = VIH, A1 = VIL, A9 = VID, Others VIL or VIH Hi-Z 5Eh (M29DW323DT) 5Fh (M29DW323DB) Extended Memory Block Verify Code VIL VIL VIH A0 = VIH, A1 = VIH, A6 = VIL, A9 = VID, Others VIL or VIH Hi-Z 81h (factory locked) 01h (not factory locked) Output Disable Note: X = VIL or VIH. Table 4. Bus Operations, BYTE = VIH Operation E G W Address Inputs A0-A20 Bus Read VIL VIL VIH Cell Address Bus Write VIL VIH VIL Command Address Data Inputs/Outputs DQ15A–1, DQ14-DQ0 Data Output Data Input X VIH VIH X Hi-Z Standby VIH X X X Hi-Z Read Manufacturer Code VIL VIL VIH A0 = VIL, A1 = VIL, A9 = VID, Others VIL or VIH 0020h Read Device Code VIL VIL VIH A0 = VIH, A1 = VIL, A9 = VID, Others VIL or VIH 225Eh (M29DW323DT) 225Fh (M29DW323DB) Extended Memory Block Verify Code VIL VIL VIH A0 = VIH, A1 = VIH, A6 = VIL, A9 = VID, Others VIL or VIH 81h (factory locked) 01h (not factory locked) Output Disable Note: X = VIL or VIH. 14/51 M29DW323DT, M29DW323DB COMMAND INTERFACE All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus Write operations will result in the memory returning to Read mode. The long command sequences are imposed to maximize data security. The address used for the commands changes depending on whether the memory is in 16-bit or 8bit mode. See either Table 5, or 6, depending on the configuration that is being used, for a summary of the commands. Read/Reset Command The Read/Reset command returns the memory to its Read mode. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command. The Read/Reset command can be issued, between Bus Write cycles before the start of a program or erase operation, to return the device to read mode. If the Read/Reset command is issued during the time-out of a Block erase operation then the memory will take up to 10µs to abort. During the abort period no valid data can be read from the memory. The Read/Reset command will not abort an Erase operation when issued while in Erase Suspend. Auto Select Command The Auto Select command is used to read the Manufacturer Code, the Device Code, the Block Protection Status and the Extended Memory Block Verify Code. It can be addressed to either Bank. Three consecutive Bus Write operations are required to issue the Auto Select command. The final Write cycle must be addressed to one of the Banks. Once the Auto Select command is issued Bus Read operations to the Bank where the command was issued output the Auto Select data. Bus Read operations to the other Bank will output the contents of the memory array. The memory remains in Auto Select mode until a Read/Reset or CFI Query command is issued. In Auto Select mode the Manufacturer Code can be read using a Bus Read operation with A0 = VIL and A1 = VIL and A19-A20 = Bank Address. The other address bits may be set to either VIL or VIH. The Device Code can be read using a Bus Read operation with A0 = VIH and A1 = VIL and A19-A20 = Bank Address. The other address bits may be set to either VIL or VIH. The Block Protection Status of each block can be read using a Bus Read operation with A0 = VIL, A1 = VIH, A19-A20 = Bank Address and A12-A18 specifying the address of the block inside the Bank. The other address bits may be set to either VIL or VIH. If the addressed block is protected then 01h is output on Data Inputs/Outputs DQ0-DQ7, otherwise 00h is output. Read CFI Query Command The Read CFI Query Command is used to read data from the Common Flash Interface (CFI) Memory Area. This command is valid when the device is in the Read Array mode, or when the device is in Auto Select mode. One Bus Write cycle is required to issue the Read CFI Query Command. Once the command is issued subsequent Bus Read operations read from the Common Flash Interface Memory Area. The Read/Reset command must be issued to return the device to the previous mode (the Read Array mode or Auto Select mode). A second Read/ Reset command would be needed if the device is to be put in the Read Array mode from Auto Select mode. See APPENDIX B., Tables 25, 26, 27, 28, 29 and 30 for details on the information contained in the Common Flash Interface (CFI) memory area. Program Command The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data, and starts the Program/Erase Controller. If the address falls in a protected block then the Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given. During the program operation the memory will ignore all commands. It is not possible to issue any command to abort or pause the operation. After programming has started, Bus Read operations in the Bank being programmed output the Status Register content, while Bus Read operations to the other Bank output the contents of the memory array. See the section on the Status Register for more details. Typical program times are given in Table 7. After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs Bus Read operations to the Bank where the command was issued will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. Note that the Program command cannot change a bit set at ’0’ back to ’1’. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’. 15/51 M29DW323DT, M29DW323DB Fast Program Commands There are two Fast Program commands available to improve the programming throughput, by writing several adjacent words or bytes in parallel. The Quadruple Byte Program command is available for x8 operations, while the Double Word Program command is available for x16 operations. Only one bank can be programmed at any one time. The other bank must be in Read mode or Erase Suspend. Fast Program commands should not be attempted when VPP/WP is not at VPP. Care must be taken because applying a 12V VPP voltage to the VPP/ WP pin will temporarily unprotect any protected block. After programming has started, Bus Read operations in the Bank being programmed output the Status Register content, while Bus Read operations to the other Bank output the contents of the memory array. After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs Bus Read operations to the Bank where the command was issued will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. Note that the Fast Program commands cannot change a bit set at ’0’ back to ’1’. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’. Typical Program times are given in Table 7., Program, Erase Times and Program, Erase Endurance Cycles. Quadruple Byte Program Command. The Quadruple Byte Program command is used to write a page of four adjacent Bytes in parallel. The four bytes must differ only for addresses A0, DQ15A-1. Five bus write cycles are necessary to issue the Quadruple Byte Program command. ■ The first bus cycle sets up the Quadruple Byte Program Command. ■ The second bus cycle latches the Address and the Data of the first byte to be written. ■ The third bus cycle latches the Address and the Data of the second byte to be written. ■ The fourth bus cycle latches the Address and the Data of the third byte to be written. ■ The fifth bus cycle latches the Address and the Data of the fourth byte to be written and starts the Program/Erase Controller. Double Word Program Command. The Double Word Program command is used to write a page of two adjacent words in parallel. The two words must differ only for the address A0. 16/51 Three bus write cycles are necessary to issue the Double Word Program command. ■ The first bus cycle sets up the Double Word Program Command. ■ The second bus cycle latches the Address and the Data of the first word to be written. ■ The third bus cycle latches the Address and the Data of the second word to be written and starts the Program/Erase Controller. Unlock Bypass Command The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memory faster than with the standard program commands. When the cycle time to the device is long, considerable time saving can be made by using these commands. Three Bus Write operations are required to issue the Unlock Bypass command. Once the Unlock Bypass command has been issued the bank enters Unlock Bypass mode. When in Unlock Bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. The Unlock Bypass Program command can be issued to program addresses within the bank, and the Unlock Bypass Reset command to return the bank to Read mode. In Unlock Bypass mode the memory can be read as if in Read mode. When VPP is applied to the VPP/Write Protect pin the memory automatically enters the Unlock Bypass mode and the Unlock Bypass Program command can be issued immediately. Care must be taken because applying a 12V VPP voltage to the VPP/WP pin will temporarily unprotect any protected block. Unlock Bypass Program Command The Unlock Bypass Program command can be used to program one address in the memory array at a time. The command requires two Bus Write operations, the final write operation latches the address and data, and starts the Program/Erase Controller. The Program operation using the Unlock Bypass Program command behaves identically to the Program operation using the Program command. The operation cannot be aborted, a Bus Read operation to the Bank where the command was issued outputs the Status Register. See the Program command for details on the behavior. Unlock Bypass Reset Command The Unlock Bypass Reset command can be used to return to Read/Reset mode from Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass Reset command. Read/ Reset command does not exit from Unlock Bypass Mode. M29DW323DT, M29DW323DB Chip Erase Command The Chip Erase command can be used to erase the entire chip. Six Bus Write operations are required to issue the Chip Erase Command and start the Program/Erase Controller. If any blocks are protected then these are ignored and all the other blocks are erased. If all of the blocks are protected the Chip Erase operation appears to start but will terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the erase operation the memory will ignore all commands, including the Erase Suspend command. It is not possible to issue any command to abort the operation. Typical chip erase times are given in Table 7. All Bus Read operations during the Chip Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Chip Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode. The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All previous data is lost. Block Erase Command The Block Erase command can be used to erase a list of one or more blocks in a Bank. It sets all of the bits in the unprotected selected blocks to ’1’. All previous data in the selected blocks is lost. Six Bus Write operations are required to select the first block in the list. Each additional block in the list can be selected by repeating the sixth Bus Write operation using the address of the additional block. All blocks must belong to the same Bank; if a block belonging to the other Bank is given it will not be erased. The Block Erase operation starts the Program/Erase Controller after a time-out period of 50µs after the last Bus Write operation. Once the Program/Erase Controller starts it is not possible to select any more blocks. Each additional block must therefore be selected within 50µs of the last block. The 50µs timer restarts when an additional block is selected. After the sixth Bus Write operation a Bus Read operation within the same Bank will output the Status Register. See the Status Register section for details on how to identify if the Program/Erase Controller has started the Block Erase operation. If any selected blocks are protected then these are ignored and all the other selected blocks are erased. If all of the selected blocks are protected the Block Erase operation appears to start but will terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the Block Erase operation the memory will ignore all commands except the Erase Suspend command and the Read/Reset command which is only accepted during the 50µs time-out period. Typical block erase times are given in Table 7. After the Erase operation has started all Bus Read operations to the Bank being erased will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Block Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs Bus Read operations to the Bank where the command was issued will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. Erase Suspend Command The Erase Suspend Command may be used to temporarily suspend a Block Erase operation and return the memory to Read mode. The command requires one Bus Write operation. The Program/Erase Controller will suspend within the Erase Suspend Latency time of the Erase Suspend Command being issued. Once the Program/ Erase Controller has stopped the memory will be set to Read mode and the Erase will be suspended. If the Erase Suspend command is issued during the period when the memory is waiting for an additional block (before the Program/Erase Controller starts) then the Erase is suspended immediately and will start immediately when the Erase Resume Command is issued. It is not possible to select any further blocks to erase after the Erase Resume. During Erase Suspend it is possible to Read and Program cells in blocks that are not being erased; both Read and Program operations behave as normal on these blocks. If any attempt is made to program in a protected block or in the suspended block then the Program command is ignored and the data remains unchanged. The Status Register is not read and no error condition is given. Reading from blocks that are being erased will output the Status Register. It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypass commands during an Erase Suspend. The Read/Reset command must be issued to return the device to Read Array mode before the Resume command will be accepted. During Erase Suspend a Bus Read operation to the Extended Block will output the Extended Block data. 17/51 M29DW323DT, M29DW323DB Erase Resume Command The Erase Resume command must be used to restart the Program/Erase Controller after an Erase Suspend. The device must be in Read Array mode before the Resume command will be accepted. An erase can be suspended and resumed more than once. Enter Extended Block Command The M29DW323D has an extra 64KByte block (Extended Block) that can only be accessed using the Enter Extended Block command. Three Bus write cycles are required to issue the Extended Block command. Once the command has been issued the device enters Extended Block mode where all Bus Read or Program operations to the Boot Block addresses access the Extended Block. The Extended Block (with the same address as the boot block) cannot be erased, and can be treated as one-time programmable (OTP) memory. In Extended Block mode the Boot Blocks are not accessible. In Extended Block mode dual operations are possible, with the Extended Block mapped in Bank A. When in Extended Block mode, Erase Commands in Bank A are not allowed. To exit from the Extended Block mode the Exit Extended Block command must be issued. The Extended Block can be protected, however once protected the protection cannot be undone. Exit Extended Block Command The Exit Extended Block command is used to exit from the Extended Block mode and return the device to Read mode. Four Bus Write operations are required to issue the command. Block Protect and Chip Unprotect Commands Groups of blocks can be protected against accidental Program or Erase. The Protection Groups are shown in APPENDIX A., Tables 23 and 24, Block Addresses. The whole chip can be unprotected to allow the data inside the blocks to be changed. Block Protect and Chip Unprotect operations are described in APPENDIX D. Command Length Table 5. Commands, 16-bit mode, BYTE = VIH Bus Write Operations 1st 2nd Addr Data 1 X F0 3 555 AA 3rd Addr Data 2AA 4th Addr Data 55 X F0 90 5th Addr Data PA PD 6th Addr Data Addr Data Read/Reset Auto Select 3 555 AA 2AA 55 (BKA) 555 Program 4 555 AA 2AA 55 555 A0 Double Word Program 3 555 50 PA0 PD0 PA1 PD1 Unlock Bypass 3 555 AA 2AA 55 555 20 Unlock Bypass Program 2 X A0 PA PD Unlock Bypass Reset 2 X 90 X 00 Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10 Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30 Erase Suspend 1 BKA B0 Erase Resume 1 BKA 30 X 00 Read CFI Query 1 55 98 Enter Extended Block 3 555 AA 2AA 55 555 88 Exit Extended Block 4 555 AA 2AA 55 555 90 Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block, BKA Bank Address. All values in the table are in hexadecimal. The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ14 and DQ15 are Don’t Care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH. 18/51 M29DW323DT, M29DW323DB Command Length Table 6. Commands, 8-bit mode, BYTE = VIL Bus Write Operations 1st Add 2nd Data 1 X F0 3 AAA AA 3rd Add Data 555 4th Add Data 55 X F0 55 (BKA) AAA 90 Add 5th Data 6th Add Data PA3 PD3 Add Data Read/Reset Auto Select 3 AAA AA 555 Program 4 AAA AA 555 55 AAA A0 PA PD Quadruple Byte Program 5 AAA 55 PA0 PD0 PA1 PD1 PA2 PD2 Unlock Bypass 3 AAA AA 555 55 AAA 20 Unlock Bypass Program 2 X A0 PA PD Unlock Bypass Reset 2 X 90 X 00 Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10 Block Erase 6+ AAA AA 555 55 AAA 80 AAA AA 555 55 BA 30 X 00 Erase Suspend 1 BKA B0 Erase Resume 1 BKA 30 Read CFI Query 1 AA 98 Enter Extended Block 3 AAA AA 555 55 AAA 88 Exit Extended Block 4 AAA AA 555 55 AAA 90 Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal. The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ14 and DQ15 are Don’t Care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH. Table 7. Program, Erase Times and Program, Erase Endurance Cycles Parameter Min Typ (1, 2) Chip Erase 40 Block Erase (64 KBytes) 0.8 Max(2) 200 (3) (3) 6 50(4) Erase Suspend Latency Time Program (Byte or Word) 10 Unit s s µs 200 (4) µs (3) µs Double Word Program (Byte or Word) 10 200 Chip Program (Byte by Byte) 40 200(3) s Chip Program (Word by Word) 20 100(3) s 10 100(3) Chip Program (Quadruple Byte or Double Word) Program/Erase Cycles (per Block) Data Retention Note: 1. 2. 3. 4. s 100,000 cycles 20 years Typical values measured at room temperature and nominal voltages. Sampled, but not 100% tested. Maximum value measured at worst case conditions for both temperature and VCC after 100,00 program/erase cycles. Maximum value measured at worst case conditions for both temperature and VCC. 19/51 M29DW323DT, M29DW323DB STATUS REGISTER The M29DW323D has a Status Register that provides information on the current or previous Program or Erase operations executed in each bank. The various bits convey information and errors on the operation. Bus Read operations from any address within the Bank, always read the Status Register during Program and Erase operations. It is also read during Erase Suspend when an address within a block being erased is accessed. The bits in the Status Register are summarized in Table 8., Status Register Bits. Data Polling Bit (DQ7). The Data Polling Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspend. The Data Polling Bit is output on DQ7 when the Status Register is read. During Program operations the Data Polling Bit outputs the complement of the bit being programmed to DQ7. After successful completion of the Program operation the memory returns to Read mode and Bus Read operations from the address just programmed output DQ7, not its complement. During Erase operations the Data Polling Bit outputs ’0’, the complement of the erased state of DQ7. After successful completion of the Erase operation the memory returns to Read Mode. In Erase Suspend mode the Data Polling Bit will output a ’1’ during a Bus Read operation within a block being erased. The Data Polling Bit will change from a ’0’ to a ’1’ when the Program/Erase Controller has suspended the Erase operation. Figure 7., Data Polling Flowchart, gives an example of how to use the Data Polling Bit. A Valid Address is the address being programmed or an address within the block being erased. Toggle Bit (DQ6). The Toggle Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspend. The Toggle Bit is output on DQ6 when the Status Register is read. During Program and Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with successive Bus Read operations at any address. After successful completion of the operation the memory returns to Read mode. During Erase Suspend mode the Toggle Bit will output when addressing a cell within a block being erased. The Toggle Bit will stop toggling when the Program/Erase Controller has suspended the Erase operation. Figure 8., Toggle Flowchart, gives an example of how to use the Data Toggle Bit. Figures 14 and 15 describe Toggle Bit timing waveform. 20/51 Error Bit (DQ5). The Error Bit can be used to identify errors detected by the Program/Erase Controller. The Error Bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the correct data to the memory. If the Error Bit is set a Read/Reset command must be issued before other commands are issued. The Error bit is output on DQ5 when the Status Register is read. Note that the Program command cannot change a bit set to ’0’ back to ’1’ and attempting to do so will set DQ5 to ‘1’. A Bus Read operation to that address will show the bit is still ‘0’. One of the Erase commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’. Erase Timer Bit (DQ3). The Erase Timer Bit can be used to identify the start of Program/Erase Controller operation during a Block Erase command. Once the Program/Erase Controller starts erasing the Erase Timer Bit is set to ’1’. Before the Program/Erase Controller starts the Erase Timer Bit is set to ’0’ and additional blocks to be erased may be written to the Command Interface. The Erase Timer Bit is output on DQ3 when the Status Register is read. Alternative Toggle Bit (DQ2). The Alternative Toggle Bit can be used to monitor the Program/ Erase controller during Erase operations. The Alternative Toggle Bit is output on DQ2 when the Status Register is read. During Chip Erase and Block Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with successive Bus Read operations from addresses within the blocks being erased. A protected block is treated the same as a block not being erased. Once the operation completes the memory returns to Read mode. During Erase Suspend the Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read operations from addresses within the blocks being erased. Bus Read operations to addresses within blocks not being erased will output the memory cell data as if in Read mode. After an Erase operation that causes the Error Bit to be set the Alternative Toggle Bit can be used to identify which block or blocks have caused the error. The Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read Operations from addresses within blocks that have not erased correctly. The Alternative Toggle Bit does not change if the addressed block has erased correctly. Figures 14 and 15 describe Alternative Toggle Bit timing waveform. M29DW323DT, M29DW323DB Table 8. Status Register Bits Address DQ7 DQ6 DQ5 DQ3 DQ2 RB Program Operation Bank Address DQ7 Toggle 0 – – 0 Program During Erase Suspend Bank Address DQ7 Toggle 0 – – 0 Program Error Bank Address DQ7 Toggle 1 – – Hi-Z Chip Erase Any Address 0 Toggle 0 1 Toggle 0 Block Erase before timeout Erasing Block 0 Toggle 0 0 Toggle 0 Non-Erasing Block 0 Toggle 0 0 No Toggle 0 Erasing Block 0 Toggle 0 1 Toggle 0 Block Erase Non-Erasing Block 0 Toggle 0 1 No Toggle 0 Erasing Block 1 No Toggle 0 – Toggle Hi-Z Good Block Address 0 Toggle 1 1 No Toggle Hi-Z Faulty Block Address 0 Toggle 1 1 Toggle Hi-Z Erase Suspend Non-Erasing Block Data read as normal Hi-Z Erase Error Note: Unspecified data bits should be ignored. Figure 7. Data Polling Flowchart Figure 8. Toggle Flowchart START START READ DQ6 ADDRESS = BA READ DQ5 & DQ7 at VALID ADDRESS DQ7 = DATA READ DQ5 & DQ6 ADDRESS = BA YES DQ6 = TOGGLE NO NO DQ5 =1 YES NO YES READ DQ7 at VALID ADDRESS DQ7 = DATA NO DQ5 =1 YES READ DQ6 TWICE ADDRESS = BA YES DQ6 = TOGGLE NO NO YES FAIL PASS FAIL AI90194 PASS AI08929b Note: BA = Address of Bank being Programmed or Erased. 21/51 M29DW323DT, M29DW323DB DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE The Multiple Bank Architecture of the M29DW323DT and M29DW323DB gives greater flexibility for software developers to split the code and data spaces within the memory array. The Dual Operations feature simplifies the software management of the device by allowing code to be executed from one bank while the other bank is being programmed or erased. The Dual Operations feature means that while programming or erasing in one bank, read operations are possible in the other bank with zero latency. Only one bank at a time is allowed to be in program or erase mode. If a read operation is required in a bank, which is programming or erasing, the program or erase operation can be suspended. Also if the suspended operation was erase then a program command can be issued to another block, so the device can have one block in Erase Suspend mode, one programming and other banks in read mode. By using a combination of these features, read operations are possible at any moment. Table 9. and Table 10. show the dual operations possible in other banks and in the same bank. Note that only the commonly used commands are represented in these tables. Table 9. Dual Operations Allowed In the Other Bank Commands allowed in the Other Bank(1) Status of First Bank(1) Read Array Read Status Register(6) Read CFI Query Auto Select Program Erase Erase Suspend Erase Resume Idle Yes Yes(2) Yes Yes Yes Yes Yes(2) Yes(3) Programming Yes No No No – – No No Erasing Yes No No No – – No No Erase Suspended Yes Yes Yes Yes Yes No - Yes Note: 1. If one bank is involved in a program or erase operation, then the other bank is available for dual operations. 2. Only after an Erase operation in that bank. 3. Only after an Erase Suspend command in that bank. Table 10. Dual Operations Allowed In Same Bank Commands allowed in same bank Read Array Read Status Register(4) Read CFI Query Auto Select Program Erase Erase Suspend Erase Resume Idle Yes Yes Yes Yes Yes Yes Yes(2) Yes(3) Programming No Yes No No – – No Yes(4) Status of bank Erasing Erase Suspended Note: 1. 2. 3. 4. 5. 22/51 No Yes No No – No Yes(5) Yes(1) Yes(5) Yes Yes Yes(1) No - Not allowed in the Block or Word that is being erased or programmed. Only after an Erase operation in that bank. Only after an Erase Suspend command in that bank. Read Status Register is not a command. The Status Register can be read during a block program or erase operation. The Status Register can be read by addressing the block being erase suspended. M29DW323DT, M29DW323DB MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Refer also to the Numonyx SURE Program and other relevant quality documents. Table 11. Absolute Maximum Ratings Symbol Parameter Min Max Unit TBIAS Temperature Under Bias –50 125 °C TSTG Storage Temperature –65 150 °C TLEAD Lead Temperature during Soldering (1) °C –0.6 VCC +0.6 V (2,3) VIO Input or Output Voltage VCC Supply Voltage –0.6 4 V VID Identification Voltage –0.6 13.5 V Program Voltage –0.6 13.5 V VPP (4) Note: 1. Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. Minimum voltage may undershoot to –2V during transition and for less than 20ns during transitions. 3. Maximum voltage may overshoot to VCC +2V during transition and for less than 20ns during transitions. 4. VPP must not remain at 12V for more than a total of 80hrs. 23/51 M29DW323DT, M29DW323DB DC AND AC PARAMETERS This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 12., Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 12. Operating and AC Measurement Conditions M29DW323D Parameter 70ns Unit Min Max VCC Supply Voltage 2.7 3.6 V Ambient Operating Temperature –40 85 °C Load Capacitance (CL) 30 pF Input Rise and Fall Times 10 Input Pulse Voltages Input and Output Timing Ref. Voltages Figure 9. AC Measurement I/O Waveform ns 0 to VCC V VCC/2 V Figure 10. AC Measurement Load Circuit VPP VCC VCC VCC VCC/2 25kΩ 0V DEVICE UNDER TEST AI05557 25kΩ CL 0.1µF 0.1µF CL includes JIG capacitance AI05558 Table 13. Device Capacitance Symbol CIN COUT Parameter Input Capacitance Output Capacitance Note: Sampled only, not 100% tested. 24/51 Test Condition Min Max Unit VIN = 0V 6 pF VOUT = 0V 12 pF M29DW323DT, M29DW323DB Table 14. DC Characteristics Symbol Parameter Max Unit 0V ≤VIN ≤VCC ±1 µA Output Leakage Current 0V ≤VOUT ≤VCC ±1 µA Supply Current (Read) E = VIL, G = VIH, f = 6MHz 10 mA ICC2 Supply Current (Standby) E = VCC ±0.2V, RP = VCC ±0.2V 100 µA ICC3 (1,2) Supply Current (Program/ Erase) VPP/WP = VIL or VIH 20 mA VPP/WP = VPP 20 mA ILI Input Leakage Current ILO ICC1(2) Test Condition Program/Erase Controller active Min VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 0.7VCC VCC +0.3 V VPP Voltage for VPP/WP Program Acceleration VCC = 2.7V ±10% 11.5 12.5 V IPP Current for VPP/WP Program Acceleration VCC = 2.7V ±10% 15 mA VOL Output Low Voltage IOL = 1.8mA 0.45 V VOH Output High Voltage IOH = –100µA VID Identification Voltage 11.5 12.5 V Program/Erase Lockout Supply Voltage 1.8 2.3 V VLKO VCC –0.4 V Note: 1. Sampled only, not 100% tested. 2. In Dual operations the Supply Current will be the sum of ICC1(read) and ICC3 (program/erase). 25/51 M29DW323DT, M29DW323DB Figure 11. Read Mode AC Waveforms tAVAV A0-A20/ A–1 VALID tAVQV tAXQX E tELQV tEHQX tELQX tEHQZ G tGLQX tGHQX tGLQV tGHQZ DQ0-DQ7/ DQ8-DQ15 VALID tBHQV BYTE tELBL/tELBH tBLQZ AI05559 Table 15. Read AC Characteristics Symbol Alt Parameter Test Condition M29DW323D Unit Min 70 ns tAVAV tRC Address Valid to Next Address Valid E = VIL, G = VIL tAVQV tACC Address Valid to Output Valid E = VIL, G = VIL Max 70 ns tELQX (1) tLZ Chip Enable Low to Output Transition G = VIL Min 0 ns tCE Max 70 ns Chip Enable Low to Output Valid G = VIL tOLZ Output Enable Low to Output Transition E = VIL Min 0 ns tGLQV tOE Output Enable Low to Output Valid E = VIL Max 30 ns tEHQZ (1) tHZ Chip Enable High to Output Hi-Z G = VIL Max 25 ns tGHQZ (1) tDF Output Enable High to Output Hi-Z E = VIL Max 25 ns tEHQX tGHQX tAXQX tOH Chip Enable, Output Enable or Address Transition to Output Transition Min 0 ns tELBL tELBH tELFL tELFH Chip Enable to BYTE Low or High Max 5 ns tBLQZ tFLQZ BYTE Low to Output Hi-Z Max 25 ns tBHQV tFHQV BYTE High to Output Valid Max 30 ns tELQV tGLQX (1) Note: 1. Sampled only, not 100% tested. 26/51 M29DW323DT, M29DW323DB Figure 12. Write AC Waveforms, Write Enable Controlled tAVAV A0-A20/ A–1 VALID tWLAX tAVWL tWHEH E tELWL tWHGL G tGHWL tWLWH W tWHWL tDVWH DQ0-DQ7/ DQ8-DQ15 tWHDX VALID VCC tVCHEL RB tWHRL AI05560 Table 16. Write AC Characteristics, Write Enable Controlled Symbol Alt tAVAV tWC Address Valid to Next Address Valid Parameter tELWL tCS Chip Enable Low to Write Enable Low Min 0 ns tWLWH tWP Write Enable Low to Write Enable High Min 45 ns tDVWH tDS Input Valid to Write Enable High Min 45 ns tWHDX tDH Write Enable High to Input Transition Min 0 ns tWHEH tCH Write Enable High to Chip Enable High Min 0 ns tWHWL tWPH Write Enable High to Write Enable Low Min 30 ns Min M29DW323D Unit 70 ns tAVWL tAS Address Valid to Write Enable Low Min 0 ns tWLAX tAH Write Enable Low to Address Transition Min 45 ns tGHWL Output Enable High to Write Enable Low Min 0 ns tWHGL tOEH Write Enable High to Output Enable Low Min 0 ns tWHRL (1) tBUSY Program/Erase Valid to RB Low Max 30 ns tVCHEL tVCS VCC High to Chip Enable Low Min 50 µs Note: 1. Sampled only, not 100% tested. 27/51 M29DW323DT, M29DW323DB Figure 13. Write AC Waveforms, Chip Enable Controlled tAVAV A0-A20/ A–1 VALID tELAX tAVEL tEHWH W tWLEL tEHGL G tGHEL tELEH E tEHEL tDVEH DQ0-DQ7/ DQ8-DQ15 tEHDX VALID VCC tVCHWL RB tEHRL AI05561 Table 17. Write AC Characteristics, Chip Enable Controlled Symbol Alt Parameter tAVAV tWC Address Valid to Next Address Valid Min M29DW323D Unit 70 ns tWLEL tWS Write Enable Low to Chip Enable Low tELEH tCP Chip Enable Low to Chip Enable High Min 0 ns Min 45 ns tDVEH tDS tEHDX tDH Input Valid to Chip Enable High Min 45 ns Chip Enable High to Input Transition Min 0 ns tEHWH tEHEL tWH Chip Enable High to Write Enable High Min 0 ns tCPH Chip Enable High to Chip Enable Low Min 30 ns tAVEL tAS Address Valid to Chip Enable Low Min 0 ns tELAX tAH Chip Enable Low to Address Transition Min 45 ns tGHEL Output Enable High Chip Enable Low Min 0 ns tEHGL tOEH Chip Enable High to Output Enable Low Min 0 ns tEHRL (1) tBUSY Program/Erase Valid to RB Low Max 30 ns tVCHWL tVCS VCC High to Write Enable Low Min 50 µs Note: 1. Sampled only, not 100% tested. 28/51 M29DW323DT, M29DW323DB Figure 14. Toggle and Alternative Toggle Bits Mechanism, Chip Enable Controlled Address Outside the Bank Being Programmed or Erased A0-A20 Address Outside the Bank Being Programmed or Erased Address in the Bank Being Programmed or Erased tAXEL E G tELQV tELQV Alternative Toggle/ Toggle Bit Alternative Toggle/ Toggle Bit Data DQ2(1)/DQ6(2) Read Operation outside the Bank Being Programmed or Erased Read Operation in the Bank Being Programmed or Erased Data Read Operation Outside the Bank Being Programmed or Erased AI08914c Note: 1. The Toggle bit is output on DQ6. 2. The Alternative Toggle bit is output on DQ2. Figure 15. Toggle and Alternative Toggle Bits Mechanism, Output Enable Controlled Address Outside the Bank Being Programmed or Erased A0-A20 Address Outside the Bank Being Programmed or Erased Address in the Bank Being Programmed or Erased tAXGL G E tGLQV Data DQ2(1)/DQ6(2) Read Operation outside the Bank Being Programmed or Erased Alternative Toggle/ Toggle Bit tGLQV Alternative Toggle/ Toggle Bit Read Operation in the Bank Being Programmed or Erased Data Read Operation Outside the Bank Being Programmed or Erased AI08915c Note: 1. The Toggle bit is output on DQ6. 2. The Alternative Toggle bit is output on DQ2. Table 18. Toggle and Alternative Toggle Bits AC Characteristics Symbol Alt Parameter M29DW323D Unit tAXEL Address Transition to Chip Enable Low Min 10 ns tAXGL Address Transition to Output Enable Low Min 10 ns Note: tELQV and tGLQV values are presented in Table 15., Read AC Characteristics. 29/51 M29DW323DT, M29DW323DB Figure 16. Reset/Block Temporary Unprotect AC Waveforms W, E, G tPHWL, tPHEL, tPHGL RB tRHWL, tRHEL, tRHGL tPLPX RP tPHPHH tPLYH AI02931B Table 19. Reset/Block Temporary Unprotect AC Characteristics Symbol Alt tPHWL (1) tPHEL tPHGL (1) tRH RP High to Write Enable Low, Chip Enable Low, Output Enable Low tRHWL (1) tRHEL (1) tRHGL (1) tRB tPLPX tRP tPLYH tREADY tPHPHH (1) tVIDR tVHVPP (1) Parameter M29DW323D Unit Min 50 ns RB High to Write Enable Low, Chip Enable Low, Output Enable Low Min 0 ns RP Pulse Width Min 500 ns RP Low to Read Mode Max 50 µs RP Rise Time to VID Min 500 ns VPP Rise and Fall Time Min 250 ns Note: 1. Sampled only, not 100% tested. Figure 17. Accelerated Program Timing Waveforms VPP VPP/WP VIL or VIH tVHVPP tVHVPP AI05563 30/51 M29DW323DT, M29DW323DB PACKAGE MECHANICAL Figure 18. TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Bottom View Package Outline 1 48 e D1 B 24 L1 25 A2 E1 E A α A1 DIE L C CP TSOP-G Note: Drawing not to scale. Table 20. TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Package Mechanical Data millimeters inches Symbol Typ Min A Max Typ Min 1.200 Max 0.0472 A1 0.100 0.050 0.150 0.0039 0.0020 0.0059 A2 1.000 0.950 1.050 0.0394 0.0374 0.0413 B 0.220 0.170 0.270 0.0087 0.0067 0.0106 0.100 0.210 0.0039 0.0083 C CP 0.080 0.0031 D1 12.000 11.900 12.100 0.4724 0.4685 0.4764 E 20.000 19.800 20.200 0.7874 0.7795 0.7953 E1 18.400 18.300 18.500 0.7244 0.7205 0.7283 e 0.500 – – 0.0197 – – L 0.600 0.500 0.700 0.0236 0.0197 0.0276 L1 0.800 α 3 0 5 0 5 0.0315 3 31/51 M29DW323DT, M29DW323DB Figure 19. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Bottom View Package Outline D D1 FD FE SD SE E E1 BALL "A1" ddd e e b A A2 A1 BGA-Z32 Note: Drawing not to scale. Table 21. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Package Mechanical Data millimeters inches Symbol Typ Min A Max Typ Min 1.200 A1 0.0472 0.260 A2 0.0102 0.900 b 0.350 0.450 6.100 – D 6.000 5.900 D1 4.000 – ddd 0.0354 0.0138 0.0177 0.2362 0.2323 0.2402 0.1575 – 0.100 8.100 – 0.0039 E 8.000 E1 5.600 – – 0.2205 – – e 0.800 – – 0.0315 – – FD 1.000 – – 0.0394 – – FE 1.200 – – 0.0472 – – SD 0.400 – – 0.0157 – – SE 0.400 – – 0.0157 – – 32/51 7.900 Max 0.3150 0.3110 0.3189 M29DW323DT, M29DW323DB PART NUMBERING Table 22. Ordering Information Scheme Example: M29DW323DB 70 N 1 T Device Type M29 Architecture D = Dual Operation Operating Voltage W = VCC = 2.7 to 3.6V Device Function 323D = 32 Mbit (x8/x16), Boot Block, 1/4-3/4 partitioning Array Matrix T = Top Boot B = Bottom Boot Speed 70 = 70 ns Package N = TSOP48: 12 x 20 mm ZE = TFBGA48: 6 x 8mm, 0.8mm pitch Temperature Range 1 = 0 to 70 °C 6 = –40 to 85 °C Option Blank = Standard Packing T = Tape & Reel Packing E = Lead-free Package, Standard Packing F = Lead-free Package, Tape & Reel Packing Note: This product is also available with the Extended Block factory locked. For further details and ordering information contact your nearest Numonyx sales office. Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the Numonyx Sales Office nearest to you. 33/51 M29DW323DT, M29DW323DB APPENDIX A. BLOCK ADDRESSES Bank Table 23. Top Boot Block Addresses, M29DW323DT Block (Kbytes/ Kwords) Protection Block Group (x8) (x16) 0 64/32 Protection Group 000000h–00FFFFh 000000h–07FFFh 1 64/32 010000h–01FFFFh 008000h–0FFFFh 2 64/32 3 Protection Group 020000h–02FFFFh 010000h–17FFFh 64/32 030000h–03FFFFh 018000h–01FFFFh 4 64/32 040000h–04FFFFh 020000h–027FFFh 5 64/32 050000h–05FFFFh 028000h–02FFFFh 6 64/32 060000h–06FFFFh 030000h–037FFFh 7 64/32 070000h–07FFFFh 038000h–03FFFFh 8 64/32 080000h–08FFFFh 040000h–047FFFh 090000h–09FFFFh 048000h–04FFFFh Protection Group 9 64/32 10 64/32 0A0000h–0AFFFFh 050000h–057FFFh 11 64/32 0B0000h–0BFFFFh 058000h–05FFFFh Protection Group 12 64/32 0C0000h–0CFFFFh 060000h–067FFFh 13 64/32 0D0000h–0DFFFFh 068000h–06FFFFh 14 64/32 0E0000h–0EFFFFh 070000h–077FFFh 15 64/32 0F0000h–0FFFFFh 078000h–07FFFFh 16 64/32 100000h–10FFFFh 080000h–087FFFh 17 64/32 110000h–11FFFFh 088000h–08FFFFh 18 64/32 120000h–12FFFFh 090000h–097FFFh 19 64/32 130000h–13FFFFh 098000h–09FFFFh Bank B Protection Group Protection Group 20 64/32 140000h–14FFFFh 0A0000h–0A7FFFh 21 64/32 150000h–15FFFFh 0A8000h–0AFFFFh 22 64/32 160000h–16FFFFh 0B0000h–0B7FFFh 23 64/32 170000h–17FFFFh 0B8000h–0BFFFFh 24 64/32 180000h–18FFFFh 0C0000h–0C7FFFh 25 64/32 190000h–19FFFFh 0C8000h–0CFFFFh 26 64/32 1A0000h–1AFFFFh 0D0000h–0D7FFFh 27 64/32 1B0000h–1BFFFFh 0D8000h–0DFFFFh Protection Group Protection Group 28 64/32 1C0000h–1CFFFFh 0E0000h–0E7FFFh 29 64/32 1D0000h–1DFFFFh 0E8000h–0EFFFFh 30 64/32 1E0000h–1EFFFFh 0F0000h–0F7FFFh 31 64/32 1F0000h–1FFFFFh 0F8000h–0FFFFFh Protection Group 34/51 Bank M29DW323DT, M29DW323DB Block (Kbytes/ Kwords) Protection Block Group (x8) (x16) 32 64/32 200000h–20FFFFh 100000h–107FFFh 33 64/32 210000h–21FFFFh 108000h–10FFFFh 34 64/32 220000h–22FFFFh 110000h–117FFFh 35 64/32 230000h–23FFFFh 118000h–11FFFFh 36 64/32 240000h–24FFFFh 120000h–127FFFh 37 64/32 250000h–25FFFFh 128000h–12FFFFh 38 64/32 260000h–26FFFFh 130000h–137FFFh 39 64/32 270000h–27FFFFh 138000h–13FFFFh Protection Group Bank B Protection Group 40 64/32 280000h–28FFFFh 140000h–147FFFh 41 64/32 290000h–29FFFFh 148000h–14FFFFh 42 64/32 2A0000h–2AFFFFh 150000h–157FFFh 43 64/32 2B0000h–2BFFFFh 158000h–15FFFFh 44 64/32 2C0000h–2CFFFFh 160000h–167FFFh 45 64/32 2D0000h–2DFFFFh 168000h–16FFFFh 46 64/32 2E0000h–2EFFFFh 170000h–177FFFh 47 64/32 2F0000h–2FFFFFh 178000h–17FFFFh Protection Group Protection Group 48 64/32 300000h–30FFFFh 180000h–187FFFh 49 64/32 310000h–31FFFFh 188000h–18FFFFh 50 64/32 320000h–32FFFFh 190000h–197FFFh 51 64/32 330000h–33FFFFh 198000h–19FFFFh 52 64/32 340000h–34FFFFh 1A0000h–1A7FFFh 53 64/32 350000h–35FFFFh 1A8000h–1AFFFFh Protection Group Bank A Protection Group 54 64/32 360000h–36FFFFh 1B0000h–1B7FFFh 55 64/32 370000h–37FFFFh 1B8000h–1BFFFFh 56 64/32 380000h–38FFFFh 1C0000h–1C7FFFh 57 64/32 390000h–39FFFFh 1C8000h–1CFFFFh 58 64/32 3A0000h–3AFFFFh 1D0000h–1D7FFFh 59 64/32 3B0000h–3BFFFFh 1D8000h–1DFFFFh 60 64/32 3C0000h–3CFFFFh 1E0000h–1E7FFFh 61 64/32 3D0000h–3DFFFFh 1E8000h–1EFFFFh 62 64/32 3E0000h–3EFFFFh 1F0000h–1F7FFFh Protection Group Protection Group 35/51 Bank A Bank M29DW323DT, M29DW323DB Block (Kbytes/ Kwords) Protection Block Group (x8) (x16) 63 8/4 Protection Group 3F0000h–3F1FFFh(1) 1F8000h–1F8FFFh(1) 64 8/4 Protection Group 3F2000h–3F3FFFh(1) 1F9000h–1F9FFFh(1) 65 8/4 Protection Group 3F4000h–3F5FFFh(1) 1FA000h–1FAFFFh(1) 66 8/4 Protection Group 3F6000h–3F7FFFh(1) 1FB000h–1FBFFFh(1) 67 8/4 Protection Group 3F8000h–3F9FFFh(1) 1FC000h–1FCFFFh(1) 1FD000h–1FDFFFh(1) 68 8/4 Protection Group 3FA000h–3FBFFFh(1) 69 8/4 Protection Group 3FC000h–3FDFFFh(1) 1FE000h–1FEFFFh(1) 70 8/4 Protection Group 3FE000h–3FFFFFh(1) 1FF000h–1FFFFFh(1) Note: 1. Used as the Extended Block Addresses in Extended Block mode. 36/51 M29DW323DT, M29DW323DB Bank A Bank Table 24. Bottom Boot Block Addresses, M29DW323DB Block (Kbytes/ Kwords) Protection Block Group (x8) 0 8/4 Protection Group 000000h-001FFFh(1) 000000h–000FFFh(1) (1) 001000h–001FFFh(1) (x16) 1 8/4 Protection Group 002000h-003FFFh 2 8/4 Protection Group 004000h-005FFFh(1) 002000h–002FFFh(1) 3 8/4 Protection Group 006000h-007FFFh(1) 003000h–003FFFh(1) 4 8/4 Protection Group 008000h-009FFFh(1) 004000h–004FFFh(1) 5 8/4 Protection Group 00A000h-00BFFFh(1) 005000h–005FFFh(1) 6 8/4 Protection Group 00C000h-00DFFFh(1) 006000h–006FFFh(1) Protection Group (1) 007000h–007FFFh(1) 7 8/4 8 64/32 9 64/32 10 64/32 00E000h-00FFFFh 010000h-01FFFFh Protection Group 008000h–00FFFFh 020000h-02FFFFh 010000h–017FFFh 030000h-03FFFFh 018000h–01FFFFh 11 64/32 040000h-04FFFFh 020000h–027FFFh 12 64/32 050000h-05FFFFh 028000h–02FFFFh 13 64/32 060000h-06FFFFh 030000h–037FFFh 14 64/32 070000h-07FFFFh 038000h–03FFFFh 15 64/32 080000h-08FFFFh 040000h–047FFFh 16 64/32 090000h-09FFFFh 048000h–04FFFFh 17 64/32 0A0000h-0AFFFFh 050000h–057FFFh 18 64/32 0B0000h-0BFFFFh 058000h–05FFFFh 19 64/32 0C0000h-0CFFFFh 060000h–067FFFh 20 64/32 0D0000h-0DFFFFh 068000h–06FFFFh 21 64/32 0E0000h-0EFFFFh 070000h–077FFFh 22 64/32 0F0000h-0FFFFFh 078000h–07FFFFh 23 64/32 100000h-10FFFFh 080000h–087FFFh 24 64/32 110000h-11FFFFh 088000h–08FFFFh 25 64/32 120000h-12FFFFh 090000h–097FFFh 26 64/32 130000h-13FFFFh 098000h–09FFFFh Protection Group Protection Group Protection Group Bank B Protection Group 27 64/32 140000h-14FFFFh 0A0000h–0A7FFFh 28 64/32 150000h-15FFFFh 0A8000h–0AFFFFh 29 64/32 160000h-16FFFFh 0B0000h–0B7FFFh 30 64/32 170000h-17FFFFh 0B8000h–0BFFFFh Protection Group 37/51 Bank M29DW323DT, M29DW323DB Block (Kbytes/ Kwords) Protection Block Group (x8) (x16) 31 64/32 180000h-18FFFFh 0C0000h–0C7FFFh 32 64/32 190000h-19FFFFh 0C8000h–0CFFFFh 33 64/32 1A0000h-1AFFFFh 0D0000h–0D7FFFh 34 64/32 1B0000h-1BFFFFh 0D8000h–0DFFFFh 35 64/32 1C0000h-1CFFFFh 0E0000h–0E7FFFh 36 64/32 1D0000h-1DFFFFh 0E8000h–0EFFFFh 37 64/32 1E0000h-1EFFFFh 0F0000h–0F7FFFh 38 64/32 1F0000h-1FFFFFh 0F8000h–0FFFFFh Protection Group Protection Group 39 64/32 200000h-20FFFFh 100000h–107FFFh 40 64/32 210000h-21FFFFh 108000h–10FFFFh 41 64/32 220000h-22FFFFh 110000h–117FFFh 42 64/32 230000h-23FFFFh 118000h–11FFFFh 43 64/32 240000h-24FFFFh 120000h–127FFFh 44 64/32 250000h-25FFFFh 128000h–12FFFFh 45 64/32 260000h-26FFFFh 130000h–137FFFh 46 64/32 270000h-27FFFFh 138000h–13FFFFh Protection Group Bank B Protection Group 47 64/32 280000h-28FFFFh 140000h–147FFFh 48 64/32 290000h-29FFFFh 148000h–14FFFFh 49 64/32 2A0000h-2AFFFFh 150000h–157FFFh 50 64/32 2B0000h-2BFFFFh 158000h–15FFFFh 51 64/32 2C0000h-2CFFFFh 160000h–167FFFh 52 64/32 2D0000h-2DFFFFh 168000h–16FFFFh 53 64/32 2E0000h-2EFFFFh 170000h–177FFFh 54 64/32 2F0000h-2FFFFFh 178000h–17FFFFh Protection Group Protection Group 55 64/32 300000h-30FFFFh 180000h–187FFFh 56 64/32 310000h-31FFFFh 188000h–18FFFFh 57 64/32 320000h-32FFFFh 190000h–197FFFh 58 64/32 330000h-33FFFFh 198000h–19FFFFh 59 64/32 340000h-34FFFFh 1A0000h–1A7FFFh 60 64/32 350000h-35FFFFh 1A8000h–1AFFFFh Protection Group Protection Group 38/51 61 64/32 360000h-36FFFFh 1B0000h–1B7FFFh 62 64/32 370000h-37FFFFh 1B8000h–1BFFFFh Bank M29DW323DT, M29DW323DB Block (Kbytes/ Kwords) Protection Block Group (x8) (x16) 63 64/32 380000h-38FFFFh 1C0000h–1C7FFFh 64 64/32 390000h-39FFFFh 1C8000h–1CFFFFh 65 64/32 3A0000h-3AFFFFh 1D0000h–1D7FFFh 66 64/32 3B0000h-3BFFFFh 1D8000h–1DFFFFh 67 64/32 3C0000h-3CFFFFh 1E0000h–1E7FFFh 68 64/32 3D0000h-3DFFFFh 1E8000h–1EFFFFh 69 64/32 70 64/32 Bank B Protection Group Protection Group Protection Group 3E0000h-3EFFFFh 1F0000h–1F7FFFh 3F0000h-3FFFFFh 1F8000h–1FFFFFh Note: 1. Used as the Extended Block Addresses in Extended Block mode. 39/51 M29DW323DT, M29DW323DB APPENDIX B. COMMON FLASH INTERFACE (CFI) The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary. When the CFI Query Command is issued the device enters CFI Query mode and the data structure is read from the memory. Tables 25, 26, 27, 28, 29 and 30 show the addresses used to retrieve the data. The CFI data structure also contains a security area where a 64 bit unique security number is written (see Table 30., Security Code Area). This area can be accessed only in Read mode by the final user. It is impossible to change the security number after it has been written by Numonyx. Table 25. Query Structure Overview Address Sub-section Name x16 Description x8 10h 20h CFI Query Identification String Command set ID and algorithm data offset 1Bh 36h System Interface Information Device timing & voltage information 27h 4Eh Device Geometry Definition Flash device layout 40h 80h Primary Algorithm-specific Extended Query table Additional information specific to the Primary Algorithm (optional) 61h C2h Security Code Area 64 bit unique device number Note: Query data are always presented on the lowest order data outputs. Table 26. CFI Query Identification String Address Data x16 x8 10h 20h 0051h 11h 22h 0052h 12h 24h 0059h 13h 26h 0002h 14h 28h 0000h Description “Q” Query Unique ASCII String "QRY" "R" "Y" Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm AMD Compatible Address for Primary Algorithm extended Query table (see Table 29.) P = 40h 15h 2Ah 0040h 16h 2Ch 0000h 17h 2Eh 0000h 18h 30h 0000h Alternate Vendor Command Set and Control Interface ID Code second vendor - specified algorithm supported 19h 32h 0000h Address for Alternate Algorithm extended Query table 1Ah 34h 0000h Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’. 40/51 Value NA NA M29DW323DT, M29DW323DB Table 27. CFI Query System Interface Information Address Data Description Value x16 x8 1Bh 36h 0027h VCC Logic Supply Minimum Program/Erase voltage bit 7 to 4BCD value in volts bit 3 to 0BCD value in 100 mV 2.7V 1Ch 38h 0036h VCC Logic Supply Maximum Program/Erase voltage bit 7 to 4BCD value in volts bit 3 to 0BCD value in 100 mV 3.6V 1Dh 3Ah 00B5h VPP [Programming] Supply Minimum Program/Erase voltage bit 7 to 4HEX value in volts bit 3 to 0BCD value in 100 mV 11.5V 1Eh 3Ch 00C5h VPP [Programming] Supply Maximum Program/Erase voltage bit 7 to 4HEX value in volts bit 3 to 0BCD value in 100 mV 12.5V 1Fh 3Eh 0004h Typical timeout per single byte/word program = 2n µs 16µs 20h 40h 0000h Typical timeout for minimum size write buffer program = 2n µs n 21h 42h 000Ah 22h 44h 0000h Typical timeout for full Chip Erase = 2 ms 23h 46h 0004h Maximum timeout for byte/word program = 2n times typical 24h 48h 0000h Maximum timeout for write buffer program = 2n times typical 25h 26h 4Ah 4Ch 0003h 0000h Typical timeout per individual block erase = 2 ms n NA 1s NA n Maximum timeout per individual block erase = 2 times typical n Maximum timeout for Chip Erase = 2 times typical 256 µs NA 8s NA Table 28. Device Geometry Definition Address Data Description Value x16 x8 27h 4Eh 0016h Device Size = 2n in number of bytes 4 MByte 28h 29h 50h 52h 0002h 0000h Flash Device Interface Code description x8, x16 Async. 2Ah 2Bh 54h 56h 0000h 0000h Maximum number of bytes in multi-byte program or page = 2n NA 2Ch 58h 0002h Number of Erase Block Regions. It specifies the number of regions containing contiguous Erase Blocks of the same size. 2 2Dh 2Eh 5Ah 5Ch 0007h 0000h Region 1 Information Number of Erase Blocks of identical size = 0007h+1 8 2Fh 30h 5Eh 60h 0020h 0000h Region 1 Information Block size in Region 1 = 0020h * 256 byte 31h 32h 62h 64h 003Eh 0000h Region 2 Information Number of Erase Blocks of identical size = 003Eh+1 33h 34h 66h 68h 0000h 0001h Region 2 Information Block size in Region 2 = 0100h * 256 byte 8Kbyte 63 64Kbyte Note: For the M29DW323DB, Region 1 corresponds to addresses 000000h to 007FFFh and Region 2 to addresses 008000h to 1FFFFFh. For the M29DW323DT, Region 1 corresponds to addresses 1F8000h to 1FFFFFh and Region 2 to addresses 000000h to 1F7FFFh. 41/51 M29DW323DT, M29DW323DB Table 29. Primary Algorithm-Specific Extended Query Table Address Data x16 Description Value x8 40h 80h 0050h 41h 82h 0052h "P" 42h 84h 0049h 43h 86h 0031h Major version number, ASCII 44h 88h 0030h Minor version number, ASCII "0" 45h 8Ah 0000h Address Sensitive Unlock (bits 1 to 0) 00 = required, 01= not required Silicon Revision Number (bits 7 to 2) Yes 46h 8Ch 0002h Erase Suspend 00 = not supported, 01 = Read only, 02 = Read and Write 2 47h 8Eh 0001h Block Protection 00 = not supported, x = number of blocks in per group 1 48h 90h 0001h Temporary Block Unprotect 00 = not supported, 01 = supported Yes 49h 92h 0004h Block Protect /Unprotect 04 = M29DW323D 04 4Ah 94h 0030h Simultaneous Operations, x = number of blocks in Bank B 48 No Primary Algorithm extended Query table unique ASCII string “PRI” "R" "I" "1" 4Bh 96h 0000h Burst Mode, 00 = not supported, 01 = supported 4Ch 98h 0000h Page Mode, 00 = not supported, 01 = 4 page word, 02 = 8 page word 4Dh 9Ah 00B5h VPP Supply Minimum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV 11.5V 4Eh 9Ch 00C5h VPP Supply Maximum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV 12.5V 4Fh 9Eh 000xh Top/Bottom Boot Block Flag 02h = Bottom Boot device, 03h = Top Boot device Table 30. Security Code Area Address 42/51 Data x16 x8 61h C3h, C2h XXXX 62h C5h, C4h XXXX 63h C7h, C6h XXXX 64h C9h, C8h XXXX Description 64 bit: unique device number No – M29DW323DT, M29DW323DB APPENDIX C. EXTENDED MEMORY BLOCK The M29DW323D has an extra block, the Extended Block, that can be accessed using a dedicated command. This Extended Block is 32 KWords in x16 mode and 64 KBytes in x8 mode. It is used as a security block (to provide a permanent security identification number) or to store additional information. The Extended Block is either Factory Locked or Customer Lockable, its status is indicated by bit DQ7. This bit is permanently set to either ‘1’ or ‘0’ at the factory and cannot be changed. When set to ‘1’, it indicates that the device is factory locked and the Extended Block is protected. When set to ‘0’, it indicates that the device is customer lockable and the Extended Block is unprotected. Bit DQ7 being permanently locked to either ‘1’ or ‘0’ is another security feature which ensures that a customer lockable device cannot be used instead of a factory locked one. Bit DQ7 is the most significant bit in the Extended Block Verify Code and a specific procedure must be followed to read it. See “Extended Memory Block Verify Code” in Tables 3 and 4, Bus Operations, BYTE = VIL and Bus Operations, BYTE = VIH, respectively, for details of how to read bit DQ7. The Extended Block can only be accessed when the device is in Extended Block mode. For details of how the Extended Block mode is entered and exited, refer to the Enter Extended Block Command and Exit Extended Block Command paragraphs, and to Tables 5 and 6, “Commands, 16-bit mode, BYTE = VIH” and “Commands, 8-bit mode, BYTE = VIL”, respectively. Factory Locked Extended Block In devices where the Extended Block is factory locked, the Security Identification Number is written to the Extended Block address space (see Table 31., Extended Block Address and Data) in the factory. The DQ7 bit is set to ‘1’ and the Extended Block cannot be unprotected. Customer Lockable Extended Block A device where the Extended Block is customer lockable is delivered with the DQ7 bit set to ‘0’ and the Extended Block unprotected. It is up to the customer to program and protect the Extended Block but care must be taken because the protection of the Extended Block is not reversible. There are two ways of protecting the Extended Block: ■ Issue the Enter Extended Block command to place the device in Extended Block mode, then use the In-System Technique with RP either at VIH or at VID (refer to APPENDIX D., In-System Technique and to the corresponding flowcharts, Figures 22 and 23, for a detailed explanation of the technique). ■ Issue the Enter Extended Block command to place the device in Extended Block mode, then use the Programmer Technique (refer to APPENDIX D., Programmer Technique and to the corresponding flowcharts, Figures 20 and 21, for a detailed explanation of the technique). Once the Extended Block is programmed and protected, the Exit Extended Block command must be issued to exit the Extended Block mode and return the device to Read mode. Table 31. Extended Block Address and Data Address(1) Device x8 Data x16 Factory Locked 3F0000h-3F000Fh 1F8000h-1F8007h Security Identification Number 3F0010h-3FFFFFh 1F8008h-1FFFFFh Unavailable 000000h-00000Fh 000000h-000007h Security Identification Number 000010h-00FFFFh 000008h-007FFFh Unavailable M29DW323DT M29DW323DB Customer Lockable Determined by Customer Determined by Customer Note: 1. See Tables 23 and 24, Top and Bottom Boot Block Addresses. 43/51 M29DW323DT, M29DW323DB APPENDIX D. BLOCK PROTECTION Block protection can be used to prevent any operation from modifying the data stored in the memory. The blocks are protected in groups, refer to APPENDIX A., Tables 23 and 24 for details of the Protection Groups. Once protected, Program and Erase operations within the protected group fail to change the data. There are three techniques that can be used to control Block Protection, these are the Programmer technique, the In-System technique and Temporary Unprotection. Temporary Unprotection is controlled by the Reset/Block Temporary Unprotection pin, RP; this is described in the Signal Descriptions section. Programmer Technique The Programmer technique uses high (VID) voltage levels on some of the bus pins. These cannot be achieved using a standard microprocessor bus, therefore the technique is recommended only for use in Programming Equipment. To protect a group of blocks follow the flowchart in Figure 20., Programmer Equipment Group Protect Flowchart. To unprotect the whole chip it is necessary to protect all of the groups first, then all groups can be unprotected at the same time. To unprotect the chip follow Figure 21., Programmer Equipment Chip Unprotect Flowchart. Table 32., Programmer Technique Bus Operations, BYTE = VIH or VIL, gives a summary of each operation. The timing on these flowcharts is critical. Care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. Do not abort the procedure before reaching the end. Chip Unprotect can take several seconds and a user message should be provided to show that the operation is progressing. In-System Technique The In-System technique requires a high voltage level on the Reset/Blocks Temporary Unprotect pin, RP(1). This can be achieved without violating the maximum ratings of the components on the microprocessor bus, therefore this technique is suitable for use after the memory has been fitted to the system. To protect a group of blocks follow the flowchart in Figure 22., In-System Equipment Group Protect Flowchart. To unprotect the whole chip it is necessary to protect all of the groups first, then all the groups can be unprotected at the same time. To unprotect the chip follow Figure 23., In-System Equipment Chip Unprotect Flowchart. The timing on these flowcharts is critical. Care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. Do not allow the microprocessor to service interrupts that will upset the timing and do not abort the procedure before reaching the end. Chip Unprotect can take several seconds and a user message should be provided to show that the operation is progressing. Note: 1. RP can be either at VIH or at VID when using the In-System Technique to protect the Extended Block. Table 32. Programmer Technique Bus Operations, BYTE = VIH or VIL E G W Address Inputs A0-A20 Data Inputs/Outputs DQ15A–1, DQ14-DQ0 Block (Group) Protect(1) VIL VID VIL Pulse A9 = VID, A12-A20 Block Address Others = X X Chip Unprotect VID VID VIL Pulse A9 = VID, A12 = VIH, A15 = VIH Others = X X Block (Group) Protection Verify VIL VIL VIH A0 = VIL, A1 = VIH, A6 = VIL, A9 = VID, A12-A20 Block Address Others = X Pass = XX01h Retry = XX00h Block (Group) Unprotection Verify VIL VIL VIH A0 = VIL, A1 = VIH, A6 = VIH, A9 = VID, A12-A20 Block Address Others = X Retry = XX01h Pass = XX00h Operation Note: 1. Block Protection Groups are shown in APPENDIX A., Tables 23 and 24. 44/51 M29DW323DT, M29DW323DB Figure 20. Programmer Equipment Group Protect Flowchart START Set-up ADDRESS = GROUP ADDRESS W = VIH n=0 G, A9 = VID, E = VIL Protect Wait 4µs W = VIL Wait 100µs W = VIH E, G = VIH, A0, A6 = VIL, A1 = VIH E = VIL Verify Wait 4µs G = VIL Wait 60ns Read DATA DATA NO = 01h YES A9 = VIH E, G = VIH ++n = 25 NO End YES PASS A9 = VIH E, G = VIH FAIL AI05574 Note: Block Protection Groups are shown in APPENDIX D., Tables 23 and 24. 45/51 M29DW323DT, M29DW323DB Figure 21. Programmer Equipment Chip Unprotect Flowchart START Set-up PROTECT ALL GROUPS n=0 CURRENT GROUP = 0 A6, A12, A15 = VIH(1) E, G, A9 = VID Unprotect Wait 4µs W = VIL Wait 10ms W = VIH E, G = VIH ADDRESS = CURRENT GROUP ADDRESS A0 = VIL, A1, A6 = VIH E = VIL Wait 4µs G = VIL INCREMENT CURRENT GROUP Verify Wait 60ns Read DATA NO End NO DATA = 00h YES ++n = 1000 YES YES A9 = VIH E, G = VIH A9 = VIH E, G = VIH FAIL PASS Note: Block Protection Groups are shown in APPENDIX D., Tables 23 and 24. 46/51 LAST GROUP NO AI05575 M29DW323DT, M29DW323DB Figure 22. In-System Equipment Group Protect Flowchart Set-up START n=0 RP = VID Protect WRITE 60h ADDRESS = GROUP ADDRESS A0 = VIL, A1 = VIH, A6 = VIL WRITE 60h ADDRESS = GROUP ADDRESS A0 = VIL, A1 = VIH, A6 = VIL Wait 100µs Verify WRITE 40h ADDRESS = GROUP ADDRESS A0 = VIL, A1 = VIH, A6 = VIL Wait 4µs READ DATA ADDRESS = GROUP ADDRESS A0 = VIL, A1 = VIH, A6 = VIL DATA NO = 01h YES End RP = VIH ISSUE READ/RESET COMMAND PASS ++n = 25 NO YES RP = VIH ISSUE READ/RESET COMMAND FAIL AI05576 Note: 1. Block Protection Groups are shown in APPENDIX D., Tables 23 and 24. 2. RP can be either at VIH or at VID when using the In-System Technique to protect the Extended Block. 47/51 M29DW323DT, M29DW323DB Figure 23. In-System Equipment Chip Unprotect Flowchart START Set-up PROTECT ALL GROUPS n=0 CURRENT GROUP = 0 RP = VID WRITE 60h ANY ADDRESS WITH A0 = VIL, A1 = VIH, A6 = VIH Unprotect WRITE 60h ANY ADDRESS WITH A0 = VIL, A1 = VIH, A6 = VIH Wait 10ms Verify WRITE 40h ADDRESS = CURRENT GROUP ADDRESS A0 = VIL, A1 = VIH, A6 = VIH Wait 4µs READ DATA ADDRESS = CURRENT GROUP ADDRESS A0 = VIL, A1 = VIH, A6 = VIH NO End NO DATA = 00h ++n = 1000 YES INCREMENT CURRENT GROUP YES LAST GROUP NO YES RP = VIH RP = VIH ISSUE READ/RESET COMMAND ISSUE READ/RESET COMMAND FAIL PASS AI05577 Note: Block Protection Groups are shown in APPENDIX D., Tables 23 and 24. 48/51 M29DW323DT, M29DW323DB REVISION HISTORY Table 33. Document Revision History Date Version Revision Details 20-Sep-2001 -01 26-Oct-2001 -02 Document expanded to full Product Preview 16-Jan-2002 -03 Corrections made in “Primary Algorithm-Specific Extended Query” Table in Appendix-B 19-Apr-2002 -04 Description of Ready/Busy signal clarified (and Figure 16. modified) Clarified allowable commands during block erase Clarified the mode the device returns to in the CFI Read Query command section tPLYH (time to reset device) re-specified. 24-Apr-2002 -05 Values for addresses 23h and 25h corrected in CFI Query System Interface Information table in Appendix B 19-Jul-2002 -06 When in Extended Block mode, the block at the boot block address can be used as OTP. Data Toggle Flow chart corrected. Document promoted from “Product Preview” to “Preliminary Data”. 08-Apr-2003 6.1 Revision numbering modified: a minor revision will be indicated by incrementing the digit after the dot, and a major revision, by incrementing the digit before the dot (revision version 06 equals 6.0). Revision History moved to end of document. TFBGA48, 6 x 8mm, 0.80mm pitch package added. Identification Current IID removed from Table 14., DC Characteristics. Erase Suspend Latency time and Data Retention parameters and notes added to Table 7., Program, Erase Times and Program, Erase Endurance Cycles. APPENDIX C., EXTENDED MEMORY BLOCK, added. Auto Select Command sued to read the Extended Memory Block. Extended Memory Block Verify Code row added to Tables 3 and 4, Bus Operations, BYTE = VIL and Bus Operations, BYTE = VIH. Bank Address modified in Auto Select Command. Chip Erase Address modified in Table 8., Status Register Bits. VSS pin connection to ground clarified. Note added to Table 22., Ordering Information Scheme. 07-May-2003 6.2 Table 20., TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Package Mechanical Data, and Figure 18., TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Bottom View Package Outline, corrected. 25-Jun-2003 7.0 Document promoted from Preliminary Data to full Datasheet status. Packing option added to Table 22., Ordering Information Scheme. 18-Sep-2003 7.1 Status of Ready/Busy signal for Erase Suspend Operation modified in Table 8., Status Register Bits. Figures 14 and 15, Toggle and Alternative Toggle Bits Mechanisms added. Table 18., Toggle and Alternative Toggle Bits AC Characteristics, added. Note 1 of Table 28., Device Geometry Definition, modified 07-Oct-2003 7.2 Figures 14 and 15, Toggle and Alternative Toggle Bits Mechanisms modified and Notes 1 and 2 added. Table 18., Toggle and Alternative Toggle Bits AC Characteristics modified. Figure 8. renamed and flowchart modified; Note added. 07-Nov-2003 7.3 Status of Ready/Busy signal for Program Error, Chip Erase and Block Erase modified in Table 8., Status Register Bits. First Issue (Target Specification) 49/51 M29DW323DT, M29DW323DB Date Version Revision Details 19-Dec-2003 7.4 VCC minimum value updated in Table 12., Operating and AC Measurement Conditions. VPP and IPP test conditions updated in Table 14., DC Characteristics. Architecture option updated in Table 22. Ordering Information Scheme. Block Protect/Unprotect code updated in APPENDIX B., Table 29. Customer Lockable Extended Block mechanism modified in APPENDIX C., Extended Memory Block. APPENDIX D., Block Protection updated: Note 1 added in the In-System Technique section and Note 2 added below Figure 22., In-System Equipment Group Protect Flowchart. Introduction of the STATUS REGISTER chapter clarified. 23-Mar-2004 8.0 12-July-2004 9.0 90ns speed class removed from datasheet. 12-Aug-2004 10.0 Section , DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE added. 27-Sep-2004 11.0 TFBGA63 package removed. 10-Dec-2004 12.0 Status of Ready/Busy signal for Program Error, Chip Erase and Block Erase modified in Table 8., Status Register Bits. 14-Mar-2005 13.0 RB updated in Table 8., Status Register Bits. Fast Program Commands restructured and updated. Unlock Bypass Command updated. 27-Mar-2008 14.0 Applied Numonyx branding. 50/51 M29DW323DT, M29DW323DB Please Read Carefully: INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. 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Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 11/5/7, Numonyx, B.V., All Rights Reserved. 51/51