AD AD9244-40PCB 14-bit, 40 msps/65 msps a/d converter Datasheet

14-Bit, 40 MSPS/65 MSPS A/D Converter
AD9244
FEATURES
FUNCTIONAL BLOCK DIAGRAM
AVDD
REFT REFB
DRVDD
AD9244
VIN+
DFS
14
10-STAGE
PIPELINE ADC
SHA
VIN–
CLK+
CLK–
OTR
OUTPUT
REGISTER
TIMING
DCS
14
D13 TO D0
REFERENCE
OEB
AGND CML
VR
VREF SENSE REF DGND
GND
02404-001
14-bit, 40 MSPS/65 MSPS ADC
Low power
550 mW at 65 MSPS
300 mW at 40 MSPS
On-chip reference and sample-and-hold
750 MHz analog input bandwidth
SNR > 73 dBc to Nyquist @ 65 MSPS
SFDR > 86 dBc to Nyquist @ 65 MSPS
Differential nonlinearity error = ±0.7 LSB
Guaranteed no missing codes over full temperature range
1 V to 2 V p-p differential full-scale analog input range
Single 5 V analog supply, 3.3 V/5 V driver supply
Out-of-range indicator
Straight binary or twos complement output data
Clock duty cycle stabilizer
Output-enable function
48-lead LQFP package
Figure 1.
APPLICATIONS
Communication subsystems (microcell, picocell)
Medical and high-end imaging equipment
Test and measurement equipment
GENERAL DESCRIPTION
The AD9244 is a monolithic, single 5 V supply, 14-bit,
40 MSPS/65 MSPS ADC with an on-chip, high performance
sample-and-hold amplifier (SHA) and voltage reference.
The AD9244 uses a multistage differential pipelined architecture with output error correction logic to provide 14-bit
accuracy at 40 MSPS/65 MSPS data rates, and guarantees no
missing codes over the full operating temperature range.
The AD9244 has an on-board, programmable voltage reference.
An external reference can also be used to suit the dc accuracy
and temperature drift requirements of the application.
A differential or single-ended clock input controls all internal
conversion cycles. The digital output data can be presented in
straight binary or in twos complement format. An out-of-range
(OTR) signal indicates an overflow condition that can be used
with the most significant bit to determine low or high overflow.
Fabricated on an advanced CMOS process, the AD9244 is
available in a 48-lead LQFP and is specified for operation over
the industrial temperature range (–40°C to +85°C).
PRODUCT HIGHLIGHTS
1. Low Power—The AD9244, at 550 mW, consumes a fraction
of the power of currently available ADCs in existing high
speed solutions.
2. IF Sampling—The AD9244 delivers outstanding
performance at input frequencies beyond the first Nyquist
zone. Sampling at 65 MSPS with an input frequency of
100 MHz, the AD9244 delivers 71 dB SNR and 86 dB SFDR.
3. Pin Compatibility—The AD9244 offers a seamless
migration from the 12-bit, 65 MSPS AD9226.
4. On-Board Sample-and-Hold (SHA)—The versatile SHA
input can be configured for either single-ended or
differential inputs.
5. Out-of-Range (OTR) Indicator—The OTR output bit
indicates when the input signal is beyond the AD9244’s
input range.
6. Single Supply—The AD9244 uses a single 5 V power
supply, simplifying system power supply design. It also
features a separate digital output driver supply to
accommodate 3.3 V and 5 V logic families.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
AD9244* PRODUCT PAGE QUICK LINKS
Last Content Update: 09/27/2017
COMPARABLE PARTS
TOOLS AND SIMULATIONS
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• Visual Analog
• AD9244 IBIS Models
EVALUATION KITS
• AD9244 Evaluation Board
REFERENCE MATERIALS
Technical Articles
DOCUMENTATION
• Buffer Adapts Single-ended Signals for Differential Inputs
Application Notes
• AN-1142: Techniques for High Speed ADC PCB Layout
• Correlating High-Speed ADC Performance to Multicarrier
3G Requirements
• AN-282: Fundamentals of Sampled Data Systems
• DNL and Some of its Effects on Converter Performance
• AN-345: Grounding for Low-and-High-Frequency Circuits
• Matching An ADC To A Transformer
• AN-501: Aperture Uncertainty and ADC System
Performance
• MS-2210: Designing Power Supplies for High Speed ADC
• AN-715: A First Approach to IBIS Models: What They Are
and How They Are Generated
DESIGN RESOURCES
• AN-737: How ADIsimADC Models an ADC
• PCN-PDN Information
• AN-741: Little Known Characteristics of Phase Noise
• Quality And Reliability
• AN-742: Frequency Domain Response of SwitchedCapacitor ADCs
• Symbols and Footprints
• AN-756: Sampled Systems and the Effects of Clock Phase
Noise and Jitter
DISCUSSIONS
• AN-807: Multicarrier WCDMA Feasibility
• AN-808: Multicarrier CDMA2000 Feasibility
• AN-827: A Resonant Approach to Interfacing Amplifiers to
Switched-Capacitor ADCs
• AD9244 Material Declaration
View all AD9244 EngineerZone Discussions.
SAMPLE AND BUY
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• AN-835: Understanding High Speed ADC Testing and
Evaluation
TECHNICAL SUPPORT
• AN-905: Visual Analog Converter Evaluation Tool Version
1.0 User Manual
Submit a technical question or find your regional support
number.
• AN-935: Designing an ADC Transformer-Coupled Front
End
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• AD9244: 14-Bit, 40/65 MSPS A/D Converter Data Sheet
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AD9244
TABLE OF CONTENTS
Features .............................................................................................. 1
Terminology .......................................................................................9
Functional Block Diagram .............................................................. 1
Typical Application Circuits ......................................................... 11
Applications....................................................................................... 1
Typical Performance Characteristics ........................................... 12
General Description ......................................................................... 1
Theory of Operation ...................................................................... 17
Product Highlights ........................................................................... 1
Analog Input and Reference Overview ................................... 17
Revision History ............................................................................... 2
Analog Input Operation ............................................................ 18
Specifications..................................................................................... 3
Reference Operation .................................................................. 20
DC Specifications ......................................................................... 3
Digital Inputs and Outputs ....................................................... 21
AC Specifications.......................................................................... 4
Evaluation Board ............................................................................ 26
Digital Specifications ................................................................... 5
Analog Input Configuration ..................................................... 26
Switching Specifications .............................................................. 6
Reference Configuration ........................................................... 26
Absolute Maximum Ratings............................................................ 7
Clock Configuration .................................................................. 26
Explanation of Test Levels ........................................................... 7
Outline Dimensions ....................................................................... 36
ESD Caution.................................................................................. 7
Ordering Guide .......................................................................... 36
Pin Configuration and Function Descriptions............................. 8
REVISION HISTORY
12/05—Rev. B to Rev. C
Updated Format..................................................................Universal
Changes to Figure 45...................................................................... 19
Added Single-Ended Input Configuration Section.................... 19
Added Reference Decoupling Section ......................................... 25
Changes to Figure 65...................................................................... 28
Changes to Figure 66...................................................................... 29
Changes to Figure 67...................................................................... 30
Added Table 15 ............................................................................... 34
2/05—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Table 1.............................................................................3
Changes to Table 2.............................................................................4
Reformatted Table 5 ..........................................................................7
Changes to Table 6.............................................................................8
Changes to Figure 12...................................................................... 12
Changed Captions on Figure 18 and Figure 21 .......................... 13
Changes to Figure 35, Figure 38, Figure 39................................. 16
Changes to Table 9.......................................................................... 18
Changes to Table 13 ....................................................................... 26
Changes to Ordering Guide .......................................................... 36
6/03—Rev. 0 to Rev. A
Changes to AC Specifications ..........................................................3
Updated Ordering Guide .................................................................6
Updated Outline Dimensions....................................................... 33
6/02—Revision 0: Initial Version
Rev. C | Page 2 of 36
AD9244
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 5 V, DRVDD = 3 V, fSAMPLE = 65 MSPS (–65) or 40 MSPS (–40), differential clock inputs, VREF = 2 V, external reference,
differential analog inputs, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
DC ACCURACY
No Missing Codes
Offset Error
Gain Error 1
Differential Nonlinearity (DNL) 2
Integral Nonlinearity (INL)2
TEMPERATURE DRIFT
Offset Error
Gain Error (EXT VREF)1
Gain Error (INT VREF) 3
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (2 VREF)
Load Regulation @ 1 mA
Output Voltage Error (1 VREF)
Load Regulation @ 0.5 mA
Input Resistance
INPUT REFERRED NOISE
VREF = 2 V
VREF = 1 V
ANALOG INPUT
Input Voltage Range (Differential)
VREF = 2 V
VREF = 1 V
Common-Mode Voltage
Input Capacitance 4
Input Bias Current 5
Analog Bandwidth (Full Power)
POWER SUPPLIES
Supply Voltages
AVDD
DRVDD
Supply Current
IAVDD
IDRVDD
PSRR
POWER CONSUMPTION
DC Input 6
Sine Wave Input
Temp
Full
Test
Level
VI
Full
Full
Full
Full
25°C
Full
Full
VI
VI
VI
VI
V
V
VI
Full
Full
Full
V
V
V
Full
Full
Full
Full
Full
VI
V
IV
V
V
25°C
25°C
AD9244BST-65
Typ
Max
Min
14
Guaranteed
±0.3
±0.6
Min
14
Guaranteed
±0.3
±0.6
±1.4
±2.0
±1.0
±0.7
±1.4
−4
AD9244BST-40
Typ
Max
±1.4
±2.0
±1.0
±0.6
±1.3
+4
−4
±2.0
±2.3
±25
+4
±2.0
±2.3
±25
±29
Unit
Bits
Bits
% FSR
% FSR
LSB
LSB
LSB
LSB
ppm/°C
ppm/°C
ppm/°C
±29
0.25
5
0.25
5
mV
mV
mV
mV
kΩ
V
V
0.8
1.5
0.8
1.5
LSB rms
LSB rms
Full
Full
Full
25°C
25°C
25°C
V
V
V
V
V
V
2
1
2
1
V p-p
V p-p
V
pF
μA
MHz
Full
Full
IV
IV
Full
Full
Full
V
V
V
109
12
±0.05
Full
Full
V
VI
550
590
0.5
0.5
±15
0.5
4
±15
0.5
10
500
750
4.75
2.7
5
1
4
10
500
750
5.25
5.25
4.75
2.7
5
5.25
5.25
64
8
±0.05
640
300
345
V
V
mA
mA
% FSR
370
mW
mW
Gain error is based on the ADC only (with a fixed 2.0 V external reference).
Measured at maximum clock rate, fIN = 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit.
Includes internal voltage reference error.
4
Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 7 for the equivalent analog input structure.
5
Input bias current is due to the input looking like a resistor that is dependent on the clock rate.
6
Measured with dc input at maximum clock rate.
2
3
Rev. C | Page 3 of 36
AD9244
AC SPECIFICATIONS
AVDD = 5 V, DRVDD = 3 V, fSAMPLE = 65 MSPS (–65) or 40 MSPS (–40), differential clock inputs, VREF = 2 V, external reference,
AIN = –0.5 dBFS, differential analog inputs, unless otherwise noted.
Table 2.
Parameter
SNR 1
fIN = 2.4 MHz
fIN = 15.5 MHz (–1 dBFS)
fIN = 20 MHz
fIN = 32.5 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 200 MHz
SINAD1
fIN = 2.4 MHz
fIN = 20 MHz
fIN = 32.5 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 200 MHz
ENOB
fIN = 2.4 MHz
fIN = 20 MHz
fIN = 32.5 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 200 MHz
THD1
fIN = 2.4 MHz
fIN = 20 MHz
fIN = 32.5 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 200 MHz
Temp
Test
Level
Full
25°C
Full
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
25°C
VI
I
IV
V
VI
I
IV
I
IV
V
V
V
Full
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
25°C
VI
I
VI
I
IV
I
IV
V
V
V
Full
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
25°C
VI
I
VI
I
IV
I
IV
V
V
V
Full
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
25°C
VI
I
VI
I
IV
I
IV
V
V
V
Min
AD9244BST-65
Typ
Max
72.4
Min
AD9244BST-40
Typ
Max
73.4
74.8
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
75.3
72.0
73.7
72.1
74.7
70.8
73.0
69.9
72.2
71.2
67.2
72.8
68.3
72.2
73.2
74.7
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
75.1
72
74.4
70.6
72.6
69.7
71.9
71
59.8
72.4
56.3
11.7
11.9
12.1
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
12.2
11.7
12.1
11.4
11.8
11.3
11.7
11.5
9.6
11.7
9.1
−78.4
−90.0
−80.7
−89.7
−80.4
−89.4
−79.2
−84.6
−78.7
−84.1
−83.0
−60.7
Rev. C | Page 4 of 36
−83.2
−56.6
Unit
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
AD9244
Parameter
WORST HARMONIC (SECOND or THIRD)1
fIN = 2.4 MHz
fIN = 20 MHz
fIN = 32.5 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 200 MHz
SFDR1
fIN = 2.4 MHz
fIN = 15.5 MHz (–1 dBFS)
fIN = 20 MHz
fIN = 32.5 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 200 MHz
1
Temp
Test
Level
25°C
25°C
25°C
25°C
25°C
25°C
V
V
V
V
V
V
Full
25°C
Full
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
25°C
VI
I
IV
V
IV
I
IV
I
IV
V
V
V
Min
AD9244BST-65
Typ
Max
Min
AD9244BST-40
Typ
Max
−94.5
−93.7
−92.8
−86.5
−86.1
−86.2
−60.7
dBc
dBc
dBc
dBc
dBc
dBc
−84.5
−56.6
78.6
82.5
94.5
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
93.7
83
90
81.4
91.8
80.0
86.4
79.5
86.1
86.2
60.7
Unit
84.5
56.6
AC specifications can be reported in dBc (degrades as signal levels are lowered) or in dBFS (always related back to converter full scale).
DIGITAL SPECIFICATIONS
AVDD = 5 V, DRVDD = 3 V, VREF = 2 V, external reference, unless otherwise noted.
Table 3.
Parameter
DIGITAL INPUTS
Logic 1 Voltage (OEB, DRVDD = 3 V)
Logic 1 Voltage (OEB, DRVDD = 5 V)
Logic 0 Voltage (OEB)
Logic 1 Voltage (DFS, DCS)
Logic 0 Voltage (DFS, DCS)
Input Current
Input Capacitance
CLOCK INPUT PARAMETERS
Differential Input Voltage
CLK− Voltage 1
Internal Clock Common-Mode
Single-Ended Input Voltage
Logic 1 Voltage
Logic 0 Voltage
Input Capacitance
Input Resistance
DIGITAL OUTPUTS (DRVDD = 5 V)
Logic 1 Voltage (IOH = 50 μA)
Logic 0 Voltage (IOL = 50 μA)
Logic 1 Voltage (IOH = 0.5 mA)
Logic 0 Voltage (IOL = 1.6 mA)
Temp
Test
Level
AD9244BST-65
Min
Typ
Max
AD9244BST-40
Min
Typ
Max
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
V
2
3.5
2
3.5
Full
Full
Full
IV
IV
V
0.4
0.25
Full
Full
Full
Full
IV
IV
V
V
2
Full
Full
Full
Full
IV
IV
IV
IV
4.5
5
V
V
V
V
V
μA
pF
1.6
V p-p
V
V
0.8
3.5
0.8
3.5
0.8
10
0.8
10
5
0.4
0.25
1.6
2
0.8
0.8
5
100
5
100
4.5
0.1
2.4
Rev. C | Page 5 of 36
0.1
2.4
0.4
Unit
0.4
V
V
pF
kΩ
V
V
V
V
AD9244
Parameter
DIGITAL OUTPUTS (DRVDD = 3 V) 2
Logic 1 Voltage (IOH = 50 μA)
Logic 0 Voltage (IOL = 50 μA)
Logic 1 Voltage (IOH = 0.5 mA)
Logic 0 Voltage (IOL = 1.6 mA)
1
2
Temp
Test
Level
Full
Full
Full
Full
IV
IV
IV
IV
Min
AD9244BST-65
Typ
Max
Min
2.95
AD9244BST-40
Typ
Max
2.95
0.05
0.05
2.8
2.8
0.4
0.4
Unit
V
V
V
V
See the Clock Overview section for more details.
Output voltage levels measured with 5 pF load on each output.
SWITCHING SPECIFICATIONS
AVDD = 5 V, DRVDD = 3 V, unless otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
Maximum Conversion Rate
Minimum Conversion Rate
Clock Period 1
Clock Pulse Width High 2
Clock Pulse Width Low2
Clock Pulse Width High 3
Clock Pulse Width Low3
DATA OUTPUT PARAMETERS
Output Delay (tPD) 4
Pipeline Delay (Latency)
Aperture Delay (tA)
Aperture Uncertainty (Jitter)
Output Enable Delay
OUT-OF-RANGE RECOVERY TIME
Temp
Test
Level
Full
Full
Full
Full
Full
Full
Full
VI
V
V
V
V
V
V
Full
Full
Full
Full
Full
Full
V
V
V
V
V
V
Min
AD9244BST-65
Typ
Max
Min
65
AD9244BST-40
Typ
Max
40
500
500
15.4
4
4
6.9
6.9
25
4
4
11.3
11.3
3.5
7
3.5
7
8
1.5
0.3
15
2
Unit
MHz
kHz
ns
ns
ns
ns
ns
ns
Clock cycles
ns
ps rms
ns
Clock cycles
8
1.5
0.3
15
1
1
The clock period can be extended to 2 μs with no degradation in specified performance at 25°C.
With duty cycle stabilizer enabled.
With duty cycle stabilizer disabled.
4
Measured from clock 50% transition to data 50% transition with 5 pF load on each output.
2
3
N+2
N+3
N+1
N+4
N
N+5
ANALOG INPUT
N+6
N+9
N+7
N+8
tA
CLOCK
N–9
N–8
N–7
N–6
N–5
N–4
N–3
N–2
N–1
N
tPD
Figure 2. Input Timing
Rev. C | Page 6 of 36
N+1
02404-002
DATA OUT
AD9244
ABSOLUTE MAXIMUM RATINGS
Table 5.
With
Parameter
Respect to
ELECTRICAL
AVDD
AGND
DRVDD
DGND
AGND
DGND
AVDD
DRVDD
REFGND
AGND
CLK+, CLK–, DCS
AGND
DFS
AGND
VIN+, VIN–
AGND
VREF
AGND
SENSE
AGND
REFB, REFT
AGND
CML
AGND
VR
AGND
OTR
DGND
D0 to D13
DGND
OEB
DGND
ENVIRONMENTAL 1
Junction Temperature
Storage Temperature
Operating Temperature
Lead Temperature (10 sec)
1
Rating
–0.3 V to +6.5 V
−0.3 V to +6.5 V
–0.3 V to +0.3 V
–6.5 V to +6.5 V
–0.3 V to +0.3 V
–0.3 V to AVDD + 0.3 V
–0.3 V to AVDD + 0.3 V
–0.3 V to AVDD + 0.3 V
–0.3 V to AVDD + 0.3 V
–0.3 V to AVDD + 0.3 V
–0.3 V to AVDD + 0.3 V
–0.3 V to AVDD + 0.3 V
–0.3 V to AVDD + 0.3 V
–0.3 V to DRVDD + 0.3 V
–0.3 V to DRVDD + 0.3 V
–0.3 V to DRVDD + 0.3 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum ratings for extended periods may affect
device reliability.
EXPLANATION OF TEST LEVELS
Table 6.
Test
Level
I
II
III
IV
V
VI
150°C
−65°C to +150°C
−40°C to +85°C
300°C
Description
100% production tested.
100% production tested at 25°C and sample tested at
specified temperatures.
Sample tested only.
Parameter is guaranteed by design and characterization
testing.
Parameter is a typical value only.
100% production tested at 25°C; guaranteed by design
and characterization testing for industrial temperature
range; 100% production tested at temperature extremes
for military devices.
Typical thermal impedances; θJA = 50.0°C/W; θJC = 17.0°C/W. These
measurements were taken on a 4-layer board in still air, in accordance with
EIA/JESD51-7.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. C | Page 7 of 36
AD9244
48 47 46 45 44 43 42
VREF
REFGND
REFB
REFB
REFT
REFT
DCS
NIC
CML
VIN+
VIN–
VR
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
41 40 39 38 37
AGND 1
36 SENSE
PIN 1
AGND 2
35 DFS
AVDD 3
34 AVDD
AVDD 4
33 AGND
AGND 5
AD9244
CLK– 6
TOP VIEW
(Not to Scale)
CLK+ 7
32 AGND
31 AVDD
30 DGND
NIC 8
29 DRVDD
OEB 9
28 OTR
D0 (LSB) 10
27 D13 (MSB)
D1 11
26 D12
D2 12
25 D11
02404-003
D10
DRVDD
DGND
D9
D8
D7
D6
D5
D4
DRVDD
D3
DGND
13 14 15 16 17 18 19 20 21 22 23 24
Figure 3. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
1, 2, 5, 32, 33
3, 4, 31, 34
6, 7
8, 44
9
10
11 to 13,
16 to 21,
24 to 26
14, 22, 30
15, 23, 29
27
28
35
36
37
38
39 to 42
43
Mnemonic
AGND
AVDD
CLK–, CLK+
NIC
OEB
D0 (LSB)
D1 to D3,
D4 to D9,
D10 to D12
DGND
DRVDD
D13 (MSB)
OTR
DFS
SENSE
VREF
REFGND
REFB, REFT
DCS
45
46, 47
48
CML
VIN+, VIN–
VR
Description
Analog Ground.
Analog Supply Voltage.
Differential Clock Inputs.
No Internal Connection.
Digital Output Enable (Active Low).
Least Significant Bit, Digital Output.
Digital Outputs.
Digital Ground.
Digital Supply Voltage.
Most Significant Bit, Digital Output.
Out-of-Range Indicator (Logic 1 Indicates OTR).
Data Format Select. Connect to AGND for straight binary, AVDD for twos complement.
Internal Reference Control.
Internal Reference.
Reference Ground.
Internal Reference Decoupling.
50% Duty Cycle Stabilizer. Connect to AVDD to activate 50% duty cycle stabilizer, AGND for
external control of both clock edges.
Common-Mode Reference (0.5 × AVDD).
Differential Analog Inputs.
Internal Bias Decoupling.
Rev. C | Page 8 of 36
AD9244
TERMINOLOGY
Analog Bandwidth (Full Power Bandwidth)
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between the 50% point of the rising edge of the clock
and the instant at which the analog input is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Analog Input Voltage Range
The peak-to-peak differential voltage must be applied to the
converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage on a single pin
and subtracting the voltage from the other pin, which is 180°
out of phase. Peak-to-peak differential is computed by rotating
the input phase 180° and taking the peak measurement again. The
difference is then found between the two peak measurements.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 14-bit resolution indicates that all 16,384
codes must be present over all operating ranges.
Dual-Tone SFDR 1
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product.
Effective Number of Bits (ENOB)
The ENOB for a device for sine wave inputs at a given input
frequency can be calculated directly from its measured SINAD by
N = (SINAD − 1.76)/6.02
Gain Error
The first code transition should occur at an analog value ½ LSB
above negative full scale. The last code transition should occur
at an analog value 1½ LSB below the nominal full scale. Gain
error is the deviation of the actual difference between first and
last code transitions and the ideal difference between first and
last code transitions.
Common-Mode Rejection Ratio (CMRR)
Common-mode (CM) signals appearing on VIN+ and VIN–
are ideally rejected by the differential front end of the ADC.
With a full-scale CM signal driving both VIN+ and VIN–,
CMRR is the ratio of the amplitude of the full-scale input CM
signal to the amplitude of signal that is not rejected, expressed
in dBFS.1
IF Sampling
Due to the effects of aliasing, an ADC is not necessarily limited
to Nyquist sampling. Higher sampled frequencies are aliased
down into the first Nyquist zone (DC − fCLOCK/2) on the output
of the ADC. Care must be taken that the bandwidth of the sampled signal does not overlap Nyquist zones and alias onto itself.
Nyquist sampling performance is limited by the bandwidth of
the input SHA and clock jitter (noise caused by jitter increases
as the input frequency increases).
Integral Nonlinearity (INL)
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each particular code to the true straight line.
Minimum Conversion Rate
The clock rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The clock rate at which parametric testing is performed.
Nyquist Sampling
When the frequency components of the analog input are below
the Nyquist frequency (fCLOCK/2).
Out-of-Range Recovery Time
The time it takes for the ADC to reacquire the analog input
after a transition from 10% above positive full scale to 10%
above negative full scale, or from 10% below negative full scale
to 10% below positive full scale.
Power Supply Rejection Ratio (PSRR)
The change in full scale from the value with the supply at its
minimum limit to the value with the supply at its maximum limit.
Signal-to-Noise-and-Distortion (SINAD)1
The ratio of the rms signal amplitude to the rms value of the
sum of all other spectral components below the Nyquist
frequency, including harmonics, but excluding dc.
T
Signal-to-Noise Ratio (SNR)1
The ratio of the rms signal amplitude to the rms value of the
sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc.
Rev. C | Page 9 of 36
AD9244
Spurious-Free Dynamic Range (SFDR)1
The difference in dB between the rms amplitude of the input
signal and the peak spurious signal.
Total Harmonic Distortion (THD)1
The ratio of the rms sum of the first six harmonic components
to the rms value of the measured input signal.
Temperature Drift
The temperature drift for offset error and gain error specifies
the maximum change from initial (25°C) value to the value at
TMIN or TMAX.
Offset Error
The major carry transition should occur for an analog value
½ LSB below VIN+ = VIN−. Offset error is defined as the
deviation of the actual transition from that point.
1
AC specifications can be reported in dBc (degrades as signal levels are
lowered) or in dBFS (always related back to converter full scale).
Rev. C | Page 10 of 36
AD9244
TYPICAL APPLICATION CIRCUITS
DRVDD
DRVDD
DGND
02404-007
02404-004
AVDD
AGND
Figure 4. D0 to D13, OTR
Figure 7. VIN+, VIN−
AVDD
DRVDD
02404-005
DGND
02404-008
200Ω
200Ω
AGND
Figure 5. Three-State (OEB)
Figure 8. DFS, DCS, SENSE
AVDD
AVDD
AGND
AGND
Figure 6. CLK+, CLK−
02404-009
CLK
BUFFER
02404-006
200Ω
Figure 9. VREF, REFT, REFB, VR, CML
Rev. C | Page 11 of 36
AD9244
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 5.0 V, DRVDD = 3.0 V, fSAMPLE = 65 MSPS with CLK duty cycle stabilizer enabled, TA = 25°C, differential analog input, commonmode voltage (VCM) = 2.5 V, input amplitude (AIN) = −0.5 dBFS, VREF = 2.0 V external, FFT length = 8K, unless otherwise noted.
0
100
SNR = 74.8dBc
SFDR = 93.6dBc
–20
90
–40
80
SFDR (dBFS)
dBFS AND dBc
–60
–80
SNR (dBFS)
70
SFDR = 90dBc
REFERENCE LINE
60
0
5
10
15
20
FREQUENCY (MHz)
25
30 32.5
40
–30
02404-010
–120
–25
–20
–15
AIN (dBFS)
–10
–5
0
02404-013
50
–100
Figure 13. Single-Tone SNR/SFDR vs. AIN, fIN = 5 MHz
Figure 10. Single-Tone FFT, fIN = 5 MHz
100
0
SNR = 74.0dBc
SFDR = 87.0dBc
SFDR (dBFS)
90
–40
80
–60
–80
SNR (dBFS)
70
SFDR (dBc)
60
SFDR = 90dBc
REFERENCE LINE
50
–100
0
5.0
10.0
15.0
20.0
FREQUENCY (MHz)
25.0
30.0 32.5
40
30
02404-011
–120
Figure 11. Single-Tone FFT, fIN = 31 MHz
0
SNR (dBc)
–25
–20
–15
AIN (dBFS)
–10
–5
0
02404-014
–20
dBFS AND dBc
AMPLITUDE (dBFS)
SNR (dBc)
0
02404-015
AMPLITUDE (dBFS)
SFDR (dBc)
Figure 14. Single-Tone SNR/SFDR vs. AIN, fIN = 31 MHz
100
SNR = 66.5dBc
SFDR = 74.0dBc
–20
90
–40
dBFS AND dBc
80
–60
–80
SNR (dBFS)
70
SFDR (dBc)
60
SFDR = 90dBc
REFERENCE LINE
SNR (dBc)
–100
50
–120
0
5
10
15
20
FREQUENCY (MHz)
25
30
Figure 12. Single-Tone FFT, fIN = 190 MHz, fSAMPLE = 61.44 MSPS
40
–30
02404-012
AMPLITUDE (dBFS)
SFDR (dBFS)
–25
–20
–15
AIN (dBFS)
–10
–5
Figure 15. Single-Tone SNR/SFDR vs. AIN, fIN = 190 MHz, fSAMPLE = 61.44 MSPS
Rev. C | Page 12 of 36
75
12.2
75
73
11.9
73
71
11.5
71
11.2
SNR (dBc)
2V SPAN
69
ENOB (Bits)
SINAD (dBc)
AD9244
2V SPAN
69
1V SPAN
67
65
0
20
40
60
80
100
INPUT FREQUENCY (MHz)
120
10.5
140
65
02404-016
10.8
0
20
Figure 16. SINAD/ENOB vs. Input Frequency
40
60
80
100
INPUT FREQUENCY (MHz)
120
140
02404-019
1V SPAN
67
Figure 19. SNR vs. Input Frequency
–100
100
–95
95
–90
90
SFDR (dBc)
–75
0
20
40
60
80
100
INPUT FREQUENCY (MHz)
2V SPAN
80
2V SPAN
120
140
75
0
20
40
60
80
100
INPUT FREQUENCY (MHz)
120
140
02404-020
–80
85
120
140
02404-021
1V SPAN
–85
02404-017
THD (dBc)
1V SPAN
Figure 20. SFDR vs. Input Frequency
Figure 17. THD vs. Input Frequency
–92
77
–90
75
–88
+25°C
THD (dBc)
73
–40°C
71
–84
–82
–80
+85°C
–78
69
+85°C
–76
67
0
20
40
60
80
100
INPUT FREQUENCY (MHz)
120
140
02404-018
SNR (dBc)
–40°C
–86
+25°C
–74
0
20
40
60
80
100
INPUT FREQUENCY (MHz)
Figure 21. THD vs. Temperature and Input Frequency, DCS Disabled
Figure 18. SNR vs. Temperature and Input Frequency, DCS Disabled
Rev. C | Page 13 of 36
AD9244
–100
100
95
FOURTH
HARMONIC
–95
SFDR, DCS ON
SNR/SFDR (dBc)
HARMONICS (dBc)
90
THIRD
HARMONIC
–90
–85
SECOND
HARMONIC
85
SFDR, DCS OFF
80
75
SNR, DCS ON
60
–80
65
20
40
60
80
100
INPUT FREQUENCY (MHz)
120
140
Figure 22. Harmonics vs. Input Frequency
76
35
40
45
50
55
DUTY CYCLE (%)
65
70
Figure 25. SNR/SFDR vs. Duty Cycle, fIN = 2.5 MHz
12.33
100
fIN = 2MHz
75
60
02404-025
0
SNR, DCS OFF
60
30
02404-022
–75
fIN = 2MHz
12.17
96
11.67
71
11.50
70
0
20
40
60
SAMPE RATE (MSPS)
80
fIN = 10MHz
88
fIN = 20MHz
84
11.34
100
80
0
Figure 23. SINAD/ENOB vs. Sample Rate
20
40
60
SAMPLE RATE (MSPS)
80
100
02404-026
fIN = 20MHz
72
92
16384
02404-027
11.83
SFDR (dBc)
73
ENOB (Bits)
12.00
fIN = 10MHz
02404-023
SINAD (dBc)
74
Figure 26. SFDR vs. Sample Rate
1.5
1.0
0.8
1.0
0.6
0.4
DNL (LSB)
0
–0.5
0.2
0
–0.2
–0.4
–0.6
–1.0
–0.8
–1.5
0
4096
8192
CODES (14-Bit)
12288
16384
02404-024
INL (LSB)
0.5
Figure 24. Typical INL
–1.0
0
4096
8192
CODES (14-Bit)
Figure 27. Typical DNL
Rev. C | Page 14 of 36
12288
AD9244
0
100
SNR = 67.5dBc
SFDR = 93.2dBc
SFDR (dBFS)
–20
90
–40
80
dBFS AND dBc
–60
–80
SNR (dBFS)
70
60
SNR (dBc)
–100
50
0
5.0
10.0
15.0
20.0
FREQUENCY (MHz)
25.0
30.0 32.5
40
–30
02404-028
–120
Figure 28. Dual-Tone FFT with fIN−1 = 44.2 MHz and
fIN−2 = 45.6 MHz (AIN1 = AIN2 = –6.5 dBFS)
–25
–20
–15
AIN (dBFS)
–10
–5
Figure 31. Dual-Tone SNR/SFDR vs. AIN with
fIN−1 = 44.2 MHz and fIN−2 = 45.6 MHz
0
100
SNR = 67.0dBc
SFDR = 78.2dBc
20
90
40
80
dBFS AND dBc
AMPLITUDE (dBFS)
SFDR = 90dBc
REFERENCE LINE
02404-031
AMPLITUDE (dBFS)
SFDR (dBc)
60
80
70
60
100
50
120
40
–30
SFDR (dBFS)
SNR (dBFS)
SFDR (dBc)
SFDR = 90dBc
REFERENCE LINE
10.0
15.0
20.0
FREQUENCY (MHz)
25.0
30.0 32.5
–10
–5
–5
100
SNR = 65.0dBc
SFDR = 69.1dBc
SFDR (dBFS)
90
–40
80
dBFS AND dBc
–20
–60
–80
SNR (dBFS)
70
SFDR (dBc)
60
–100
50
–120
40
–30
SFDR = 90dBc
REFERENCE LINE
SNR (dBc)
0
5.0
10.0
15.0
20.0
FREQUENCY (MHz)
25.0
30.0 32.5
02404-030
AMPLITUDE (dBFS)
–20
–15
AIN (dBFS)
Figure 32. Dual-Tone SNR/SFDR vs. AIN with
fIN−1 = 69.2 MHz and= fIN−2 = 70.6 MHz
Figure 29. Dual-Tone FFT with fiN−1 = 69.2 MHz and
fIN−2 = 70.6 MHz (AIN1 = AIN2 = –6.5 dBFS)
0
–25
02404-032
5.0
02404-033
0
02404-029
SNR (dBc)
Figure 30. Dual-Tone FFT with fIN−1 = 139.2 MHz and
fIN−2 = 140.7 MHz (AIN1 = AIN2 = –6.5 dBFS)
–25
–20
–15
AIN (dBFS)
–10
Figure 33. Dual-Tone SNR/SFDR vs. AIN with
fIN−1 = 139.2 MHz and fIN−2 = 140.7 MHz
Rev. C | Page 15 of 36
AD9244
0
100
–20
90
–40
80
dBFS AND dBc
AMPLITUDE (dBFS)
SNR = 62.6dBc
SFDR = 60.7dBc
–60
–80
–100
SFDR (dBFS)
SNR (dBFS)
70
SFDR (dBc)
60
SFDR = 90dBc
REFERENCE LINE
50
0
5
10
15
20
FREQUENCY (MHz)
25
30.0 32.5
40
–30
02404-034
–120
Figure 34. Dual-Tone with fIN−1 = 239.1 MHz and
fIN−2 = 240.7 MHz (AIN−1 = AIN−2 = –6.5 dBFS)
–25
–20
–15
AIN (dBFS)
–10
–5
02404-037
SNR (dBc)
Figure 37. Dual-Tone SNR/SFDR vs. AIN with
fIN−1 = 239.1 MHz and fIN−2 = 240.7 MHz
0
100
SNR = 71.3dBc
THD = –90.8dBc
–10
95
–20
SFDR (dBFS)
SFDR = 90dBc
REFERENCE LINE
90
85
–40
dBFS AND dBc
AMPLITUDE (dBFS)
–30
–50
–60
–70 NOTE: SPUR FLOOR
BELOW 90dBFS @ 240MHz
–80
SFDR (dBc)
80
SNR (dBFS)
75
70
65
–90
60
–100
SNR (dBc)
5
10
15
20
FREQUENCY (MHz)
25
30
50
–21
–15
–12
–9
AIN (dBFS)
–6
–3
0
0
Figure 38. Driving ADC Inputs with Transformer and
Balun SNR/SFDR vs. AIN, fIN = 240 MHz
95
100
90
95
85
90
80
dBFS AND dBc
105
85
80
SFDR (dBFS)
SFDR (dBc)
SFDR = 90dBc
REFERENCE LINE
75
SNR (dBFS)
70
75
65
70
60
SNR (dBc)
65
0
50
100
150
INPUT FREQUENCY (MHz)
200
250
02404-036
AMPLITUDE (dBFS)
Figure 35. Driving ADC Inputs with Transformer and Balun,
fIN = 240 MHz, AIN = –8.5 dBFS
–18
02404-038
0
02404-035
–120
02404-039
55
–110
55
–21
–18
–15
–12
–9
AIN (dBFS)
–6
–3
Figure 39. Driving ADC Inputs with Transformer and
Balun SNR/SFDR vs. AIN, fIN = 190 MHz
Figure 36. CMRR vs. Input Frequency (AIN = 0 dBFS and CML = 2.5 V)
Rev. C | Page 16 of 36
AD9244
THEORY OF OPERATION
The AD9244 has a duty clock stabilizer (DCS) that generates its
own internal falling edge to create an internal 50% duty cycle
clock, independent of the externally applied duty cycle. Control
of straight binary or twos complement output format is accomplished with the DFS pin.
The ADC samples the analog input on the rising edge of the
clock. While the clock is low, the input SHA is in sample mode.
When the clock transitions to a high logic level, the SHA goes
into the hold mode. System disturbances just prior to or immediately after the rising edge of the clock and/or excessive clock
jitter can cause the SHA to acquire the wrong input value and
should be minimized.
ANALOG INPUT AND REFERENCE OVERVIEW
The differential input span of the AD9244 is equal to the potential at the VREF pin. The VREF potential can be obtained from
the internal AD9244 reference or an external source.
AD9244
33Ω
VIN+
50V
20pF
0.1μF
VIN–
33Ω
2.5V
+
+
0.1μF
2V
1.5V
REFT
VREF
10μF
REFB
0.1μF
10μF
0.1μF
02404-040
SENSE
REFGND
Figure 40. 2 V p-p Differential Input, Common-Mode Voltage = 2 V
3.0V
2.0V
AD9244
33Ω
VIN+
20pF
0.1μF
33Ω
0.1μF
2V
+
REFT
VIN–
VREF
+
10μF
REFB
0.1μF
10μF
0.1μF
SENSE
REFGND
Figure 41. 2 V p-p Single-Ended Input, Common-Mode Voltage = 2 V
2.5V
3.0V
AD9244
0.1pF
2.0V
33Ω
VIN+
50Ω
20pF
33Ω
3.0V
+
REFT
+
0.1μF
2V
2.0V
0.1μF
VIN–
VREF
10μF
REFB
0.1μF
10μF
0.1μF
SENSE
REFGND
02404-042
The pipeline architecture allows a greater throughput rate at the
expense of pipeline delay or latency. While the converter captures a new input sample every clock cycle, it takes eight clock
cycles for the conversion to be fully processed and appear at the
output, as illustrated in Figure 2. This latency is not a concern
in many applications. The digital output, together with the OTR
indicator, is latched into an output buffer to drive the output
pins. The output drivers of the AD9244 can be configured to
interface with 5 V or 3.3 V logic families.
1.5V
02404-041
The AD9244 uses a calibrated 10-stage pipeline architecture
with a patented, wideband, input sample-and-hold amplifier
(SHA) implemented on a cost-effective CMOS process. Each
stage of the pipeline, excluding the last, consists of a low resolution flash ADC along with a switched capacitor DAC and
interstage residue amplifier (MDAC). The MDAC amplifies the
difference between the reconstructed DAC output and the flash
input for the next stage in the pipeline. One bit of redundancy is
used in each of the stages to facilitate digital correction of flash
errors. The last stage simply consists of a flash ADC.
2.5V
Figure 42. 2 V p-p Differential Input, Common-Mode Voltage = 2.5 V
Figure 43 is a simplified model of the AD9244 analog input,
showing the relationship between the analog inputs, VIN+,
VIN–, and the reference voltage, VREF. Note that this is only a
symbolic model and that no actual negative voltages exist inside
the AD9244. Similar to the voltages applied to the top and bottom of the resistor ladder in a flash ADC, the value VREF/2
defines the minimum and maximum input voltages to the
ADC core.
In differential applications, the center point of the input span is
the common-mode level of the input signals. In single-ended
applications, the center point is the dc potential applied to one
input pin while the signal is applied to the opposite input pin.
Figure 40 to Figure 42 show various system configurations.
AD9244
+VREF/2
VIN+
+
–
VCORE
ADC
CORE
14
VIN–
–VREF/2
Figure 43. Equivalent Analog Input of AD9244
Rev. C | Page 17 of 36
02404-043
The AD9244 is a high performance, single-supply 14-bit ADC.
In addition to high dynamic range Nyquist sampling, it is
designed for excellent IF undersampling performance with an
analog input as high as 240 MHz.
AD9244
A differential input structure allows the user to easily configure the
inputs for either single-ended or differential operation. The ADC’s
input structure allows the dc offset of the input signal to be varied
independent of the input span of the converter. Specifically, the
input to the ADC core can be defined as the difference of the
voltages applied at the VIN+ and VIN– input pins.
The range of valid inputs for VIN+ and VIN− is any combination
that satisfies Equation 2, Equation 3, and Equation 4.
For additional information showing the relationship between
VIN+, VIN–, VREF, and the analog input range of the AD9244,
see Table 8 and Table 9.
ANALOG INPUT OPERATION
Therefore, the equation
VCORE = (VIN+) – (VIN−)
(1)
defines the output of the differential input stage and provides
the input to the ADC core. The voltage, VCORE, must satisfy the
condition
−VREF/2 < VCORE < VREF/2
(2)
Figure 44 shows the equivalent analog input of the AD9244,
which consists of a 750 MHz differential SHA. The differential
input structure of the SHA is flexible, allowing the device to be
configured for either a differential or single-ended input. The
analog inputs VIN+ and VIN– are interchangeable, with the
exception that reversing the inputs to the VIN+ and VIN– pins
results in a data inversion (complementing the output word).
where VREF is the voltage at the VREF pin.
S
In addition to the limitations placed on the input voltages VIN+
and VIN– by Equation 1 and Equation 2, boundaries on the
inputs also exist based on the power supply voltages according
to the conditions
(3)
AGND − 0.3 V < VIN− < AVDD + 0.3 V
(4)
CS
CH
VIN+
CPIN, PAR
S
H
CS
VIN–
CH
CPIN, PAR
where:
S
AGND is nominally 0 V.
02404-044
AGND − 0.3 V < VIN+ < AVDD + 0.3 V
S
Figure 44. Analog Input of AD9244 SHA
AVDD is nominally 5 V.
Table 8. Analog Input Configuration Summary
Input
Connection
Single-Ended
Coupling
DC or AC
Input
Span (V)
1.0
2.0
Input Range (V)
VIN+ 1
VIN−1
0.5 to 1.5
1.0
1 to 3
2.0
Input CM
Voltage (V)
1.0
2.0
Differential
DC or AC
1.0
2.25 to 2.75
2.75 to 2.25
2.5
2.0
2.0 to 3.0
3.0 to 2.0
2.5
Comments
Best for stepped input response applications.
Optimum noise performance for single-ended
mode often requires low distortion op amp
with VCC > 5 V due to its headroom issues.
Optimum full-scale THD and SFDR performance
well beyond the ADC’s Nyquist frequency.
Optimum noise performance for differential
mode. Preferred mode for applications.
1
VIN+ and VIN− can be interchanged if data inversion is required.
Table 9. Reference Configuration Summary
Reference Operating Mode
Internal
Internal
Internal
External
Connect
SENSE
SENSE
R1
R2
SENSE
VREF
To
VREF
AGND
VREF and SENSE
SENSE and REFGND
AVDD
EXTERNAL REF
Resulting VREF (V)
1
2
1 ≤ VREF ≤ 2.0
VREF = (1 + R1/R2)
1 ≤ VREF ≤ 2.0
Rev. C | Page 18 of 36
Input Span (VIN+ − VIN−) (V p-p)
1
2
1 ≤ SPAN ≤ 2
(SPAN = VREF)
SPAN = EXTERNAL REF
AD9244
The optimum noise and dc linearity performance for either
differential or single-ended inputs is achieved with the largest
input signal voltage span (that is, 2 V input span) and matched
input impedance for VIN+ and VIN–. Only a slight degradation
in dc linearity performance exists between the 2 V and 1 V
input spans; however, the SNR is lower in the 1 V input span.
When the ADC is driven by an op amp and a capacitive load is
switched onto the output of the op amp, the output momentarily drops due to its effective output impedance. As the output
recovers, ringing can occur. To remedy the situation, a series
resistor, RS, can be inserted between the op amp and the SHA
input, as shown in Figure 45. A shunt capacitance also acts like
a charge reservoir, sinking or sourcing the additional charge
required by the sampling capacitor, CS, further reducing current
transients seen at the op amp’s output.
AD9244
VIN+
CS
20pF
0.1μF
5Ω
RS
33Ω
VIN–
VREF
10μF
0.1μF
SENSE
REFCOM
02404-045
+
The optimum mode of operation, analog input range, and associated interface circuitry is determined by the particular application’s
performance requirements as well as power supply options.
Differential operation requires that VIN+ and VIN− be
simultaneously driven with two equal signals that are 180°out of
phase with each other.
Differential modes of operation (ac-coupled or dc-coupled input)
provide the best SFDR performance over a wide frequency range.
They should be considered for the most demanding spectralbased applications; that is, direct IF conversion to digital.
Figure 45. Resistors Isolating SHA Input from Op Amp
The optimum size of this resistor is dependent on several
factors, including the ADC sampling rate, the selected op amp,
and the particular application. In most applications, a 30 Ω to
100 Ω resistor is sufficient.
For noise-sensitive applications, the very high bandwidth of the
AD9244 can be detrimental, and the addition of a series resistor
and/or shunt capacitor can help limit the wideband noise at the
ADC’s input by forming a low-pass filter. The source impedance
driving VIN+ and VIN− should be matched. Failure to provide
matching can result in degradation of the SNR, THD, and SFDR
performance.
The differential input characterization was performed using the
configuration in Figure 46. The circuit uses a Mini-Circuits® RF
transformer, model T1-1T, which has an impedance ratio of 1:1.
This circuit assumes that the signal source has a 50 Ω source
impedance. The secondary center tap of the transformer allows
a dc common-mode voltage to be added to the differential input
signal. In Figure 46, the center tap is connected to a resistor
divider providing a half supply voltage. It could also be
connected to the CML pin of the AD9244. For IF sampling
applications (70 MHz < fIN < 200 MHz), it is recommended that
the 20 pF differential capacitor between VIN+ and VIN− be
reduced or removed.
AVDD
RS
33Ω
Single-Ended Input Configuration
1kΩ
AD9244
VIN+
A single-ended input can provide adequate performance in
cost-sensitive applications. In this configuration, there is
degradation in distortion performance due to large input
common-mode swing. However, if the source impedances on
each input are matched, there should be little effect on SNR
performance.
0.1μF
REFT
50Ω
20pF
0.1μF
0.1μF
1kΩ
Rev. C | Page 19 of 36
10μF
0.1μF
MINI-CIRCUITS R
S
T1–1T
33Ω
VIN–
Figure 46. Transformer-Coupled Input
The internal reference can be used to drive the inputs. Figure 45
shows an example of VREF driving VIN−. In this operating
mode, a 5 Ω resistor and a 0.1 μF capacitor must be connected
between VREF and VIN−, as shown in Figure 45, to limit the
reference noise sampled by the analog input.
+
REFB
02404-046
VEE
The AD9244 has a very flexible input structure, allowing it to
interface with single-ended or differential inputs.
Because not all applications have a signal precondition for
differential operation, there is often a need to perform a singleended-to-differential conversion. In systems that do not require
dc coupling, an RF transformer with a center tap is the best
method for generating differential input signals for the AD9244.
This provides the benefit of operating the ADC in the differential mode without contributing additional noise or distortion.
An RF transformer also has the added benefit of providing
electrical isolation between the signal source and the ADC.
VCC
RS
33Ω
Differentially Driving the Analog Inputs
AD9244
The circuit in Figure 47 shows a method for applying a differential,
direct-coupled signal to the AD9244. An AD8138 amplifier is used
to derive a differential signal from a single-ended signal.
10μF
+
0.1μF
1kΩ
0V
10μF
+
5V
0.1μF
10μF
1kΩ
499Ω
1V p-p
AVDD
VIN+
33Ω
475Ω
50Ω
0.1μF
REFT
AD9244
AD8138
499Ω
20pF
0.1μF
+
The actual reference voltages used by the internal circuitry of
the AD9244 appear on the REFT and REFB pins. The voltages
on these pins are symmetrical about midsupply or CML. For
proper operation, it is necessary to add a capacitor network to
decouple these pins. Figure 49 shows the recommended
decoupling network. The turn-on time of the reference voltage
appearing between REFT and REFB is approximately 10 ms and
should be taken into consideration in any power-down mode of
operation. The VREF pin should be bypassed to the REFGND
pin with a 10 μF tantalum capacitor in parallel with a low
inductance 0.1 μF ceramic capacitor.
10μF
0.1μF
VREF
REFB
+
0.1μF
10μF
0.1μF
REFT
AD9244
0.1μF1
+
10μF
VIN–
REFGND REFB
0.1μF
1LOCATE
Figure 47. Direct-Coupled Drive Circuit with AD8138 Differential Op Amp
02404-049
33Ω
02404-047
499Ω
AS CLOSE AS POSSIBLE TO REFT/REFB PINS.
Figure 49. Reference Decoupling
REFERENCE OPERATION
The AD9244 contains a band gap reference that provides a pinstrappable option to generate either a 1 V or 2 V output. With
the addition of two external resistors, the user can generate
reference voltages between 1 V and 2 V. Another alternative is
to use an external reference for designs requiring enhanced
accuracy and/or drift performance, as described later in this
section. Figure 48 shows a simplified model of the internal
voltage reference of the AD9244. A reference amplifier buffers a
1 V fixed reference. The output from the reference amplifier,
A1, appears on the VREF pin. As stated earlier, the voltage on
the VREF pin determines the full-scale differential input span
of the ADC.
Pin-Programmable Reference
By shorting the VREF pin directly to the SENSE pin, the internal reference amplifier is placed in a unity gain mode, and the
resulting VREF output is 1 V. By shorting the SENSE pin directly to
the REFGND pin, the internal reference amplifier is configured
for a gain of 2, and the resulting VREF output is 2 V.
Resistor-Programmable Reference
Figure 50 shows an example of how to generate a reference
voltage other than 1.0 V or 2.0 V with the addition of two
external resistors. Use the equation
VREF = 1 V × (1 + R1/R2)
(5)
AD9244
to determine the appropriate values for R1 and R2. These resistors
should be in the 2 kΩ to 10 kΩ range. For the example shown, R1
equals 2.5 kΩ and R2 equals 5 kΩ. From the previous equation, the
resulting reference voltage on the VREF pin is 1.5 V. This sets the
differential input span to 1.5 V p-p. The midscale voltage can also
be set to VREF by connecting VIN− to VREF.
REFT
2.5V
A2
REFB
VREF
1V
3.25V
A1
R
AD9244
33Ω
VIN+
1.75V
20pF
2.5V
33Ω
SENSE
+
LOGIC
R
REFGND
02404-048
DISABLE
A1
Figure 48. Equivalent Reference Circuit
The voltage appearing at the VREF pin and the state of the
internal reference amplifier, A1, are determined by the voltage
present at the SENSE pin. The logic circuitry contains comparators that monitor the voltage at the SENSE pin. The various
reference modes are summarized in Table 9 and are described
in the next few sections.
Rev. C | Page 20 of 36
10μF
0.1μF
0.1μF
VIN–
1.5V
R1
2.5kΩ
R2
5kΩ
REFT
0.1μF
VREF
SENSE
+
10μF
REFB
0.1μF
REFGND
Figure 50. Resistor-Programmable Reference
(1.5 V p-p Input Span, Differential Input with VCM = 2.5 V)
02404-050
TO
ADC
AD9244
Using an External Reference
Digital Outputs
To use an external reference, the internal reference must be disabled by connecting the SENSE pin to AVDD. The AD9244
contains an internal reference buffer, A2 (see Figure 48), that
simplifies the drive requirements of an external reference. The
external reference must be able to drive a 5 kΩ (±20%) load.
The bandwidth of the reference is deliberately left small to
minimize the reference noise contribution. As a result, it is not
possible to drive VREF externally with high frequencies.
Table 10 details the relationship among the ADC input, OTR,
and digital output format.
Data Format Select (DFS)
The AD9244 can be programmed for straight binary or twos
complement data on the digital outputs. Connect the DFS pin to
AGND for straight binary and to AVDD for twos complement.
Digital Output Driver Considerations
Figure 51 shows an example of an external reference driving
both VIN– and VREF. In this case, both the common-mode
voltage and input span are directly dependent on the value of
VREF. Both the input span and the center of the input span are
equal to the external VREF. Thus, the valid input range extends
from (VREF + VREF/2) to (VREF − VREF/2). For example, if
the Precision Reference Part REF191, a 2.048 V external reference, is used, the input span is 2.048 V. In this case, 1 LSB of the
AD9244 corresponds to 0.125 mV.
The AD9244 output drivers can be configured to interface with
5 V or 3.3 V logic families by setting DRVDD to 5 V or 3.3 V,
respectively. The output drivers are sized to provide sufficient
output current to drive a wide variety of logic families.
However, large drive currents tend to cause glitches on the
supplies and can affect converter performance. Applications
requiring the ADC to drive large capacitive loads or large
fanouts can require external buffers or latches.
It is essential that a minimum of a 10 μF capacitor, in parallel
with a 0.1 μF low inductance ceramic capacitor, decouple the
reference output to AGND.
VREF + VREF/2
33Ω
20pF
0.1μF
10μF
+ 33Ω
0.1μF
VIN–
REFT
0.1μF
VREF
10μF
REFB
0.1μF
AVDD
+
0.1μF
SENSE
02404-051
VREF
5V
AD9244
VIN+
VREF – VREF/2
Figure 51. Using an External Reference
DIGITAL INPUTS AND OUTPUTS
Table 10. Output Data Format
Input (V)
VIN+ – VIN−
VIN+ – VIN−
VIN+ – VIN−
VIN+ – VIN−
VIN+ – VIN−
Condition (V)
< –VREF/2 − 0.5 LSB
= −VREF/2
=0
= +VREF/2 − 1.0 LSB
> +VREF/2 − 0.5 LSB
Binary Output Mode
00 0000 0000 0000
00 0000 0000 0000
10 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1111
Rev. C | Page 21 of 36
Twos Complement Mode
10 0000 0000 0000
10 0000 0000 0000
00 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1111
OTR
1
0
0
0
1
AD9244
Out of Range (OTR)
Digital Output Enable Function (OEB)
An out-of-range condition exists when the analog input voltage
is beyond the input range of the ADC. OTR is a digital output
that is updated along with the data output corresponding to the
particular sampled input voltage. Thus, OTR has the same pipeline latency as the digital data. OTR is low when the analog
input voltage is within the analog input range and high when
the analog input voltage exceeds the input range, as shown in
Figure 52. OTR remains high until the analog input returns to
within the input range and another conversion is completed.
The AD9244 has three-state ability. If the OEB pin is low, the
output data drivers are enabled. If the OEB pin is high, the output data drivers are placed in a high impedance state. The
three-state ability is not intended for rapid access to the data
bus. Note that OEB is referenced to the digital supplies
(DRVDD) and should not exceed that supply voltage.
By logically AND’ing OTR with the MSB and its complement,
overrange high or underrange low conditions can be detected.
Table 11 is a truth table for the overrange/underrange circuit in
Figure 53, which uses NAND gates. Systems requiring
programmable gain conditioning of the AD9244 can after eight
clock cycles detect an OTR condition, thus eliminating gain
selection iterations. In addition, OTR can be used for digital
offset and gain calibration.
OTR DATA OUTPUTS
1 1111 1111 1111
0 1111 1111 1111
0 1111 1111 1110
+FS – 1 LSB
OTR
–FS + 1/2 LSB
The AD9244 has a flexible clock interface that accepts either a
single-ended or differential clock. An internal bias voltage
facilitates ac coupling using two external capacitors. To remain
backward compatible with the single-pin clock scheme of the
AD9226, the AD9244 can be operated with a dc-coupled,
single-pin clock by grounding the CLK− pin and driving CLK+.
When the CLK− pin is not grounded, the CLK+ and CLK– pins
function as a differential clock receiver. When CLK+ is greater
than CLK–, the SHA is in hold mode; when CLK+ is less than
CLK–, the SHA is in track mode (see Figure 54 for timing). The
rising edge of the clock (CLK+ – CLK–) switches the SHA from
track to hold, and timing jitter on this transition should be minimized, especially for high frequency analog inputs.
CLK–
0000 0000 0001
0000 0000 0000
0000 0000 0000
–FS
–FS – 1/2 LSB
+FS
+FS – 1/2 LSB
02404-052
0
0
1
Clock Overview
CLK+
SHA IN
HOLD
Figure 52. OTR Relation to Input Voltage and Output Data
SHA IN
TRACK
Table 11. Output Data Format
MSB
0
1
0
1
MSB
Analog Input Is
Within range
Within range
Underrange
Overrange
CLK–
CLK+
Figure 54. SHA Timing
OVER = 1
UNDER = 1
Figure 53. Overrange/Underrange Logic
02404-053
OTR
MSB
02404-054
OTR
0
0
1
1
It is often difficult to maintain a 50% duty cycle to the ADC,
especially when driving the clock with a single-ended or sine
wave input. To ease the constraint of providing an accurate 50%
clock, the ADC has an optional internal duty cycle stabilizer
(DCS) that allows the rising clock edge to pass through with
minimal jitter, and interpolates the falling edge, independent of
the input clock falling edge. The DCS is described in greater
detail in the Clock Stabilizer (DCS) section.
Rev. C | Page 22 of 36
AD9244
Clock Input Modes
CLK+
Figure 55 to Figure 59 illustrate the modes of operation of the
clock receiver. Figure 55 shows a differential clock directly
coupled to CLK+ and CLK–. In this mode, the common mode
of the CLK+ and CLK– signals should be close to 1.6 V. Figure 56
illustrates a single-ended clock input. The capacitor decouples
the internal bias voltage on the CLK– pin (about 1.6 V), establishing a threshold for the CLK+ pin. Figure 57 provides
backward compatibility with the AD9226. In this mode, CLK−
is grounded, and the threshold for CLK+ is 1.5 V. Figure 58
shows a differential clock ac-coupled by connecting through
two capacitors. AC coupling a single-ended clock can also be
accomplished using the circuit in Figure 59.
1.6V
AD9244
CLK–
02404-056
0.1μF
AGND
Figure 56. Single-Ended Clock Input, DC-Coupled
CLK+
AD9244
02404-057
CLK–
AGND
Figure 57. Single-Ended Input, Retains Pin Compatibility with AD9226
When using the differential clock circuits of Figure 55 or Figure 58,
if CLK− drops below 250 mV, the mode of the clock receiver
may change, causing conversion errors. It is essential that CLK−
remains above 250 mV when the clock is ac-coupled or dc-coupled.
CLK+
AD9244
02404-058
CLK–
100pF
TO 0.1μF
Clock Input Considerations
Figure 58. Differential Clock Input, AC-Coupled
The analog input is sampled on the rising edge of the clock.
Timing variations, or jitter, on this edge causes the sampled
input voltage to be in error by an amount proportional to the
slew rate of the input signal and to the amount of the timing
variation. Thus, to maintain the excellent high frequency SFDR
and SNR characteristics of the AD9244, it is essential that the
clock edge be kept as clean as possible.
0.1μF
CLK+
1.6V
AD9244
CLK–
02404-059
0.1μF
AGND
The clock should be treated like an analog signal. Clock drivers
should not share supplies with digital logic or noisy circuits.
The clock traces should not run parallel to noisy traces. Using a
pair of symmetrically routed, differential clock signals can help
to provide immunity from common-mode noise coupled from
the environment.
Most of the power dissipated by the AD9244 is from the analog
power supplies. However, lower clock speeds reduce digital
supply current. Figure 60 shows the relationship between power
and clock rate.
600
550
AD9244-65
500
02404-055
AD9244
450
400
350
AD9244-40
300
Figure 55. Differential Clock Input, DC-Coupled
250
200
0
10
20
30
40
50
SAMPLE RATE (MHz)
60
Figure 60. Power Consumption vs. Sample Rate
Rev. C | Page 23 of 36
70
02404-060
CLK+
CLK–
Clock Power Dissipation
POWER (mW)
The clock receiver functions like a differential comparator. At
the CLK inputs, a slowly changing clock signal results in more
jitter than a rapidly changing one. Driving the clock with a low
amplitude sine wave input is not recommended. Running a high
speed clock through a divider circuit provides a fast rise/fall
time, resulting in the lowest jitter in most systems.
Figure 59. Single-Ended Clock Input, AC-Coupled
AD9244
Clock Stabilizer (DCS)
Analog Supply Decoupling
The clock stabilizer circuit in the AD9244 desensitizes the ADC
from clock duty cycle variations. System clock constraints are
eased by internally restoring the clock duty cycle to 50%,
independent of the clock input duty cycle. Low jitter on the
rising edge (sampling edge) of the clock is preserved while the
falling edge is generated on-chip.
The AD9244 features separate analog and digital supply and
ground circuits, helping to minimize digital corruption of
sensitive analog signals. In general, AVDD (analog power)
should be decoupled to AGND (analog ground). The AVDD
and AGND pins are adjacent to one another. Figure 61 shows
the recommended decoupling for each pair of analog supplies;
0.1 μF ceramic chip and 10 μF tantalum capacitors should provide adequately low impedance over a wide frequency range.
The decoupling capacitors (especially 0.1 μF) should be located
as close to the pins as possible.
Grounding and Decoupling
Analog and Digital Grounding
Proper grounding is essential in high speed, high resolution
systems. Multilayer printed circuit boards (PCBs) are recommended to provide optimal grounding and power distribution.
The use of power and ground planes offers distinct advantages,
including:
•
The minimization of the loop area encompassed by a signal
and its return path
•
The minimization of the impedance associated with ground
and power paths
•
The inherent distributed capacitor formed by the power
plane, PCB material, and ground plane
It is important to design a layout that minimizes noise from
coupling onto the input signal. Digital input signals should not
be run in parallel with input signal traces and should be routed
away from the input circuitry. While the AD9244 features separate analog and digital ground pins, it should be treated as an
analog component. The AGND and DGND pins must be joined
together directly under the AD9244. A solid ground plane
under the ADC is acceptable if the power and ground return
currents are carefully managed.
10μF
AVDD
+
0.1μF1
AD9244
1LOCATE
AS CLOSE AS POSSIBLE TO SUPPLY PINS.
02404-061
AGND
Figure 61. Analog Supply Decoupling
Digital Supply Decoupling
The digital activity on the AD9244 falls into two categories:
correction logic and output drivers. The internal correction
logic draws relatively small surges of current, mainly during
the clock transitions. The output drivers draw large current
impulses when the output bits change state. The size and
duration of these currents are a function of the load on the
output bits; large capacitive loads should be avoided.
For the digital decoupling shown in Figure 62, 0.1 μF ceramic
chip and 10 μF tantalum capacitors are appropriate. The
decoupling capacitors (especially 0.1 μF) should be located as
close to the pins as possible. Reasonable capacitive loads on the
data pins are less than 20 pF per bit. Applications involving
greater digital loads should consider increasing the digital
decoupling and/or using external buffers/latches.
A complete decoupling scheme also includes large tantalum or
electrolytic capacitors on the power supply connector to reduce
low frequency ripple to insignificant levels.
Rev. C | Page 24 of 36
10μF
DRVDD
+
0.1μF1
AD9244
DGND
1LOCATE
AS CLOSE AS POSSIBLE TO SUPPLY PINS.
Figure 62. Digital Supply Decoupling
02404-062
It may be desirable to disable the clock stabilizer, or necessary
when the clock frequency is varied or completely stopped. Note
that stopping the clock is not recommended with ac-coupled
clocks. Once the clock frequency is changed, more than 100
clock cycles may be required for the clock stabilizer to settle to
the new speed. When the stabilizer is disabled, the internal
switching is directly affected by the clock state. If CLK+ is high,
the SHA is in hold mode; if CLK+ is low, the SHA is in track
mode. Figure 25 shows the benefits of using the clock stabilizer.
Connecting DCS to AVDD implements the internal clock
stabilization function in the AD9244. If the DCS pin is
connected to ground, the AD9244 uses both edges of the
external clock in its internal timing circuitry (see the
Specifications section for timing requirements).
AD9244
Reference Decoupling
VR
The VREF pin should be bypassed to the REFGND pin with a
10 μF tantalum capacitor in parallel with a low inductance
0.1 μF ceramic capacitor. It is also necessary to add a capacitor
network to decouple the REFT and REFB pins. Figure 49 shows
the recommended decoupling networks.
VR is an internal bias point on the AD9244. It must be
decoupled to AGND with a 0.1 μF capacitor.
AD9244
VR
0.1μF
CML
The AD9244 has a midsupply reference point. This is used
within the internal architecture of the AD9244 and must be
decoupled with a 0.1 μF capacitor. It sources or sinks a load of
up to 300 μA. If more current is required, the CML pin should
be buffered with an amplifier.
Rev. C | Page 25 of 36
Figure 63. CML/VR Decoupling
02404-063
CML
0.1μF
AD9244
EVALUATION BOARD
ANALOG INPUT CONFIGURATION
REFERENCE CONFIGURATION
Table 12 provides a summary of the analog input configuration.
The analog inputs of the AD9244 on the evaluation board can
be driven differentially through a transformer via Connector S4,
or through the AD8138 amplifier via Connector S2, or they can
be driven single-ended directly via Connector S3. When using
the transformer or AD8138 amplifier, a single-ended source can
be used, as both of these devices are configured on the AD9244
evaluation board to convert single-ended signals to differential
signels.
As described in the Analog Input and Reference Overview
section, the AD9244 can be configured to use its own internal
or an external reference. An external reference, D3, and reference buffer, U5, are included on the AD9244 evaluation board.
Jumper JP8 and Jumper JP22 to Jumper JP24 can be used to
select the desired reference configuration (see Table 13).
Optimal AD9244 performance is achieved above 500 kHz by
using the input transformer. To drive the AD9244 via the transformer, connect solderable Jumper JP45 and Jumper JP46. DC
bias is provided by Resistor R8 and Resistor R28. The evaluation
board has positions for through-hole and surface-mount
transformers.
For applications requiring lower frequencies or dc applications,
the AD8138 can be used. The AD8138 provides good distortion
and noise performance, as well as input buffering up to 30 MHz.
For more information, refer to the AD8138 data sheet. To use
the AD8138 to drive the AD9244, remove the transformer (T1
or T4) and connect solderable Jumper JP42 and Jumper JP43.
The AD9244 can be driven single-ended directly via S3 and can
be ac-coupled or dc-coupled by removing or inserting JP5. To
run the evaluation board in this way, remove the transformer
(T1 or T4) and connect solderable Jumper JP40 and Jumper JP41.
Resistor R40, Resistor R41, Resistor R8, and Resistor R28 are
used to bias the AD9244 inputs to the correct common-mode
levels in this application.
CLOCK CONFIGURATION
The AD9244 evaluation board was designed to achieve optimal
performance as well as to be easily configurable by the user. To
configure the clock input, begin by connecting the correct combination of solderable jumpers (see Table 14). The specific
jumper configuration is dependent on the application and can
be determined by referring to the Clock Input Modes section. If
the differential clock input mode is selected, an external sine
wave generator applied to S5 can be used as the clock source.
The clock buffer/drive MC10EL16 from ON Semiconductor® is
used on the evaluation board to buffer and square the clock
input. If the single-ended clock configuration is used, an external clock source can be applied to S1.
The AD9244 evaluation board generates a buffered clock at
TTL/CMOS levels for use with a data capture system, such as
the HSC-ADC-EVAL-SC system. The clock buffering is provided by U4 and U7 and is configured by Jumper JP3,
Jumper JP4, Jumper JP9, and Jumper JP18 (see Table 14).
Table 12. Analog Input Jumper Configuration
Analog Input
Differential: Transformer
Differential: Amplifier
Single-Ended
Input Connector
S4
S2
S3
Jumpers
45, 46
42, 43
5, 40, 41
Notes
R8, R28 provide dc bias; optimal for 500 kHz.
Remove T1 or T4; used for low input frequencies.
Remove T1 or T4. JP5: connected for dc-coupled, not connected for ac-coupling.
Table 13. Reference Jumper Configuration
Reference
Internal
Internal
Internal
External
Voltage
2V
1V
1 V ≤ VREF ≤ 2 V
1 V ≤ VREF ≤ 2 V
Jumpers
23
24
25
8, 22
Notes
JP8 not connected
JP8 not connected
JP8 not connected; VREF = 1 + R1/R2
Set VREF with R26
Rev. C | Page 26 of 36
AD9244
Table 14. Clock Jumper Configuration
Input Connector
Jumpers
S5
S1
S1
11, 13
12, 15
12, 14
N/A
N/A
S6
9, 18A
9, 18B
3 or 4
5V
+
5V
–
AVDD
REFIN
SIGNAL SYNTHESIZER
2.5MHz, 0.8V p-p
HP8644
2.5MHz
BAND-PASS FILTER
S4
INPUT
xFMR
–
3V
+
GND DUT
AVDD
–
3V
+
GND DUT
DVDD
AD9244
EVALUATION BOARD
10MHz
REFOUT
CLK SYNTHESIZER
65MHz, 1V p-p
HP8644
CLOCK
DIVIDER
S1/S5
INPUT
CLOCK
Figure 64. Evaluation Board Connections
Rev. C | Page 27 of 36
–
+
DVDD
OUTPUT
BUSS
J1
DSP
EQUIPMENT
02404-064
Clock Input
DUT CLOCK
Differential
Single-Ended
AD9226-Compatible
DATA CAPTURE CLOCK
Internal
Differential DUT Clock
Single-Ended DUT Clock
External
Rev. C | Page 28 of 36
Figure 65. AD9244 Evaluation Board, ADC, External Reference, and Power Supply Circuitry
02404-065
DVDDIN TB1 6
AGND TB1 4
DRVDDIN TB1 5
AVDDIN TB1 1
AGND TB1 3
2
1
R26
2kΩ
R16
2.55kΩ
AVDD
C59
0.1μF
C52
0.1μF
C53
0.1μF
C6
22μF +
25V
C14
0.1μF
FBEAD L4
C48
22μF +
25V
FBEAD L3
C47
22μF +
25V
FBEAD L2
C58
22μF +
25V
–IN
+IN
R20
2kΩ
DVDD
DUTDRVDD
AVDD
1
U5
JP8
C30
0.1μF
DIFFB
DIFFA
SECLK
R4
DNP
C32
0.1μF
JP15
C23 +
10μF
10V
DUTDRVDD
C42
0.001μF
C50
0.1μF
C1 +
10μF
10V
VIN–
VIN+
C39
0.001μF
C41
0.001μF
C36
0.1μF
DUTAVDD
C33
0.1μF
C22 +
10μF
10V
JP22
C38
0.1μF
C20
10μF +
10V
JP24
JP25
JP23
JP13 DUTAVDD
JP14
JP11
JP12
C34
0.1μF
C21 +
C35
10μF
0.1μF
10V
TP5
WHT
R3
DNP
AD822
OUT
AGND; 4
AVDD; 8
DUTAVDD
R17
2kΩ
2
3
TP11
TP12
TP13
TP14
BLK
BLK
BLK
BLK
TP4
RED
TP3
RED
TP1
RED
TP2
RED
C29
0.1μF
CW
FBEAD L1
D3
1.2V
AVDD
AD822
U5
7
AGND; 4
AVDD; 8
OUT
C28
0.1μF
–IN
+IN
DUTAVDDIN TB1 2
C27
+
10μF
10V
6
5
U1
NIC 8
VR 48
C37
0.1μF
22 DGND
C45
0.001μF
D0O
D1O
D2O
D3O
D4O
D5O
D6O
C40
0.001μF
DGND 14
23 DRVDD DRVDD 15
NIC 44
AGND 5
30 DGND
29 DRVDD
DCS 43
DFS 35
34 AVDD
31 AVDD
33 AGND
OEB 9
6 CLK–
32 AGND
LSB-D0 10
D1 11
D2 12
D3 13
D4 16
D5 17
D6 18
7 CLK+
47 VIN–
46 VIN+
45 CML
42 REFT
41 REFT
40 REFB
D7O
D8O
D8 20
38 REFGND
D7 19
D9O
D9 21
37 VREF
39 REFB
D10O
D10 24
36 SENSE
D11O
D12O
D11 25
D12 26
2 AGND
1 AGND
OTRO
D13O
OTR 28
4 AVDD MSB-D13 27
3 AVDD
AD9244
+ C56
DNP
R10
1kΩ
R6
1kΩ
R42
1kΩ
JP2
JP1
JP6
C2
0.1μF
AVDD
C57
DNP
AD9244
Figure 66. AD9244 Evaluation Board, Clock Input, and Digital Output Buffer Circuitry
Rev. C | Page 29 of 36
JP18
02404-066
3
B A
2
SECLK
S1
AVDD
DIFFB
DIFFA
DIFFCLK
S5
1
2
74VHC04
AVDD; 14
AGND; 7
U4
S6
DATACLK
1
TP7
WHT
CW
6
4
U4
12
74VHC04
U4
74VHC04
AVDD
+
JP3
JP4
D0O
D1O
D2O
D3O
D4O
D5O
D6O
D7O
D8O
D9O
D10O
D11O
D12O
D13O
+
6
3
4
3
5
6
7
8
1
2
5
6
3
4
7
8
1
2
5
6
3
4
7
8
2
1
5
7
2
4
8
1
U4 DECOUPLING
AVDD
JP9
SECLK
U3 DECOUPLING
AVDD
74VHC04
CW
AVDD
R27
2k
13
3
5
U4
AVDD
AVDD
1
RESET
2
CLK
3
CLK
4
VBB
U3
MC10EL16
VCC
7
Q
6
Q
5
VEE
8
AVDD
CW
OTRO
11
9
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
9
8
7
6
5
4
3
2
19
1
9
8
7
6
5
4
3
2
19
1
10
74VHC04
U4
74VHC04
8
OTR
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
U4
D10
D11
D12
D13
OTR
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
GND
VCC
A8
A7
A6
A5
A4
Y3
A2
A1
G2
G1
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
GND
VCC
U7
74VHC541
A8
A7
A6
A5
A4
Y3
A2
A1
G2
G1
U6
74VHC541
11
12
13
14
15
16
17
18
10
20
+
11
12
13
14
15
16
17
18
10
20
+
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
DVDD
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
CLK
OTR
MSB
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
HEADER RIGHT ANGLE MALE NO EJECTORS
J1
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
AD9244
AD9244
AVDD
R40
1kΩ
JP5
SINGLE
INPUT
C7
0.1μF
S3
JP42
R5
C9
49.9Ω 0.33μF
C15
10μF
10V
AVDD
R41
1kΩ
JP40
AVDD
+
R33
10kΩ
C8
0.1μF
R37
499Ω
AMP INPUT
U2
R31
49.9Ω
R35
499Ω
VIN+
C24
20pF
VIN–
C43
DNP
JP43
R46
33Ω
4
OUT+
VOCM
AD8138
8
S2
–IN
C44
DNP
2
OUT–
+IN
V–
R47
33Ω
5
6
1
R36
499Ω
ADT4-6T
P T4 S
6
AVDD
5
3
4
NC= 2
XFMRINPUT
CW
S4
T1-1TX65
5
R24
49.9Ω
R28
2kΩ
1
P
NC = 5
4
S
2
3
T1
R8
500Ω
Figure 67. AD9244 Evaluation Board, Analog Input Circuitry
Rev. C | Page 30 of 36
C25
0.33μF
C16
0.1μF
02404-067
1
JP46
R22
33Ω
JP41
3
R34
523Ω
R21
33Ω
R32
10kΩ
C69
0.1μF
V+
JP45
02404-068
AD9244
02404-069
Figure 68. AD9244 Evaluation Board, PCB Assembly, Top
Figure 69. AD9244 Evaluation Board, PCB Assembly, Bottom
Rev. C | Page 31 of 36
02404-070
AD9244
02404-071
Figure 70. AD9244 Evaluation Board, PCB Layer 1 (Top)
Figure 71. AD9244 Evaluation Board, PCB Layer 2 (Ground Plane)
Rev. C | Page 32 of 36
02404-072
AD9244
02404-073
Figure 72. AD9244 Evaluation Board, PCB Layer 3 (Power Plane)
Figure 73. AD9244 Evaluation Board, PCB Layer 4 (Bottom)
Rev. C | Page 33 of 36
AD9244
Table 15. Evaluation Board Bill of Materials
Item
1
2
Qty.
11
28
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
40a
41
42
43
44
45
46
47
48
49
4
2
1
3
5
2
1
1
1
12
11
1
4
6
1
2
5
2
1
2
2
1
2
2
6
3
4
1
3
1
2
1
2
4
6
1
1
1
1
4
2
4
1
1
1
1
1
2
Reference Designator
C1, C3, C4, C5, C15, C20, C21, C22, C23, C26, C27
C2, C7, C8, C10, C11, C12, C13, C14, C16, C17, C18, C19, C28, C29,
C31, C32, C33, C34, C35, C36, C37, C38, C50, C52, C53, C59, C61, C69
C6, C47, C48, C58
C9, C25
C24
C30, C46, C49
C39, C40, C41, C42, C45
C43, C44
C60
D3
J1
JP1, JP2, JP3, JP4, JP5, JP6, JP8, JP9, JP22, JP23, JP24, JP25
JP11, JP12, JP13, JP14, JP15, JP40, JP41, JP42, JP43, JP45, JP46
JP18
L1, L2, L3, L4
R1, R5, R11, R24, R29, R31
R2
R3, R4
R6, R10, R40, R41, R42
R7, R9
R8
R12, R13
R14, R15
R16
R17, R20
R18, R19
R21, R22, R23, R25, R46, R47
R26, R27, R28
R30, R32, R33, R38
R34
R35, R36, R37
R39
R43, R44
R45
RP1, RP2
RP3, RP4, RP5, RP6
S1, S2, S3, S4, S5, S6
T1
T4
TB1
TB1a
TP1, TP2, TP3, TP4
TP5, TP7
TP11, TP12, TP13, TP14
U1
U2
U3
U4
U5
U6, U7
Rev. C | Page 34 of 36
Description
Tantalum capacitors
Chip capacitors
Package
BCASE
1206
Value
10 μF
0.1 μF
Tantalum capacitors
Chip capacitors
Chip capacitor
Chip capacitors
Chip capacitors
DNP 1
Chip capacitor
Diode
Header male
Headers
Solder jumpers
Header
Chip inductors
Chip resistors
Potentiometer
DNP1
Chip resistors
Chip resistors
Chip resistor
Chip resistors
Chip resistors
Chip resistor
Chip resistors
Chip resistors
Chip resistors
Potentiometers
Chip resistors
Chip resistor
Chip resistors
Chip resistor
Chip resistors
Potentiometer
Resistor packs
Resistor packs
SMA connectors 50 Ω
Transformer
Transformer
Header
Header
Test points
Test points
Test points
AD9244
AD8138 amplifier
ECL divider
Hex inverter
AD822 op amp
Octal registers
DCASE
1206
0805
0805
0805
0805
1206
SOT-23 Can
40 PIN RA
JPRBLK02
22 μF
0.33 μF
20 pF
0.1 μF
0.001 μF
DNP1
0.01 μF
1.2 V
Header
JPRBLK03
LC1210
RC07CUP
RV3299UP
RC07CUP
1206
1206
1206
1206
1206
1206
1206
1206
1206
RV3299UP
1206
1206
1206
1206
1206
RV3299UP
RCTS766
RCA74204
SMA200UP
DIP06RCUP
MINI_CD637
TBLK06REM
LOOPTP
LOOPMINI
LOOPTP
LQFP-48
R-8
SO8
TSSOP14
SOIC-8
SOL20
FBEAD
49.9 Ω
5 kΩ
DNP1
1 kΩ
22 Ω
500 Ω
113 Ω
90 Ω
2.55 kΩ
2 kΩ
4 kΩ
33 Ω
2 kΩ
10 kΩ
523 Ω
499 Ω
49.9 Ω
100 Ω
10 kΩ
22 Ω
22 Ω
T1-1TX65
ADT4-6T
RED
WHT
BLK
AD9244
AD8138
MC10EL16
74VHC04MTC
AD822
74VHC541
AD9244
Item
50
51
Total
1
Qty.
14
2
183
Reference Designator
Sockets for through resistors
C56, C57
Description
Solder sockets
Package
Value
DNP1
Do not place.
Rev. C | Page 35 of 36
AD9244
OUTLINE DIMENSIONS
0.75
0.60
0.45
9.00
BSC SQ
1.60
MAX
37
48
36
1
PIN 1
0.15
0.05
7.00
BSC SQ
TOP VIEW
1.45
1.40
1.35
SEATING
PLANE
0.20
0.09
7°
3.5°
0°
0.08 MAX
COPLANARITY
(PINS DOWN)
25
12
13
VIEW A
0.50
BSC
LEAD PITCH
VIEW A
24
0.27
0.22
0.17
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
Figure 74. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD9244BST-65
AD9244BSTRL-65
AD9244BSTZ-65 1
AD9244BSTZRL-651
AD9244BST-40
AD9244BSTRL-40
AD9244BSTZ-401
AD9244BSTZRL-401
AD9244-65PCB
AD9244-40PCB
1
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Description
48-Lead Low Profile Quad Flat Package (LQFP)
48-Lead Low Profile Quad Flat Package (LQFP)
48-Lead Low Profile Quad Flat Package (LQFP)
48-Lead Low Profile Quad Flat Package (LQFP)
48-Lead Low Profile Quad Flat Package (LQFP)
48-Lead Low Profile Quad Flat Package (LQFP)
48-Lead Low Profile Quad Flat Package (LQFP)
48-Lead Low Profile Quad Flat Package (LQFP)
Evaluation Board
Evaluation Board
Z = Pb-free part.
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C02404-0-12/05(C)
Rev. C | Page 36 of 36
Package Option
ST-48
ST-48
ST-48
ST-48
ST-48
ST-48
ST-48
ST-48