MPS NB638DL High efficiency, fast transient, 7a, 28v synchronous step-down converter in a tiny 3x4mm qfn package Datasheet

NB638
High Efficiency, Fast Transient, 7A, 28V
Synchronous Step-down Converter
in a Tiny 3x4mm QFN Package
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The NB638 is a fully integrated, high frequency
synchronous rectified step-down switch mode
converter. It offers a very compact solution to
achieve 7A continuous output current over a
wide input supply range with excellent load and
line regulation. The NB638 operates at high
efficiency over a wide output current load range.
•
•
•
Wide 4.5V to 28V Operating Input Range
7A Output Current
Internal 30mΩ High-Side, 12mΩ Low-Side
Power MOSFETs
Proprietary Switching Loss Reduction
Technique
1% Reference Voltage
Programmable Soft Start Time
Soft Shutdown
200kHz to 1MHz Switching Frequency
SCP, OCP, OVP, UVP Protection and
Thermal Shutdown
Output Adjustable from 0.8V to 13V
Available in a QFN20 (3x4mm) Package
•
•
•
•
•
•
Constant-On-Time
(COT)
control
mode
provides fast transient response and eases loop
stabilization.
Full protection features include SCP, OCP, OVP,
UVP and thermal shutdown.
•
•
The NB638 requires a minimum number of
readily available standard external components
and is available in a space-saving QFN20
(3x4mm) package.
APPLICATIONS
•
•
•
•
Notebook Systems and I/O Power
Networking Systems
Optical Communication Systems
Distributed Power and POL Systems
All MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit MPS website under Products, Quality Assurance page.
“MPS” and “The Future of Analog IC Technology” are registered trademarks of
Monolithic Power Systems, Inc.
TYPICAL APPLICATION
VIN
8,19
R7
BST 7
IN
CIN
NB638
SW
2
FREQ
20
VCC
EN
C3
9,10,17,18
VOUT 1.05V
R4
6
PGOOD
5
EN
FB
C4
R1
C2
3
R2
SS AGND PGND
4
NB638 Rev.1.16
4/18/2012
1
CSS
33nF
11-16
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1
NB638–HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
ORDERING INFORMATION
Part Number*
Package
Top Marking
NB638DL
QFN20 (3x4mm)
NB638
* For Tape & Reel, add suffix –Z (e.g. NB638DL–Z)
For RoHS compliant packaging, add suffix –LF (e.g. NB638DL–LF–Z)
PACKAGE REFERENCE
TOP VIEW
AGND
FREQ
VCC
IN
SW SW
20
19
18
17
1
IN
2
SW
FB
3
16
PGND
15
PGND
14
PGND
13
PGND
12
PGND
11
PGND
IN
SS
4
SW
EN
5
IN
PGOOD
6
7
8
9
10
BST IN SW SW
EXPOSED PAD
ON BACKSIDE
ABSOLUTE MAXIMUM RATINGS (1)
Supply Voltage VIN ....................................... 30V
VSW ........................................-0.3V to VIN + 0.3V
VBST ...................................................... VSW + 6V
IVIN (RMS) ........................................................ 3.5A
VPGOOD ....................................-0.3V to VCC+0.6V
All Other Pins ..................................-0.3V to +6V
Continuous Power Dissipation (TA = +25°C) (2)
………………………………… …………….2.6W
Junction Temperature ...............................150°C
Lead Temperature ....................................260°C
Storage Temperature............... -65°C to +150°C
Recommended Operating Conditions
(3)
Thermal Resistance
(4)
θJA
θJC
QFN20 (3x4mm) ......................48 ...... 10 ... °C/W
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD(MAX)=(TJ(MAX)TA)/θJA. Exceeding the maximum allowable power dissipation
will cause excessive die temperature, and the regulator will go
into thermal shutdown. Internal thermal shutdown circuitry
protects the device from permanent damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
Supply Voltage VIN ...........................4.5V to 28V
Output Voltage VOUT .........................0.8V to 13V
Maximum Junct. Temp (TJ)...... -40°C to +125°C
NB638 Rev.1.16
4/18/2012
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NB638–HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
ELECTRICAL CHARACTERISTICS
VIN = 12V, TA = +25°C, unless otherwise noted.
Parameters
Supply Current (Shutdown)
Symbol
IIN
Supply Current (Quiescent)
IIN
HS Switch On Resistance (5)
LS Switch On Resistance (5)
HSRDS-ON
LSRDS-ON
Switch Leakage
SWLKG
Current Limit
ILIMIT
One-Shot On Time
TON
Minimum Off Time(5)
Fold-back Off Time(5)
OCP hold-off time(5)
TOFF
TFB
TOC
Feedback Voltage
Feedback Current
Soft Start Charging Current
Soft Stop Charging Current
Power Good Rising Threshold
Power Good Falling Threshold
Power Good Rising delay
Power Good Rising delay
Power Good Rising delay
EN Rising Threshold
EN Threshold Hysteresis
EN Input Current
VIN Under-Voltage Lockout
Threshold Rising
VIN Under-Voltage Lockout
Threshold Hysteresis
VCC Regulator
VCC Load Regulation
Vo Over-Voltage Protection
Threshold
Vo Under-Voltage Detection
Threshold
Thermal Shutdown
Thermal Shutdown Hysteresis
VFB
IFB
ISS
ISS
PGOODVth-Hi
PGOODVth-Lo
TPGOOD
TPGOOD
TPGOOD
ENVth-Hi
ENVth-Hys
IEN
Condition
VEN = 0V
VEN = 2V
VFB = 1V
Min
VEN = 0V
VSW = 0V or 12V
Typ
0
ILIM=1(HIGH)
ILIM=1(HIGH)
μA
30
12
mΩ
mΩ
10
A
250
ns
100
1.4
ns
μs
μs
40
TA=25°C
815
823
0°C <TA<70°C
VFB = 815mV
VSS=0V
VSS=0.815V
803
815
827
10
8.5
8.5
0.9
0.85
1
1.5
2
1.35
420
2
50
1.05
250
VEN = 2V
3.8
INUVVth
μA
12
807
TSS=1ms
TSS =2ms
TSS =3ms
Units
μA
500
0
R7=301kΩ
VOUT=1.2V
Max
4.0
1.60
550
4.2
mV
nA
μA
μA
VFB
VFB
ms
ms
ms
V
mV
μA
V
INUVHYS
880
mV
VCC
5
5
V
%
VOVP
1.25
VFB
VUVP
0.7
VFB
TSD
150
25
°C
°C
ICC=5mA
TSD-HYS
Note:
5) Guaranteed by design.
NB638 Rev.1.16
4/18/2012
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3
NB638–HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
PIN FUNCTIONS
Pin #
Name
Description
1
AGND
2
FREQ
3
FB
4
SS
5
EN
Analog Ground.
Frequency Set during CCM operation. The ON period is determined by the input
voltage and the frequency-set resistor connected to FREQ pin. Connect a resistor
to IN for line feed-forward. Decouple with a 1nF capacitor.
Feedback. An external resistor divider from the output to GND, tapped to the FB
pin, sets the output voltage.
Soft Start. Connect an external SS capacitor to program the soft start time for the
switch mode regulator. When the EN pin becomes high, an internal current source
(8.5µA) charges up the SS capacitor and the SS voltage slowly ramps up from 0 to
VFB smoothly. When the EN pin becomes low, an internal current source (8.5μA)
discharges the SS capacitor and the SS voltage slowly ramps down.
EN=1 to enable the NB638. For automatic start-up, connect EN pin to IN with a
100kΩ resistor. It includes an internal 1MΩ pull-down resistor.
Power Good Output. The output of this pin is an open drain and is high if the
output voltage is higher than 90% of the nominal voltage. There is delay from FB ≥
90% to PGOOD high, which is 50% of SS time plus 0.5ms.
Bootstrap. A 0.1µF-1µF capacitor connected between SW and BS pins is required
to form a floating supply across the high-side switch driver.
Supply Voltage. The NB638 operates from a +4.5V to +28V input rail. CIN is
needed to decouple the input rail. Use wide PCB traces and multiple vias to make
the connection.
Switch Output. Use wide PCB traces and multiple vias to make the connection.
System Ground. This pin is the reference ground of the regulated output voltage.
For this reason care must be taken in PCB layout.
Internal Bias Supply. Decouple with a 1µF capacitor as close to the pin as
possible.
6
PGOOD
7
BST
8, 19
IN
9, 10, 17, 18
SW
11-16
PGND
20
VCC
NB638 Rev.1.16
4/18/2012
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NB638–HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS
VIN=12V, VOUT =1.05V, L=1µH, TA=+25°C, unless otherwise noted.
NB638 Rev.1.16
4/18/2012
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NB638–HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN=12V, VOUT =1.05V, L=1µH, TA=+25°C, unless otherwise noted.
NB638 Rev.1.16
4/18/2012
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NB638–HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN=12V, VOUT =1.05V, L=1µH, TA=+25°C, unless otherwise noted.
NB638 Rev.1.16
4/18/2012
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NB638–HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
BLOCK DIAGRAM
Figure 1—Functional Block Diagram
NB638 Rev.1.16
4/18/2012
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NB638–HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
OPERATION
PWM Operation
The NB638 is a fully integrated synchronous
rectified step-down switch mode converter.
Constant-on-time (COT) control is employed to
provide fast transient response and easy loop
stabilization. At the beginning of each cycle, the
high-side MOSFET (HS-FET) is turned ON when
the feedback voltage (VFB) is below the reference
voltage (VREF), which indicates insufficient output
voltage. The ON period is determined by the
input voltage and the frequency-set resistor as
follows:
TON ( ns ) =
6 × R7 ( kΩ )
VIN ( V ) − 0.4
+ 40 ( ns )
(1)
After the ON period elapses, the HS-FET is
turned off, or becomes OFF state. It is turned ON
again when VFB drops below VREF. By repeating
operation this way, the converter regulates the
output voltage. The integrated low-side MOSFET
(LS-FET) is turned on when the HS-FET is in its
OFF state to minimize the conduction loss. There
will be a dead short between input and GND if
both HS-FET and LS-FET are turned on at the
same time. It’s called shoot-through. In order to
avoid shoot-through, a dead-time (DT) is
internally generated between HS-FET off and LSFET on, or LS-FET off and HS-FET on.
As Figure 2 shows, when the output current is
high, the HS-FET and LS-FET repeat on/off as
described above. In this operation, the inductor
current will never go to zero. It’s called
continuous-conduction-mode (CCM) operation. In
CCM operation, the switching frequency (FSW) is
fairly constant.
Light-Load Operation
At light load or no load condition, the output
drops very slowly and the NB638 reduces the
switching frequency automatically to maintain
high efficiency. The light load operation is shown
in Figure 3. The VFB does not reach VREF when
the inductor current is approaching zero. The LSFET driver turns into tri-state (high Z) whenever
the inductor current reaches zero. A current
modulator takes over the control of LS-FET and
limits the inductor current to less than -1mA.
Hence, the output capacitors discharge slowly to
GND through LS-FET. As a result, the efficiency
at light load condition is greatly improved. At light
load condition, the HS-FET is not turned ON as
frequently as at heavy load condition. This is
called skip mode.
Heavy-Load Operation
Figure 3—Light Load Operation
As the output current increases from the light
load condition, the time period within which the
current modulator regulates becomes shorter.
The HS-FET is turned ON more frequently.
Hence, the switching frequency increases
correspondingly. The output current reaches the
critical level when the current modulator time is
zero. The critical level of the output current is
determined as follows:
Figure 2—Heavy Load Operation
NB638 Rev.1.16
4/18/2012
IOUT =
(VIN − VOUT ) × VOUT
2 × L × FSW × VIN
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(2)
9
NB638–HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
It turns into PWM mode once the output current
exceeds the critical level. After that, the switching
frequency stays fairly constant over the output
current range.
Switching Frequency
Constant on-time (COT) control is used in the
NB638 and there is no dedicated oscillator in the
IC. The input voltage is feed-forwarded to the ontime one-shot timer through the resistor R7. The
duty ratio is kept as VOUT/VIN. Hence, the
switching frequency is fairly constant over the
input voltage range. The switching frequency
can be set as follows:
10 6
(3)
FSW ( kHz ) =
magnitude of the VFB ripple doesn’t directly affect
the noise immunity directly.
Figure 4—Jitter in PWM Mode
6 × R 7 (kΩ )
V (V)
× IN
+ T DEALY ( ns )
VIN ( V ) − 0.4 VOUT ( V )
Where TDELAY is the comparator delay. It’s about
40ns.
Frequency vs. RFREQ
Figure 5—Jitter in Skip Mode
FREQUENCY (kHz)
1400
VOUT=3.3V
1200
1000
VOUT=2.5V
800
600
400
200
0
0
VOUT=1.05V
200
400
600
800
1000
Ramp with Large ESR Cap
In the case of POSCAP or other types of
capacitor with larger ESR is applied as output
capacitor. The ESR ripple dominates the output
ripple, and the slope on the FB is quite ESR
related. Figure 6 shows an equivalent circuit in
PWM mode with the HS-FET off and without an
external ramp circuit. Turn to application
information section for design steps with large
ESR caps.
SW
Generally, the NB638 is set for 200 kHz to 1MHz
application. It is optimized to operate at high
switching frequency with high efficiency. High
switching frequency makes it possible to utilize
small sized LC filter components to save system
PCB space.
Jitter and FB Ramp Slope
Figure 4 and Figure 5 show jitter occurring in
both PWM mode and skip mode. When there is
noise in the VFB downward slope, the ON time of
HS-FET deviates from its intended location and
produces jitter. It is necessary to understand that
there is a relationship between a system’s
stability and the steepness of the VFB ripple’s
downward slope. The slope steepness of the VFB
ripple dominates in noise immunity. The
NB638 Rev.1.16
4/18/2012
Vo
L
FB
R1
ESR
POSCAP
R2
Figure 6—Simplified Circuit in PWM Mode
without External Ramp Compensation
To realize the stability when no external ramp is
used, usually the ESR value should be chosen
as follow:
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NB638–HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
RESR
TSW
T
+ ON
2
≥ 0.7 × π
COUT
(4)
TSW
T
+ ON -RESRCOUT
Io ×10−3
(9)
-Vslope1 ≥ 0.7 × π 2
VOUT +
2 × L × COUT
TSW -Ton
Tsw is the switching period.
Ramp with small ESR Cap
When the output capacitors are ceramic ones,
the ESR ripple is not high enough to stabilize the
system, and external ramp compensation is
needed. Skip to application information section
for design steps with small ESR caps.
L
SW
R4
Vo
Io is the load current.
In skip mode, the downward slope of the VFB
ripple is almost the same whether the external
ramp is used or not. Fig.9 shows the simplified
circuit of the skip mode when both the HS-FET
and LS-FET are off.
Vo
C4
IR4
IC4
R9
limitation from equation 5, then we can only
reduce R4. For a stable PWM operation, the
Vslope1 should be design follow equation 9.
R1
FB
I FB
R1
Ceramic
FB
Cout
R2
R2
Figure 7—Simplified Circuit in PWM Mode
with External Ramp Compensation
In PWM mode, an equivalent circuit with HS-FET
off and the use of an external ramp
compensation circuit (R4, C4) is simplified in
Figure 7. The external ramp is derived from the
inductor ripple current. If one chooses C4, R9,
R1 and R2 to meet the following condition:
⎞
1
1 ⎛ R × R2
< ×⎜ 1
+ R9 ⎟
2π × FSW × C4 5 ⎝ R1 + R 2
⎠
(5)
Where:
IR4 = IC4 + IFB ≈ IC4
(6)
And the ramp on the VFB can then be estimated
as:
VRAMP =
VIN − VO
R1 // R2
× TON ×
R 4 × C4
R1 // R2 + R9
(7)
The downward slope of the VFB ripple then
follows
VSLOPE1 =
− VOUT
− VRAMP
=
Toff
R 4 × C4
Ro
Figure 8—Simplified Circuit in skip Mode
The downward slope of the VFB ripple in skip
mode can be determined as follow:
VSLOPE2 =
− VREF
((R1 + R2 ) // Ro) × COUT
(10)
Where Ro is the equivalent load resistor.
As described in Fig.5, VSLOPE2 in the skip mode is
lower than that is in the PWM mode, so it is
reasonable that the jitter in the skip mode is
larger. If one wants a system with less jitter
during ultra light load condition, the values of the
VFB resistors should not be too big, however, that
will decrease the light load efficiency.
Soft Start/Stop
The NB638 employs soft start/stop (SS)
mechanism to ensure smooth output during
power-up and power shutdown. When the EN pin
becomes high, an internal current source (8.5μA)
charges up the SS CAP. The SS CAP voltage
takes over the REF voltage to the PWM
comparator. The output voltage smoothly ramps
(8)
As can be seen from equation 8, if there is
instability in PWM mode, we can reduce either
R4 or C4. If C4 can not be reduced further due to
NB638 Rev.1.16
4/18/2012
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NB638–HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
up with the SS voltage. Once the SS voltage
reaches the same level as the REF voltage, it
keeps ramping up while VREF takes over the
PWM comparator. At this point, the soft start
finishes and it enters into steady state operation.
When the EN pin becomes low, the SS CAP
voltage is discharged through an 8.5μA internal
current source. Once the SS voltage reaches
REF voltage, it takes over the PWM comparator.
The output voltage will decrease smoothly with
SS voltage until zero level. The SS Cap value
can be determined as follows:
CSS ( nF ) =
TSS ( ms ) × ISS ( μA )
VREF ( V )
(11)
Power Good (PGOOD)
The NB638 has power-good (PGOOD) output.
The PGOOD pin is the open drain of a MOSFET.
It should be connected to VCC or other voltage
source through a resistor (e.g. 100k). After the
input voltage is applied, the MOSFET is turned
on so that the PGOOD pin is pulled to GND
before SS is ready. After FB voltage reaches
90% of REF voltage, the PGOOD pin is pulled
high after a delay.
The PGOOD delay time is determined as follows:
(12)
When the FB voltage drops to 85% of REF
voltage, the PGOOD pin will be pulled low.
Over-Current Protection (OCP) and ShortCircuit Protection (SCP)
The NB638 has cycle-by-cycle over-current limit
control. The inductor current is monitored during
the ON state. Once it detects that the inductor
current is higher than the current limit, the HS-
NB638 Rev.1.16
4/18/2012
If short circuit happens, then the current limit will
be hit immediately and the FB voltage will
become lower than 50% of the REF voltage.
When the current limit is hit and the FB voltage is
lower than 50% of the REF voltage (0.815V), the
device considers this as a dead short on the
output and triggers SCP latch-off immediately.
This is short circuit protection (SCP).
Over/Under-voltage Protection (OVP/UVP)
If the output capacitors have large capacitance
value, it’s not recommended to set the SS time
too small. Otherwise, it’s easy to hit the current
limit during SS. A minimum value of 4.7nF should
be used if the output capacitance value is larger
than 330μF.
TPGOOD (ms) = 0.5 × TSS (ms) + 0.5
FET is turned off. At the same time, the OCP
timer is started. The OCP timer is set as 40μs. If
in the following 40μs, the current limit is hit for
every cycle, then it’ll trigger OCP latch-off. The
converter needs power cycle to restart after it
triggers OCP.
The NB638 monitors the output voltage through a
resistor divider feedback (FB) voltage to detect
overvoltage and undervoltage on the output.
When the FB voltage is higher than 125% of the
REF voltage (0.8V), it’ll trigger OVP latch-off.
Once it triggers OVP, the LS-FET is always on
while the HS-FET is always off. It needs power
cycle to power up again. When the FB voltage is
below 50% of the REF voltage (0.815V), it is
recognized as UV (under-voltage). Usually, UVP
accompanies a hit in current limit and results in
SCP.
UVLO protection
The NB638 has under-voltage lock-out protection
(UVLO). When the input voltage is higher than
the UVLO rising threshold voltage, the NB638 will
be powered up. It shuts off when the input
voltage is lower than the UVLO falling threshold
voltage. This is non-latch protection.
Thermal Shutdown
Thermal shutdown is employed in the NB638.
The junction temperature of the IC is internally
monitored. If the junction temperature exceeds
the threshold value (typically 150ºC), the
converter shuts off. This is a non-latch protection.
There is about 25ºC hysteresis. Once the
junction temperature drops to about 125ºC, it
initiates a SS.
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NB638–HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
APPLICATION INFORMATION
Setting the Output Voltage-Large ESR Caps
For applications that electrolytic capacitor or POS
capacitor with a controlled output of ESR is set
as output capacitors. The output voltage is set by
feedback resistors R1 and R2. As figure 9 shows.
SW
L
Vo
ESR
R1
FB
POSCAP
R2
Figure 9—Simplified Circuit of POS Capacitor
First, choose a value for R2. R2 should be
chosen reasonably, a small R2 will lead to
considerable quiescent current loss while too
large R2 makes the FB noise sensitive. It is
recommended to choose a value within 5kΩ50kΩ for R2, using a comparatively larger R2
when Vout is low, etc.,1.05V, and a smaller R2
when Vout is high. Then R1 is determined as
follow with the output ripple considered:
1
VOUT − ΔVOUT − VREF
2
(13)
R1 =
R2
VREF
ΔVOUT is the output ripple determined by equation
21.
Setting the Output Voltage-Small ESR Caps
SW
FB
Vo
L
R4
C4
R9
R1
Ceramic
R2
Figure 10—Simplified Circuit of Ceramic
Capacitor
When low ESR ceramic capacitor is used in the
output, an external voltage ramp should be
added to FB through resistor R4 and capacitor
C4.The output voltage is influenced by ramp
voltage VRAMP besides R divider as shown in
figure 11. The VRAMP can be calculated as shown
NB638 Rev.1.16
4/18/2012
in equation 7. R2 should be chosen reasonably,
a small R2 will lead to considerable quiescent
current loss while too large R2 makes the FB
noise sensitive. It is recommended to choose a
value within 5kΩ-50kΩ for R2, using a
comparatively larger R2 when Vo is low,
etc.,1.05V, and a smaller R2 when Vo is high.
And the value of R1 then is determined as follow:
R1=
R2
VFB(AVG)
(14)
R2
(VOUT -VFB(AVG) ) R4 +R9
The VFB(AVG) is the average value on the FB,
VFB(AVG) varies with the Vin, Vo, and load
condition, etc., its value on the skip mode would
be lower than that of the PWM mode, which
means the load regulation is strictly related to the
VFB(AVG). Also the line regulation is related to the
VFB(AVG) ,if one wants to gets a better load or line
regulation, a lower Vramp is suggested once it
meets equation 9.
For PWM operation, VFB(AVG) value can be
deduced from equation 15.
R1 //R2
1
VFB(AVG) = VREF + VRAMP ×
2
R1 //R2 + R9
(15)
Usually, R9 is set to 0Ω, and it can also be set
following equation 16 for a better noise immunity.
It should also set to be 5 timers smaller than
R1//R2 to minimize its influence on Vramp.
R9 ≤
1
2π× C4 × 2FSW
(16)
Using equation 14 to calculate the output voltage
can be complicated. To simplify the calculation of
R1 in equation 14, a DC-blocking capacitor Cdc
can be added to filter the DC influence from R4
and R9. Figure 12 shows a simplified circuit with
external ramp compensation and a DC-blocking
capacitor. With this capacitor, R1 can easily be
obtained by using equation 17 for PWM mode
operation.
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NB638–HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
1
(VOUT − VREF − VRAMP )
2
R1 =
R2
1
VREF + VRAMP
2
(17)
Cdc is suggested to be at least 10 times larger
than C4 for better DC blocking performance, and
should also not larger than 0.47μF considering
start up performance. In case one wants to use
larger Cdc for a better FB noise immunity,
combined with reduced R1 and R2 to limit the
Cdc in a reasonable value without affecting the
system start up. Be noted that even when the
Cdc is applied, the load and line regulation are
still Vramp related.
SW
FB
L
R4
Vo
C4
Ceramic
R2
Figure 11—Simplified Circuit of Ceramic
Capacitor with DC blocking capacitor
Input Capacitor
The input current to the step-down converter is
discontinuous. Therefore, a capacitor is required
to supply the AC current to the step-down
converter while maintaining the DC input voltage.
Ceramic capacitors are recommended for best
performance. In the layout, it’s recommended to
put the input capacitors as close to the IN pin as
possible.
The capacitance varies significantly over
temperature. Capacitors with X5R and X7R
ceramic dielectrics are recommended because
they are fairly stable over temperature.
The capacitors must also have a ripple current
rating greater than the maximum input ripple
current of the converter. The input ripple current
can be estimated as follows:
ICIN = IOUT ×
VOUT
V
× (1 − OUT )
VIN
VIN
(18)
The worst-case condition occurs at VIN = 2VOUT,
where:
NB638 Rev.1.16
4/18/2012
IOUT
2
(19)
For simplification, choose the input capacitor
whose RMS current rating is greater than half of
the maximum load current.
The input capacitance value determines the input
voltage ripple of the converter. If there is input
voltage ripple requirement in the system design,
choose the input capacitor that meets the
specification
The input voltage ripple can be estimated as
follows:
ΔVIN =
IOUT
V
V
× OUT × (1 − OUT )
FSW × CIN VIN
VIN
(20)
The worst-case condition occurs at VIN = 2VOUT,
where:
I
1
(21)
ΔVIN = × OUT
4 FSW × CIN
Output Capacitor
R1
Cdc
ICIN =
The output capacitor is required to maintain the
DC output voltage. Ceramic or POSCAP
capacitors are recommended. The output voltage
ripple can be estimated as:
ΔVOUT =
VOUT
V
1
× (1 − OUT ) × (RESR +
) (22)
FSW × L
VIN
8 × FSW × COUT
In the case of ceramic capacitors, the impedance
at the switching frequency is dominated by the
capacitance. The output voltage ripple is mainly
caused by the capacitance. For simplification, the
output voltage ripple can be estimated as:
ΔVOUT =
VOUT
V
× (1 − OUT )
2
8 × FSW × L × COUT
VIN
(23)
The output voltage ripple caused by ESR is very
small. Therefore, an external ramp is needed to
stabilize the system. The external ramp can be
generated through resistor R4 and capacitor C4
following equation 5, 8 and 9.
In the case of POSCAP capacitors, the ESR
dominates the impedance at the switching
frequency. The ramp voltage generated from the
ESR is high enough to stabilize the system.
Therefore, an external ramp is not needed. A
minimum ESR value around 12mΩ is required to
ensure stable operation of the converter. For
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NB638–HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
simplification, the
approximated as:
ΔVOUT =
output
ripple
can
VOUT
V
× (1 − OUT ) × RESR
FSW × L
VIN
below the maximum switch current limit. The
inductance value can be calculated as:
be
(24)
Inductor
The inductor is required to supply constant
current to the output load while being driven by
the switching input voltage. A larger value
inductor will result in less ripple current that will
result in lower output ripple voltage. However, a
larger value inductor will have a larger physical
size, higher series resistance, and/or lower
saturation current. A good rule for determining
the inductor value is to allow the peak-to-peak
ripple current in the inductor to be approximately
30~40% of the maximum switch current limit.
Also, make sure that the peak inductor current is
L=
VOUT
V
× (1 − OUT )
FSW × ΔIL
VIN
(25)
Where ΔIL is the peak-to-peak inductor ripple
current.
Choose an inductor that will not saturate under
the maximum inductor peak current. The peak
inductor current can be calculated as:
ILP = IOUT +
VOUT
V
× (1 − OUT )
2FSW × L
VIN
(26)
The inductors listed in Table 1 are highly
recommended for the high efficiency they can
provide.
Table 1—Inductor Selection Guide
Part Number
Manufacturer
Inductance
(µH)
DCR
(mΩ)
Current
Rating (A)
Dimensions
L x W x H (mm3)
Switching
Frequency
(kHz)
PCMC-135T-R68MF
Cyntec
0.68
1.7
34
13.5 x 12.6 x 4.8
600
FDA1254-1R0M
FDA1254-1R2M
TOKO
TOKO
1
1.2
2
2.05
25.2
20.2
13.5 x 12.6 x 5.4
13.5 x 12.6 x 5.4
R1
R2
(kΩ)
(kΩ)
12.1
26.1
30
14.3
40.2
13.3
300~600
300~600
R7
(kΩ)
442
845
1000
Typical Design Parameter Tables
The following tables include recommended
component values for typical output voltages
(1.2V, 2.5V, 3.3V) and switching frequencies
(300kHz, 500kHz, and 700kHz). Refer to Tables
2-4 for design cases without external ramp
compensation and Tables 5-7 for design cases
with external ramp compensation. External ramp
is not needed when high-ESR capacitors, such
as electrolytic or POSCAPs are used. External
ramp is needed when low-ESR capacitors, such
as ceramic capacitors are used. For cases not
listed in this datasheet, a calculator in excel
spreadsheet can also be requested through a
local sales representative to assist with the
calculation.
Table 2—300kHz, 12VIN
VOUT
(V)
1.2
2.5
3.3
L
(μH)
2.2
2.2
1
R1
(kΩ)
12.1
30
40.2
R2
(kΩ)
26.1
14.3
13.3
R7
(kΩ)
750
1500
1600
VOUT
(V)
1.2
2.5
3.3
L
(μH)
1
1
1
Table 4—700kHz, 12VIN
VOUT
(V)
1.2
2.5
3.3
L
(μH)
1
1
1
R1
(kΩ)
12.1
30
40.2
R2
(kΩ)
26.1
14.3
13.3
R7
(kΩ)
316
590
806
Table 5—300kHz, 12VIN
VOUT
(V)
1.2
2.5
3.3
L
(μH)
2.2
2.2
2.2
R1
(kΩ)
12.1
30
40.2
R2
(kΩ)
26.1
14.3
12.4
R4
(kΩ)
330
402
422
C4
(pF)
220
220
220
R7
(kΩ)
750
1500
1600
Table 3—500kHz, 12VIN
NB638 Rev.1.16
4/18/2012
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NB638–HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
Table 6—500kHz, 12VIN
VOUT
(V)
1.2
2.5
3.3
L
(μH)
1
1
1
NB638 Rev.1.16
4/18/2012
R1
(kΩ)
12.1
30
40.2
R2
(kΩ)
26.1
14.3
12.4
R4
(kΩ)
374
412
422
C4
(pF)
220
220
220
Table 7—700kHz, 12VIN
R7
(kΩ)
442
845
1000
VOUT
(V)
1.2
2.5
3.3
L
(μH)
1
1
1
R1
(kΩ)
12.1
30
40.2
R2
(kΩ)
26.1
14.3
12.4
R4
(kΩ)
240
412
422
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C4
(pF)
220
220
220
R7
(kΩ)
316
590
806
16
NB638–HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL APPLICATION
U1
8,19
VIN
BST
IN
7
GND
R5
100k
NB638
C7
1nF
2
20
SW
R3
4.7
R7
301k
9,10,17,18
VOUT
FREQ
1.05V
VCC
R6
100k
R1
12.1k
6
PGOOD
PGOOD
5 EN
EN
FB
GND
3
R2
42.2k
SS AGND PGND
4
11-16
1
C6
33nF
Figure 12 — Typical Application Circuit with No External Ramp
U1
8,19
VIN
BST
IN
7
GND
R5
100k
C7
1nF
NB638
2
20
SW
9,10,17,18
FREQ
EN
VOUT
VCC
R9
0
PGOOD
5 EN
FB
GND
220pF
360k
6
1.05V
C4
R4
R6
100k
PGOOD
R3
4.7
R7
301k
R1
12.1k
3
R2
43.2k
SS AGND PGND
4
11-16
1
C6
33nF
Figure 13 — Typical Application Circuit with Low ESR Ceramic Capacitor
R7
301k
10nF
Figure 14 — Typical Application Circuit with Low ESR Ceramic Capacitor
and DC-Blocking Capacitor.
NB638 Rev.1.16
4/18/2012
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17
NB638–HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
LAYOUT RECOMMENDATION
1. The high current paths (GND, IN, and SW)
should be placed very close to the device
with short, direct and wide traces.
2. Put the input capacitors as close to the IN
and GND pins as possible.
3. Put the decoupling capacitor as close to the
VCC and GND pins as possible.
4. Keep the switching node SW short and away
from the feedback network.
5. The external feedback resistors should be
placed next to the FB pin. Make sure that
there is no via on the FB trace.
6. Keep the BST voltage path (BST, C3, and
SW) as short as possible.
7. Keep the bottom IN and SW pads connected
with large copper to achieve better thermal
performance.
8. Four-layer layout is strongly recommended to
achieve better thermal performance.
Inner1 Layer
GND
Inner2 Layer
Top Layer
Bottom Layer
Figure 15—PCB Layout
NB638 Rev.1.16
4/18/2012
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NB638–HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
PACKAGE INFORMATION
QFN20 (3x4mm)
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
NB638 Rev.1.16
4/18/2012
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19
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