Cypress CY7C1354DV25 9-mbit (256k x 36/512k x 18) pipelined sram with nobl architecture Datasheet

CY7C1354DV25, CY7C1356DV25
9-Mbit (256K x 36/512K x 18)
Pipelined SRAM with NoBL™ Architecture
Features
Functional Description
■
Pin compatible with and functionally equivalent to ZBT™
■
Supports 250 MHz bus operations with zero wait states
■
Available speed grades are 250, 200, and 166 MHz
■
Internally self timed output buffer control to eliminate the need
to use asynchronous OE
■
Fully registered (inputs and outputs) for pipelined operation
■
Byte Write capability
■
Single 2.5V power supply (VDD)
The CY7C1354DV25 and CY7C1356DV25 are 2.5V, 256K x 36
and 512K x 18 Synchronous pipelined burst SRAMs with No Bus
Latency™ (NoBL™) logic, respectively. They are designed to
support unlimited true back to back read and write operations
with no wait states. The CY7C1354DV25 and CY7C1356DV25
are equipped with the advanced (NoBL) logic required to enable
consecutive read and write operations with data being transferred on every clock cycle. This feature dramatically improves
the throughput of data in systems that require frequent write and
read transitions. The CY7C1354DV25 and CY7C1356DV25 are
pin compatible with and functionally equivalent to ZBT devices.
■
Fast clock-to-output times
❐ 2.8 ns (for 250 MHz device)
■
Clock Enable (CEN) pin to suspend operation
■
Synchronous self timed writes
■
Available in Pb-free 100-pin TQFP package, Pb-free and non
Pb-free 119-ball BGA package, and 165-ball FBGA package
■
IEEE 1149.1 JTAG compatible boundary scan
■
Burst capability–linear or interleaved burst order
■
“ZZ” Sleep mode and Stop Clock options
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the Clock Enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle.
Write operations are controlled by the Byte Write Selects
(BWa–BWd for CY7C1354DV25 and BWa–BWb for
CY7C1356DV25) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide easy bank selection
and output tri-state control. To avoid bus contention, the output
drivers are synchronously tri-stated during the data portion of a
write sequence. For best practices recommendations, please
refer to the Cypress application note System Design Guidelines
on www.cypress.com.
Selection Guide
Description
250 MHz
200 MHz
166 MHz
Unit
Maximum Access Time
2.8
3.2
3.5
ns
Maximum Operating Current
250
220
180
mA
Maximum CMOS Standby Current
40
40
40
mA
Cypress Semiconductor Corporation
Document #: 001-48974 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 31, 2009
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CY7C1354DV25
CY7C1356DV25
Logic Block Diagram – CY7C1354DV25 (256K x 36)
A0, A1, A
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
MODE
ADV/LD
C
C
CLK
CEN
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
S
E
N
S
E
ADV/LD
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BW a
BW b
BW c
BW d
WRITE
DRIVERS
MEMORY
ARRAY
A
M
P
S
WE
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
INPUT
REGISTER 1
OE
CE1
CE2
CE3
S
T
E
E
R
I
N
G
B
U
F
F
E
R
S
DQ s
DQ Pa
DQ Pb
DQ Pc
DQ Pd
E
INPUT
REGISTER 0
E
O
U
T
P
U
T
D
A
T
A
E
READ LOGIC
SLEEP
CONTROL
ZZ
Logic Block Diagram – CY7C1356DV25 (512K x 18)
A0, A1, A
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
MODE
CLK
CEN
ADV/LD
C
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
S
E
N
S
E
ADV/LD
BW a
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
A
M
P
S
BW b
WE
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
O
U
T
P
U
T
D
A
T
A
B
U
F
F
E
R
S
S
T
E
E
R
I
N
G
E
INPUT
REGISTER 1
OE
CE1
CE2
CE3
ZZ
Document #: 001-48974 Rev. *A
E
DQ s
DQ Pa
DQ Pb
E
INPUT
REGISTER 0
E
READ LOGIC
Sleep
Control
Page 2 of 29
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CY7C1354DV25
CY7C1356DV25
Pin Configuration
The pin configuration for CY7C1354DV25 and CY7C1356DV25 follow.
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
DQPb
DQb
DQb
VDDQ
VSS
NC
NC
NC
VDDQ
VSS
NC
NC
DQb
DQb
VSS
VDDQ
CY7C1356DV25
(512K × 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
A
A
A
A
A
A
A
NC(72M)
NC(36M)
VSS
VDD
NC(288M)
NC(144M)
A
A
A
A
A
A
A
NC(72M)
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
DQb
DQb
NC
VSS
VDD
NC
VDD
NC
VSS
ZZ
DQb
DQa
DQa
DQb
VDDQ VDDQ
VSS
VSS
DQa
DQb
DQa
DQb
DQa DQPb
NC
DQa
VSS
VSS
VDDQ VDDQ
NC
DQa
DQa
NC
DQPa
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
Document #: 001-48974 Rev. *A
NC(36M)
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQPd
VSS
VDD
NC
CY7C1354DV25
(256K × 36)
NC(288M)
NC(144M)
DQc
DQc
NC
VDD
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
DQPc
DQc
DQc
VDDQ
A
A
A
A
CE1
CE2
NC
NC
BWb
BWa
CE3
VDD
VSS
CLK
WE
CEN
OE
ADV/LD
NC(18M)
A
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE1
CE2
BWd
BWc
BWb
BWa
CE3
VDD
VSS
CLK
WE
CEN
OE
ADV/LD
NC(18M)
A
100-Pin TQFP Pinout
Page 3 of 29
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CY7C1354DV25
CY7C1356DV25
Pin Configuration
(continued)
The pin configuration for CY7C1354DV25 and CY7C1356DV25 follow.
119-Ball BGA Pinout CY7C1354DV25 (256K x 36)
1
2
3
4
5
6
7
A
VDDQ
A
A
NC/18M
A
A
VDDQ
B
NC/576M
CE2
A
ADV/LD
A
CE3
NC
C
NC/1G
A
A
VDD
A
A
NC
D
DQc
DQPc
VSS
NC
VSS
DQPb
DQb
E
DQc
DQc
VSS
CE1
VSS
DQb
DQb
F
VDDQ
DQc
VSS
OE
VSS
DQb
VDDQ
G
DQc
DQc
BWc
A
BWb
DQb
DQb
H
DQc
DQc
VSS
WE
VSS
DQb
DQb
J
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
K
DQd
DQd
VSS
CLK
VSS
DQa
DQa
L
DQd
DQd
BWd
NC
BWa
DQa
DQa
M
VDDQ
DQd
VSS
CEN
VSS
DQa
VDDQ
N
DQd
DQd
VSS
A1
VSS
DQa
DQa
P
DQd
DQPd
VSS
A0
VSS
DQPa
DQa
R
NC/144M
A
MODE
VDD
NC
A
NC/288M
T
NC
NC/72M
A
A
A
NC/36M
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
119-Ball BGA Pinout CY7C1356DV25 (512K x 18)
1
2
3
4
5
6
7
A
VDDQ
A
A
NC/18M
A
A
VDDQ
B
NC/576M
CE2
A
ADV/LD
A
CE3
NC
C
NC/1G
A
A
VDD
A
A
NC
D
DQb
NC
VSS
NC
VSS
DQPa
NC
E
NC
DQb
VSS
CE1
VSS
NC
DQa
F
VDDQ
NC
VSS
OE
VSS
DQa
VDDQ
G
NC
DQb
BWb
A
VSS
NC
DQa
H
DQb
NC
VSS
WE
VSS
DQa
NC
J
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
K
NC
DQb
VSS
CLK
VSS
NC
DQa
L
DQb
NC
VSS
NC
BWa
DQa
NC
M
VDDQ
DQb
VSS
CEN
VSS
NC
VDDQ
N
DQb
NC
VSS
A1
VSS
DQa
NC
P
NC
DQPb
VSS
A0
VSS
NC
DQa
R
NC/144M
A
MODE
VDD
NC
A
NC/288M
T
NC/72M
A
A
NC/36M
A
A
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Document #: 001-48974 Rev. *A
Page 4 of 29
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CY7C1354DV25
CY7C1356DV25
Pin Configuration
(continued)
The pin configuration for CY7C1354DV25 and CY7C1356DV25 follow.
165-Ball FBGA Pinout CY7C1354DV25 (256K x 36)
1
2
3
4
5
6
7
8
9
10
11
A
NC/576M
A
CE1
BWc
BWb
CE3
CEN
ADV/LD
A
A
NC
B
NC/1G
A
CE2
BWd
BWa
CLK
WE
OE
NC/18M
A
NC
C
DQPc
NC
VDDQ
VSS
VSS
VSS
VSS
VSS
VDDQ
NC
DQPb
D
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
E
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
F
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
G
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
H
NC
NC
NC
VDD
VSS
VSS
VSS
VDD
NC
NC
ZZ
J
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
K
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
L
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
M
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
N
DQPd
NC
VDDQ
VSS
NC
NC
NC
VSS
VDDQ
NC
DQPa
A
A
TDI
A1
TDO
A
A
A
NC/288M
A
A
TMS
A0
TCK
A
A
A
A
P
R
NC/144M NC/72M
MODE
NC/36M
165-Ball FBGA Pinout CY7C1356DV25 (512K x 18)
1
2
3
4
5
6
7
8
9
10
11
A
NC/576M
A
CE1
BWb
NC
CE3
CEN
ADV/LD
A
A
A
B
NC/1G
A
CE2
NC
BWa
CLK
WE
OE
NC/18M
A
NC
C
NC
NC
VDDQ
VSS
VSS
VSS
VSS
VSS
VDDQ
NC
DQPa
D
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
E
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
F
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
G
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
H
NC
NC
NC
VDD
VSS
VSS
VSS
VDD
NC
NC
ZZ
J
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
K
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
L
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
M
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
N
DQPb
NC
VDDQ
VSS
NC
NC
NC
VSS
VDDQ
NC
NC
A
A
TDI
A1
TDO
A
A
A
NC/288M
A
A
TMS
A0
TCK
A
A
A
A
P
R
NC/144M NC/72M
MODE
NC/36M
Document #: 001-48974 Rev. *A
Page 5 of 29
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CY7C1354DV25
CY7C1356DV25
Pin Definitions
Pin Name
A0
A1
A
IO
Pin Description
InputAddress Inputs used to Select One of the Address Locations. Sampled at the rising edge of the CLK.
Synchronous
BWa,BWb,
InputByte Write Select Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on
BWc,BWd, Synchronous the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb, BWc controls DQc
and DQPc, BWd controls DQd and DQPd.
WE
InputWrite Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal
Synchronous must be asserted LOW to initiate a write sequence.
ADV/LD
InputAdvance or Load Input used to Advance the On-Chip Address Counter or Load a New Address.
Synchronous When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new
address can be loaded into the device for an access. After being deselected, ADV/LD should be driven
LOW in order to load a new address.
CLK
InputClock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is
only recognized if CEN is active LOW.
CE1
InputChip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
Synchronous and CE3 to select and deselect the device.
CE2
InputChip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE3 to select and deselect the device.
CE3
InputChip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE2 to select and deselect the device.
OE
InputOutput Enable, Active LOW. Combined with the synchronous logic block inside the device to control
Asynchronous the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted
HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the data portion of a Write
sequence, during the first clock when emerging from a deselected state and when the device is
deselected.
CEN
InputClock Enable Input, Active LOW. When asserted LOW the clock signal is recognized by the SRAM.
Synchronous When deasserted HIGH the clock signal is masked. Because deasserting CEN does not deselect the
device, CEN can be used to extend the previous cycle when required.
DQS
I/OBidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by the
Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by
addresses during the previous clock rise of the read cycle. The direction of the pins is controlled by OE
and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH,
DQa–DQd are placed in a tri-state condition. The outputs are automatically tri-stated during the data
portion of a write sequence, during the first clock when emerging from a deselected state, and when the
device is deselected, regardless of the state of OE.
DQPX
I/OBidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQ[a:d]. During write
Synchronous sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc, and
DQPd is controlled by BWd.
MODE
Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled
LOW selects the linear burst order. MODE should not change states during operation. When left floating
MODE is default HIGH, to an interleaved burst order.
TDO
JTAG Serial Serial Data-Out to the JTAG Circuit. Delivers data on the negative edge of TCK.
Output
Synchronous
TDI
JTAG Serial Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK.
Input
Synchronous
Document #: 001-48974 Rev. *A
Page 6 of 29
[+] Feedback
CY7C1354DV25
CY7C1356DV25
Pin Definitions
Pin Name
(continued)
IO
Pin Description
TMS
Test Mode Controls the Test Access Port State Machine. Sampled on the rising edge of TCK.
Select
Synchronous
TCK
JTAG-Clock
VDD
VDDQ
Clock Input to the JTAG Circuitry.
Power Supply Power Supply Inputs to the Core of the Device.
I/O Power
Supply
Power Supply for the I/O Circuitry.
VSS
Ground
NC
–
No Connects. This pin is not connected to the die.
NC (18,
36, 72,
144, 288,
576, 1G
–
These Pins are not Connected. They will be used for expansion to the 18M, 36M, 72M, 144M 288M,
576M, and 1G densities.
ZZ
Ground for the Device. Should be connected to ground of the system.
InputZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with
Asynchronous data integrity preserved. For normal operation, this pin has to be LOW or left floating.
ZZ pin has an internal pull-down.
Functional Overview
The CY7C1354DV25 and CY7C1356DV25 are synchronous
pipelined Burst NoBL SRAMs designed specifically to eliminate
wait states during Write/Read transitions. All synchronous inputs
pass through input registers controlled by the rising edge of the
clock. The clock signal is qualified with the Clock Enable input
signal (CEN). If CEN is HIGH, the clock signal is not recognized
and all internal states are maintained. All synchronous operations are qualified with CEN. All data outputs pass through output
registers controlled by the rising edge of the clock. Maximum
access delay from the clock rise (tCO) is 2.8 ns (250 MHz device).
Accesses are initiated by asserting all three Chip Enables (CE1,
CE2, CE3) active at the rising edge of the clock. If Clock Enable
(CEN) is active LOW and ADV/LD is asserted LOW, the address
presented to the device is latched. The access can either be a
read or write operation, depending on the status of the Write
Enable (WE). BW[d:a] can be used to conduct Byte Write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self timed write
circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
must be driven LOW when the device is deselected to load a new
address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the Write Enable input
Document #: 001-48974 Rev. *A
signal WE is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the address register and presented to the memory core and
control logic. The control logic determines that a read access is
in progress and allows the requested data to propagate to the
input of the output register. At the rising edge of the next clock
the requested data is allowed to propagate through the output
register and onto the data bus within 2.8 ns (250 MHz device)
provided OE is active LOW. After the first clock of the read
access the output buffers are controlled by OE and the internal
control logic. OE must be driven LOW for the device to drive out
the requested data. During the second clock, a subsequent
operation (read, write, and deselect) is initiated. Deselecting the
device is also pipelined. Therefore, when the SRAM is
deselected at clock rise by one of the chip enable signals, its
output tri-states following the next clock rise.
Burst Read Accesses
The CY7C1354DV25 and CY7C1356DV25 have an on-chip
burst counter that provides the ability to supply a single address
and conduct up to four reads without reasserting the address
inputs. ADV/LD must be driven LOW to load a new address into
the SRAM, as described in the Single Read Accesses section.
The sequence of the burst counter is determined by the MODE
input signal. A LOW input on MODE selects a linear burst mode,
a HIGH selects an interleaved burst sequence. Both burst
counters use A0 and A1 in the burst sequence, and wraps
around when incremented sufficiently. A HIGH input on ADV/LD
increments the internal burst counter regardless of the state of
chip enables inputs or WE. WE is latched at the beginning of a
burst cycle. Therefore, the type of access (read or write) is
maintained throughout the burst sequence.
Page 7 of 29
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CY7C1354DV25
CY7C1356DV25
Single Write Accesses
Burst Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the write signal WE is
asserted LOW. The address presented to A0∠A16 is loaded into
the Address Register. The write signals are latched into the
Control Logic block.
The CY7C1354DV25 and CY7C1356DV25 has an on-chip burst
counter that provides the ability to supply a single address and
conduct up to four WRITE operations without reasserting the
address inputs. ADV/LD must be driven LOW to load the initial
address, as described in the Single Write Access section above.
When ADV/LD is driven HIGH on the subsequent clock rise, the
chip enables (CE1, CE2, and CE3) and WE inputs are ignored
and the burst counter is incremented. The correct BW (BWa,b,c,d
for CY7C1354DV25 and BWa,b for CY7C1356DV25) inputs must
be driven in each cycle of the burst write to write the correct bytes
of data.
On the subsequent clock rise the data lines are automatically
tri-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1354DV25 and DQa,b/DQPa,b for
CY7C1356DV25). In addition, the address for the subsequent
access (read, write, and deselect) is latched into the address
register (provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1354DV25 and DQa,b/DQPa,b for
CY7C1356DV25) (or a subset for byte write operations, see
Write Cycle Description tables for details) inputs is latched into
the device and the write is complete.
The data written during the write operation is controlled by BW
(BWa,b,c,d for CY7C1354DV25 and BWa,b for CY7C1356DV25)
signals. The CY7C1354DV25/CY7C1356DV25 provides Byte
Write capability that is described in the Write Cycle Description
tables. Asserting the Write Enable input (WE) with the selected
Byte Write Select (BW) input selectively writes to only the desired
bytes. Bytes not selected during a Byte Write operation remains
unaltered. A synchronous self timed write mechanism is
provided to simplify the write operations. Byte Write capability is
included to greatly simplify read, modify, and write sequences,
which can be reduced to simple Byte Write operations.
Because the CY7C1354DV25 and CY7C1356DV25 are
common I/O devices, data should not be driven into the device
while the outputs are active. The Output Enable (OE) can be
deasserted HIGH before presenting data to the DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1354DV25 and DQa,b/DQPa,b for
CY7C1356DV25) inputs. Doing so tri-states the output drivers.
As a safety precaution, DQ and DQP (DQa,b,c,d/DQPa,b,c,d for
CY7C1354DV25 and DQa,b/DQPa,b for CY7C1356DV25) are
automatically tri-stated during the data portion of a write cycle,
regardless of the state of OE.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
When in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE1, CE2,
and CE3, must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1,A0
00
01
10
11
Second
Address
A1,A0
01
00
11
10
Third
Address
A1,A0
10
11
00
01
Fourth
Address
A1,A0
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
A1,A0
00
01
10
11
Second
Address
A1,A0
01
10
11
00
Third
Address
A1,A0
10
11
00
01
Fourth
Address
A1,A0
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
tZZI
tRZZI
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
Document #: 001-48974 Rev. *A
Test Conditions
ZZ > VDD − 0.2V
ZZ > VDD − 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Min
Max
50
2tCYC
2tCYC
2tCYC
0
Unit
mA
ns
ns
ns
ns
Page 8 of 29
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CY7C1354DV25
CY7C1356DV25
Truth Table
The truth table for CY7C1354DV25 and CY7C1356DV25 follows.[1, 2, 3, 4, 5, 6, 7]
Operation
Deselect Cycle
Continue Deselect Cycle
Read Cycle (Begin Burst)
Read Cycle (Continue Burst)
NOP/Dummy Read (Begin Burst)
Dummy Read (Continue Burst)
Write Cycle (Begin Burst)
Write Cycle (Continue Burst)
NOP/WRITE ABORT (Begin Burst)
WRITE ABORT (Continue Burst)
IGNORE CLOCK EDGE (Stall)
SLEEP MODE
Address
Used
None
None
External
Next
External
Next
External
Next
None
Next
Current
None
CE
H
X
L
X
L
X
L
X
L
X
X
X
ZZ
L
L
L
L
L
L
L
L
L
L
L
H
ADV/LD
L
H
L
H
L
H
L
H
L
H
X
X
WE
X
X
H
X
H
X
L
X
L
X
X
X
BWx
X
X
X
X
X
X
L
L
H
H
X
X
OE
X
X
L
L
H
H
X
X
X
X
X
X
CEN
L
L
L
L
L
L
L
L
L
L
H
X
CLK
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
X
DQ
Tri-State
Tri-State
Data Out (Q)
Data Out (Q)
Tri-State
Tri-State
Data In (D)
Data In (D)
Tri-State
Tri-State
–
Tri-State
Write Cycle Description
Write cycle description for CY7C1354DV25 follows.[1, 2, 3, 8]
Function
WE
H
BWd
BWc
BWb
BWa
X
X
X
X
Write –No Bytes Written
L
H
H
H
H
Write Byte a– (DQa and DQPa)
L
H
H
H
L
Read
Write Byte b – (DQb and DQPb)
L
H
H
L
H
Write Bytes b, a
L
H
H
L
L
Write Byte c – (DQc and DQPc)
L
H
L
H
H
Write Bytes c, a
L
H
L
H
L
Write Bytes c, b
L
H
L
L
H
Write Bytes c, b, a
L
H
L
L
L
Write Byte d – (DQd and DQPd)
L
L
H
H
H
Write Bytes d, a
L
L
H
H
L
Write Bytes d, b
L
L
H
L
H
Write Bytes d, b, a
L
L
H
L
L
Write Bytes d, c
L
L
L
H
H
Write Bytes d, c, a
L
L
L
H
L
Write Bytes d, c, b
L
L
L
L
H
Write All Bytes
L
L
L
L
L
Notes
1. X = “Don’t Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid
signifies that the desired Byte Write Selects are asserted, see Write Cycle Description tables for details.
2. Write is defined by WE and BWX. See Write Cycle Description tablse for details.
3. When a write cycle is detected, all I/Os are tri-stated, even during Byte Writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQPX = Tri-state when OE is inactive
or when the device is deselected, and DQs = data when OE is active.
Document #: 001-48974 Rev. *A
Page 9 of 29
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CY7C1354DV25
CY7C1356DV25
Write cycle description for CY7C1356DV25 follows.[1, 2, 3, 8]
Function
WE
BWb
BWa
Read
H
x
x
Write – No Bytes Written
L
H
H
Write Byte a − (DQa and DQPa)
L
H
L
Write Byte b – (DQb and DQPb)
L
L
H
Write Both Bytes
L
L
L
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1354DV25 and CY7C1356DV25 incorporates a serial
boundary scan test access port (TAP) in the BGA package only.
The TQFP package does not offer this functionality. This part
operates in accordance with IEEE Standard 1149.1-1900, but
does not have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note the TAP controller
functions in a manner that does not conflict with the operation of
other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC-standard 2.5V I/O logic levels.
Figure 1. TAP Controller State Diagram[9]
1
TEST-LOGIC
RESET
0
RUN-TEST/
IDLE
0
1
SELECT
DR-SCAN
1
SELECT
IR-SCAN
0
1
0
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
The CY7C1354DV25 and CY7C1356DV25 contains a TAP
controller, instruction register, boundary scan register, bypass
register, and ID register.
0
SHIFT-IR
1
1
EXIT1-IR
0
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should be
left unconnected. During power up, the device comes up in a
reset state which does not interfere with the operation of the
device.
0
PAUSE-IR
1
0
1
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-DR
UPDATE-IR
1
1
0
PAUSE-DR
0
0
1
EXIT1-DR
Disabling the JTAG Feature
1
0
1
0
Notes
8. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active.
9. The 0/1 next to each state represents the value of TMS at the rising edge of the TCK.
Document #: 001-48974 Rev. *A
Page 10 of 29
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CY7C1354DV25
CY7C1356DV25
Test Access Port (TAP)
Performing a TAP Reset
Test Clock (TCK)
A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.Test MODE SELECT (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this ball unconnected if the TAP is not used.
The ball is pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see Figure 1. TDI is internally
pulled up and can be unconnected if the TAP is unused in an
application. TDI is connected to the most significant bit (MSB) of
any register. (See Figure 2.)
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine. The output changes on the falling edge
of TCK. TDO is connected to the least significant bit (LSB) of any
register. (See Figure 1.)
Bypass Register
2 1 0
Instruction Register
31 30 29 . . . 2 1 0
Identification Register
x . . . . . 2 1 0
Boundary Scan Register
TCK
TMS
TAP CONTROLLER
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test circuitry.
Only one register can be selected at a time through the
instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling
edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in TAP Controller Block Diagram.
During power up, the instruction register is loaded with the
IDCODE instruction.
It is also loaded with the IDCODE instruction if the controller is
placed in a reset state as described in the previous section.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board-level serial test data path.
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW (VSS)
when the BYPASS instruction is executed.
0
TDI
TAP Registers
Bypass Register
Figure 2. TAP Controller Block Diagram
Selection
Circuitry
During power up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
Selection
Circuitry
TDO
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used to
capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the bits
are connected. Each bit corresponds to one of the bumps on the
SRAM package. The MSB of the register is connected to TDI,
and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the Identification Register Definitions
table.
Document #: 001-48974 Rev. *A
Page 11 of 29
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CY7C1354DV25
CY7C1356DV25
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the Identification Codes table. Three of these instructions are listed as
RESERVED and should not be used. The other five instructions
are described in detail below.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction after it is shifted in, the TAP controller must be
moved into the Update-IR state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
during power up or whenever the TAP controller is given a test
logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High-Z state until the next command is given
during the “Update IR” state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
Document #: 001-48974 Rev. *A
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output undergoes a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK# captured in the boundary scan register.
When the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required—that is, while data captured
is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST
The EXTEST instruction enables the preloaded data to be driven
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the shift-DR controller state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Page 12 of 29
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CY7C1354DV25
CY7C1356DV25
TAP Timing
Figure 3 shows the TAP timings.
Figure 3. TAP Timing and Test Conditions
1
2
3
4
5
6
Test Clock
(TCK)
t
t TH
t TMSS
t TMSH
t TDIS
t TDIH
TL
t CYC
Test Mode Select
(TMS)
Test Data-In
(TDI)
t TDOV
t TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics
Over the Operating Range [10, 11]
Parameter
Description
Min
Max
Unit
20
MHz
Clock
tTCYC
TCK Clock Cycle Time
tTF
TCK Clock Frequency
tTH
TCK Clock HIGH Time
20
ns
tTL
TCK Clock LOW Time
20
ns
50
ns
Output Times
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock LOW to TDO Invalid
0
ns
tTMSS
TMS Setup to TCK Clock Rise
5
ns
tTDIS
TDI Setup to TCK Clock Rise
5
ns
tCS
Capture Setup to TCK Rise
5
ns
10
ns
Setup Times
Hold Times
tTMSH
TMS Hold after TCK Clock Rise
5
ns
tTDIH
TDI Hold after Clock Rise
5
ns
tCH
Capture Hold after Clock Rise
5
ns
Notes
10. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
11. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns.
Document #: 001-48974 Rev. *A
Page 13 of 29
[+] Feedback
CY7C1354DV25
CY7C1356DV25
2.5V TAP AC Test Conditions
Figure 4. 2.5V TAP AC Output Load Equivalent
1.25V
Input pulse levels ................................................ VSS to 2.5V
Input rise and fall time ....................................................1 ns
Input timing reference levels ........................................ 1.25V
50Ω
Output reference levels ............................................... 1.25V
TDO
Test load termination supply voltage .................... ........1.25V
Z O = 50Ω
20p F
TAP DC Electrical Characteristics and Operating Conditions
(0°C < TA < +70°C; VDD = 2.5V ±0.125V unless otherwise noted)[12]
Parameter
Description
Test Conditions
VOH1
Output HIGH Voltage
VOH2
VOL1
Min
IOH = –1.0 mA, VDDQ = 2.5V
2.0
Output HIGH Voltage
IOH = –100 µA,VDDQ = 2.5V
2.1
Output LOW Voltage
IOL = 8.0 mA, VDDQ = 2.5V
VOL2
Output LOW Voltage
IOL = 100 µA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IX
Input Load Current
Max
Unit
V
V
VDDQ = 2.5V
0.4
V
0.2
V
VDDQ = 2.5V
1.7
VDD + 0.3
V
VDDQ = 2.5V
–0.3
0.7
V
–5
5
µA
GND < VIN < VDDQ
Identification Register Definitions
Instruction Field
CY7C1354DV25
CY7C1356DV25
000
000
Cypress Device ID (28:12)
01011001000100110
01011001000010110
Cypress JEDEC ID (11:1)
00000110100
00000110100
ID Register Presence (0)
1
1
Revision Number (31:29)
Description
Reserved for version number.
Reserved for future use.
Allows unique identification of SRAM vendor.
Indicate the presence of an ID register.
Scan Register Sizes
Register Name
Instruction
Bit Size (x36)
Bit Size (x18)
3
3
Bypass
1
1
ID
32
32
Boundary Scan Order (119-Ball BGA
Package)
69
69
Boundary Scan Order (165-Ball FBGA
Package)
69
69
Note:
12. All voltages referenced to VSS (GND).
Document #: 001-48974 Rev. *A
Page 14 of 29
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CY7C1354DV25
CY7C1356DV25
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures the Input/Output ring contents. Places the boundary scan register between the TDI and
TDO. Forces all SRAM outputs to High-Z state.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO. This
operation does not affect SRAM operation.
SAMPLE Z
010
Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO.
Does not affect the SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.
Document #: 001-48974 Rev. *A
Page 15 of 29
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CY7C1354DV25
CY7C1356DV25
Boundary Scan Exit Order (256K × 36)
Bit #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
119-Ball ID
K4
H4
M4
F4
B4
G4
C3
B3
D6
H7
G6
E6
D7
E7
F6
G7
H6
T7
K7
L6
N6
P7
N7
M6
L7
K6
P6
T4
A3
C5
B5
A5
C6
A6
P4
N4
R6
T5
T3
R2
R3
P2
P1
L2
K1
N2
Document #: 001-48974 Rev. *A
Boundary Scan Exit Order (256K × 36) (continued)
165-Ball ID
B6
B7
A7
B8
A8
A9
B10
A10
C11
E10
F10
G10
D10
D11
E11
F11
G11
H11
J10
K10
L10
M10
J11
K11
L11
M11
N11
R11
R10
P10
R9
P9
R8
P8
R6
P6
R4
P4
R3
P3
R1
N1
L2
K2
J2
M2
Bit #
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
119-Ball ID
N1
M2
L1
K2
Not Bonded
(Preset to 1)
H1
G2
E2
D1
H2
G1
F2
E1
D2
C2
A2
E4
B2
L3
G3
G5
L5
B6
165-Ball ID
M1
L1
K1
J1
Not Bonded
(Preset to 1)
G2
F2
E2
D2
G1
F1
E1
D1
C1
B2
A2
A3
B3
B4
A4
A5
B5
A6
Page 16 of 29
[+] Feedback
CY7C1354DV25
CY7C1356DV25
Boundary Scan Exit Order (512K × 18)
Bit #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
119-Ball ID
K4
H4
M4
F4
B4
G4
C3
B3
T2
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
D6
E7
F6
G7
H6
T7
K7
L6
N6
P7
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
T6
A3
C5
B5
A5
C6
A6
P4
N4
R6
T5
T3
R2
R3
Not Bonded
(Preset to 0)
Document #: 001-48974 Rev. *A
Boundary Scan Exit Order (512K × 18) (continued)
165-Ball ID
B6
B7
A7
B8
A8
A9
B10
A10
A11
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
C11
D11
E11
F11
G11
H11
J10
K10
L10
M10
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
R11
R10
P10
R9
P9
R8
P8
R6
P6
R4
P4
R3
P3
R1
Not Bonded
(Preset to 0)
Bit #
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
69
69
68
69
66
67
68
69
119-Ball ID
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
P2
N1
M2
L1
K2
Not Bonded
(Preset to 1)
H1
G2
E2
D1
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
C2
A2
E4
B2
Not Bonded
(Preset to 0
G3
Not Bonded
(Preset to 0
L5
B6
B6
B6
L5
B6
G3
Not Bonded
(Preset to 0
L5
B6
165-Ball ID
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
N1
M1
L1
K1
J1
Not Bonded
(Preset to 1)
G2
F2
E2
D2
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
B2
A2
A3
B3
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
A4
B5
A6
A6
A6
B5
A6
Not Bonded
(Preset to 0)
A4
B5
A6
Page 17 of 29
[+] Feedback
CY7C1354DV25
CY7C1356DV25
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Supply Voltage on VDD Relative to GND ........–0.5V to +3.6V
Supply Voltage on VDDQ Relative to GND.......–0.5V to +VDD
DC to Outputs in Tri-State.................... –0.5V to VDDQ + 0.5V
DC Input Voltage ................................... –0.5V to VDD + 0.5V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch Up Current ................................................... > 200 mA
Operating Range
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
VDD/VDDQ
2.5V ± 5%
Electrical Characteristics
Over the Operating Range[13, 14]
Parameter
Description
Test Conditions
Min
Max
Unit
2.375
2.625
V
2.375
VDD
V
VDD
Power Supply Voltage
VDDQ
I/O Supply Voltage
for 2.5V I/O
VOH
Output HIGH Voltage
for 2.5V I/O, IOH = −1.0 mA
VOL
Output LOW Voltage
for 2.5V I/O, IOL= 1.0 mA
VIH
Input HIGH Voltage
for 2.5V I/O
VIL
Input LOW Voltage[13]
for 2.5V I/O
IX
Input Leakage Current
except ZZ and MODE
GND ≤ VI ≤ VDDQ
–5
Input Current of MODE
Input = VSS
–30
2.0
0.4
V
1.7
VDD + 0.3V
V
–0.3
0.7
V
5
μA
Input = VDD
Input Current of ZZ
V
μA
5
Input = VSS
Input = VDD
30
IOZ
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
IDD
VDD Operating Supply
μA
μA
–5
μA
5
μA
4 ns cycle, 250 MHz
250
mA
5 ns cycle, 200 MHz
220
mA
6 ns cycle, 166 MHz
180
mA
Automatic CE
Power Down
Current—TTL Inputs
Max VDD, Device Deselected, VIN 4 ns cycle, 250 MHz
≥ VIH or VIN ≤ VIL, f = fMAX = 1/tCYC 5 ns cycle, 200 MHz
130
mA
120
mA
6 ns cycle, 166 MHz
110
mA
ISB2
Automatic CE
Power Down
Current—CMOS Inputs
Max VDD, Device Deselected, VIN All speed grades
≤ 0.3V or VIN > VDDQ − 0.3V, f = 0
40
mA
ISB3
Automatic CE
Power Down
Current—CMOS Inputs
Max VDD, Device Deselected, VIN 4 ns cycle, 250 MHz
≤ 0.3V or VIN > VDDQ − 0.3V, f = 5 ns cycle, 200 MHz
fMAX = 1/tCYC
6 ns cycle, 166 MHz
120
mA
110
mA
100
mA
Automatic CE
Power Down
Current—TTL Inputs
Max VDD, Device Deselected, VIN All speed grades
≥ VIH or VIN ≤ VIL, f = 0
40
mA
ISB1
ISB4
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
–5
Notes
13. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> –2V (Pulse width less than tCYC/2).
14. TPower-up: Assumes a linear ramp from 0V to VDD (minimum) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document #: 001-48974 Rev. *A
Page 18 of 29
[+] Feedback
CY7C1354DV25
CY7C1356DV25
Capacitance[15]
Parameter
Description
Test Conditions
CIN
Input Capacitance
CCLK
Clock Input Capacitance
CI/O
Input/Output Capacitance
100 TQFP
Max
119 BGA Max
165 FBGA
Max
Unit
5
5
5
pF
TA = 25°C, f = 1 MHz,
VDD = 2.5V, VDDQ = 2.5V
5
5
5
pF
5
7
7
pF
Thermal Resistance[15]
Parameters
Description
Thermal Resistance
ΘJA
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
Test conditions follow standard
test methods and procedures
for measuring thermal
impedance, per EIA/JESD51.
100 TQFP
Package
29.41
119 BGA
Package
34.1
165 FBGA
Package
16.8
Unit
°C/W
6.13
14
3.0
°C/W
Figure 5. AC Test Loads and Waveforms
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
Z0 = 50Ω
10%
(a)
INCLUDING
JIG AND
SCOPE
90%
10%
90%
GND
5 pF
VT = 1.25V
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50Ω
R = 1538Ω
(b)
≤ 1 ns
≤ 1 ns
(c)
Note
15. Tested initially and after any design or process change that may affect these parameters.
Document #: 001-48974 Rev. *A
Page 19 of 29
[+] Feedback
CY7C1354DV25
CY7C1356DV25
Switching Characteristics
Over the Operating Range [17, 18]
–250
Parameter
tPower
[16]
–200
Max
Min
–166
Description
Min
Max
Min
Max
Unit
VCC (Typical) to the First Access Read or Write
1
1
1
ms
4.0
5
6
ns
Clock
tCYC
Clock Cycle Time
FMAX
Maximum Operating Frequency
tCH
Clock HIGH
1.8
2.0
2.4
ns
tCL
Clock LOW
1.8
2.0
2.4
ns
250
200
166
MHz
Output Times
tCO
Data Output Valid after CLK Rise
2.8
3.2
3.5
ns
tEOV
OE LOW to Output Valid
2.8
3.2
3.5
ns
3.5
ns
tDOH
Data Output Hold after CLK Rise
1.25
tCHZ
Clock to High-Z[19, 20, 21]
1.25
tCLZ
Clock to Low-Z[19, 20, 21]
1.25
tEOHZ
tEOLZ
OE HIGH to Output
High-Z[19, 20, 21]
OE LOW to Output
Low-Z[19, 20, 21]
1.5
2.8
1.5
1.5
3.2
1.5
2.8
1.5
ns
1.5
3.2
ns
3.5
ns
0
0
0
ns
Setup Times
tAS
Address Setup before CLK Rise
1.4
1.5
1.5
ns
tDS
Data Input Setup before CLK Rise
1.4
1.5
1.5
ns
tCENS
CEN Setup before CLK Rise
1.4
1.5
1.5
ns
tWES
WE, BWx Setup before CLK Rise
1.4
1.5
1.5
ns
tALS
ADV/LD Setup before CLK Rise
1.4
1.5
1.5
ns
tCES
Chip Select Setup
1.4
1.5
1.5
ns
tAH
Address Hold after CLK Rise
0.4
0.5
0.5
ns
tDH
Data Input Hold after CLK Rise
0.4
0.5
0.5
ns
tCENH
CEN Hold after CLK Rise
0.4
0.5
0.5
ns
tWEH
WE, BWx Hold after CLK Rise
0.4
0.5
0.5
ns
tALH
ADV/LD Hold after CLK Rise
0.4
0.5
0.5
ns
tCEH
Chip Select Hold after CLK Rise
0.4
0.5
0.5
ns
Hold Times
Notes
16. This part has a voltage regulator internally; tpower is the time power needs to be supplied above VDD minimum initially, before a read or write operation can be initiated.
17. Timing reference level is when VDDQ = 2.5V.
18. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
19. tCHZ, tCLZ, tEOLZ, and tEOHZ are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
20. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
High-Z prior to Low-Z under the same system conditions.
21. This parameter is sampled and not 100% tested.
Document #: 001-48974 Rev. *A
Page 20 of 29
[+] Feedback
CY7C1354DV25
CY7C1356DV25
Switching Waveforms
Figure 6. Read/Write Timing[22, 23, 24]
1
2
3
t CYC
4
5
6
A3
A4
7
8
9
A5
A6
10
CLK
t CENS
t CENH
t CH
t CL
CEN
t CES
t CEH
CE
ADV/LD
WE
BW X
A1
ADDRESS
A2
A7
t CO
t AS
t DS
t AH
Data
In-Out (DQ)
t DH
D(A1)
t CLZ
D(A2)
D(A2+1)
t DOH
Q(A3)
t OEV
Q(A4)
t CHZ
Q(A4+1)
D(A5)
Q(A6)
t OEHZ
t DOH
t OELZ
OE
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
D(A2+1)
READ
Q(A3)
DON’T CARE
READ
Q(A4)
BURST
READ
Q(A4+1)
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
UNDEFINED
Notes
22. For this waveform ZZ is tied LOW.
23. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH,CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
24. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document #: 001-48974 Rev. *A
Page 21 of 29
[+] Feedback
CY7C1354DV25
CY7C1356DV25
Switching Waveforms (continued)
Figure 7. NOP, STALL and DESELECT CYCLES[22, 23, 25]
1
2
A1
A2
3
4
5
A3
A4
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BW X
ADDRESS
A5
t CHZ
D(A1)
Data
Q(A2)
D(A4)
Q(A3)
Q(A5)
In-Out (DQ)
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
DON’T CARE
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
UNDEFINED
Note
25. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.
Document #: 001-48974 Rev. *A
Page 22 of 29
[+] Feedback
CY7C1354DV25
CY7C1356DV25
Switching Waveforms (continued)
Figure 8. ZZ Mode Timing[26, 27]
CLK
t
ZZ
I
t
ZZ
ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
A LL INPUTS
DESELECT or READ Only
(except ZZ)
Outputs (Q)
High-Z
DON’T CARE
Notes
26. Device must be deselected when entering ZZ mode. See Write Cycle Description tables for all possible signal conditions to deselect the device.
27. I/Os are in High-Z when exiting ZZ sleep mode.
Document #: 001-48974 Rev. *A
Page 23 of 29
[+] Feedback
CY7C1354DV25
CY7C1356DV25
Ordering Information
Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit
www.cypress.com for actual products offered.
Speed
(MHz)
166
Ordering Code
CY7C1354DV25-166AXC
Package
Diagram
Part and Package Type
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Operating
Range
Commercial
CY7C1356DV25-166AXC
CY7C1354DV25-166BGC
51-85115 119-Ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1356DV25-166BGC
CY7C1354DV25-166BGXC
51-85115 119-Ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
CY7C1356DV25-166BGXC
CY7C1354DV25-166BZC
51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1356DV25-166BZC
CY7C1354DV25-166BZXC
51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
CY7C1356DV25-166BZXC
CY7C1354DV25-166AXI
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Industrial
CY7C1356DV25-166AXI
CY7C1354DV25-166BGI
51-85115 119-Ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1356DV25-166BGI
CY7C1354DV25-166BGXI
51-85115 119-Ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
CY7C1356DV25-166BGXI
CY7C1354DV25-166BZI
51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1356DV25-166BZI
CY7C1354DV25-166BZXI
51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
CY7C1356DV25-166BZXI
200
CY7C1354DV25-200AXC
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Commercial
CY7C1356DV25-200AXC
CY7C1354DV25-200BGC
51-85115 119-Ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1356DV25-200BGC
CY7C1354DV25-200BGXC
51-85115 119-Ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
CY7C1356DV25-200BGXC
CY7C1354DV25-200BZC
51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1356DV25-200BZC
CY7C1354DV25-200BZXC
51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
CY7C1356DV25-200BZXC
CY7C1354DV25-200AXI
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Industrial
CY7C1356DV25-200AXI
CY7C1354DV25-200BGI
51-85115 119-Ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1356DV25-200BGI
CY7C1354DV25-200BGXI
51-85115 119-Ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
CY7C1356DV25-200BGXI
CY7C1354DV25-200BZI
51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1356DV25-200BZI
CY7C1354DV25-200BZXI
51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
CY7C1356DV25-200BZXI
Document #: 001-48974 Rev. *A
Page 24 of 29
[+] Feedback
CY7C1354DV25
CY7C1356DV25
Ordering Information (continued)
Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit
www.cypress.com for actual products offered.
Speed
(MHz)
250
Ordering Code
CY7C1354DV25-250AXC
Package
Diagram
Part and Package Type
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Operating
Range
Commercial
CY7C1356DV25-250AXC
CY7C1354DV25-250BGC
51-85115 119-Ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1356DV25-250BGC
CY7C1354DV25-250BGXC
51-85115 119-Ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
CY7C1356DV25-250BGXC
CY7C1354DV25-250BZC
51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1356DV25-250BZC
CY7C1354DV25-250BZXC
51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
CY7C1356DV25-250BZXC
CY7C1354DV25-250AXI
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Industrial
CY7C1356DV25-250AXI
CY7C1354DV25-250BGI
51-85115 119-Ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1356DV25-250BGI
CY7C1354DV25-250BGXI
51-85115 119-Ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
CY7C1356DV25-250BGXI
CY7C1354DV25-250BZI
51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1356DV25-250BZI
CY7C1354DV25-250BZXI
51-85180 165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
CY7C1356DV25-250BZXI
Document #: 001-48974 Rev. *A
Page 25 of 29
[+] Feedback
CY7C1354DV25
CY7C1356DV25
Package Diagrams
Figure 9. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) (51-85050)
16.00±0.20
1.40±0.05
14.00±0.10
100
81
80
1
20.00±0.10
22.00±0.20
0.30±0.08
0.65
TYP.
30
12°±1°
(8X)
SEE DETAIL
A
51
31
50
0.20 MAX.
R 0.08 MIN.
0.20 MAX.
0.10
1.60 MAX.
0° MIN.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
0.25
NOTE:
1. JEDEC STD REF MS-026
GAUGE PLANE
0°-7°
R 0.08 MIN.
0.20 MAX.
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0.60±0.15
0.20 MIN.
1.00 REF.
DETAIL
Document #: 001-48974 Rev. *A
A
51-85050-*B
Page 26 of 29
[+] Feedback
CY7C1354DV25
CY7C1356DV25
Package Diagrams (continued)
Figure 10. 119-Ball BGA (14 x 22 x 2.4 mm) (51-85115)
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.75±0.15(119X)
Ø1.00(3X) REF.
1
2
3 4
5
6
7
7
6
5
4 3 2 1
A
A
B
B
C
D
1.27
C
D
E
E
F
F
H
19.50
J
K
L
20.32
G
H
22.00±0.20
G
J
K
L
M
10.16
M
N
P
N
P
R
R
T
T
U
U
1.27
0.70 REF.
A
3.81
7.62
30° TYP.
14.00±0.20
0.15(4X)
0.15 C
2.40 MAX.
B
0.90±0.05
0.25 C
12.00
C
Document #: 001-48974 Rev. *A
0.60±0.10
0.56
SEATING PLANE
51-85115-*B
Page 27 of 29
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CY7C1354DV25
CY7C1356DV25
Package Diagrams (continued)
Figure 11. 165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180)
BOTTOM VIEW
PIN 1 CORNER
TOP VIEW
Ø0.05 M C
Ø0.25 M C A B
PIN 1 CORNER
Ø0.50 -0.06 (165X)
+0.14
1
2
3
4
5
6
7
8
9
10
11
11
9
8
7
6
5
4
3
2
1
A
B
B
C
C
1.00
A
D
D
E
F
F
G
G
H
J
14.00
E
15.00±0.10
15.00±0.10
10
H
J
K
L
L
7.00
K
M
M
N
N
P
P
R
R
A
A
1.00
5.00
10.00
B
B
13.00±0.10
13.00±0.10
0.15 C
1.40 MAX.
0.53±0.05
0.25 C
0.15(4X)
NOTES :
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
PACKAGE WEIGHT : 0.475g
JEDEC REFERENCE : MO-216 / DESIGN 4.6C
PACKAGE CODE : BB0AC
0.35±0.06
0.36
SEATING PLANE
C
Document #: 001-48974 Rev. *A
51-85180-*A
Page 28 of 29
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CY7C1354DV25
CY7C1356DV25
Document History Page
Document Title: CY7C1354DV25/CY7C1356DV25, 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL™ Architecture
Document Number: 001-48974
Origin of Submission
Change
Date
Rev.
ECN No.
**
2594961
VKN
10/22/08
*A
2746930
07/31/09
NJY
Description of Change
NSO data sheet for Tellabs
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