INTEGRATED CIRCUITS FB2041 7-bit Futurebus+ transceiver Product specification IC19 Data Handbook 1995 May 25 Philips Semiconductors Product specification 7-bit Futurebus+ transceiver FB2041 • Allows incident wave switching in heavily loaded backplane buses • Reduced BTL voltage swing produces less noise and reduces DESCRIPTION The FB2041 is a 7-bit bidirectional BTL transceiver and is intended to provide the electrical interface to a high performance wired-OR bus. The FB2041 is an inverting transceiver. power consumption • Built-in precision band-gap reference provides accurate receiver The B-port drivers are Low-capacitance open collectors with controlled ramp and are designed to sink 100mA. Precision band gap references on the B-port insure very good noise margins by limiting the switching threshold to a narrow region centered at 1.55V. thresholds and improved noise immunity • Compatible with IEEE Futurebus+ or proprietary BTL backplanes • Controlled output ramp and multiple GND pins minimize ground bounce • Each BTL driver has a dedicated Bus GND for a signal return • Glitch-free power up/power down operation • Low ICC current • Tight output skew • Supports live insertion • Pins for the optional JTAG boundary scan function are provided • High density packaging in plastic Quad Flatpack FEATURES • 7-bit BTL transceiver • Separate I/O on TTL A-port • Inverting • Three separate pairs of driver enables in a 1 bit, 3 bit, 3 bit arrangement • Drives heavily loaded backplanes with equivalent load impedances down to 10Ω. • High drive 100mA BTL open collector drivers on B-port QUICK REFERENCE DATA SYMBOL PARAMETER TYPICAL tPLH Propagation delay 3.7 tPHL AIn to Bn 2.7 tPLH Propagation delay 3.4 tPHL Bn to AOn 3.2 COB Output capacitance (B0 - B6 only) IOL Output current (B0 - B6 only) ICC Supply Current UNIT ns ns 6 pF 100 mA Standby 19 AIn to Bn (outputs Low or High) 40 Bn to AOn (outputs Low) 22 Bn to AOn (outputs High) 19 mA ORDERING INFORMATION PACKAGE 52-pin Plastic Quad Flatpack 1995 May 25 COMMERCIAL RANGE VCC = 5V±10%; Tamb = 0 to +70°C INDUSTRIAL RANGE VCC = 5V±10%; Tamb = -40 to +85°C DWG No. FB2041BB CD3207BB SOT379-1 2 853-1561 15279 Philips Semiconductors Product specification 7-bit Futurebus+ transceiver FB2041 B0 TMS (option) BUS GND TCK (option) BUS VCC OEB0 OEB1 OEA1 LOGIC VCC BIAS V AI0 AO0 AO1 PIN CONFIGURATION 52 51 50 49 48 47 46 45 44 43 42 41 40 LOGIC GND 1 39 BUS GND AI1 2 38 B1 AI2 3 37 BUS GND AO2 4 36 B2 LOGIC GND 5 7-Bit Transceiver 35 BUS GND AO3 6 FB2041 34 B3 LOGIC GND 7 33 BUS GND 32 B4 31 BUS GND AI3 8 AI4 9 AO4 10 30 B5 LOGIC GND 11 29 BUS GND AO5 12 28 B6 LOGIC GND 13 27 BUS GND 52-lead PQFP OEB3 OEB2 OEA3 BUS VCC TDI (option) To support live insertion, OEB0 is held Low during power on/off cycles to insure glitch free B port drivers. Proper bias for B port drivers during live insertion is provided by the BIAS V pin when at a 5V level while VCC is Low. If live insertion is not a requirement, the BIAS V pin should be tied to a VCC pin. The B-port interfaces to “Backplane Transceiver Logic” (See the IEEE 1194.1 BTL standard). BTL features low power consumption by reducing voltage swing (1Vp-p, between 1V and 2V) and reduced capacitive loading by placing an internal series diode on the drivers. BTL also provides incident wave switching, a necessity for high performance backplanes. The LOGIC GND and BUS GND pins are isolated in the package to minimize noise coupling between the BTL and TTL sides. These pins should be tied to a common ground external to the package. There are three separate pairs of driver enables in a 1 bit, 3 bit, 3 bit arrangement. The TTL/BTL output drivers for bit 0 are enabled with OEA1/OEB1, output drivers for bits 1–2–3 are enabled with OEA2/OEB2 and output drivers for bits 4–5–6 are enabled with OEA3/OEB3. Each BTL driver has an associated BUS GND pin that acts as a signal return path and these BUS GND pins are internally isolated from each other. In the event of a ground return fault, a “hard” signal failure occurs instead of a pattern dependent error that may be very infrequent and impossible to trouble-shoot. The A-port operates at TTL levels with separate I/O. The 3-state A-port drivers are enabled when OEAn goes High after an extra 6ns delay which is built in to provide a break-before-make function. When OEAn goes Low, A-port drivers become High impedance without any extra delay. During power on/off cycles, the A-port drivers are held in a High impedance state when VCC is below 2.5V. The LOGIC VCC and BUS VCC pins are also isolated internally to minimize noise and may be externally decoupled separately or simply tied together. JTAG boundary scan functionality is provided as an option with signals TMS, TCK, TDI and TDO. When this option is not present, TMS and TCK are no-connects (no bond wires) and TDI and TDO are shorted together internally. The B-port has an output enable, OEB0, which affects all seven drivers. When OEB0 is High and OEBn is Low the output driver will be enabled. When OEB0 is Low or if OEBn is High, the B-port drivers will be inactive and at the level of the backplane signal. 1995 May 25 TDO (option) OEA2 LOGIC GND AI6 LOGIC VCC AO6 AI5 LOGIC GND 14 15 16 17 18 19 20 21 22 23 24 25 26 3 Philips Semiconductors Product specification 7-bit Futurebus+ transceiver FB2041 PIN DESCRIPTION SYMBOL PIN NUMBER TYPE AI0 – AI6 51, 2, 3, 8, 9, 14, 18 Input NAME AND FUNCTION AO0 – AO6 50, 52, 4, 6, 10, 12, 16 Output B0 – B6 40, 38, 36, 34, 32, 30, 28 I/O OEB0 46 Input Enables the Bn outputs when High OEB1 45 Input Enables the B0 output when Low OEB2 25 Input Enables the B1 – B3 outputs when Low OEB3 26 Input Enables the B4 – B6 outputs when Low OEA1 47 Input Enables the A0 outputs when High OEA2 20 Input Enables the A1 – A3 outputs when High OEA3 24 Input Enables the A4 – A6 outputs when High BUS GND 41, 39, 37, 35, 33, 31, 29, 27 GND Bus ground (0V) LOGIC GND 1, 5, 7, 11, 13, 15, 19 GND Logic ground (0V) BUS VCC 23, 43 Power Positive supply voltage LOGIC VCC 17, 49 Power Positive supply voltage BIAS V 48 Power Positive supply voltage TMS 42 Input Test Mode Select (no-connect) TCK 44 Input Test Clock (no-connect) TDI 22 Input Test Data In (shorted to TDO) TDO 21 Output Data inputs (TTL) 3-state outputs (TTL) Data inputs/Open Collector outputs, High current drive (BTL) Test Data Out (TDI) ABSOLUTE MAXIMUM RATINGS Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range. PARAMETER SYMBOL VCC Supply voltage VIN Input In ut voltage IIN Input current VOUT IOUT TSTG RATING UNIT -0.5 to +7.0 V AI0 – AI6, OEB0, OEBn, OEAn -1.2 to +7.0 V B0 – B6 -1.2 to +5.5 -18 to +5.0 Voltage applied to output in High output state Current applied to output in Low output state mA -0.5 to +VCC V AO0 – AO6 48 mA B0 – B6 200 Storage temperature °C -65 to +150 RECOMMENDED OPERATING CONDITIONS VCC VIH COMMERCIAL LIMITS VCC = 5V±10%; Tamb = 0 to +70°C PARAMETER SYMBOL Supply voltage High-level in input ut voltage VIL input Low-level in ut voltage IIK Input clamp current IOH High-level output current MIN TYP MAX MIN TYP MAX 4.5 5.0 5.5 4.5 5.0 5.5 Except B0–B6 2.0 B0 – B6 1.62 2.0 1.55 1.62 UNIT V V 1.55 Except B0–B6 0.8 0.8 B0 – B6 1.47 1.47 V -18 -18 mA AO0 – AO6 -3 -3 mA AO0 – AO6 24 24 mA B0 – B6 100 100 IOL Low-level out output ut current COB Output capacitance on B port Tamb Operating free-air temperature range 1995 May 25 INDUSTRIAL LIMITS VCC = 5V±10%; Tamb = -40 to +85°C 6 0 7 +70 4 6 -40 7 pF +85 °C Philips Semiconductors Product specification 7-bit Futurebus+ transceiver FB2041 FUNCTION TABLE MODE AIn to Bn AI0 to B0 AI1 – AI3 to B1 – B3 AI4 – AI6 to B4 – B6 Disable Bn outputs INPUTS OUTPUTS AIn Bn* OEB0 OEB1 OEB2 OEB3 OEA1 OEA2 OEA3 AOn Bn* L — H L L L L L L Z H** H — H L L L L L L Z L L — H L L L H H H L H** H — H L L L H H H H L L — H L X X L L L Z H** H — H L X X L L L Z L L — H L X X H H H L H** H — H L X X H H H H L L — H X L X L L L Z H** H — H X L X L L L Z L H** L — H X L X H H H L H — H X L X H H H H L L — H X X L L L L Z H** H — H X X L L L L Z L L — H X X L H H H L H** H — H X X L H H H H L X X L X X X X X X X H** X X X H H H X X X X H** Disable B0 outputs X X H H X X X X X X H** Disable B1 – B3 outputs X X H X H X X X X X H** Disable B4 – B6 outputs X X H X X H X X X X H** X L L X X X H H H H Input X H L X X X H H H L Input X L X H H H H H H H Input X H X H H H H H H L Input X L L X X X H X X H Input X H L X X X H X X L Input X L X H H H H X X H Input X H X H H H H X X L Input X L L X X X X H X H Input X H L X X X X H X L Input X L X H H H X H X H Input X H X H H H X H X L Input X L L X X X X X H H Input X H L X X X X X H L Input X L X H H H X X H H Input X H X H H H X X H L Input Disable AOn outputs X X X X X X L L L Z X Disable AO0 outputs X X X X X X L X X Z X Disable AO1 – AO3 outputs X X X X X X X L X Z X Disable AO4 – AO6 outputs X X X X X X X X L Z X Bn to AOn B0 to AO0 B1 – B3 to AO1 – AO3 B4 – B6 to AO4 – AO6 NOTES: H = L = X = Z = — = H** = B* = Z — H** B* High voltage level Low voltage level Don’t care High-impedance (OFF) state Input not externally driven Goes to level of pull-up voltage Precaution should be taken to ensure B inputs do not float. If they do, they are equal to Low state. 1995 May 25 5 = = = = High-impedance (OFF) state Input not externally driven Goes to level of pull-up voltage Precaution should be taken to ensure B inputs do not float. If they do, they are equal to Low state. Philips Semiconductors Product specification 7-bit Futurebus+ transceiver FB2041 LOGIC DIAGRAM OEB0 OEB1 OEA1 46 45 47 40 AI0 AO0 OEB2 OEA2 51 50 25 20 38 AI1 AO1 2 AO2 3 34 AO3 OEB3 OEA3 8 AO4 AO5 24 9 AO6 TMS TCK TDI TDO LOGIC VCC LOGIC GND BUS VCC BUS GND BIAS V = = = = = B4 10 14 B5 12 28 AI6 BTL Levels 26 30 AI5 B3 6 32 AI4 B2 4 TTL Levels AI3 B1 52 36 AI2 B0 18 B6 16 42 44 22 21 (Future JTAG Boundary Scan option) 17, 49 1, 5, 7, 11, 13, 15, 19 23, 43 27, 29, 31, 33, 35, 37, 39, 41 48 SG00071 1995 May 25 6 Philips Semiconductors Product specification 7-bit Futurebus+ transceiver FB2041 LIVE INSERTION SPECIFICATIONS SYMBOL VBIASV IBIASV S LIMITS PARAMETER Bias pin voltage MIN VCC = 0 to 5.25V, Bn = 0 to 2.0V Bias pin DC current TYP 4.5 UNIT MAX 5.5 V VCC = 0 to 4.75V, Bn = 0 to 2.0V, Bias V = 4.5 to 5.5V 1 mA VCC = 4.5 to 5.5V, Bn = 0 to 2.0V, Bias V = 4.5 to 5.5V 10 µA VBn Bus voltage during prebias B0 – B8 = 0V, Bias V = 5.0V ILM Fall current during prebias B0 – B8 = 2V, Bias V = 4.5 to 5.5V 1 µA IHM Rise current during prebias B0 – B8 = 1V, Bias V = 4.5 to 5.5V -1 µA IBnPEAK Peak bus current during insertion VCC = 0 to 5.25V, B0 – B8 = 0 to 2.0V, Bias V = 4.5 to 5.5V, OEB0 = 0.8V, tr = 2ns 10 IOL O OFF Power up current VCC = 0 to 5.25V, OEB0 = 0.8V 100 VCC = 0 to 2.2V, OEB0 = 0 to 5V 100 tGR Input glitch rejection VCC = 5.0V 1.62 1.0 2.1 V mA µA 1.35 ns DC ELECTRICAL CHARACTERISTICS Over recommended operating free-air temperature range unless otherwise noted. SYMBOL TEST CONDITIONS1 PARAMETER LIMITS MIN TYP2 MAX UNIT IOH High level output current B0 – B6 VCC = MAX, VIL = MAX, VIH = MIN, VOH = 2.1V 100 µA IOFF Power-off output current B0 – B6 VCC = 0.0V, VIL = MAX, VIH = MIN, VOH = 2.1V 100 µA VOH High-level output voltage AO0 – AO6 3 VCC = MIN, VIL = MAX, VIH = MIN, IOH = -3mA 3 VCC = MIN, VIL = MAX, VIH = MIN, IOL = 24mA AO0 – AO6 VOL VIK II IIH IIL Low-level output voltage B0 – B6 Input clamp voltage VCC = MIN, VIL = MAX, VIH = MIN, IOL = 80mA 2.5 .75 2.85 V 0.33 0.5 1.0 1.10 VCC = MIN, VIL = MAX, VIH = MIN, IOL = 100mA 1.15 V VCC = MIN, II = IIK -1.2 V Input current at maximum input voltage OEB0, OEBn, OEAn, AI0 – AI6 VCC = MAX, VI = GND or 5.5V ±50 µA g High-level input current OEB0, OEBn, OEAn, AI0 – AI6 VCC = MAX, VI = 2.7V 20 µ µA B0 – B6 VCC = MAX, VI = 2.1V 100 OEB0, OEBn, OEAn, AI0 – AI6 VCC = MAX, VI = 0.5V B0 – B6 VCC = MAX, VI = 0.75V Low-level input current -20 µ µA -100 IOZH Off-state output current AO0 – AO6 VCC = MAX, VO = 2.7V 50 µA IOZL Off-state output current AO0 – AO6 VCC = MAX, VO = 0.5V -50 µA Output current AO0 – AO6 only VCC = MAX -55 -150 mA ICCZ (standby) VCC = MAX 19 30 ICCB, AIn to Bn VCC = MAX, outputs Low or High 40 60 ICCA, Bn to AOn VCC = MAX, outputs Low 22 35 ICCA, Bn to AOn VCC = MAX, outputs High 19 35 IO ICC Supply current (total) -30 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type. 2. All typical values are at VCC = 5V, TA = 25°C. 3. Due to test equipment limitations, actual test conditions are VIH = 1.8V and VIL = 1.3V for the B side. 1995 May 25 7 Philips Semiconductors Product specification 7-bit Futurebus+ transceiver FB2041 AC ELECTRICAL CHARACTERISTICS (Commercial) A PORT LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25°C, VCC = 5V, CL = 50pF, RL = 500Ω Tamb = 0 to 70°C, VCC = 5V±10%, CL = 50pF, RL = 500Ω UNIT MIN TYP MAX MIN MAX Waveform 1, 2 1.8 1.6 3.4 3.2 5.0 4.9 1.6 1.6 5.5 5.0 ns Output enable time, OEA to AOn Waveform 4, 5 2.2 2.0 5.0 4.0 6.5 6.5 2.0 1.8 10.0 8.0 ns tPHZ tPLZ Output disable time, OEA to AOn Waveform 4, 5 1.5 1.8 3.3 3.0 4.8 5.0 1.2 1.5 5.0 5.5 ns tTLH tTHL Transition time, AOn Port (10% to 90% or 90% to 10%) Test Circuit and Waveforms 1.5 1.5 2.2 2.4 3.0 3.0 1.5 1.5 3.5 3.5 ns 0.4 1.0 1.0 ns tPLH tPHL Propagation delay, Bn to AOn tPZH tPZL tSK(o) Output skew between receivers in same package1 Waveform 3 B PORT LIMITS SYMBOL PARAMETER tPLH tPHL Propagation delay, AIn to Bn tPLH tPHL Tamb = +25°C, VCC = 5V, CD = 30pF, RU = 9Ω TEST CONDITION Tamb = 0 to 70°C, VCC = 5V±10%, CD = 30pF, RU = 9Ω UNIT Waveform 1, 2 2.4 1.5 3.7 2.7 4.9 4.4 1.9 1.5 5.7 5.0 ns Enable/disable time, OEB0 to Bn Waveform 2 2.4 1.9 3.7 3.5 4.9 4.9 1.9 1.8 6.4 5.4 ns tPLH tPHL Enable/disable time, OEB1 to Bn Waveform 1 2.4 1.9 4.0 3.6 5.5 5.5 1.9 2.5 5.9 5.9 ns tTLH tTHL Transition time, Bn Port (1.3V to 1.8V) Test Circuit and Waveforms 1.0 0.5 1.4 1.1 3.0 3.0 1.0 0.5 3.0 3.0 ns 0.3 1.0 1.0 ns tSK(o) SYMBOL Output skew between drivers in same package1 Waveform 3 PARAMETER TEST CONDITION tPLH tPHL Propagation delay, AIn to Bn tPLH tPHL RU = 16.5Ω RU = 16.5Ω UNIT Waveform 1, 2 2.5 1.6 3.8 2.8 5.0 4.5 2.0 1.6 5.8 5.1 ns Enable/disable time, OEB0 to Bn Waveform 2 2.5 2.0 3.8 3.6 5.0 5.0 2.0 1.9 6.5 5.5 ns tPLH tPHL Enable/disable time, OEB1 to Bn Waveform 1 2.5 2.0 4.1 3.7 5.6 5.6 2.0 2.6 6.0 6.0 ns tTLH tTHL Transition time, Bn Port (1.3V to 1.8V) Test Circuit and Waveforms 1.0 0.5 1.5 1.1 3.0 3.0 1.0 0.5 3.0 3.0 ns 0.3 1.0 1.0 ns tSK(o) Output skew between drivers in same package1 Waveform 3 NOTES: 1. tPNactual – tPMactual for any data input to output path compared to any other data input to output path where N and M are either LH or HL. Skew times are valid only under same test conditions (temperature, VCC, loading, etc.). 1995 May 25 8 Philips Semiconductors Product specification 7-bit Futurebus+ transceiver FB2041 AC ELECTRICAL CHARACTERISTICS (Industrial) A PORT LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25°C, VCC = 5V, CL = 50pF, RL = 500Ω Tamb = -40 to +85°C, VCC = 5V±10%, CL = 50pF, RL = 500Ω UNIT MIN TYP MAX MIN MAX Waveform 1, 2 1.8 1.6 3.4 3.2 5.0 4.9 1.6 1.6 5.5 5.5 ns Output enable time, OEA to AOn Waveform 4, 5 2.2 2.0 5.0 4.0 6.5 6.5 1.5 1.5 8.0 8.0 ns tPHZ tPLZ Output disable time, OEA to AOn Waveform 4, 5 1.5 1.5 3.3 3.0 4.8 5.0 0.8 1.2 6.0 6.0 ns tTLH tTHL Transition time, AOn Port (10% to 90% or 90% to 10%) Test Circuit and Waveforms 1.5 1.5 2.2 2.4 3.0 3.0 1.5 1.5 3.5 3.5 ns 0.4 1.0 1.0 ns tPLH tPHL Propagation delay, Bn to AOn tPZH tPZL tSK(o) Output skew between receivers in same package1 Waveform 3 B PORT LIMITS SYMBOL PARAMETER tPLH tPHL Propagation delay, AIn to Bn tPLH tPHL TEST CONDITION Tamb = +25°C, VCC = 5V, CD = 30pF, RU = 9Ω Tamb = -40 to +85°C, VCC = 5V±10%, CD = 30pF, RU = 9Ω UNIT Waveform 1, 2 2.4 1.5 3.7 2.7 4.9 4.4 1.9 1.5 5.9 5.0 ns Enable/disable time, OEB0 to Bn Waveform 2 2.4 1.9 3.7 3.5 4.9 4.9 1.9 1.8 6.4 5.9 ns tPLH tPHL Enable/disable time, OEB1 to Bn Waveform 1 2.4 1.9 4.0 3.6 5.5 5.5 1.9 1.5 6.8 6.8 ns tTLH tTHL Transition time, Bn Port (1.3V to 1.8V) Test Circuit and Waveforms 1.0 0.5 1.4 1.1 3.0 3.0 1.0 0.5 3.0 3.0 ns 0.3 1.0 1.0 ns tSK(o) SYMBOL Output skew between drivers in same package1 Waveform 3 PARAMETER TEST CONDITION tPLH tPHL Propagation delay, AIn to Bn tPLH tPHL RU = 16.5Ω RU = 16.5Ω UNIT Waveform 1, 2 2.5 1.6 3.8 2.8 5.0 4.5 2.0 1.6 6.0 5.1 ns Enable/disable time, OEB0 to Bn Waveform 2 2.5 2.0 3.8 3.6 5.0 5.0 2.0 1.9 6.5 6.0 ns tPLH tPHL Enable/disable time, OEB1 to Bn Waveform 1 2.5 2.0 4.1 3.7 5.5 5.5 2.0 1.6 6.9 6.9 ns tTLH tTHL Transition time, Bn Port (1.3V to 1.8V) Test Circuit and Waveforms 1.0 0.5 1.5 1.1 3.0 3.0 1.0 0.5 3.0 3.0 ns 0.3 1.0 1.0 ns tSK(o) Output skew between drivers in same package1 Waveform 3 NOTES: 1. tPNactual – tPMactual for any data input to output path compared to any other data input to output path where N and M are either LH or HL. Skew times are valid only under same test conditions (temperature, VCC, loading, etc.). 1995 May 25 9 Philips Semiconductors Product specification 7-bit Futurebus+ transceiver FB2041 AC WAVEFORMS VM AIn, Bn or Bn OEBn AIn, Bn OEB0 VM tPLH VM AOn or Bn VM tPHL VM tPHL VM AOn, Bn Waveform 1. Propagation Delay for Data or Output Enable to Output tPLH VM VM Waveform 2. Propagation Delay for Data or Output Enable to Output VM AIn, Bn tSK(o) AOn, Bn OEA tPZH AOn Waveform 3. Output Skews VM VM VM OEAn tPZL tPHZ VM VOH -0.3V AOn OV Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level tPLZ VM VOL +0.3V Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level NOTE: VM = 1.55V for Bn, VM = 1.5V for all others. 1995 May 25 VM VM 10 SG00079 Philips Semiconductors Product specification 7-bit Futurebus+ transceiver FB2041 TEST CIRCUIT AND WAVEFORMS VCC BIAS V VIN RL VOUT PULSE GENERATOR tW 90% 7.0V NEGATIVE PULSE RT CL VM VM 10% D.U.T. RL 10% tTHL (tf) tTLH (tr) tTHL VM (tr) (tf) VIN 90% VM 10% Test Circuit for 3-State Outputs on A Port LOW V tTLH 90% POSITIVE PULSE VIN 90% 10% tW LOW V VM = 1.55V for Bn, VM = 1.5V for all others. Input Pulse Definitions SWITCH POSITION TEST SWITCH tPLZ, tPZL All other closed open VCC BIAS V VIN 2.0V (for RU = 9 Ω) 2.1V (for RU = 16.5 Ω) VOUT PULSE GENERATOR INPUT PULSE REQUIREMENTS Family FB+ Amplitude Low V Rep. Rate A Port 3.0V 0.0V 1MHz 500ns 2.5ns 2.5ns B Port 2.0V 1.0V 1MHz 500ns 2.5ns 2.5ns tW tTLH tTHL RU D.U.T. RT CD Test Circuit for Outputs on B Port DEFINITIONS: RL = Load Resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. CD = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RU = Pull up resistor; see AC CHARACTERISTICS for value. SG00059 1995 May 25 11 Philips Semiconductors Product specification 7-bit Futurebus+ transceiver FB2041 QFP52: plastic quad flat package; 52 leads (lead length 1.6 mm); body 10 x 10 x 2.0 mm 1995 May 25 12 SOT379-1 Philips Semiconductors Product specification 7-bit Futurebus+ transceiver FB2041 NOTES 1995 May 25 13 Philips Semiconductors Product specification 7-bit Futurebus+ transceiver FB2041 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: 1995 May 25 14 Date of release: 08-98