TI CD74ACT86 Quad 2-input exclusive-or gate Datasheet

[ /Title
(CD74
AC86,
CD74
ACT86
)
/Subject
(Quad
2-Input
ExclusiveOR
Gate)
/Autho
r ()
/Keywords
(Harris
Semiconductor,
Advan
ced
CMOS
, Harris
Semiconductor,
Advan
ced
TTL)
/Creator ()
/DOCI
NFO
pdf-
CD74AC86,
CD54/74ACT86
Data sheet acquired from Harris Semiconductor
SCHS232A
Quad 2-Input Exclusive-OR Gate
September 1998 - Revised May 2000
Features
Description
• Buffered Inputs
The CD74AC86 and ’ACT86 are quad 2-input Exclusive-OR
gates that utilize Advanced CMOS Logic technology
• Typical Propagation Delay
- 3.2ns at VCC = 5V, TA = 25oC, CL = 50pF
Ordering Information
• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015
PART
NUMBER
• SCR-Latchup-Resistant CMOS Process and Circuit
Design
TEMP. RANGE (oC)
0 to 70oC, -40 to 85,
CD74AC86E
PACKAGE
14 Ld PDIP
-55 to 125
0 to 70oC, -40 to 85,
-55 to 125
• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption
CD74AC86M
• Balanced Propagation Delays
CD54ACT86F3A
-55 to 125
14 Ld CERDIP
0 to 70oC, -40 to 85,
CD74ACT86E
• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply
14 Ld SOIC
14 Ld PDIP
-55 to 125
0 to 70oC, -40 to 85,
-55 to 125
CD74ACT86M
• ±24mA Output Drive Current
- Fanout to 15 FAST™ ICs
- Drives 50Ω Transmission Lines
14 Ld SOIC
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local TI sales office or
customer service for ordering information.
Pinout
Functional Diagram
CD54ACT86
(CERDIP)
CD74AC86, CD74ACT86
(PDIP, SOIC)
TOP VIEW
14 VCC
1B 2
13 4B
1Y 3
12 4A
2A 4
11 4Y
2B 5
10 3B
2Y 6
9 3A
GND 7
8 3Y
14
2
13
1B
1Y
1A 1
1
1A
2A
2B
2Y
GND
VCC
4B
3
12
4
11
5
10
6
9
7
8
4A
4Y
3B
3A
3Y
TRUTH TABLE
INPUTS
nB
nY
L
L
L
H
H
L
H
L
H
L
H
H
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.
Copyright © 2000, Texas Instruments Incorporated
1
OUTPUT
nA
CD74AC86, CD54/74ACT86
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
DC VCC or Ground Current, ICC or IGND (Note 3) . . . . . . . . .±100mA
Thermal Resistance (Typical, Note 5)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
175
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC (Note 4) . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Slew Rate, dt/dv
4.5V to 5.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. For up to 4 outputs per device, add ±25mA for each additional output.
4. Unless otherwise specified, all voltages are referenced to ground.
5. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
-40oC TO
85oC
25oC
-55oC TO
125oC
SYMBOL
VI (V)
IO (mA)
VCC
(V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
VIH
-
-
1.5
1.2
-
1.2
-
1.2
-
V
AC TYPES
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
VIL
VOH
VOL
-
VIH or VIL
VIH or VIL
3
2.1
-
2.1
-
2.1
-
V
5.5
3.85
-
3.85
-
3.85
-
V
1.5
-
0.3
-
0.3
-
0.3
V
3
-
0.9
-
0.9
-
0.9
V
5.5
-
1.65
-
1.65
-
1.65
V
-0.05
1.5
1.4
-
1.4
-
1.4
-
V
-0.05
3
2.9
-
2.9
-
2.9
-
V
-0.05
4.5
4.4
-
4.4
-
4.4
-
V
-4
3
2.58
-
2.48
-
2.4
-
V
-24
4.5
3.94
-
3.8
-
3.7
-
V
-75
(Note 6, 7)
5.5
-
-
3.85
-
-
-
V
-50
(Note 6, 7)
5.5
-
-
-
-
3.85
-
V
0.05
1.5
-
0.1
-
0.1
-
0.1
V
0.05
3
-
0.1
-
0.1
-
0.1
V
0.05
4.5
-
0.1
-
0.1
-
0.1
V
12
3
-
0.36
-
0.44
-
0.5
V
24
4.5
-
0.36
-
0.44
-
0.5
V
75
(Note 6, 7)
5.5
-
-
-
1.65
-
-
V
50
(Note 6, 7)
5.5
-
-
-
-
-
1.65
V
-
2
CD74AC86, CD54/74ACT86
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
-40oC TO
85oC
25oC
-55oC TO
125oC
SYMBOL
VI (V)
IO (mA)
VCC
(V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
II
VCC or
GND
-
5.5
-
±0.1
-
±1
-
±1
µA
ICC
VCC or
GND
0
5.5
-
4
-
40
-
80
µA
High Level Input Voltage
VIH
-
-
4.5 to
5.5
2
-
2
-
2
-
V
Low Level Input Voltage
VIL
-
-
4.5 to
5.5
-
0.8
-
0.8
-
0.8
V
High Level Output Voltage
VOH
VIH or VIL
-0.05
4.5
4.4
-
4.4
-
4.4
-
V
-24
4.5
3.94
-
3.8
-
3.7
-
V
-75
(Note 6, 7)
5.5
-
-
3.85
-
-
-
V
-50
(Note 6, 7)
5.5
-
-
-
-
3.85
-
V
0.05
4.5
-
0.1
-
0.1
-
0.1
V
24
4.5
-
0.36
-
0.44
-
0.5
V
75
(Note 6, 7)
5.5
-
-
-
1.65
-
-
V
50
(Note 6, 7)
5.5
-
-
-
-
-
1.65
V
PARAMETER
Input Leakage Current
Quiescent Supply Current,
FF
ACT TYPES
Low Level Output Voltage
Input Leakage Current
Quiescent Supply Current,
FF
Additional Supply Current per
Input Pin TTL Inputs High
1 Unit Load
VOL
VIH or VIL
II
VCC or
GND
-
5.5
-
±0.1
-
±1
-
±1
µA
ICC
VCC or
GND
0
5.5
-
4
-
40
-
80
µA
∆ICC
VCC
-2.1
-
4.5 to
5.5
-
2.4
-
2.8
-
3
mA
NOTES:
6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize
power dissipation.
7. Test verifies a minimum 50Ω transmission-line-drive capability at 85oC, 75Ω at 125oC.
ACT Input Load Table
INPUT
UNIT LOAD
All
0.48
NOTE: Unit load is ∆ICC limit specified in DC Electrical Specifications
Table, e.g., 2.4mA max at 25oC.
Switching Specifications Input tr, tf = 3ns, CL = 50pF (Worst Case)
-40oC TO 85oC
PARAMETER
-55oC TO 125oC
SYMBOL
VCC (V)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
tPHL, tPLH
1.5
-
-
123
-
-
135
ns
3.3
(Note 9)
3.9
-
13.7
3.8
-
15.1
ns
5
(Note 10)
2.8
-
9.8
2.7
-
10.8
ns
AC TYPES
Propagation Delay, Input to
Output
3
CD74AC86, CD54/74ACT86
Switching Specifications Input tr, tf = 3ns, CL = 50pF (Worst Case)
(Continued)
-40oC TO 85oC
PARAMETER
SYMBOL
VCC (V)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
CI
-
-
-
10
-
-
10
pF
CPD
(Note 11)
-
-
57
-
-
57
-
pF
tPHL, tPLH
5
(Note 10)
3.8
-
13.3
3.7
-
14.6
ns
CI
-
-
-
10
-
-
10
pF
CPD
(Note 11)
-
-
57
-
-
57
-
pF
Input Capacitance
Power Dissipation Capacitance
-55oC TO 125oC
ACT TYPES
Propagation Delay, Input to
Output
Input Capacitance
Power Dissipation Capacitance
NOTES:
8. Limits tested at 100%.
9. 3.3V Min at 3.6V, Max at 3V.
10. 5V Min at 5.5V, Max at 4.5V.
11. CPD is used to determine the dynamic power consumption per gate.
AC: PD = VCC2 fi (CPD + CL)
ACT: PD = VCC2 fi (CPD + CL) + VCC ∆ICC where fi = input frequency, CL = output load capacitance, VCC = supply voltage.
OUTPUT
RL (NOTE)
500Ω
DUT
tr = 3ns
OUTPUT
LOAD
tf = 3ns
90%
VS
10%
nA OR nB
NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ.
AC
ACT
VCC
3V
Input Switching Voltage, VS
0.5 VCC
1.5V
Output Switching Voltage, VS
0.5 VCC
0.5 VCC
tPHL
tPLH
CL
50pF
Input Level
VS
OUTPUT nY
FIGURE 1.
FIGURE 2. PROPAGATION DELAY TIMES
4
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