PHILIPS ADC0803 Cmos 8-bit a/d converter Datasheet

INTEGRATED CIRCUITS
ADC0803/0804
CMOS 8-bit A/D converters
Product data
Supersedes data of 2001 Aug 03
2002 Oct 17
Philips Semiconductors
Product data
CMOS 8-bit A/D converters
ADC0803/0804
DESCRIPTION
PIN CONFIGURATION
The ADC0803 family is a series of three CMOS 8-bit successive
approximation A/D converters using a resistive ladder and
capacitive array together with an auto-zero comparator. These
converters are designed to operate with microprocessor-controlled
buses using a minimum of external circuitry. The 3-State output data
lines can be connected directly to the data bus.
D, N PACKAGES
The differential analog voltage input allows for increased
common-mode rejection and provides a means to adjust the
zero-scale offset. Additionally, the voltage reference input provides a
means of encoding small analog voltages to the full 8 bits of
resolution.
CS 1
20 VCC
RD 2
19 CLK R
WR 3
18 D0
4
17 D1
INTR 5
16 D2
VIN(+) 6
15 D3
VIN(–) 7
14 D4
8
13 D5
VREF/2 9
12 D6
D GND 10
11 D7
CLK IN
A GND
FEATURES
• Compatible with most microprocessors
• Differential inputs
• 3-State outputs
• Logic levels TTL and MOS compatible
• Can be used with internal or external clock
• Analog input range 0 V to VCC
• Single 5 V supply
• Guaranteed specification with 1 MHz clock
TOP VIEW
SL00016
Figure 1. Pin configuration
APPLICATIONS
• Transducer-to-microprocessor interface
• Digital thermometer
• Digitally-controlled thermostat
• Microprocessor-based monitoring and control systems
ORDERING INFORMATION
TEMPERATURE
RANGE
DESCRIPTION
ORDER CODE
TOPSIDE MARKING
DWG #
20-pin plastic small outline (SO) package
0 to 70 °C
ADC0803CD, ADC0804CD
ADC0803-1CD, ADC0804-1CD
SOT163-1
20-pin plastic small outline (SO) package
–40 to 85 °C
ADC0803LCD, ADC0804LCD
ADC0803-1LCD, ADC0804-1LCD
SOT163-1
20-pin plastic dual in-line package (DIP)
0 to 70 °C
ADC0803CN, ADC0804CN
ADC0803-1CN, ADC0804-1CN
SOT146-1
20-pin plastic dual in-line package (DIP)
–40 to +85 °C
ADC0803LCN, ADC0804LCN
ADC0803-1LCN, ADC0804-1LCN
SOT146-1
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VCC
PARAMETER
CONDITIONS
Supply voltage
Logic control input voltages
All other input voltages
RATING
UNIT
6.5
V
–0.3 to +16
V
–0.3 to (VCC +0.3)
V
Operating temperature range
ADC0803LCD/ADC0804LCD
ADC0803LCN/ADC0804LCN
ADC0803CD/ADC0804CD
ADC0803CN/ADC0804CN
–40 to +85
–40 to +85
0 to +70
0 to +70
°C
°C
°C
°C
Tstg
Storage temperature
–65 to +150
°C
Tsld
Lead soldering temperature (10 seconds)
230
°C
1690
1390
mW
mW
Tamb
PD
Maximum power
N package
D package
Tamb = 25 °C (still air)
dissipation1
NOTE:
1. Derate above 25 °C, at the following rates: N package at 13.5 mW/°C; D package at 11.1 mW/°C.
2002 Oct 17
2
Philips Semiconductors
Product data
CMOS 8-bit A/D converters
ADC0803/0804
BLOCK DIAGRAM
VIN (–)
7
+
M
VIN (+)
6
–
+
9
VREF/2
8
AUTO ZERO
COMPARATOR
LADDER AND
DECODER
A GND
VCC
–
20
D7 (MSB) (11)
OUTPUT
LATCHES
SAR
10
D GND
LE
D6
D5
D4
(12)
(13)
(14)
D3
D2
D1
D0 (LSB)
(15)
(16)
(17)
(18)
OE
3
WR
8–BIT
SHIFT REGISTER
CLOCK
1
CS
S
INTR
FF
R
Q
2
RD
5
INTR
4
CLK IN
Figure 2. Block diagram
2002 Oct 17
3
19
CLK R
SL00017
Philips Semiconductors
Product data
CMOS 8-bit A/D converters
ADC0803/0804
DC ELECTRICAL CHARACTERISTICS
VCC = 5.0 V, fCLK = 1 MHz, Tmin ≤ Tamb ≤ Tmax, unless otherwise specified.
LIMITS
SYMBOL
RIN
PARAMETER
TEST CONDITIONS
ADC0803 relative accuracy error (adjusted)
Full-Scale adjusted
ADC0804 relative accuracy error (unadjusted)
VREF/2 = 2.500 VDC
VREF/2 input resistance3
Analog input voltage
VCC = 0 V2
range3
Min
400
Typ
Max
0.50
LSB
1
LSB
Ω
680
–0.05
DC common-mode error
Over analog input voltage range
1/16
Power supply sensitivity
VCC = 5V ±10%1
1/16
UNIT
VCC+0.05
V
1/8
LSB
LSB
Control inputs
VIH
Logical “1” input voltage
VCC = 5.25 VDC
VIL
Logical “0” input voltage
VCC = 4.75 VDC
IIH
Logical “1” input current
VIN = 5 VDC
IIL
Logical “0” input current
VIN = 0 VDC
2.0
0.005
–1
–0.005
15
VDC
0.8
VDC
1
µADC
µADC
Clock in and clock R
VT+
Clock in positive-going threshold voltage
2.7
3.1
3.5
VDC
VT–
Clock in negative-going threshold voltage
1.5
1.8
2.1
VDC
VH
Clock in hysteresis (VT+)–(VT–)
0.6
1.3
2.0
VDC
VOL
Logical “0” clock R output voltage
IOL = 360 µA, VCC = 4.75 VDC
0.4
VDC
VOH
Logical “1” clock R output voltage
IOH = –360 µA, VCC = 4.75 VDC
2.4
VDC
Data output and INTR
VOL
Logical “0” output voltage
Data outputs
INTR outputs
IOL = 1.6 mA, VCC = 4.75 VDC
IOL = 1.0 mA, VCC = 4.75 VDC
IOH = –360 µA, VCC = 4.75 VDC
2.4
IOH = –10 µA, VCC = 4.75 VDC
4.5
–3
0.4
VDC
0.4
VDC
VOH
O
Logical “1” output voltage
IOZL
3-State output leakage
VOUT = 0 VDC, CS = logical “1”
IOZH
3-State output leakage
VOUT = 5 VDC, CS = logical “1”
ISC
+Output short-circuit current
VOUT = 0 V, Tamb = 25 °C
4.5
12
mADC
ISC
–Output short-circuit current
VOUT = VCC, Tamb = 25 °C
9.0
30
mADC
ICC
Power supply current
fCLK = 1 MHz, VREF/2 = OPEN,
CS = Logical “1”, Tamb = 25 °C
4
µADC
3
NOTES:
1. Analog inputs must remain within the range: –0.05 ≤ VIN ≤ VCC + 0.05 V.
2. See typical performance characteristics for input resistance at VCC = 5 V.
3. VREF/2 and VIN must be applied after the VCC has been turned on to prevent the possibility of latching.
2002 Oct 17
VDC
C
3.0
3.5
µADC
mA
Philips Semiconductors
Product data
CMOS 8-bit A/D converters
ADC0803/0804
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
TO
FROM
TEST CONDITIONS
fCLK = 1 MHz1
Conversion time
fCLK
Min
0.1
Clock duty cycle1
40
Clock
Free-running conversion rate
tW(WR)L
Start pulse width
tACC
Access time
t1H, t0H
3-State control
tW1, tR1
INTR delay
CIN
Logic input=capacitance
Typ
66
frequency1
CR
1.0
CS = 0, fCLK = 1 MHz
INTR tied to WR
CS = 0
Output
Max
UNIT
73
µs
3.0
MHz
60
%
13690
conv/s
30
ns
RD
CS = 0, CL = 100 pF
75
100
ns
Output
RD
CL = 10 pF, RL = 10 kΩ
See 3-State test circuit
70
100
ns
INTR
WD
or RD
100
150
ns
5
7.5
pF
5
7.5
pF
COUT
3-State output capacitance
NOTE:
1. Accuracy is guaranteed at fCLK = 1 MHz. Accuracy may degrade at higher clock frequencies.
FUNCTIONAL DESCRIPTION
ANALOG OPERATION
These devices operate on the Successive Approximation principle.
Analog switches are closed sequentially by successive
approximation logic until the input to the auto-zero comparator
[ VIN(+)–VIN(–) ] matches the voltage from the decoder. After all bits
are tested and determined, the 8-bit binary code corresponding to
the input voltage is transferred to an output latch. Conversion begins
with the arrival of a pulse at the WR input if the CS input is low. On
the High-to-Low transition of the signal at the WR or the CS input,
the SAR is initialized, the shift register is reset, and the INTR output
is set high. The A/D will remain in the reset state as long as the CS
and WR inputs remain low. Conversion will start from one to eight
clock periods after one or both of these inputs makes a Low-to-High
transition. After the conversion is complete, the INTR pin will make a
High-to-Low transition. This can be used to interrupt a processor, or
otherwise signal the availability of a new conversion result. A read
(RD) operation (with CS low) will clear the INTR line and enable the
output latches. The device may be run in the free-running mode as
described later. A conversion in progress can be interrupted by
issuing another start command.
Analog Input Current
The analog comparisons are performed by a capacitive charge
summing circuit. The input capacitor is switched between VIN(+)4
and VIN(–), while reference capacitors are switched between taps on
the reference voltage divider string. The net charge corresponds to
the weighted difference between the input and the most recent total
value set by the successive approximation register.
The internal switching action causes displacement currents to flow
at the analog inputs. The voltage on the on-chip capacitance is
switched through the analog differential input voltage, resulting in
proportional currents entering the VIN(+) input and leaving the VIN(–)
input. These transient currents occur at the leading edge of the
internal clock pulses. They decay rapidly so do not inherently cause
errors as the on-chip comparator is strobed at the end of the clock
period.
Input Bypass Capacitors and Source Resistance
Bypass capacitors at the input will average the charges mentioned
above, causing a DC and an AC current to flow through the output
resistance of the analog signal sources. This charge pumping action
is worse for continuous conversions with the VIN(+) input at full
scale. This current can be a few microamps, so bypass capacitors
should NOT be used at the analog inputs of the VREF/2 input for
high resistance sources (> 1 kΩ). If input bypass capacitors are
desired for noise filtering and a high source resistance is desired to
minimize capacitor size, detrimental effects of the voltage drop
across the input resistance can be eliminated by adjusting the full
scale with both the input resistance and the input bypass capacitor
in place. This is possible because the magnitude of the input current
is a precise linear function of the differential voltage.
Digital Control Inputs
The digital control inputs (CS, WR, RD) are compatible with
standard TTL logic voltage levels. The required signals at these
inputs correspond to Chip Select, START Conversion, and Output
Enable control signals, respectively. They are active-Low for easy
interface to microprocessor and microcontroller control buses. For
applications not using microprocessors, the CS input (Pin 1) can be
grounded and the A/D START function is achieved by a
negative-going pulse to the WR input (Pin 3). The Output Enable
function is achieved by a logic low signal at the RD input (Pin 2),
which may be grounded to constantly have the latest conversion
present at the output.
2002 Oct 17
LIMITS
5
Philips Semiconductors
Product data
CMOS 8-bit A/D converters
ADC0803/0804
Large values of source resistance where an input bypass capacitor
is not used will not cause errors as the input currents settle out prior
to the comparison time. If a low pass filter is required in the system,
use a low valued series resistor (< 1 kΩ) for a passive RC section or
add an op amp active filter (low pass). For applications with source
resistances at or below 1 kΩ, a 0.1 µF bypass capacitor at the inputs
will prevent pickup due to series lead inductance or a long wire. A
100 Ω series resistor can be used to isolate this capacitor (both the
resistor and capacitor should be placed out of the feedback loop)
from the output of the op amp, if used.
Reference Voltage Span Adjust
Note that the Pin 9 (VREF/2) voltage is either 1/2 the voltage applied
to the VCC supply pin, or is equal to the voltage which is externally
forced at the VREF/2 pin. In addition to allowing for flexible
references and full span voltages, this also allows for a ratiometric
voltage reference. The internal gain of the VREF/2 input is 2, making
the full-scale differential input voltage twice the voltage at Pin 9.
For example, a dynamic voltage range of the analog input voltage
that extends from 0 to 4 V gives a span of 4 V (4–0), so the VREF/2
voltage can be made equal to 2 V (half of the 4 V span) and full
scale output would correspond to 4 V at the input.
Analog Differential Voltage Inputs and
Common-Mode Rejection
On the other hand, if the dynamic input voltage had a range of
0.5 to 3.5 V, the span or dynamic input range is 3 V (3.5–0.5). To
encode this 3 V span with 0.5 V yielding a code of zero, the
minimum expected input (0.5 V, in this case) is applied to the VIN(–)
pin to account for the offset, and the VREF/2 pin is set to 1/2 the 3 V
span, or 1.5 V. The A/D converter will now encode the VIN(+) signal
between 0.5 and 3.5 V with 0.5 V at the input corresponding to a
code of zero and 3.5 V at the input producing a full scale output
code. The full 8 bits of resolution are thus applied over this reduced
input voltage range. The required connections are shown in
Figure 7.
These A/D converters have additional flexibility due to the analog
differential voltage input. The VIN(–) input (Pin 7) can be used to
subtract a fixed voltage from the input reading (tare correction). This
is also useful in a 4/20 mA current loop conversion. Common-mode
noise can also be reduced by the use of the differential input.
The time interval between sampling VIN(+) and VIN(–) is 4.5 clock
periods. The maximum error due to this time difference is given by:
V(max) = (VP) (2fCM) (4.5/fCLK),
where:
Operating Mode
V = error voltage due to sampling delay
These converters can be operated in two modes:
VP = peak value of common-mode voltage
1) absolute mode
2) ratiometric mode
fCM = common mode frequency
In absolute mode applications, both the initial accuracy and the
temperature stability of the reference voltage are important factors in
the accuracy of the conversion. For VREF/2 voltages of 2.5 V, initial
errors of ±10 mV will cause conversion errors of ±1 LSB due to the
gain of 2 at the VREF/2 input. In reduced span applications, the initial
value and stability of the VREF/2 input voltage become even more
important as the same error is a larger percentage of the VREF/2
nominal value. See Figure 8.
For example, with a 60 Hz common-mode frequency, fcm, and a
1 MHz A/D clock, fCLK, keeping this error to 1/4 LSB (about 5 mV)
would allow a common-mode voltage, VP, which is given by:
VP +
[V(max) (f CLK)
(2f CM)(4.5)
or
VP +
(5 x 10 *3) (10 4)
+ 2.95V
(6.28) (60) (4.5)
In ratiometric converter applications, the magnitude of the reference
voltage is a factor in both the output of the source transducer and
the output of the A/D converter, and, therefore, cancels out in the
final digital code. See Figure 9.
The allowed range of analog input voltages usually places more
severe restrictions on input common-mode voltage levels than this,
however.
Generally, the reference voltage will require an initial adjustment.
Errors due to an improper reference voltage value appear as
full-scale errors in the A/D transfer function.
An analog input span less than the full 5 V capability of the device,
together with a relatively large zero offset, can be easily handled by
use of the differential input. (See Reference Voltage Span Adjust).
ERRORS AND INPUT SPAN ADJUSTMENTS
There are many sources of error in any data converter, some of
which can be adjusted out. Inherent errors, such as relative
accuracy, cannot be eliminated, but such errors as full-scale and
zero scale offset errors can be eliminated quite easily. See Figure 7.
Noise and Stray Pickup
The leads of the analog inputs (Pins 6 and 7) should be kept as
short as possible to minimize input noise coupling and stray signal
pick-up. Both EMI and undesired digital signal coupling to these
inputs can cause system errors. The source resistance for these
inputs should generally be below 5 kΩ to help avoid undesired noise
pickup. Input bypass capacitors at the analog inputs can create
errors as described previously. Full scale adjustment with any input
bypass capacitors in place will eliminate these errors.
Zero Scale Error
Zero scale error of an A/D is the difference of potential between the
ideal 1/2 LSB value (9.8 mV for VREF/2=2.500 V) and that input
voltage which just causes an output transition from code 0000 0000
to a code of 0000 0001.
Reference Voltage
If the minimum input value is not ground potential, a zero offset can
be made. The converter can be made to output a digital code of
0000 0000 for the minimum expected input voltage by biasing the
VIN(–) input to that minimum value expected at the VIN(–) input to
that minimum value expected at the VIN(+) input. This uses the
differential mode of the converter. Any offset adjustment should be
done prior to full scale adjustment.
For application flexibility, these A/D converters have been designed
to accommodate fixed reference voltages of 5V to Pin 20 or 2.5 V to
Pin 9, or an adjusted reference voltage at Pin 9. The reference can
be set by forcing it at VREF/2 input, or can be determined by the
supply voltage (Pin 20). Figure 6 indicates how this is accomplished.
2002 Oct 17
6
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Product data
CMOS 8-bit A/D converters
ADC0803/0804
Full Scale Adjustment
DRIVING THE DATA BUS
Full scale gain is adjusted by applying any desired offset voltage to
VIN(–), then applying the VIN(+) a voltage that is 1-1/2 LSB less than
the desired analog full-scale voltage range and then adjusting the
magnitude of VREF/2 input voltage (or the VCC supply if there is no
VREF/2 input connection) for a digital output code which just
changes from 1111 1110 to 1111 1111. The ideal VIN(+) voltage for
this full-scale adjustment is given by:
This CMOS A/D converter, like MOS microprocessors and
memories, will require a bus driver when the total capacitance of the
data bus gets large. Other circuitry tied to the data bus will add to
the total capacitive loading, even in the high impedance mode.
V IN()) + V IN(*) * 1.5 x
There are alternatives in handling this problem. The capacitive
loading of the data bus slows down the response time, although DC
specifications are still met. For systems with a relatively low CPU
clock frequency, more time is available in which to establish proper
logic levels on the bus, allowing higher capacitive loads to be driven
(see Typical Performance Characteristics).
V MAX * V MIN
255
where:
At higher CPU clock frequencies, time can be extended for I/O
reads (and/or writes) by inserting wait states (8880) or using
clock-extending circuits (6800, 8035).
VMAX = high end of analog input range (ground referenced)
VMIN = low end (zero offset) of analog input (ground referenced)
Finally, if time is critical and capacitive loading is high, external bus
drivers must be used. These can be 3-State buffers (low power
Schottky is recommended, such as the N74LS240 series) or special
higher current drive products designed as bus drivers. High current
bipolar bus drivers with PNP inputs are recommended as the PNP
input offers low loading of the A/D output, allowing better response
time.
CLOCKING OPTION
The clock signal for these A/Ds can be derived from external
sources, such as a system clock, or self-clocking can be
accomplished by adding an external resistor and capacitor, as
shown in Figure 11.
Heavy capacitive or DC loading of the CLK R pin should be avoided
as this will disturb normal converter operation. Loads less than 50pF
are allowed. This permits driving up to seven A/D converter CLK IN
pins of this family from a single CLK R pin of one converter. For
larger loading of the clock line, a CMOS or low power TTL buffer or
PNP input logic should be used to minimize the loading on the CLK
R pin.
POWER SUPPLIES
Noise spikes on the VCC line can cause conversion errors as the
internal comparator will respond to them. A low inductance filter
capacitor should be used close to the converter VCC pin and values
of 1 µF or greater are recommended. A separate 5 V regulator for
the converter (and other 5 V linear circuitry) will greatly reduce
digital noise on the VCC supply and the attendant problems.
Restart During a Conversion
WIRING AND LAYOUT PRECAUTIONS
A conversion in process can be halted and a new conversion began
by bringing the CS and WR inputs low and allowing at least one of
them to go high again. The output data latch is not updated if the
conversion in progress is not completed; the data from the
previously completed conversion will remain in the output data
latches until a subsequent conversion is completed.
Digital wire-wrap sockets and connections are not satisfactory for
breadboarding this (or any) A/D converter. Sockets on PC boards
can be used. All logic signal wires and leads should be grouped or
kept as far as possible from the analog signal leads. Single wire
analog input leads may pick up undesired hum and noise, requiring
the use of shielded leads to the analog inputs in many applications.
Continuous Conversion
A single-point analog ground separate from the logic or digital
ground points should be used. The power supply bypass capacitor
and the self-clocking capacitor, if used, should be returned to digital
ground. Any VREF/2 bypass capacitor, analog input filter capacitors,
and any input shielding should be returned to the analog ground
point. Proper grounding will minimize zero-scale errors which are
present in every code. Zero-scale errors can usually be traced to
improper board layout and wiring.
To provide continuous conversion of input data, the CS and RD
inputs are grounded and INTR output is tied to the WR input. This
INTR/WR connection should be momentarily forced to a logic low
upon power-up to insure circuit operation. See Figure 10 for one
way to accomplish this.
2002 Oct 17
7
Philips Semiconductors
Product data
CMOS 8-bit A/D converters
ADC0803/0804
the NE5521 data sheet for a complete description of the operation of
that part.
APPLICATIONS
Microprocessor Interfacing
This family of A/D converters was designed for easy microprocessor
interfacing. These converters can be memory mapped with
appropriate memory address decoding for CS (read) input. The
active-Low write pulse from the processor is then connected to the
WR input of the A/D converter, while the processor active-Low read
pulse is fed to the converter RD input to read the converted data. If
the clock signal is derived from the microprocessor system clock,
the designer/programmer should be sure that there is no attempt to
read the converter until 74 converter clock pulses after the start
pulse goes high. Alternatively, the INTR pin may be used to interrupt
the processor to cause reading of the converted data. Of course, the
converter can be connected and addressed as a peripheral (in I/O
space), as shown in Figure 12. A bus driver should be used as a
buffer to the A/D output in large microprocessor systems where the
data leaves the PC board and/or must drive capacitive loads in
excess of 100 pF. See Figure 14.
Circuit Adjustment
To adjust the full scale and zero scale of the A/D, determine the range
of voltages that the transducer interface output will take on. Set the
LVDT core for null and set the Zero Scale Scale Adjust Potentiometer
for a digital output from the A/D of 1000 000. Set the LVDT core for
maximum voltage from the interface and set the Full Scale Adjust
potentiometer so the A/D output is just barely 1111 1111.
Interfacing the SCN8048 microcomputer family is pretty simple, as
shown in Figure 13. Since the SCN8048 family has 24 I/O lines, one
of these (shown here as bit 0 or port 1) can be used as the chip
select signal to the converter, eliminating the need for an address
decoder. The RD and WR signals are generated by reading from
and writing to a dummy address.
The desired temperature is set by holding either of the set buttons
closed. The SCC80C451 programming could cause the desired
(set) temperature to be displayed while either button is depressed
and for a short time after it is released. At other times the ambient
temperature could be displayed.
A Digital Thermostat
Circuit Description
The schematic of a Digital Thermostat is shown in Figure 16. The
A/D digitizes the output of the LM35, a temperature transducer IC
with an output of 10 mV per °C. With VREF/2 set for 2.56 V, this
10 mV corresponds to 1/2 LSB and the circuit resolution is 2 °C.
Reducing VREF/2 to 1.28 yields a resolution of 1 °C. Of course, the
lower VREF/2 is, the more sensitive the A/D will be to noise.
The set temperature is stored in an SCN8051 internal register. The
A/D conversion is started by writing anything at all to the A/D with
port pin P10 set high. The desired temperature is compared with the
digitized actual temperature, and the heater is turned on or off by
clearing setting port pin P12. If desired, another port pin could be
used to turn on or off an air conditioner.
Digitizing a Transducer Interface Output
Circuit Description
Figure 15 shows an example of digitizing transducer interface output
voltage. In this case, the transducer interface is the NE5521, an
LVDT (Linear Variable Differential Transformer) Signal Conditioner.
The diode at the A/D input is used to insure that the input to the A/D
does not go excessively beyond the supply voltage of the A/D. See
2002 Oct 17
The display drivers are NE587s if common anode LED displays are
used. Of course, it is possible to interface to LCD displays as well.
8
Philips Semiconductors
Product data
CMOS 8-bit A/D converters
ADC0803/0804
TYPICAL PERFORMANCE CHARACTERISTICS
Power Supply Current vs
Temperature
Clock Frequency vs
Clock Capacitor
5.5 V
2.4
5.0 V
2.2
4.0
3
VCC = 5.0 V
Tamb = 25 oC
4
2
2.0
MAX.
1
(mA)
2.6
5
1.0
0.8
0.6
REF/2
2.8
10.0
8.0
6.0
0
–1
f
fCLK = 1 MHz
CS = H
3.0
CLOCK FRQ (MHz)
POWER SUPPLY CURRENT (mA)
3.2
Input Current vs
Applied Voltage at VREF/2 Pin
–2
0.4
TYP.
–3
0.2
4.5 V
2.0
–4
MIN.
–5
0.1
1.8
0
25
50
75
10
100 125
20
40 60 80100
Logic Input Threshold
Voltage vs Supply Voltage
4.5
CLK–IN THRESHOLD VOLTAGE (V)
LOGIC INPUT (V)
+25 °C
+125 °C
1.50
1.40
1.30
4.50
4.75
5.00
2
5.25
VCC = 5.0 V
3.0
2.5
VT
16
14
VO = 2.5 V
12
10
VO = 0.4 V
8
1.5
1.0
4.50
5.50
18
VT+
2.0
5
4
Output Current vs
Temperature
4.0
3.5
3
APPLIED VREF/2 (V)
–55 °C ≤ Tamb ≤ 125 °C
VCC SUPPLY VOLTAGE (V)
4.75
5.00
5.25
6
–50
5.50
–25
0
25
50
75
100
125
AMBIENT TEMPERATURE (oC)
VCC SUPPLY VOLTAGE (V)
Delay From RD Falling
Edge to Data Valid vs
Load Capacitance
Full Scale Error vs
Conversion Time
4
350
VCC = 5.0 V
VREF/2 = 2.5 V
VCC = 5.0 V
Tamb = 25 oC
300
3
250
DEALY (ns)
ERROR (LSB)
1
CLK–IN Threshold Voltage vs
Supply Voltage
–55 °C
1.60
0
CLOCK CAP (pF)
AMBIENT TEMPERATURE (°C)
1.70
200 400 600 1000
OUTPUT CURRENT (mA)
–50 –25
2
200
150
100
1
50
0
0
0
20
40
60
80
100
0
120
CONVERSION TIME (µs)
400
600
800
LOAD CAPACITANCE (pF)
Figure 3. Typical Performance Characteristics
2002 Oct 17
200
9
1000
SL00018
Philips Semiconductors
Product data
CMOS 8-bit A/D converters
ADC0803/0804
3-STATE TEST CIRCUITS AND WAVEFORMS (ADC0801-1)
20ns
VCC
VCC
RD
RD
DATA
OUTPUT
CS
CL
GND
VCC
VCC
90%
50%
10%
RD
10 kΩ
t1H
VOH
10 kΩ
10 pF
VCC
tr
RD
90%
DATA
OUTPUT GND
DATA
OUTPUT
CS
CL
t1H
10 pF
GND
tr
90%
50%
10%
t0H
VOH
DATA
OUTPUT GND
10%
tOH
SL00019
Figure 4. 3-State Test Circuits and Waveforms (ADC0801-1)
TIMING DIAGRAMS (All timing is measured from the 50% voltage points)
START
CONVERSION
CS
WR
tWI
tW(WR)L
”BUSY”
ACTUAL INTERNAL
STATUS OF THE
CONVERTER
DATA IS VALID IN
OUTPUT LATCHES
”NOT BUSY”
INTERNAL TC
1 TO 8 X 1/fCLK
(LAST DATA WAS READ)
INTR
(LAST DATA WAS NOT READ)
INT ASSERTED
1/2 TCLK
INTR
INTR RESET
CS
tRI
RD
NOTE
DATA
OUTPUTS
THREE–STATE
tACC
t1H, t0H
Output Enable and Reset INTR
NOTE:
Read strobe must occur 8 clock periods (8/fCLK) after assertion of interrupt to guarantee reset of INTR.
Figure 5. Timing Diagrams
2002 Oct 17
10
SL00020
Philips Semiconductors
Product data
CMOS 8-bit A/D converters
ADC0803/0804
VCC
20
(5V)
VREF
VREF
R
VREF/2
9
–
FS
OFFSET
ADJUST
330 Ω
TO VREF/2
0.1 µF
+
DIGITAL
CIRCUITS
ZS
OFFSET
ADJUST
ANALOG
CIRCUITS
R
TO VIN(–)
SL00022
Figure 7. Offsetting the Zero Scale and Adjusting the Input
Range (Span)
8
10
NOTE:
The VREF/2 voltage is either 1/2 the VCC voltage or is that which is forced at Pin 9.
SL00021
Figure 6. Internal Reference Design
+5V
+5V
VCC
+
VIN(+)
VCC
10 µF
+
VIN(+)
+5V
10 µF
2 kΩ
A/D
A/D
2 kΩ
100 Ω
2 kΩ
2 kΩ
VREF/2
VREF/2
VIN(–)
a. Fixed Reference
VOLTAGE
REFERENCE
VREF/2
VIN(–)
b. Fixed Reference Derived from VCC
c. Optional Full
Scale Adjustment
SL00023
Figure 8. Absolute Mode of Operation
2002 Oct 17
11
Philips Semiconductors
Product data
CMOS 8-bit A/D converters
ADC0803/0804
VCC
VIN(+)
VCC
+
TRANSDUCER
10µF
2 kΩ
A/D
FULL SCALE
OPTIONAL
100 Ω
VREF/2
VIN(–)
2 kΩ
SL00024
Figure 9. Ratiometric Mode of Operation with Optional Full
Scale Adjustment
10k
+5 V
+5 V
10 kΩ
2.7 kΩ
47 µF TO
100 µF
10 kΩ
56 pF
CS
1
20 VCC
RD
2
19 CLK R
WR
3
18 D0
CLK IN
4
17 D1
INTR
5
16 D2
A/D
DB1
DB2
VIN(+)
6
VIN(–)
7
14 D4
A GND
8
13 D5
9
12 D6
D GND 10
11 D7
VREF/2
DB0
15 D3
DB3
DB4
DB5
DB6
DB7
SL00025
Figure 10. Connection for Continuous Conversion
INT
CLK R 19
I/O WR
I/O RD
R
CLK IN 4
C
A/D
+5 V
10 kΩ
CLK
fCLK = 1/1.7 R C
R = 10 kΩ
SL00026
Figure 11. Self-Clocking the Converter
CS
1
RD
2
20 VCC
19 CLK R
WR
3
18 D0
CLK IN
4
17 D1
INTR
5
16 D2
VIN(+) 6
ANALOG
INPUTS
56 pF
DB0
DB1
DB2
A/D
15 D3
DB3
VIN(–) 7
14 D4
A GND 8
13 D5
VREF/2 9
12 D6
D GND 10
11 D7
DB4
DB5
DB6
DB7
ADDRESS
DECODE
LOGIC
SL00027
Figure 12. Interfacing to 8080A Microprocessor
2002 Oct 17
12
Philips Semiconductors
Product data
CMOS 8-bit A/D converters
ADC0803/0804
+5 V
18 D0
17 D1
16 D2
VCC
VCC
40
SCN8051
OR
SCN80C51
1
P1.0
D0 18
2
P1.1
D1 17
3
P1.2
D2 16
4
P1.3
D3 15
5
P1.4
D4 14
6
P1.5
D5 13
7
P1.6
D6 12
8
P1.7
D7 11
17 RD
RD 2
16 WR
WR 3
12 INTO
39 P0.0
20
8–BIT
BUFFER
15 D3
19 CLK R
A/D
10 kΩ
13 D5
N74LS241
N74LS244
N74LS541
12 D6
4 CLK IN
11 D7
56 pF
OE
A/D
6
VIN(+)
7
VREF/2
INTR
5
12 A GND
CS
1
11 D GND
SL00029
ANALOG
INPUTS
Figure 14. Buffering the A/D Output to Drive High Capacitance
Loads and for Driving Off-Board Loads
SL00028
Figure 13. SCN8051 Interfacing
+5 V
Ct
18 kΩ
4.7 kΩ
1.5 kΩ
820 Ω
LVDT
NE5521
1µF
4.7 kΩ
0.47 µF
22 kΩ
+5 V
470 Ω
IN4148
VCC
VIN(+)
3.3 kΩ
2 kΩ
A/D
2 kΩ
VIN(–)
VREF/2
100 Ω
FULL SCALE
ADJUST
2 kΩ
SL00030
Figure 15. Digitizing a Transducer Interface Output
2002 Oct 17
DATA
BUS
14 D4
13
Philips Semiconductors
Product data
CMOS 8-bit A/D converters
ADC0803/0804
RBI 5
6
2
1
1/4
HEF4071
NE587
7
7
8
3
RBO
6
4
10 kΩ
RBI 5
2
1
1/4
HEF4071
NE587
7
7
8
3
10 kΩ
LOWER
P15
13
14
RAISE
P16
SCC80C51
18
DB0
D0 18
17
DB1
D1 17
16
DB2
D2 16
15
DB3
D3 15
14
DB4
D4 14
13
DB5
D5 13
12
DB6
D6 12
11
DB7
D7 11
8
RD
RD 2
10
WR
WR
3
6
INT
INTR
5
+5 V
20 VCC
+
10 µF
19 CLK R
10 kΩ
A/D
4
CLK IN
56 pF
27
CS
P10
1
D GND
29 P12 20 GND
+V
6 VIN(+)
LM35
7 VIN(–)
10 8
A GND
2N3906
1N4148
TO HEATER
SL00031
Figure 16. Digital Thermostat
2002 Oct 17
14
Philips Semiconductors
Product data
CMOS 8-bit A/D converters
ADC0803/0804
SO20: plastic small outline package; 20 leads; body width 7.5 mm
2002 Oct 17
15
SOT163-1
Philips Semiconductors
Product data
CMOS 8-bit A/D converters
ADC0803/0804
DIP20: plastic dual in-line package; 20 leads (300 mil)
2002 Oct 17
16
SOT146-1
Philips Semiconductors
Product data
CMOS 8-bit A/D converters
ADC0803/0804
REVISION HISTORY
Rev
Date
Description
_3
20021017
Product data; third version; supersedes data of 2001 Aug 03.
Engineering Change Notice 853–0034 28949 (date: 20020916).
Modifications:
• Add “Topside Marking” column to Ordering Information table.
_2
20010803
Product data; second version (9397 750 08926).
Engineering Change Notice 853–0034 26832 (date: 20010803).
_1
19940831
Product data; initial version.
Engineering Change Notice 853–0034 13721 (date: 19940831).
2002 Oct 17
17
Philips Semiconductors
Product data
CMOS 8-bit A/D converters
ADC0803/0804
Data sheet status
Level
Data sheet status [1]
Product
status [2] [3]
Definitions
I
Objective data
Development
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described
or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated
via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys
no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent,
copyright, or mask work right infringement, unless otherwise specified.
 Koninklijke Philips Electronics N.V. 2002
All rights reserved. Printed in U.S.A.
Contact information
For additional information please visit
http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
Date of release: 10-02
For sales offices addresses send e-mail to:
[email protected].
2002 Oct 17
Document order number:
18
9397 750 10538