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Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics. HD74LV595A 8-bit Shift Registers with 3-state Outputs REJ03D0335–0200Z (Previous ADE-205-281 (Z)) Rev.2.00 Jun. 28, 2004 Description This device each contains an 8-bit serial-in, parallel-out shift registers that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift register and the storage register. The shift register has a direct-overriding clear, serial input, and serial output pins for cascading. Both the shift register and the storage register clocks are positive-edge triggered. If the user wishes to connect both clocks together, the shift register state will always be one clock pulse ahead of the storage register. Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook computers), and the low-power consumption extends the battery life. Features • • • • • • • VCC = 2.0 V to 5.5 V operation All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max.) = 5.5 V (@VCC = 0 V) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C) Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V) Ordering Information Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) HD74LV595AFPEL HD74LV595ARPEL HD74LV595ATELL SOP–16 pin (JEITA) SOP–16 pin (JEDEC) TSSOP–16 pin FP–16DAV FP–16DNV TTP–16DAV FP RP T EL (2,000 pcs/reel) EL (2,500 pcs/reel) ELL (2,000 pcs/reel) Note: Please consult the sales office for the above package availability. Function Table Inputs SER X X X L H X X X Note: H: L: X: ↑: ↓: SRCLK SRCLR X X X X X L ↑ H ↑ H ↓ H X X X X High level Low level Immaterial Low to high transition High to low transition Rev.2.00 Jun. 28, 2004 page 1 of 13 RCLK X X X X X X ↑ ↓ G H L X X X X X X Function Force outputs into high-impedance state Enable parallel output Reset shift register Shift data into shift register Shift data into shift register Shift register remains unchanged Transfer shift register contents to latch register Latch register remains unchanged HD74LV595A Pin Arrangement QB 1 16 VCC QC 2 15 QA QD 3 14 SER QE 4 13 G QF 5 12 RCLK QG 6 11 SRCLK QH 7 10 SRCLR 9 QH' GND 8 (Top view) Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage range Input voltage range*1 Output voltage range*1, 2 VCC VI VO V V V Input clamp current Output clamp current Continuous output current Continuous current through VCC or GND Maximum power dissipation at Ta = 25°C (in still air)*3 IIK IOK IO –0.5 to 7.0 –0.5 to 7.0 –0.5 to VCC + 0.5 –0.5 to 7.0 –20 ±50 ±25 ±70 Storage temperature Tstg ICC or IGND PT 785 500 –65 to 150 mA mA mA mA mW Conditions Output: H or L Output: Z or VCC: OFF VI < 0 VO < 0 or VO > VCC VO = 0 to VCC SOP TSSOP °C Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The maximum package power dissipation was calculated using a junction temperature of 150°C. Rev.2.00 Jun. 28, 2004 page 2 of 13 HD74LV595A Recommended Operating Conditions Item Symbol Min Max Unit Supply voltage range VCC Input voltage range Output voltage range VI VO IOH 5.5 5.5 VCC 5.5 –50 –2 –6 –12 50 2 6 12 200 100 20 V V V Output current 2.0 0 0 0 — — — — — — — — 0 0 0 –40 85 °C IOL Input transition rise or fall rate ∆t /∆v Operating free-air temperature Ta Note: Unused or floating inputs must be held high or low. Rev.2.00 Jun. 28, 2004 page 3 of 13 µA mA µA mA ns/V Conditions H or L High impedance state VCC = 2.0 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 2.0 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V HD74LV595A Logic Diagram G RCLK SRCLR SRCLK SER (13) (12) (10) (11) (14) 1D 3R C1 R C3 3S 2S 2R 3R C2 R C3 3S 2S 2R 3R C2 R C3 3S 2S 2R 3R C2 R C3 3S 2S 2R 3R C2 R C3 3S 2S 2R 3R C2 R C3 3S 2S 2R 3R C2 R C3 3S 2S 2R 3R C2 R C3 3S (15) (1) (2) (3) (4) (5) (6) (7) (9) Rev.2.00 Jun. 28, 2004 page 4 of 13 QA QB QC QD QE QF QG QH QH' HD74LV595A Timing Diagram SRCLK SER RCLK SRCLR G QA QB QC QD QE QF QG QH QH' SHIFT HIGH IMPEDANCE CLEAR DC Electrical Characteristics Ta = –40 to 85°C Item Symbol VCC (V) Min Typ Max Unit Input voltage VIH 2.0 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 2.0 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 Min to Max 2.3 3.0 4.5 Min to Max 1.5 VCC × 0.7 VCC × 0.7 VCC × 0.7 — — — — VCC – 0.1 2.0 2.48 3.8 — — — — — — — — — — — — — — — — — — 0.5 VCC × 0.3 VCC × 0.3 VCC × 0.3 — — — — 0.1 V — — — — — — — — — — 0.4 0.44 0.55 ±1 ±5 µA µA IOL = 2 mA IOL = 6 mA IOL = 12 mA VIN = 5.5 V or GND VO = VCC or GND VIL Output voltage VOH VOL V Test Conditions IOH = –50 µA IOH = –2 mA IOH = –6 mA IOH = –12 mA IOL = 50 µA Input current IIN Off-state output current IOZ 2.3 3.0 4.5 0 to 5.5 5.5 Quiescent supply current ICC 5.5 — — 20 µA VIN = VCC or GND, IO = 0 Output leakage current Input capacitance IOFF 0 — — 5 µA VI or VO = 0 to 5.5 V CIN 3.3 — 3.5 — pF VI = VCC or GND Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions. Rev.2.00 Jun. 28, 2004 page 5 of 13 HD74LV595A Switching Characteristics VCC = 2.5 ± 0.2 V Ta = 25°C Ta = –40 to 85°C Item Symbol Min Typ Max Min Max Unit Maximum clock frequency fmax tPLH/tPHL 80 70 11.6 14.8 10.5 13.7 11.2 14.4 10.3 12.2 7.6 14.4 — — — — — — 16.4 19.4 15.3 18.3 16.2 19.2 14.8 17.7 11.5 18.2 — — — — 45 40 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 5.5 10.5 11.0 5.0 — — 19.5 22.5 18.0 21.0 18.2 21.2 17.5 20.5 13.5 19.2 — — — — MHz Propagation delay time 65 60 — — — — — — — — — — 5.5 10.0 10.0 5.0 2.0 0.5 0.5 7.0 7.0 6.0 — — — — — — — — — — — — 2.0 0.5 0.5 7.5 7.5 6.5 — — — — — — ns tPHL Enable time tZH tZL Disable time tHZ tLZ Setup time tSU Hold time th Pulse width tw Rev.2.00 Jun. 28, 2004 page 6 of 13 ns ns ns ns ns Test Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF FROM (Input) TO (Output) SRCLK QH' RCLK Q A – QH SRCLK QH' G Q A – QH SER before SRCLK ↑ SRCLK ↑ before RCLK ↑ SRCLR low before RCLK ↑ SRCLR high (inactive) before SRCLK ↑ SER after SRCLK ↑ SRCLK ↑ after RCLK ↑ SRCLR low after RCLK ↑ RCLK high or low SRCLK high or low SRCLR low HD74LV595A Switching Characteristics (cont) VCC = 3.3 ± 0.3 V Ta = 25°C Ta = –40 to 85°C Item Symbol Min Typ Max Min Max Unit Maximum clock frequency fmax tPLH/tPHL 150 130 8.8 11.3 7.7 10.2 8.4 10.9 7.5 9.0 5.9 12.1 — — — — — — 13.0 16.5 11.9 15.4 12.8 16.3 11.5 15.0 11.7 15.7 — — — — 70 50 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 3.5 8.5 9.0 3.0 — — 15.0 18.5 13.5 17.0 13.7 17.2 13.5 17.0 13.5 16.2 — — — — MHz Propagation delay time 80 55 — — — — — — — — — — 3.5 8.0 8.0 3.0 1.5 0.0 0.0 5.0 5.0 5.0 — — — — — — — — — — — — 1.5 0.0 0.0 5.0 5.0 5.0 — — — — — — ns tPHL Enable time tZH tZL Disable time tHZ tLZ Setup time tSU Hold time th Pulse width tw Rev.2.00 Jun. 28, 2004 page 7 of 13 ns ns ns ns ns Test Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF FROM (Input) TO (Output) SRCLK QH' RCLK Q A – QH SRCLK QH' G Q A – QH SER before SRCLK ↑ SRCLK ↑ before RCLK ↑ SRCLR low before RCLK ↑ SRCLR high (inactive) before SRCLK ↑ SER after SRCLK ↑ SRCLK ↑ after RCLK ↑ SRCLR low after RCLK ↑ RCLK high or low SRCLK high or low SRCLR low HD74LV595A Switching Characteristics (cont) VCC = 5.0 ± 0.5 V Ta = 25°C Ta = –40 to 85°C Item Symbol Min Typ Max Min Max Unit Maximum lock frequency fmax tPLH/tPHL 185 155 6.2 7.7 5.4 6.9 5.9 7.4 4.8 8.3 4.8 7.6 — — — — — — 8.2 10.2 7.4 9.4 8.0 10.0 8.6 10.6 8.6 11.0 — — — — 115 85 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 3.0 5.0 5.0 2.5 — — 9.4 11.4 8.5 10.5 9.1 11.1 10.0 12.0 10.0 11.0 — — — — MHz Propagation delay time 135 95 — — — — — — — — — — 3.0 5.0 5.0 2.5 2.0 0.0 0.0 5.0 5.0 5.0 — — — — — — — — — — — — 2.0 0.0 0.0 5.0 5.0 5.0 — — — — — — ns tPHL Enable time tZH tZL Disable time tHZ tLZ Setup time tSU Hold time th Pulse width tw ns ns ns Test Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF FROM (Input) TO (Output) SRCLK QH' RCLK Q A – QH SRCLK QH' G Q A – QH SER before SRCLK ↑ SRCLK ↑ before RCLK ↑ SRCLR low before RCLK ↑ ns SRCLR high (inactive) before SRCLK ↑ SER after SRCLK ↑ SRCLK ↑ after RCLK ↑ SRCLR low after RCLK ↑ RCLK high or low SRCLK high or low SRCLR low ns Output-skew Characteristics CL = 50 pF Ta = 25°C Ta = –40 to 85°C Item Symbol VCC = (V) Min Max Min Max Unit Output skew tsk (O) 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 — — — 2.0 1.5 1.0 — — — 2.0 1.5 1.0 ns Note: Skew between any outputs of the same package switching in the same direction. This parameter is warranted but not production tested. Rev.2.00 Jun. 28, 2004 page 8 of 13 HD74LV595A Operating Characteristics CL = 50 pF Ta = 25°C Item Symbol VCC = (V) Min Typ Max Unit Test Conditions Power dissipation capacitance CPD 3.3 5.0 — — 32.7 33.1 — — pF f = 10 MHz Noise Characteristics CL = 50 pF Ta = 25°C Item Symbol VCC = (V) Min Typ Max Unit Quiet output, maximum dynamic VOL VOL (P) 3.3 — 0.65 0.8 V Quiet output, minimum dynamic VOL VOL (V) 3.3 — –0.59 –0.8 V Quiet output, minimum dynamic VOH VOH (V) 3.3 — 2.84 — V High-level dynamic input voltage VIH (D) 3.3 2.31 — — V Low-level dynamic input voltage VIL (D) 3.3 — — 0.99 V Test Circuit Output 1 KΩ S2 OPEN GND CL VCC TEST t PLH / t PHL S2 OPEN t ZH/ t HZ t ZL / t LZ GND VCC Note: C L includes the probe and jig capacitance. Rev.2.00 Jun. 28, 2004 page 9 of 13 Test Conditions HD74LV595A Waveform − 1 tr SRCLK tf VCC 90% 50% VCC 10% GND tw 1/fmax tPLH tPHL 90% QH' 50% VCC 10% tTLH tTHL Waveform − 2 tw SRCLR VCC 50% VCC GND QH' tPHL 50% VCC tsu VCC 50% VCC SRCLK GND Waveform − 3 VCC RCLK 50% VCC GND tPLH/tPHL QA-QH Rev.2.00 Jun. 28, 2004 page 10 of 13 50% VCC HD74LV595A Waveform − 4 tr tf 90 % G VCC 90 % 50 % V CC 50 % V CC 10 % t ZL 10 % 0V t LZ VCC Waveform − A 50 % V CC t ZH VOL + 0.3 V t HZ Waveform − B 50 % V CC VOH − 0.3 V VOL VOH 0V Waveform − 5 Valid VCC 50% VCC SER GND th tsu VCC SRCLK 50% VCC GND Waveform − 6 VCC 50% VCC SRCLK GND tsu VCC RCLK 50% VCC GND tw Notes: 1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, t ≤ 3 ns, t ≤ 3 ns 2. Waveform−A is for an output with internal conditions such that the output is low except when disabled by the output control. 3. Waveform−B is for an output with internal conditions such that the output is high except when disabled by the output control. 4. The output are measured one at a time with one transition per measurement. Rev.2.00 Jun. 28, 2004 page 11 of 13 HD74LV595A Package Dimensions As of January, 2003 Unit: mm 10.06 10.5 Max 9 1 8 1.27 *0.40 ± 0.06 0.20 7.80 +– 0.30 1.15 0 ˚ – 8˚ 0.10 ± 0.10 0.80 Max *0.20 ± 0.05 2.20 Max 5.5 16 0.70 ± 0.20 0.15 0.12 M Package Code JEDEC JEITA Mass (reference value) *Ni/Pd/Au plating FP-16DAV — Conforms 0.24 g As of January, 2003 Unit: mm 9.9 10.3 Max 9 1 8 0.635 Max *0.40 ± 0.06 0.15 *0.20 ± 0.05 1.27 0.11 0.14 +– 0.04 1.75 Max 3.95 16 0.10 6.10 +– 0.30 1.08 0˚ – 8˚ 0.67 0.60 +– 0.20 0.25 M *Ni/Pd/Au plating Rev.2.00 Jun. 28, 2004 page 12 of 13 Package Code JEDEC JEITA Mass (reference value) FP-16DNV Conforms Conforms 0.15 g HD74LV595A As of January, 2003 Unit: mm 4.40 5.00 5.30 Max 16 9 1 8 0.65 1.0 0.13 M 6.40 ± 0.20 *Ni/Pd/Au plating Rev.2.00 Jun. 28, 2004 page 13 of 13 0.10 *0.15 ± 0.05 1.10 Max 0.65 Max 0.07 +0.03 –0.04 *0.20 ± 0.05 0˚ – 8˚ 0.50 ± 0.10 Package Code JEDEC JEITA Mass (reference value) TTP-16DAV — — 0.05 g Sales Strategic Planning Div. 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