ON MC74VHCT257A Quad 2-channel multiplexer with 3-state output Datasheet

MC74VHCT257A
Quad 2−Channel Multiplexer
with 3−State Outputs
The MC74VHCT257A is an advanced high speed CMOS quad
2−channel multiplexer fabricated with silicon gate CMOS technology.
It achieves high speed operation similar to equivalent Bipolar
Schottky TTL while maintaining CMOS low power dissipation.
It consists of four 2−input digital multiplexers with common select
(S) and enable (OE) inputs. When (OE) is held High, selection of data
is inhibited and all the outputs go Low.
The select decoding determines whether the A or B inputs get routed
to the corresponding Y outputs.
The VHCT inputs are compatible with TTL levels. This device can be
used as a level converter for interfacing 3.3 V to 5.0 V because it has full
5 V CMOS level output swings.
The VHCT257A input structures provide protection when voltages
between 0 V and 5.5 V are applied, regardless of the supply voltage. The
output structures also provide protection when VCC = 0 V. These input and
output structures help prevent device destruction caused by supply
voltage—input/output voltage mismatch, battery backup, hot insertion, etc.
The internal circuit is composed of three stages, including a buffered
output which provides high noise immunity and stable output. The inputs
tolerate voltages up to 7 V, allowing the interface of 5 V systems to 3 V
systems.
•
•
•
•
•
•
•
•
•
•
High Speed: tPD = 4.1 ns (Typ) at VCC = 5.0 V
Low Power Dissipation: ICC = 4.0 A (Max) at TA = 25°C
TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
Designed for 2.0 V to 5.5 V Operating Range
Low Noise: VOLP = 0.8 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance: HBM > 2000 V; Machine Model > 200 V
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MARKING DIAGRAMS
16
9
VHCT257A
AWLYWW
SO−16
D SUFFIX
CASE 751B
1
8
16
9
VHCT257A
ALYW
TSSOP−16
DT SUFFIX
CASE 948F
1
8
9
16
VHCT257A
ALYW
EIAJ SO−16
M SUFFIX
CASE 966
A
L, WL
Y
W, WW
8
1
=
=
=
=
Assembly Location
Wafer Lot
Year
Work Week
ORDERING INFORMATION
Device
Package
Shipping†
S
1
16
VCC
MC74VHCT257AD
SO−16
48 Units/Rail
A0
2
15
OE
MC74VHCT257ADR2
SO−16
2500 Tape & Reel
B0
3
14
A3
TSSOP−16
96 Units/Rail
Y0
4
13
B3
A1
5
12
Y3
B1
6
11
A2
MC74VHCT257AM
Y1
7
10
B2
MC74VHCT257AMEL EIAJSO−16 2000 Tape & Reel
9
Y2
GND
8
MC74VHCT257ADT
MC74VHCT257ADTR2 TSSOP−16 2500 Tape & Reel
September, 2004 − Rev. 2
50 Units/Rail
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Figure 1. Pin Assignment
 Semiconductor Components Industries, LLC, 2004
EIAJSO−16
1
Publication Order Number:
MC74VHCT257A/D
MC74VHCT257A
OE
I0a
I1a
I0b
I1b
I0c
Zb
Za
I1c
I0d
Zc
I1d
S
Zd
Figure 2. Expanded Logic Diagram
OE
S
A0
B0
A1
B1
A2
B2
A3
B3
15
1
2
3
5
6
EN
G1
1
1
MUX
4
7
11
10
14
13
9
12
Y0
Y1
Y2
Y3
Figure 3. IEC Logic Symbol
FUNCTION TABLE
Inputs
OE
S
Outputs
Y0 − Y3
H
L
L
X
L
H
Z
A0 −A3
B0 −B3
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V CC ).
Unused outputs must be left open.
A0 − A3, B0 − B3 = the levels
of the respective Data−Word
Inputs.
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2
MC74VHCT257A
MAXIMUM RATINGS
Value
Unit
VCC
Symbol
Positive DC Supply Voltage
Parameter
−0.5 to +7.0
V
VIN
Digital Input Voltage
−0.5 to +7.0
V
VOUT
DC Output Voltage
−0.5 to +7.0
−0.5 to VCC +0.5
V
IIK
Input Diode Current
−20
mA
IOK
Output Diode Current
20
mA
IOUT
DC Output Current, per Pin
25
mA
ICC
DC Supply Current, VCC and GND Pins
75
mA
PD
Power Dissipation in Still Air
200
180
mW
TSTG
Storage Temperature Range
−65 to +150
°C
VESD
ESD Withstand Voltage
Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
>2000
>200
>2000
V
ILATCHUP
Latchup Performance
Above VCC and Below GND at 125°C (Note 4)
300
mA
JA
Thermal Resistance, Junction−to−Ambient
143
164
°C/W
Output in 3−State
High or Low State
SOIC Package
TSSOP
SOIC Package
TSSOP
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1 Tested to EIA/JESD22−A114−A
2 Tested to EIA/JESD22−A115−A
3 Tested to JESD22−C101−A
4 Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
Min
Max
Unit
4.5
5.5
V
VCC
DC Supply Voltage
VIN
DC Input Voltage
0
5.5
V
VOUT
DC Output Voltage
0
5.5
V
TA
Operating Temperature Range, all Package Types
−55
125
°C
tr, tf
Input Rise or Fall Time
0
20
ns/V
VCC = 5.0 V + 0.5 V
90
419,300
47.9
100
178,700
20.4
110
79,600
9.4
120
37,000
4.2
130
17,800
2.0
140
8,900
1.0
TJ = 80 ° C
117.8
TJ = 90 ° C
1,032,200
TJ = 100 ° C
80
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
TJ = 110° C
Time, Years
TJ = 120° C
Time, Hours
TJ = 130 ° C
Junction
Temperature °C
NORMALIZED FAILURE RATE
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
1
1
10
100
1000
TIME, YEARS
Figure 4. Failure Rate vs. Time Junction Temperature
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3
MC74VHCT257A
DC CHARACTERISTICS (Voltages Referenced to GND)
VCC
Symbol
Parameter
Condition
(V)
Min
2
VIH
Minimum High−Level
Input Voltage
4.5 to
5.5
VIL
Maximum Low−Level
Input Voltage
4.5 to
5.5
VOH
Maximum High−Level
Output
Ou
u Voltage
o age
VOL
Maximum Low−Level
Output
Ou
u Voltage
o age
TA ≤ 85°C
TA = 25°C
Typ
Max
Min
−55°C ≤ TA ≤ 125°C
Max
Min
2
0.8
Max
2
0.8
V
0.8
VIN = VIH or VIL
IOH = −50 A
4.5
3.94
3.8
3.66
VIN = VIH or VIL
IOH = −8 mA
4.5
3.94
3.8
3.66
VIN = VIH or VIL
IOL = 50 A
4.5
VIN = VIH or VIL
IOH = 8 mA
Unit
V
V
V
0
0.1
0.1
0.1
4.5
0.36
0.44
0.52
IIN
Input Leakage Current
VIN = 5.5 V or GND
0 to
5.5
±0.1
±1.0
±1.0
A
IOZ
Maximum 3−State
Leakage Current
VIN = VIH or VIL
VOUT = VCC or GND
5.5
±0.25
±2.5
±2.5
A
ICCT
Maximum Quiescent
Supply Current
VIN = VCC or GND
5.5
1.35
1.5
1.65
mA
ICC
Additional Quiescent
Supply Current
(per pin)
VIN = VCC or GND
5.5
4.0
40
40
A
IOPD
Output Leakage
Current
VOUT = 5.5 V
0
0.5
5
5
A
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AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
TA = ≤ 85°C
TA = 25°C
Max
Min
Max
Min
Max
Unit
CL = 15 pF
CL = 50 pF
5.8
8.3
9.3
12.8
1.0
1.0
11.0
14.5
1.0
1.0
11.0
14.5
ns
VCC = 5.0 ± 0.5 V
CL = 15 pF
CL = 50 pF
3.6
5.1
5.9
7.9
1.0
1.0
7.0
9.0
1.0
1.0
7.0
9.0
Maximum
Propagation
Delay,
g
y
S to Y
VCC = 3.3 ± 0.3 V
CL = 15 pF
CL = 50 pF
7.0
9.5
11.0
14.5
1.0
1.0
13.0
16.5
1.0
1.0
13.0
16.5
VCC = 5.0 ± 0.5 V
CL = 15 pF
CL = 50 pF
4.0
5.5
6.8
8.8
1.0
1.0
8.0
10.0
1.0
1.0
8.0
10.0
Maximum Output
Enable,
Time OE to Y
Time,
VCC = 3.3 ± 0.3 V
RL = 1 k
CL = 15 pF
CL = 50 pF
6.7
9.2
10.5
14.0
1.0
1.0
12.5
16.0
1.0
1.0
12.5
16.0
VCC = 5.0 ± 0.5 V
RL = 1 k
CL = 15 pF
CL = 50 pF
3.6
5.1
6.8
11.0
1.0
12.0
8.0
10.0
1.0
1.0
8.0
12.0
Maximum Output
Disable,
Time OE to Y
Time,
VCC = 3.3 ± 0.3 V
RL = 1 k
CL = 50 pF
10.5
14.0
1.0
15.0
1.0
15.0
VCC = 5.0 ± 0.5 V
RL = 1 k
CL = 50 pF
9.5
12.0
1.0
13.0
1.0
13.0
4
10
Parameter
tPLH,
tPHL
Maximum
Propagation
Delay,
g
y
A or B to Y
VCC = 3.3 ± 0.3 V
tPLH,
tPHL
tPZL,
tPZH
tPLZ,
tPHZ
CIN
Min
−55°C ≤ TA ≤ 125°C
Typ
Symbol
Test Conditions
Maximum Input
Capacitance
10
10
ns
ns
ns
pF
Typical @ 25°C, VCC = 5.0 V
CPD
20
Power Dissipation Capacitance (Note 5)
pF
5. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no−load dynamic
power consumption; PD = CPD VCC2 fin + ICC VCC.
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4
MC74VHCT257A
NOISE CHARACTERISTICS (Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V)
TA = 25°C
Symbol
Characteristic
Typ
Max
Unit
VOLP
Quiet Output Maximum Dynamic VOL
0.3
0.8
V
VOLV
Quiet Output Minimum Dynamic VOL
− 0.3
− 0.8
V
VIHD
Minimum High Level Dynamic Input Voltage
2.0
V
VILD
Maximum Low Level Dynamic Input Voltage
0.8
V
OE
VCC
50%
GND
VCC
A, B or S
50%
tPLH
Y
tPZL
GND
tPHL
tPLZ
50% VCC
Y
tPZH
50% VCC
VOH − 0.3V
HIGH
IMPEDANCE
Figure 6. Switching Waveform
TEST POINT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
VOL + 0.3V
tPHZ
50% VCC
Y
Figure 5. Switching Waveform
HIGH
IMPEDANCE
DEVICE
UNDER
TEST
CL*
*Includes all probe and jig capacitance
OUTPUT
1 kΩ
CL *
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
*Includes all probe and jig capacitance
Figure 7. Test Circuit
Figure 8. Test Circuit
INPUT
Figure 9. Input Equivalent Circuit
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5
MC74VHCT257A
PACKAGE DIMENSIONS
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE J
−A−
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
−B−
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
DIM
A
B
C
D
F
G
J
K
M
P
R
F
X 45 C
−T−
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
M
T B
S
A
S
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0
7
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0
7
0.229
0.244
0.010
0.019
TSSOP−16
DT SUFFIX
CASE 948F−01
ISSUE O
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
K
ÉÉ
ÇÇÇ
ÇÇÇ
ÉÉ
K1
2X
L/2
16
9
J1
B
−U−
L
SECTION N−N
J
PIN 1
IDENT.
8
1
N
0.25 (0.010)
0.15 (0.006) T U
S
A
−V−
M
N
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
F
DETAIL E
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
DETAIL E
H
D
G
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6
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0
8
INCHES
MIN
MAX
0.193
0.200
0.169
0.177
−−−
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.007
0.011
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0
8
MC74VHCT257A
PACKAGE DIMENSIONS
SOIC EIAJ−16
M SUFFIX
CASE 966−01
ISSUE O
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
9
Q1
M
E HE
1
8
L
DETAIL P
Z
D
e
VIEW P
A
A1
b
0.13 (0.005)
c
M
0.10 (0.004)
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7
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
−−−
2.05
0.05
0.20
0.35
0.50
0.18
0.27
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 0
0.70
0.90
−−−
0.78
INCHES
MIN
MAX
−−−
0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 0
0.028
0.035
−−−
0.031
MC74VHCT257A
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MC74VHCT257A/D
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