3/25/08
CS5566
±2.5 V / 5 V, 5 kSps, 24-bit ∆Σ ADC
Features & Description
General Description
Differential Analog Input
The CS5566 is a single-channel, 24-bit analog-to-digital
converter capable of 5 kSps conversion rate. The input
accepts a fully differential analog input signal. On-chip
buffers provide high input impedance for both the AIN inputs and the VREF+ input. This significantly reduces the
drive requirements of signal sources and reduces errors
due to source impedances. The CS5566 is a delta-sigma
converter capable of switching multiple input channels at
a high rate with no loss in throughput. The ADC uses a
low-latency digital filter architecture. The filter is designed
for fast settling and settles to full accuracy in one conversion. The converter's 24-bit data output is in serial form,
with the serial port acting as either a master or a slave. The
converter is designed to support bipolar, ground-referenced signals when operated from ±2.5V analog supplies.
On-chip Buffers for High Input Impedance
Conversion Time = 200 µS
Settles in One Conversion
Linearity Error = 0.0005%
Signal-to-Noise = 110 dB
24 Bits, No Missing Codes
Simple three/four-wire serial interface
Power Supply Configurations:
- Analog: +5V/GND; IO: +1.8V to +3.3V
- Analog: ±2.5V; IO: +1.8V to +3.3V
The converter can operate from an analog supply of 0-5V
or from ±2.5V. The digital interface supports standard logic operating from 1.8, 2.5, or 3.3 V.
Power Consumption: 20 mW @ 5 kSps
ORDERING INFORMATION:
See Ordering Information on page 30.
V1+
VL
V2+
CS5566
VREF+
SMODE
VREFCS
SERIAL
INTERFACE
DIGITAL
FILTER
LOGIC
ADC
AI N +
SCLK
SDO
AI N-
RDY
SLEEP
BUFEN
RST
DIGITAL CONTROL
CONV
OSC/CLOCK
GENERATOR
BP/UP
MCLK
V1-
V2-
TST
Preliminary Product Information
http://www.cirrus.com
DCR
VLR
VLR2
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright © Cirrus Logic, Inc. 2008
(All Rights Reserved)
MAR ‘08
DS806PP1
3/25/08
CS5566
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
ANALOG CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
SWITCHING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DIGITAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
DIGITAL FILTER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
GUARANTEED LOGIC LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
RECOMMENDED OPERATING CONDITIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
ABSOLUTE MAXIMUM RATINGS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2. OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3. THEORY OF OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 Converter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5 Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.6 Output Coding Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.7 Typical Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.8 AIN & VREF Sampling Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.9 Converter Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.10 Digital Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.11 Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.11.1 SSC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.11.2 SEC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.12 Power Supplies & Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.13 Using the CS5566 in Multiplexing Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.14 Synchronizing Multiple Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4. PIN DESCRIPTIONS
26
5. PACKAGE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6. ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION . . . . . . . . . . . . . . 30
8. REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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LIST OF FIGURES
Figure 1. Converter Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. SSC Mode - Read Timing, CS remaining low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. SSC Mode - Read Timing, CS falling after RDY falls . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. SEC Mode - Continuous SCLK Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5. SEC Mode - Discontinuous SCLK Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6. Power Consumption vs. Conversion Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. Voltage Reference Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8. CS5566 Configured Using ±2.5V Analog Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 9. CS5566 Configured Using a Single 5V Analog Supply . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 10. CS5566 DNL Plot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11. Spectral Performance, 0 dB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12. Spectral Performance, -6 dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 13. Spectral Performance, -12 dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 14. Spectral Performance, -20 dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 15. Spectral Performance, -80 dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 16. Spectral Performance, -120 dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 17. Spectral Performance, -130 dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 19. Noise Histogram (4096 Samples) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 18. Spectral Plot of Noise with Shorted Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 20. Digital Filter Response (DC to 2.5 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
LIST OF TABLES
Table 1. Output Coding, Two’s Complement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 2. Output Coding, Offset Binary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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1. CHARACTERISTICS AND SPECIFICATIONS
•
Min / Max characteristics and specifications are guaranteed over the specified operating conditions.
•
Typical characteristics and specifications are measured at nominal supply voltages and TA = 25°C.
•
VLR = 0 V. All voltages with respect to 0 V.
ANALOG CHARACTERISTICS TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V,
±5%; VL -VLR = 3.3 V, ±5%; VREF = (VREF+) - (VREF-) = 4.096V; MCLK = 8 MHz; SMODE = VL. BUFEN = V1+
unless otherwise stated. Connected per Figure 8. Bipolar mode unless otherwise stated.
Parameter
Min
Typ
Max
Unit
-
0.0005
-
±%FS
-
±0.1
-
LSB24
Positive Full-scale Error
-
1.0
-
%FS
Negative Full-scale Error
-
1.0
-
%FS
Accuracy
Linearity Error
Differential Linearity Error
(Note 1)
Full-scale Drift
(Note 2)
-
1
-
PPM / °C
Bipolar Offset
(Note 2)
-
±500
-
LSB24
Bipolar Offset Drift
(Note 2)
-
1
-
LSB / °C
-
9.5
-
µVrms
Noise
Dynamic Performance
Peak Harmonic or Spurious Noise
200 Hz, -0.5 dB Input
-
-115
-
dB
Total Harmonic Distortion
200 Hz, -0.5 dB Input
-
-110
-100
dB
108
110
-
dB
-0.5 dB Input, 200 Hz
-60 dB Input, 200 Hz
-
109
50
-
dB
dB
(Note 3)
-
21
-
kHz
Signal-to-Noise
S/(N + D) Ratio
-3 dB Input Bandwidth
Analog Input
Analog Input Range (Differential)
Input Capacitance
CVF Current
(Note 4)
AIN Buffer On (BUFEN = V+)
AIN Buffer Off (BUFEN = V-)
Common Mode Rejection Ratio (DC to 2 kHz)
1.
2.
3.
4.
4
0 to +VREF
±VREF
Unipolar
Bipolar
V
V
-
10
-
pF
-
600
130
-
nA
µA
-100
-110
-
dB
No missing codes is guaranteed at 24 bits resolution over the specified temperature range.
One LSB is equivalent to (2 x VREF) ÷ 224 or (2 x 4.096) ÷ 16,777,216 = 488 nV.
Scales with MCLK.
Measured using an input signal of 1 V DC.
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CS5566
ANALOG CHARACTERISTICS (CONTINUED)
TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- =
V2- = -2.5 V, ±5%; VL -VLR = 3.3 V, ±5%; VREF = (VREF+) - (VREF-) = 4.096V; MCLK = 8 MHz; SMODE = VL.;
BUFEN = V1+ unless otherwise stated. Connected per Figure 8.
Parameter
Min
Typ
Max
Unit
2.4
4.096
4.2
V
-
10
-
pF
-
3
1
1
-
µA
mA
mA
Voltage Reference Input
Voltage Reference Input Range
(VREF+) – (VREF-)
(Note 5)
Input Capacitance
CVF Current
VREF+ Buffer On (BUFEN = V+)
VREF+ Buffer Off (BUFEN = V-)
VREF-
Power Supplies
Average DC Power Supply Currents (Note 6)
IV1
IV2
IVL
-
-
5
0.6
0.4
mA
mA
mA
Peak DC Power Supply Currents
IV1
IV2
IVL
-
-
9
1.2
280
mA
mA
µA
-
20
15
6
-
mW
mW
mW
75
75
85
85
-
dB
dB
(Note 6)
Average Power Consumption
Normal Operation Buffers On
(Note 6)
Buffers Off
Sleep (SLEEP = 0)
Power Supply Rejection
(Note 7)
V1+ , V2+ Supplies
V1-, V2- Supplies
5.
For optimum performance, VREF+ should always be less than (V+) - 0.2 volts to prevent saturation of the VREF+ input buffer.
6.
Specification is for MCLK = 8MHz and 5 kSps conversion rate. MCLK frequency and conversion rate affect power consumption.
See Section 3.2 Power Consumption for more details.
7.
Tested with 100 mVP-P on any supply up to 2 kHz. V1+ and V2+ supplies at the same voltage potential, V1- and V2- supplies at
the same voltage potential.
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CS5566
SWITCHING CHARACTERISTICS
TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%;
VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%
Input levels: Logic 0 = 0V Low; Logic 1 = VD+ = High; CL = 15 pF.
Parameter
Symbol
Min
Typ
Max
Unit
XIN
fclk
6
0.5
7
8
8
8.1
MHz
MHz
40
-
60
%
tres
1
-
-
µs
twup
-
240
3084
-
µs
MCLKs
tcpw
4
-
-
MCLKs
tscn
0
-
-
ns
CONV low to start of conversion
tscn
-
1182
1186
MCLKs
Perform Single Conversion (CONV high before RDY falling)
tbus
20
-
-
MCLKs
(Note 9)
Start of Conversion to RDY falling
tbuh
-
-
1604
MCLKs
SLEEP low to low-power state
SLEEP high to device active (Note 10)
tcon
tcon
-
50
3083
-
µs
MCLKs
Master Clock Frequency
Internal Oscillator
External Clock
Master Clock Duty Cycle
Reset
RST Low Time
RST rising to RDY falling
Internal Oscillator
External Clock
Conversion
CONV Pulse Width
BP/UP setup to CONV falling
Conversion Time
(Note 8)
Sleep Mode
8.
9.
BP/UP can be changed coincident CONV falling. BP/UP must remain stable until RDY falls.
If CONV is held low continuously, conversions occur every 1600 MCLK cycles.
If RDY is tied to CONV, conversions will occur every 1602 MCLKs.
If CONV is operated asynchronously to MCLK, a conversion may take up to 1604 MCLKs.
RDY falls at the end of conversion.
10. RDY will fall when the device is fully operational when coming out of sleep mode.
tbus
CONVERT
RDY
Converter
Status
IDLE
CONVERT
1182 - 1186 MCLKs
SDO
ACTIVE
IDLE
354 + 64 MCLKs
1600 - 1604 MCLKs
Figure 1. Converter Status (Not to scale)
6
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CS5566
SWITCHING CHARACTERISTICS (CONTINUED)
TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%;
VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%
Input levels: Logic 0 = 0V Low; Logic 1 = VD+ = High; CL = 15 pF.
Parameter
Symbol
Min
Typ
Max
Unit
RDY falling to MSB stable
t1
-
-2
-
MCLKs
Data hold time after SCLK rising
t2
-
10
-
ns
t3
t4
100
100
-
-
ns
ns
t5
-
8
-
MCLKs
Serial Port Timing in SSC Mode (SMODE = VL)
Serial Clock (Out)
(Note 11, 12)
Pulse Width (low)
Pulse Width (high)
RDY rising after last SCLK rising
11.
12.
SDO and SCLK will be high impedance when CS is high. In some systems it may require a pull-down resistor.
SCLK = MCLK/2.
MCLK
RDY
t5
t1
CS
t2
t3
t4
SCLK(o)
SDO
MSB
MSB–1
LSB+1
LSB
Figure 2. SSC Mode - Read Timing, CS remaining low (Not to Scale)
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SWITCHING CHARACTERISTICS (CONTINUED)
TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%;
VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%
Input levels: Logic 0 = 0V Low; Logic 1 = VD+ = High; CL = 15 pF.
Parameter
Symbol
Min
Typ
Max
Unit
t7
-
10
-
ns
t8
t9
100
100
-
-
ns
ns
RDY rising after last SCLK rising
t10
-
8
-
MCLKs
CS falling to MSB stable
t11
-
10
-
ns
First SCLK rising after CS falling
t12
-
8
-
MCLKs
CS hold time (low) after SCLK rising
t13
10
-
-
ns
SCLK, SDO tri-state after CS rising
t14
-
5
-
ns
Serial Port Timing in SSC Mode (SMODE = VL)
Data hold time after SCLK rising
Serial Clock (Out)
(Note 13, 14)
Pulse Width (low)
Pulse Width (high)
13.
SDO and SCLK will be high impedance when CS is high. In some systems SCLK and SDO may require pull-down
resistors.
14. SCLK = MCLK/2.
MCLK
t10
RDY
t13
CS
t12
t7
t8
t9
t14
SCLK(o)
t11
SDO
MSB
MSB–1
LSB+1
LSB
Figure 3. SSC Mode - Read Timing, CS falling after RDY falls (Not to Scale)
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SWITCHING CHARACTERISTICS (CONTINUED)
TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%;
VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%
Input levels: Logic 0 = 0V Low; Logic 1 = VD+ = High; CL = 15 pF.
Parameter
Symbol
Min
Typ
Max
Unit
SCLK(in) Pulse Width (High)
-
30
-
-
ns
SCLK(in) Pulse Width (Low)
-
30
-
-
ns
CS hold time (high) after RDY falling
t15
10
-
-
ns
CS hold time (high) after SCLK rising
t16
10
-
-
ns
t17
-
10
-
ns
Data hold time after SCLK rising
t18
-
10
-
ns
Data setup time before SCLK rising
t19
10
-
-
ns
CS hold time (low) after SCLK rising
t20
10
-
1
10
SCLK
ns
RDY rising after SCLK falling
t21
-
10
-
ns
Serial Port Timing in SEC Mode (SMODE = VLR)
CS low to SDO out of Hi-Z
15.
(Note 15)
SDO will be high impedance when CS is high. In some systems SDO may require a pull-down resistor.
MCLK
t21
RDY
t15
t20
CS
t16
SCLK(i)
t17
SDO
t18 t19
MSB
LSB
Figure 4. SEC Mode - Continuous SCLK Read Timing (Not to Scale)
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MCLK
t21
RDY
t15
t20
CS
SCLK(i)
t17
SDO
t18 t19
MSB
LSB
Figure 5. SEC Mode - Discontinuous SCLK Read Timing (Not to Scale)
DIGITAL CHARACTERISTICS
TA = TMIN to TMAX; VL = 3.3V, ±5% or VL = 2.5V, ±5% or 1.8V, ±5%; VLR = 0V
Parameter
Symbol
Min
Typ
Max
Unit
Input Leakage Current
Iin
-
-
2
µA
Digital Input Pin Capacitance
Cin
-
3
-
pF
Digital Output Pin Capacitance
Cout
-
3
-
pF
DIGITAL FILTER CHARACTERISTICS
TA = TMIN to TMAX; VL = 3.3V, ±5% or VL = 2.5V, ±5% or 1.8V, ±5%; VLR = 0V
Parameter
Group Delay
16.
10
(Note 16)
Symbol
Min
Typ
Max
Unit
-
-
160
-
MCLKs
See Figure 4 to understand conversion timing. The 160 MCLK group delay occurs during the 354 MCLK high-power period of a
conversion cycle. See Section 3.2 Power Consumption for more detail.
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GUARANTEED LOGIC LEVELS
TA = -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%;
VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%
Input levels: Logic 0 = 0V Low; Logic 1 = VD+ = High; CL = 15 pF.
Guaranteed Limits
Parameter
Sym
VL
Min
3.3
1.9
2.5
1.6
1.8
1.2
Typ
Max
Unit
Conditions
Logic Inputs
Minimum High-level Input Voltage:
Maximum Low-level Input Voltage:
VIH
VIL
V
3.3
1.1
2.5
0.95
1.8
0.6
V
Logic Outputs
Minimum High-level Output Voltage:
Maximum Low-level Output Voltage:
DS806PP1
VOH
VOL
3.3
2.9
2.5
2.1
1.8
1.65
3.3
0.36
2.5
0.36
1.8
0.44
V
IOH = -2 mA
V
IOH = -2 mA
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CS5566
RECOMMENDED OPERATING CONDITIONS
(VLR = 0V, see Note 17)
Parameter
Symbol
Min
Typ
Max
Unit
(Note 17)
V1+
V2+
V1V2-
V1+
V2V1+
V2-
4.75
4.75
-
5.0
5.0
0
0
5.25
5.25
-
V
V
V
V
(Note 17)
V1+
V2+
V1V2-
V1+
V2V1+
V2-
+2.375
+2.375
-2.375
-2.375
+2.5
+2.5
-2.5
-2.5
+2.625
+2.625
-2.625
-2.625
V
V
V
V
VREF
2.4
4.096
4.2
V
Single Analog Supply
DC Power Supplies:
Dual Analog Supplies
DC Power Supplies:
Analog Reference Voltage
17.
18.
(Note 18)
[VREF+] – [VREF-]
The logic supply can be any value VL – VLR = +1.71 to +3.465 volts as long as VLR ≥ V2- and VL ≤ 3.465 V.
The differential voltage reference magnitude is constrained by the V1+ or V1- supply magnitude.
ABSOLUTE MAXIMUM RATINGS
(VLR = 0V)
Parameter
Symbol
Min
Typ
Max
Unit
-
0
0
-
5.5
6.1
V
V
IIN
-
-
±10
mA
VINA
(V1-) – 0.3
-
(V1+) + 0.3
V
Digital Input Voltage
VIND
VLR – 0.3
-
VL + 0.3
V
Storage Temperature
Tstg
-65
-
150
°C
DC Power Supplies:
[V1+] – [V1-] (Note 19)
VL + [ |V1-| ] (Note 20)
Input Current, Any Pin Except Supplies
Analog Input Voltage
(Note 21)
(AIN and VREF pins)
Notes: 19. V1+ = V2+; V1- = V220.
21.
V1- = V2Transient currents of up to 100 mA will not cause SCR latch-up.
WARNING:
Recommended Operating Conditions indicate limits to which the device is functionally operational. Absolute Maximum Ratings indicate limits beyond which permanent damage to the device may occur. The Absolute Maximum Ratings are stress ratings only and the device should not be operated at these limits.
Operation at conditions beyond the Recommended Operating Conditions may affect device reliability, and
functional operation beyond Recommended Operating Conditions is not implied. Performance specifications are intended for the conditions specified for each table in the Characteristics and Specifications section.
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CS5566
2. OVERVIEW
The CS5566 is a 24-bit analog-to-digital converter capable of 5 kSps conversion rate. The device is capable of switching multiple input channels at a high rate with no loss in throughput. The ADC uses a
low-latency digital filter architecture. The filter is designed for fast settling and settles to full accuracy in
one conversion.
The converter is a serial output device. The serial port can be configured to function as either a master or
a slave.
The converter can operate from an analog supply of 5V or from ±2.5V. The digital interface supports standard logic operating from 1.8, 2.5, or 3.3 V.
The CS5566 converts at 5 kSps when operating from a 8 MHz input clock.
3. THEORY OF OPERATION
The CS5566 converter provides high-performance measurement of DC or AC signals. The converter can
be used to perform single conversions or continuous conversions upon command. Each conversion is independent of previous conversions and can settle to full specified accuracy, even with a full-scale input
voltage step. This is due to the converter architecture which uses a combination of a high-speed delta-sigma modulator and a low-latency filter architecture.
Once power is established to the converter, a reset must be performed. A reset initializes the internal converter logic.
If CONV is held low then the converter will convert continuously with RDY falling every 1600 MCLKs. This
is equivalent to 5 kSps if MCLK = 8.0 MHz. If CONV is tied to RDY, a conversion will occur every
1602 MCLKs. If CONV is operated asynchronously to MCLK, it may take up to 1604 MCLKs from CONV
falling to RDY falling.
Multiple converters can operate synchronously if they are driven by the same MCLK source and CONV
to each converter falls on the same MCLK falling edge. Alternately, CONV can be held low and all devices
are reset with RST rising on the same falling edge of MCLK.
The output coding of the conversion word is a function of the BP/UP pin.
The active-low SLEEP signal causes the device to enter a low-power state. When exiting sleep, the converter will take 3083 MCLK cycles before conversions can be performed. RST should remain inactive
(high) when SLEEP is asserted (low).
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CS5566
3.1 Converter Operation
The converter should be reset after the power supplies and voltage reference are stable.
The CS5566 converts at 5 kSps when synchronously operated (CONV = VLR) from a 8.0 MHz master
clock. Conversion is initiated by taking CONV low. A conversion lasts 1600 master clock cycles, but if
CONV is asynchronous to MCLK there may be an uncertainty of 0-4 MCLK cycles after CONV falls to
when a conversion actually begins. This may extend the throughput to 1604 MCLKs
When the conversion is completed, the output word is placed into the serial port and RDY goes low. To
convert continuously, CONV should be held low. In continuous conversion mode with CONV held low, a
conversion is performed in 1600 MCLK cycles. Alternately RDY can be tied to CONV and a conversion
will occur every 1602 MCLK cycles.
To perform only one conversion, CONV should return high at least 20 master clock cycles before RDY
falls.
Once a conversion is completed and RDY falls, RDY will return high when all the bits of the data word are
emptied from the serial port or if the conversion data is not read and CS is held low, RDY will go high two
MCLK cycles before the end of conversion. RDY will fall at the end of the next conversion when new data
is put into the port register.
See Section 3.11 Serial Port for information about reading conversion data.
Conversion performance can be affected by several factors. These include the choice of clock source for
the chip, the timing of CONV, and the choice of the serial port mode.
The converter can be operated from an internal oscillator. This clock source has greater jitter than an external crystal-based clock. Jitter may not be an issue when measuring DC signals, or very-low-frequency
AC signals, but can become an issue for higher frequency AC signals. For maximum performance when
digitizing AC signals, a low-jitter MCLK should be used.
To maximize performance, the CONV pin should be held low in the continuous conversion state to perform multiple conversions, or CONV should occur synchronous to MCLK, falling when MCLK falls.
If the converter is operated at maximum throughput, the SSC serial port mode is less likely to cause interference to measurements as the SCLK output is synchronized to the MCLK. Alternately, any interference due to serial port clocking can also be minimized if data is read in the SEC serial port mode when a
conversion is not in progress.
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CS5566
3.2 Power Consumption
Power Consumption (mW)
The power consumption of the CS5566 converter is a function of the conversion rate. Figure 6 illustrates
the typical power consumption of the converter when operating from either MCLK = 8 MHz or
MCLK = 4 MHz. The rate at which conversions are performed directly affects the power consumption.
When the converter is powered but not converting, it is in an idle state where its power consumption is
about 11 mW. When the CONV signal goes low to start a conversion, the converter delays the actual start
of conversion for 1182 to 1186 MCLK cycles, depending upon how CONV is controlled. The timing for the
conversion sequence is shown in Figure 1 on page 6. After the 1182 - 1186 MCLK delay from when
CONV goes low, the converter enters a higher-power state for 354 MCLK cycles and then returns to a
lower-power state for 64 MCLK cycles, after which the RDY signal falls to indicate the completion of a
conversion. Since the peak operating current for the converter occurs during the 354 MCLK, higher-power state, it is recommended that a large capacitor be used on the supply to the converter (as shown in
Figures 9 and 10). This capacitor filters the peak current demand from the power supply. The average
power consumption for the converter will depend upon the frequency of MCLK and the rate at which conversions are performed as illustrated in Figure 1 on page 6.
20
17.5
MCLK = 4MHz
15
MCLK = 8MHz
12.5
10
7.5
0
500
1k
1.5
2k 2.5k 3k 3.5k 4k 4.5k 5k
Word Rate (Sps)
Figure 6. Power Consumption vs. Conversion Rate
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CS5566
3.3 Clock
The CS5566 can be operated from its internal oscillator or from an external master clock. The state of
MCLK determines which clock source will be used. If MCLK is tied low, the internal oscillator will start and
be used as the clock source for the converter. If an external CMOS-compatible clock is input into MCLK
the converter will power down the internal oscillator and use the external clock. If the MCLK pin is held
high, the internal oscillator will be held in the stopped state. The MCLK input can be held high to delete
clock cycles to aid in operating multiple converters in different phase relationships.
The internal oscillator can be used if the signals to be measured are essentially DC. The internal oscillator
exhibits jitter at about 500 picoseconds rms. If the CS5566 is used to digitize AC signals, an external
low-jitter clock source should be used.
If the internal oscillator is used as the clock for the CS5566, the maximum conversion rate will be dictated
by the oscillator frequency.
If driven from an external MCLK source, the fast rise and fall times of the MCLK signal can result in clock
coupling from the internal bond wire of the IC to the analog input. Adding a 50 ohm resistor on the external
MCLK source significantly reduces this effect.
3.4 Voltage Reference
The voltage reference for the CS5566 can range from 2.4 volts to 4.2 volts. A 4.096 volt reference is required to achieve the specified performance. Figure 8 and Figure 9 illustrate the connection of the voltage
reference with either a single +5 V analog supply or with ±2.5 V.
For optimum performance, the voltage reference device should be one that provides a capacitor connection to provide a means of noise filtering, or the output should include some type of bandwidth-limiting filter. Some 4.096 volt reference devices need only 5 volts total supply for operation and can be connected
as shown in Figure 8 or Figure 9. The reference should have a local bypass capacitor and an appropriate
output capacitor.
Some older 4.096 voltage reference designs require more headroom and must operate from an input voltage of 5.5 to 6.5 volts. If this type of voltage reference is used ensure that when power is applied to the
system, the voltage reference rise time is slower than the rise time of the V1+ and V1- power supply voltage to the converter. An example circuit to slow the output startup time of the reference is illustrated in
Figure 7.
5.5 to 15 V
2k
10µF
VIN
VOUT
4.096 V
GND
Refer to V1- and VREF1 pins.
Figure 7. Voltage Reference Circuit
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CS5566
3.5 Analog Input
The analog input of the converter is fully differential with a peak-to-peak input of 4.096 volts on each input.
Therefore, the differential, peak-to-peak input is 8.192 volts. This is illustrated in Figure 8 and Figure 9.
These diagrams also illustrate a differential buffer amplifier configuration for driving the CS5566.
The capacitors at the outputs of the amplifiers provide a charge reservoir for the dynamic current from the
A/D inputs while the resistors isolate the dynamic current from the amplifier. The amplifiers can be powered from higher supplies than those used by the A/D but precautions should be taken to ensure that the
opamp output voltage remains within the power supply limits of the A/D, especially under start-up conditions.
3.6 Output Coding Format
The reference voltage directly defines the input voltage range in both the unipolar and bipolar configurations. In the unipolar configuration (BP/UP low), the first code transition occurs 0.5 LSB above zero, and
the final code transition occurs 1.5 LSBs below VREF. In the bipolar configuration (BP/UP high), the first
code transition occurs 0.5 LSB above -VREF and the last transition occurs 1.5 LSBs below +VREF. See
Table 1 for the output coding of the converter.
Table 1. Output Coding, Two’s Complement
Bipolar Input Voltage
Two’s
Complement
>(VREF-1.5 LSB)
7F FF FF
7F FF FF
VREF-1.5 LSB
7F FF FE
00 00 00
-0.5 LSB
FF FF FF
80 00 01
-VREF+0.5 LSB
80 00 00
<(-VREF+0.5 LSB)
80 00 00
NOTE: VREF = (VREF+) - (VREF-)
Table 2. Output Coding, Offset Binary
Unipolar Input Voltage
Offset
Binary
>(VREF-1.5 LSB)
FF FF FF
FF FF FF
VREF-1.5 LSB
FF FF FE
80 00 00
(VREF/2)-0.5 LSB
7F FF FF
00 00 01
+0.5 LSB
00 00 00
<(+0.5 LSB)
00 00 00
NOTE: VREF = (VREF+) - (VREF-)
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CS5566
3.7 Typical Connection Diagrams
The following figure depicts the CS5566 powered from bipolar analog supplies, +2.5 V and - 2.5 V.
4700pF
C0G
R1
C1
AIN+
47pF
4.99k
4.99k
R1
C1
CS5566
49.9
49.9
+2.048 V
0V
-2.048 V
SMODE
+2.048 V
0V
-2.048 V
CS
5
SCLK
AIN47pF
4700pF
C0G
4.99k
5
SDO
RDY
4.99k
(V+) Buffers On
CONV
BUFEN
+2.5 V
BP/UP
(V-) Buffers Off
+4.096
Voltage
Reference
(NOTE 1)
SLEEP
VREF+
10 µF
RST
0.1 µF
50
MCLK
VREFTST
-2.5 V
+3.3 V to +1.8 V
+2.5 V
V1+
VL
10
0.1 µF
V2+
47 µF
0.1 µF
0.1 µF
10
V20.1 µF
X7R
DCR
V1-
VLR2
VLR
-2.5 V
NOTES
1. See Section 3.3 Voltage Reference for information on required
voltage reference performance criteria.
2.Locate capacitors so as to minimize loop length.
3. The ±2.5 V supplies should also be bypassed to ground at the converter.
4. VLR and the power supply ground for the ±2.5 V should be
connected to the same ground plane under the chip.
5. SCLK and SDO may require pull-down resistors in some applications.
6. An RC input filter can be used to band limit the input to reduce noise.
Select R to be equal to the parallel combination of the feedback of the
feedback resistors 4.99k || 4.99k = 2.5k0 0
Figure 8. CS5566 Configured Using ±2.5V Analog Supplies
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CS5566
The following figure depicts the CS5566 device powered from a single 5V analog supply.
4700pF
C0G
49.9
2.048 V
AIN+
47pF
CS5566
4.548 V
2.5 V
+0.452 V
4.99k
SMODE
+4.548 V
2.5 V
+0.452 V
49.9
CS
4
SCLK
AIN4.096 V
47pF
4700pF
C0G
4.99k
4
SDO
RDY
(V+) Buffers On
CONV
BUFEN
+5 V
(V-) Buffers Off
BP/UP
SLEEP
+4.096
Voltage
Reference
(NOTE 1)
VREF+
10 µF
RST
0.1 µF
50
MCLK
VREFTST
+3.3 V to 1.8 V
+5 V
V1+
0.1 µF
VL
10
V2+
47 µF
0.1 µF
0.1 µF
V20.1 µF
X7R
DCR
V1-
VLR2
VLR
NOTES
1. See Section 3.3 Voltage Reference for information on
required voltage reference performance criteria.
2. Locate capacitors so as to minimize loop length.
3. V1-, V2-, and VLR should be connected to the same
ground plane under the chip.
4. SCLK and SDO may require pull-down resistors in
some applications.
Figure 9. CS5566 Configured Using a Single 5V Analog Supply
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CS5566
3.8 AIN & VREF Sampling Structures
The CS5566 uses on-chip buffers on the AIN+, AIN-, and the VREF+ inputs. Buffers provide much higher
input impedance and therefore reduce the amount of drive current required from an external source. This
helps minimize errors.
The Buffer Enable (BUFEN) pin determines if the on-chip buffers are used or not. If the BUFEN pin is connected to the V1+ supply, the buffers will be enabled. If the BUFEN pin is connected to the V1- pin, the
buffers are off. The converter will consume about 5 mW less power when the buffers are off, but the input
impedances of AIN+, AIN- and VREF+ will be significantly less than with the buffers enabled.
3.9 Converter Performance
The CS5566 achieves excellent differential nonlinearity (DNL). Figure 10 illustrates the code widths on
the typical scale of ±1 LSB and on a zoomed scale of ±0.2 LSB.
(Zoom View)
Figure 10. CS5566 DNL Plot
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CS5566
Figure 11 through Figure 16 illustrate the performance of the converter with various input signal magnitudes.
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
277 Hz, 0 dB
32k Samples @ 5 kSps
0
500
1k
1.5k
Frequency (Hz)
2k
2.5k
Figure 11. Spectral Performance, 0 dB
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
500
1k
1.5k
Frequency (Hz)
2k
500
1k
1.5k
Frequency (Hz)
2k
Figure 15. Spectral Performance, -80 dB
DS806PP1
1k
1.5k
Frequency (Hz)
2k
2.5k
277 Hz, -20 dB
32k Samples @ 5 kSps
0
2.5k
500
1k
1.5k
Frequency (Hz)
2k
2.5k
Figure 14. Spectral Performance, -20 dB
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
277 Hz, -80 dB
32k Samples @ 5 kSps
0
500
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
Figure 13. Spectral Performance, -12 dB
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
0
Figure 12. Spectral Performance, -6 dB
277 Hz, -12 dB
32k Samples @ 5 kSps
0
277 Hz, -6 dB
32k Samples @ 5 kSps
2.5k
277 Hz, -120 dB
32k Samples @ 5 kSps
0
500
1k
1.5k
Frequency (Hz)
2k
2.5k
Figure 16. Spectral Performance, -120 dB
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CS5566
Figure 16 illustrates the device with a small signal 1/1,000,000 of full scale. The signal input for figure 15
is about 8.2 microvolts peak to peak, or about 17 codes peak to peak. Figure 17 illustrates the converter
with a signal at about 2.6 microvolts peak to peak, or about 5 codes peak to peak. The CS5566 achieves
superb performance with this small signal.
Figure 18 illustrates the noise floor of the converter from 0.1 Hz to 2.5 kHz. The plot is entirely free of spurious frequency content due to digital activity inside the chip.
Figure 19 illustrates a noise histogram of the converter constructed from 4096 samples.
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
277 Hz, -130 dB
32k Samples @ 5 kSps
0
500
1k
1.5k
Frequency (Hz)
2k
2.5k
Figure 17. Spectral Performance, -130 dB
-60
Shorted Input
2M Samples @ 5 kSps
16 Averages
-80
-100
-120
-140
-160
-180
0.1
1
10
Frequency (Hz)
100
1k
2.5k
Number of Occurances
Figure 18. Spectral Plot of Noise with Shorted Input
100
90
80
70
60
50
40
30
20
10
0
4096 Samples
Mean = 96.32
Std. Dev. = 21.3
Max - Min = 150
Output Codes
Figure 19. Noise Histogram (4096 Samples)
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CS5566
3.10 Digital Filter Characteristics
The digital filter is designed for fast settling, therefore it exhibits very little in-band attenuation. The filter
attenuation is -0.0414 dB at 2.5 kHz when sampling at 5 kSps.
-0.001646 dB
fs = 5 kSps
-0.00663 dB
-0.0149 dB
-0.0262 dB
-0.0414 dB
Frequency (Hz)
Figure 20. Digital Filter Response (DC to 2.5 kHz)
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CS5566
3.11 Serial Port
The serial port on the CS5566 can operate in two different modes: synchronous self clock (SSC) mode &
synchronous external clock (SEC) mode. The serial port must be placed into the SEC mode if the offset
and gain registers of the converter are to be read or written. The converter must be idle when reading or
writing to the on-chip registers.
3.11.1 SSC Mode
If the SMODE pin is high (SMODE = VL), the serial port operates in the SSC (Synchronous Self Clock)
mode. In the SSC mode the port shifts out conversion data words with SCLK as an output. SCLK is generated inside the converter from MCLK. Data is output from the SDO (Serial Data Output) pin. If CS is
high, the SDO and SCLK pins will stay in a high-impedance state. If CS is low when RDY falls, the conversion data word will be output from SDO MSB first. Data is output on the rising edge of SCLK and should
be latched into the external logic on the subsequent rising edge of SCLK. When all bits of the conversion
word are output from the port the RDY signal will return to high.
3.11.2 SEC Mode
If the SMODE pin is low (SMODE = VLR), the serial port operates in the SEC (Synchronous External
Clock mode). In this mode, the user usually monitors RDY. When RDY falls at the end of a conversion,
the conversion data word is placed into the output data register in the serial port. CS is then activated low
to enable data output. Note that CS can be held low continuously if it is not necessary to have the SDO
output operate in the high impedance state. When CS is taken low (after RDY falls) the conversion data
word is then shifted out of the SDO pin by driving the SCLK pin from system logic external to the converter.
Data bits are advanced on rising edges of SCLK and latched by the subsequent rising edge of SCLK.
If CS is held low continuously, the RDY signal will fall at the end of a conversion and the conversion data
will be placed into the serial port. If the user starts a read, the user will maintain control over the serial port
until the port is empty. However, if SCLK is not toggled, the converter will overwrite the conversion data
at the completion of the next conversion. If CS is held low and no read is performed, RDY will rise just
prior to the end of the next conversion and then fall to signal that new data has been written into the serial
port.
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CS5566
3.12 Power Supplies & Grounding
The CS5566 can be configured to operate with its analog supply operating from 5V, or with its analog supplies operating from ±2.5V. The digital interface supports digital logic operating from either 1.8V, 2.5V, or
3.3V.
Figure 8 on page 18 illustrates the device configured to operate from ±2.5V analog. Figure 9 on page 19
illustrates the device configured to operate from 5V analog. Note that the schematic indicates a 47 µF capacitor between V1+ and V1-. This capacitor is necessary to reduce the peak current required from the
power supply during conversion. See Power Consumption on page 16 for a more detailed discussion.
To maximize converter performance, the analog ground and the logic ground for the converter should be
connected at the converter. In the dual analog supply configuration, the analog ground for the ±2.5V supplies should be connected to the VLR pin at the converter with the converter placed entirely over the analog ground plane.
In the single analog supply configuration (+5V), the ground for the +5V supply should be directly tied to
the VLR pin of the converter with the converter placed entirely over the analog ground plane. Refer to
Figure 9 on page 19.
3.13 Using the CS5566 in Multiplexing Applications
The actual conversion process inside the CS5566 begins 1182 MCLK cycles after the CONV signal is taken low. This would be over 147 microseconds when MCLK = 8 MHz. If the input channel of an external
multiplexer is changed coincident with CONV going low, the 1182 MCLK delay should be more than an
adequate time for settling. If there is an operational amplifier between the multiplexer and the converter,
one should be certain that the amplifier can settle within the 1182 MCLK delay period. If not, the multiplexer will need to be switched some time prior to CONV going low.
3.14 Synchronizing Multiple Converters
Many measurement systems have multiple converters that need to operate synchronously. The converters should all be driven from the same master clock. In this configuration, the converters will convert synchronously if the same CONV signal is used to drive all the converters, and CONV falls on a falling edge
of MCLK. If CONV is held low continuously, reset (RST) can be used to synchronize multiple converters
if RST is released on a falling edge of MCLK.
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CS5566
4. PIN DESCRIPTIONS
Chip Select
Factory Test
Serial Mode Select
Differential Analog Input
Differential Analog Input
Negative Power 1
Positive Power 1
Buffer Enable
Voltage Reference Input
Voltage Reference Input
Bipolar/Unipolar Select
Sleep Mode Select
CS
TST
SMODE
AIN+
AINV1V1+
BUFEN
VREF+
VREFBP/UP
SLEEP
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
RDY
SCLK
SDO
VL
VLR
MCLK
V2V2+
DCR
CONV
VLR2
RST
Ready
Serial Clock Input/Output
Serial Data Output
Logic Interface Power
Logic Interface Return
Master Clock
Negative Voltage 2
Positive Voltage 2
Digital Core Regulator
Convert
Logic Interface Return
Reset
CS – Chip Select, Pin 1
The Chip Select pin allows an external device to access the serial port. If SMODE = VL (SSC
Mode) and CS is held high, the SDO output and the SCLK output will be held in a
high-impedance output state.
TST – Factory Test, Pin 2
Factory test only. Connect to VLR.
SMODE – Serial Mode Select, Pin 3
The serial interface mode pin (SMODE) dictates whether the serial port behaves as a master or
slave interface. If SMODE is tied high (to VL), the port will operate in the Synchronous
Self-Clocking (SSC) mode. In SSC mode, the port acts as a master in which the converter outputs both the SDO and SCLK signals. If SMODE is tied low (to VLR), the port will operate in the
Synchronous External Clocking (SEC) mode. In SEC mode, the port acts as a slave in which
the external logic or microcontroller generates the SCLK used to output the conversion data
word from the SDO pin.
AIN+, AIN- – Differential Analog Input, Pin 4, 5
AIN+ and AIN- are differential inputs for the converter.
V1- – Negative Power 1, Pin 6
The V1- and V2- pins provide a negative supply voltage to the core circuitry of the chip. These
two pins should be decoupled as shown in the application block diagrams. V1- and V2- should
be supplied from the same source voltage. For single-supply operation, these two voltages are
nominally 0 V (Ground). For dual-supply operation, they are nominally -2.5 V.
V1+ – Positive Power 1, Pin 7
The V1+ and V2+ pins provide a positive supply voltage to the core circuitry of the chip. These
two pins should be decoupled as shown in the application block diagrams. V1+ and V2+ should
be supplied from the same source voltage. For single supply-operation, these two voltages are
nominally +5 V. For dual-supply operation, they are nominally +2.5 V.
BUFEN – Buffer Enable, Pin 8
Buffers on input pins AIN+ and AIN- are enabled if BUFEN is connected to V1+ and disabled if
connected to V1-.
VREF+, VREF- – Voltage Reference Input, Pin 9, 10
A differential voltage reference input on these pins functions as the voltage reference for the
converter. The voltage between these pins can range between 2.4 volts and 4.2 volts, with
4.096 volts being the nominal reference voltage value.
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BP/UP – Bipolar/Unipolar Select, Pin 11
The BP/UP pin determines the span and the output coding of the converter. When set high to
select BP (bipolar), the input span of the converter is -4.096 volts to +4.096 volts fully differential
(assuming the voltage reference is 4.096 volts) and output data is coded in two's complement
format. When set low to select UP (unipolar), the input span is 0 to +4.096 fully differential and
the output data is coded in binary format.
SLEEP – Sleep Mode Select, Pin 12
When taken low, the SLEEP pin will cause the converter to enter into a low-power state. SLEEP
will stop the internal oscillator and power down all internal analog circuitry.
RST – Reset, Pin 13
Reset is necessary after power is initially applied to the converter. When the RST input is taken
low, the logic in the converter will be reset. When RST is released to go high, certain portions of
the analog circuitry are started. RDY falls when reset is complete.
CONV – Convert, Pin 15
The CONV pin initiates a conversion cycle if taken low, unless a previous conversion is in
progress. When the conversion cycle is completed, the conversion word is output to the serial
port register and the RDY signal goes low. If CONV is held low and remains low when RDY
falls, another conversion cycle will be started.
DCR – Digital Core Regulator, Pin 16
DCR is the output of the on-chip regulator for the digital logic core. DCR should be bypassed
with a capacitor to V2-. The DCR pin is not designed to power any external load.
V2+ – Positive Power 2, Pin 17
The V1+ and V2+ pins provide a positive supply voltage to the circuitry of the chip. These two
pins should be decoupled as shown in the application block diagrams. V1+ and V2+ should be
supplied from the same source voltage. For single-supply operation, these two voltages are
nominally +5 V. For dual-supply operation, they are nominally +2.5 V.
V2- – Negative Power 2, Pin 18
The V1- and V2- pins provide a negative supply voltage to the circuitry of the chip. These two
pins should be decoupled as shown in the application block diagrams. V1- and V2- should be
supplied from the same source voltage. For single-supply operation, these two voltages are
nominally 0 V (Ground). For dual-supply operation, they are nominally -2.5 V.
MCLK – Master Clock, Pin 19
The master clock pin (MCLK) is a multi-function pin. If tied low (MCLK = VLR), the on-chip oscillator will be enabled. If tied high (MCLK = VL), all clocks to the internal circuitry of the converter
will stop. When MCLK is held high the internal oscillator will also be stopped. MCLK can also
function as the input for an external CMOS-compatible clock that conforms to supply voltages
on the VL and VLR pins.
VLR2, VLR, VL – Logic Interface Power/Return, Pins 14, 20, 21
VL and VLR are the supply voltages for the digital logic interface. VL and VLR can be configured with a wide range of common mode voltage. The following interface pins function from the
VL/VLR supply: SMODE, CS, SCLK, SDO, RDY, SLEEP, CONV, RST, BP/UP, and MCLK.
SDO – Serial Data Output, Pin 22
SDO is the output pin for the serial output port. Data from this pin will be output at a rate determined by SCLK and in a format determined by the BP/UP pin. Data is output MSB first and
advances to the next data bit on the rising edges of SCLK. SDO will be in a high impedance
state when CS is high.
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SCLK – Serial Clock Input/Output, Pin 23
The SMODE pin determines whether the SCLK signal is an input or an output signal. SCLK
determines the rate at which data is clocked out of the SDO pin. If the converter is in SSC
mode, the SCLK frequency will be determined by the master clock frequency of the converter
(either MCLK or the internal oscillator). In SEC mode, the user determines the SCLK frequency.
If SMODE = VL (SSC Mode), SCLK will be in a high-impedance state when CS is high.
RDY – Ready, Pin 24
If CONV is low the converter will immediately start a conversion and RDY will remain high until
the conversion is completed. At the end of any conversion RDY falls to indicate that a conversion word has been placed into the serial port. RDY will return high after all data bits are shifted
out of the serial port or two master clock cycles before new data becomes available if the CS pin
is inactive (high); or two master clock cycles before new data becomes available if the user
holds CS low but has not started reading the data from the converter when in SEC mode.
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5. PACKAGE DIMENSIONS
24L SSOP PACKAGE DRAWING
N
D
E11
A2
E
e
b2
SIDE VIEW
A
∝
A1
L
END VIEW
SEATING
PLANE
1 2 3
TOP VIEW
DIM
A
A1
A2
b
D
E
E1
e
L
MIN
-0.002
0.064
0.009
0.311
0.291
0.197
0.022
0.025
0°
∝
INCHES
NOM
-0.006
0.068
-0.323
0.307
0.209
0.026
0.03
4°
MAX
0.084
0.010
0.074
0.015
0.335
0.323
0.220
0.030
0.041
8°
MIN
-0.05
1.62
0.22
7.90
7.40
5.00
0.55
0.63
0°
MILLIMETERS
NOM
-0.13
1.73
-8.20
7.80
5.30
0.65
0.75
4°
NOTE
MAX
2.13
0.25
1.88
0.38
8.50
8.20
5.60
0.75
1.03
8°
2,3
1
1
JEDEC #: MO-150
Controlling Dimension is Millimeters.
Notes:
1.“D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured
at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side.
2.Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b”
dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least
material condition.
3.These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
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6. ORDERING INFORMATION
Model
CS5566-ISZ
Linearity
Temperature
Conversion Time
Throughput
Package
0.0005%
-40 to +85 °C
200 µs
5 kSps
24-pin SSOP
7. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION
Model Number
Peak Reflow Temp
MSL Rating*
Max Floor Life
260 °C
3
7 Days
CS5566-ISZ
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
8. REVISION HISTORY
Revision
PP1
Date
MAR 2008
Changes
Preliminary release.
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com
IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available.
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
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IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
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Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
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