IS41C16105 IS41LV16105 1M x 16 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE DESCRIPTION The 1+51 IS41C16105 and IS41LV16105 are 1,048,576 x FEATURES TTL compatible inputs and outputs; tristate I/O Refresh Interval: 1,024 cycles/16 ms Refresh Mode: RAS-Only, CAS-before-RAS (CBR), Hidden JEDEC standard pinout Single power supply: 5V ± 10% (IS41C16105) 3.3V ± 10% (IS41LV16105) Byte Write and Byte Read operation via two CAS 16-bit high-performance CMOS Dynamic Random Access Memories. Fast Page Mode allows 1,024 random accesses within a single row with access cycle time as short as 20 ns per 16-bit word. The Byte Write control, of upper and lower byte, makes the IS41C16105 ideal for use in 16-, 32-bit wide data bus systems. These features make the IS41C16105 and IS41LV16105 ideally suited for high-bandwidth graphics, digital signal processing, high-performance computing systems, and peripheral applications. Industrail temperature range -40oC to 85oC The IS41C16105 and IS41LV16105 are packaged in a 42-pin 400mil SOJ and 400mil 44- (50-) pin TSOP-2. KEY TIMING PARAMETERS Parameter -50 -60 Unit Max. RAS Access Time (tRAC) 50 60 ns Max. CAS Access Time (tCAC) 13 15 ns Max. Column Address Access Time (tAA) 25 30 ns Min. Fast Page Mode Cycle Time (tPC) 20 25 ns Min. Read/Write Cycle Time (tRC) 84 104 ns PIN CONFIGURATIONS 44(50)-Pin TSOP-2 VCC 1 50 GND I/O0 2 49 I/O15 I/O1 3 48 I/O14 I/O2 4 47 I/O13 I/O3 5 46 I/O12 VCC 6 45 GND 42-Pin SOJ VCC 1 42 GND I/O0 2 41 I/O15 I/O1 3 40 I/O14 I/O2 4 39 I/O13 I/O3 5 38 I/O12 VCC 6 37 GND I/O4 7 44 I/O11 I/O5 8 43 I/O10 I/O4 7 36 I/O11 I/O6 9 42 I/O9 I/O5 8 35 I/O10 9 34 I/O9 PIN DESCRIPTIONS A0-A9 Address Inputs I/O0-15 Data Inputs/Outputs I/O7 10 41 I/O8 I/O6 NC 11 40 NC I/O7 10 33 I/O8 NC 11 32 NC WE Write Enable NC 15 36 NC NC 12 31 LCAS NC 16 35 LCAS WE 13 30 UCAS OE Output Enable WE 17 34 UCAS RAS 14 29 OE RAS 18 33 OE RAS Row Address Strobe NC 15 28 A9 NC 19 32 A9 NC 16 27 A8 UCAS Upper Column Address Strobe NC 20 31 A8 A0 21 30 A7 A0 17 26 A7 LCAS Lower Column Address Strobe A1 22 29 A6 A1 18 25 A6 28 A5 19 24 A5 Power 23 A2 Vcc A2 A3 24 27 A4 A3 20 23 A4 GND Ground VCC 25 26 GND VCC 21 22 GND NC No Connection ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc. Integrated Circuit Solution Inc. DR005-0C 1 IS41C16105 IS41LV16105 FUNCTIONAL BLOCK DIAGRAM OE WE LCAS UCAS CAS CLOCK GENERATOR WE CONTROL LOGICS CAS WE OE CONTROL LOGIC OE DATA I/O BUS COLUMN DECODERS SENSE AMPLIFIERS ADDRESS BUFFERS A0-A9 2 ROW DECODER REFRESH COUNTER MEMORY ARRAY 1,048,576 x 16 DATA I/O BUFFERS RAS CLOCK GENERATOR RAS RAS I/O0-I/O15 Integrated Circuit Solution Inc. DR005-0C IS41C16105 IS41LV16105 TRUTH TABLE Standby Read: Word Read: Lower Byte RAS H L L Read: Upper Byte L H L H L ROW/COL Write: Word (Early Write) Write: Lower Byte (Early Write) L L L L L H L L X X ROW/COL ROW/COL Write: Upper Byte (Early Write) L H L L X ROW/COL L L→H→L L→H→L L H→L L L L H L L L L H L H→L H L X X L→H L X X X ROW/COL ROW/COL ROW/COL ROW/NA X Function Read-Write(1,2) Hidden Refresh Read Write(1,3) RAS-Only Refresh CBR Refresh(4) (2) LCAS UCAS H H L L L H WE X H H OE X L L Address tR/tC X ROW/COL ROW/COL I/O High-Z DOUT Lower Byte, DOUT Upper Byte, High-Z Lower Byte, High-Z Upper Byte, DOUT DIN Lower Byte, DIN Upper Byte, High-Z Lower Byte, High-Z Upper Byte, DIN DOUT, DIN DOUT DOUT High-Z High-Z Notes: 1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active). 2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active). 3. EARLY WRITE only. 4. At least one of the two CAS signals must be active (LCAS or UCAS). Integrated Circuit Solution Inc. DR005-0C 3 IS41C16105 IS41LV16105 Functional Description Write Cycle The IS41C16105 and IS41LV16105 is a CMOS DRAM optimized for high-speed bandwidth, low power applications. During READ or WRITE cycles, each bit is uniquely addressed through the 10 address bits. These are entered ten bits (A0-A9) at a time. The row address is latched by the Row Address Strobe (RAS). The column address is latched by the Column Address Strobe (CAS). RAS is used to latch the first ten bits and CAS is used the latter ten bits. The IS41C16105 and IS41LV16105 has two CAS controls, LCAS and UCAS. The LCAS and UCAS inputs internally generates a CAS signal functioning in an identical manner to the single CAS input on the other 1M x 16 DRAMs. The key difference is that each CAS controls its corresponding I/O tristate logic (in conjunction with OE and WE and RAS). LCAS controls I/O0 through I/O7 and UCAS controls I/O8 through I/O15. The IS41C16105 and IS41LV16105 CAS function is determined by the first CAS (LCAS or UCAS) transitioning LOW and the last transitioning back HIGH. The two CAS controls give the IS41C16105 and IS41LV16105 both BYTE READ and BYTE WRITE cycle capabilities. A write cycle is initiated by the falling edge of CAS and WE, whichever occurs last. The input data must be valid at or before the falling edge of CAS or WE, whichever occurs last. Memory Cycle A memory cycle is initiated by bring RAS LOW and it is terminated by returning both RAS and CAS HIGH. To ensures proper device operation and data integrity any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. A new cycle must not be initiated until the minimum precharge time tRP, tCP has elapsed. Refresh Cycle To retain data, 1,024 refresh cycles are required in each 16 ms period. There are two ways to refresh the memory. 1. By clocking each of the 1,024 row addresses (A0 through A9) with RAS at least once every 16 ms. Any read, write, read-modify-write or RAS-only cycle refreshes the addressed row. 2. Using a CAS-before-RAS refresh cycle. CAS-beforeRAS refresh is activated by the falling edge of RAS, while holding CAS LOW. In CAS-before-RAS refresh cycle, an internal 10-bit counter provides the row addresses and the external address inputs are ignored. CAS-before-RAS is a refresh-only mode and no data access or device selection is allowed. Thus, the output remains in the High-Z state during the cycle. Power-On After application of the VCC supply, an initial pause of 200 µs is required followed by a minimum of eight initialization cycles (any combination of cycles containing a RAS signal). During power-on, it is recommended that RAS track with VCC or be held at a valid VIH to avoid current surges. Read Cycle A read cycle is initiated by the falling edge of CAS or OE, whichever occurs last, while holding WE HIGH. The column address must be held for a minimum time specified by tAR. Data Out becomes valid only when tRAC, tAA, tCAC and tOEA are all satisfied. As a result, the access time is dependent on the timing relationships between these parameters. 4 Integrated Circuit Solution Inc. DR005-0C IS41C16105 IS41LV16105 ABSOLUTE MAXIMUM RATINGS(1) Symbol Parameters VT Voltage on Any Pin Relative to GND VCC Supply Voltage IOUT PD TA Output Current Power Dissipation Commercial Operation Temperature Industrail Operation Temperature Storage Temperature TSTG 5V 3.3V 5V 3.3V Rating Unit 1.0 to +7.0 0.5 to +4.6 1.0 to +7.0 0.5 to +4.6 50 1 0 to +70 40 to +85 55 to +125 V V mA W °C °C °C Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.) Symbol Parameter VCC Supply Voltage VIH Input High Voltage VIL Input Low Voltage TA Commercial Ambient Temperature Industrail Ambient Temperature 5V 3.3V 5V 3.3V 5V 3.3V Min. Typ. Max. Unit 4.5 3.0 2.4 2.0 1.0 0.3 0 40 5.0 3.3 5.5 3.6 VCC + 1.0 VCC + 0.3 0.8 0.8 70 85 V V V °C °C CAPACITANCE(1,2) Symbol Parameter CIN1 CIN2 CIO Input Capacitance: A0-A9 Input Capacitance: RAS, UCAS, LCAS, WE, OE Data Input/Output Capacitance: I/O0-I/O15 Max. Unit 5 7 7 pF pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, Integrated Circuit Solution Inc. DR005-0C 5 IS41C16105 IS41LV16105 ELECTRICAL CHARACTERISTICS(1) (Recommended Operating Conditions unless otherwise noted.) Symbol Parameter Test Condition IIL Input Leakage Current IIO Speed Min. Max. Unit Any input 0V < VIN < Vcc Other inputs not under test = 0V 5 5 µA Output Leakage Current Output is disabled (Hi-Z) 0V < VOUT < Vcc 5 5 µA VOH Output High Voltage Level IOH = 5.0 mA (5V) IOH = 2.0 mA (3.3V) 2.4 V VOL Output Low Voltage Level IOL = 4.2 mA (5V) IOL = 2.0 mA (3.3V) 0.4 V ICC1 Standby Current: TTL RAS, LCAS, UCAS > VIH Commerical 2 1 3 2 mA 5V 3.3V Extended & Idustrial 5V 3.3V mA ICC2 Standby Current: CMOS RAS, LCAS, UCAS > VCC 0.2V 5V 3.3V 1 0.5 mA ICC3 Operating Current: Random Read/Write(2,3,4) Average Power Supply Current RAS, LCAS, UCAS, Address Cycling, tRC = tRC (min.) -50 -60 160 145 mA ICC4 Operating Current: Fast Page Mode(2,3,4) Average Power Supply Current RAS = VIL, LCAS, UCAS, Cycling tPC = tPC (min.) -50 -60 90 80 mA ICC5 Refresh Current: RAS-Only(2,3) Average Power Supply Current RAS Cycling, LCAS, UCAS > VIH tRC = tRC (min.) -50 -60 160 145 mA ICC6 Refresh Current: RAS, LCAS, UCAS Cycling CBR(2,3,5) tRC = tRC (min.) Average Power Supply Current -50 -60 160 145 mA Notes: 1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded. 2. Dependent on cycle rates. 3. Specified values are obtained with minimum cycle time and the output open. 4. Column-address is changed once each Fast page cycle. 5. Enables on-chip refresh and address counters. 6 Integrated Circuit Solution Inc. DR005-0C IS41C16105 IS41LV16105 AC CHARACTERISTICS(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) Symbol tRC tRAC tCAC tAA tRAS tRP tCAS tCP tCSH tRCD tASR tRAH tASC tCAH tAR tRAD tRAL tRPC tRSH tRHCP tCLZ tCRP tOD tOE tOED tOEHC tOEP tOES tRCS tRRH tRCH tWCH tWCR tWP tWPZ tRWL tCWL tWCS tDHR Parameter Random READ or WRITE Cycle Time Access Time from RAS(6, 7) Access Time from CAS(6, 8, 15) Access Time from Column-Address(6) RAS Pulse Width RAS Precharge Time CAS Pulse Width(26) CAS Precharge Time(9, 25) CAS Hold Time (21) RAS to CAS Delay Time(10, 20) Row-Address Setup Time Row-Address Hold Time Column-Address Setup Time(20) Column-Address Hold Time(20) Column-Address Hold Time (referenced to RAS) RAS to Column-Address Delay Time(11) Column-Address to RAS Lead Time RAS to CAS Precharge Time RAS Hold Time(27) RAS Hold Time from CAS Precharge CAS to Output in Low-Z(15, 29) CAS to RAS Precharge Time(21) Output Disable Time(19, 28, 29) Output Enable Time(15, 16) Output Enable Data Delay (Write) OE HIGH Hold Time from CAS HIGH OE HIGH Pulse Width OE LOW to CAS HIGH Setup Time Read Command Setup Time(17, 20) Read Command Hold Time (referenced to RAS)(12) Read Command Hold Time (referenced to CAS)(12, 17, 21) Write Command Hold Time(17, 27) Write Command Hold Time (referenced to RAS)(17) Write Command Pulse Width(17) WE Pulse Widths to Disable Outputs Write Command to RAS Lead Time(17) Write Command to CAS Lead Time(17, 21) Write Command Setup Time(14, 17, 20) Data-in Hold Time (referenced to RAS) Integrated Circuit Solution Inc. DR005-0C -50 Max. Min. -60 Max. 84 50 30 8 9 38 12 0 8 0 8 30 50 13 25 10K 10K 37 104 60 40 10 9 40 14 0 10 0 10 40 60 15 30 10K 10K 45 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 25 5 8 37 0 5 3 20 5 10 5 0 0 25 15 13 12 30 5 10 37 0 5 3 20 5 10 5 0 0 30 15 15 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0 0 ns 8 40 10 50 ns ns 8 10 13 8 0 39 10 10 15 10 0 39 ns ns ns ns ns ns Min. Units 7 IS41C16105 IS41LV16105 AC CHARACTERISTICS (Continued)(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) Symbol tACH tOEH tDS tDH tRWC tRWD tCWD tAWD tPC tRASP tCPA tPRWC tCOH tOFF tWHZ tCLCH tCSR tCHR tORD tREF tT Parameter Column-Address Setup Time to CAS Precharge during WRITE Cycle OE Hold Time from WE during READ-MODIFY-WRITE cycle(18) Data-In Setup Time(15, 22) Data-In Hold Time(15, 22) READ-MODIFY-WRITE Cycle Time RAS to WE Delay Time during READ-MODIFY-WRITE Cycle(14) CAS to WE Delay Time(14, 20) Column-Address to WE Delay Time(14) Fast Page Mode READ or WRITE Cycle Time(24) RAS Pulse Width Access Time from CAS Precharge(15) READ-WRITE Cycle Time(24) Data Output Hold after CAS LOW Output Buffer Turn-Off Delay from CAS or RAS(13,15,19, 29) Output Disable Delay from WE Last CAS going LOW to First CAS returning HIGH(23) CAS Setup Time (CBR REFRESH)(30, 20) CAS Hold Time (CBR REFRESH)(30, 21) OE Setup Time prior to RAS during HIDDEN REFRESH Cycle Auto Refresh Period (1,024 Cycles) Transition Time (Rise or Fall)(2, 3) Min. -50 Max. Min. -60 Max. Units 15 15 ns 8 10 ns 0 8 108 64 0 10 133 77 ns ns ns ns 26 39 20 32 47 25 ns ns ns 50 56 5 1.6 100K 30 12 60 68 5 1.6 100K 35 15 ns ns ns ns ns 3 10 10 3 10 10 ns ns 5 8 0 5 10 0 ns ns ns 1 16 50 1 16 50 ms ns AC TEST CONDITIONS Output load: Two TTL Loads and 50 pF (Vcc = 5.0V ±10%) One TTL Load and 50 pF (Vcc = 3.3V ±10%) Input timing reference levels: VIH = 2.4V, VIL = 0.8V (Vcc = 5.0V ±10%); VIH = 2.0V, VIL = 0.8V (Vcc = 3.3V ±10%) Output timing reference levels: VOH = 2.0V, VOL = 0.8V (Vcc = 5V ±10%, 3.3V ±10%) 8 Integrated Circuit Solution Inc. DR005-0C IS41C16105 IS41LV16105 Notes: 1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded. 2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH and VIL (or between VIL and VIH) and assume to be 1 ns for all inputs. 3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 4. If CAS and RAS = VIH, data output is High-Z. 5. If CAS = VIL, data output may contain data from the last valid READ cycle. 6. Measured with a load equivalent to one TTL gate and 50 pF. 7. Assumes that tRCD < tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCD exceeds the value shown. 8. Assumes that tRCD > tRCD (MAX). 9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the data output buffer, CAS and RAS must be pulsed for tCP. 10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD is greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC. 11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD is greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA. 12. Either tRCH or tRRH must be satisfied for a READ cycle. 13. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. 14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS > tWCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD > tRWD (MIN), tAWD > tAWD (MIN) and tCWD > tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle. 15. Output parameter (I/O) is referenced to corresponding CAS input, I/O0-I/O7 by LCAS and I/O8-I/O15 by UCAS. 16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE WRITE or READ-MODIFY-WRITE is not possible. 17. Write command is defined as WE going low. 18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW and OE is taken back to LOW after tOEH is met. 19. The I/Os are in open during READ cycles once tOD or tOFF occur. 20. The first χCAS edge to transition LOW. 21. The last χCAS edge to transition HIGH. 22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READMODIFY-WRITE cycles. 23. Last falling χCAS edge to first rising χCAS edge. 24. Last rising χCAS edge to next cycles last rising χCAS edge. 25. Last rising χCAS edge to first falling χCAS edge. 26. Each χCAS must meet minimum pulse width. 27. Last χCAS to go LOW. 28. I/Os controlled, regardless UCAS and LCAS. 29. The 3 ns minimum is a parameter guaranteed by design. 30. Enables on-chip refresh and address counters. Integrated Circuit Solution Inc. DR005-0C 9 IS41C16105 IS41LV16105 READ CYCLE tRC tRAS tRP RAS tCSH tCRP tRSH tCAS tCLCH tRCD tRRH UCAS/LCAS tAR tRAD tASR ADDRESS tRAH tRAL tCAH tASC Row Column Row tRCS tRCH WE tAA tRAC tCAC tCLC I/O tOFF(1) Open Open Valid Data tOE tOD OE tOES Don’t Care Note: 1. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last. 10 Integrated Circuit Solution Inc. DR005-0C IS41C16105 IS41LV16105 READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles) tRWC tRAS tRP RAS tCSH tCRP tRSH tCAS tCLCH tRCD UCAS/LCAS tAR tRAD tRAH tASR tRAL tCAH tASC tACH ADDRESS Row Column Row tRWD tCWL tRWL tCWD tRCS tAWD tWP WE tAA tRAC tCAC tCLZ I/O tDS Open Valid DOUT tOE tOD tDH Valid DIN Open tOEH OE Don’t Care Integrated Circuit Solution Inc. DR005-0C 11 IS41C16105 IS41LV16105 EARLY WRITE CYCLE (OE = DON'T CARE) tRC tRAS tRP RAS tCSH tCRP tRSH tCAS tCLCH tRCD UCAS/LCAS tAR tRAD tASR ADDRESS tRAH tRAL tCAH tACH tASC Row Column Row tCWL tRWL tWCR tWCS tWCH tWP WE tDHR tDS I/O tDH Valid Data Don’t Care 12 Integrated Circuit Solution Inc. DR005-0C IS41C16105 IS41LV16105 FAST PAGE MODE READ CYCLE tRASP tRP RAS tPRWC tCAS tCSH tCAS tCRP tRCD tRSH tCAS tCP tCRP tCP UCAS/LCAS tAR tRAH tRAD tASC tASR ADDRESS tCPWD tRAL tCAH tCPWD Row tCAH tASC tAR Column tCAH Column tASC Column tRCS WE tAA tAA tCAC tAA tCAC tOE tCAC tOE tOE OE tRAC tOED tCLZ I/O tOED tCLZ OUT tOED tCLZ OUT OUT Don’t Care Integrated Circuit Solution Inc. DR005-0C 13 IS41C16105 IS41LV16105 FAST PAGE MODE READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles) tRASP tRP RAS tPRWC tCAS tCSH tCAS tCRP tRCD tRSH tCAS tCP tCRP tCP UCAS/LCAS tAR tRAH tRAD tASC tASR ADDRESS tCPWD tRAL tCAH tCPWD Row tCAH tAR Column tASC Column tCWL tRWD tAWD tCWD tRCS tCAH tASC Column tCWL tRWL tCWL tAWD tCWD tWP tAWD tCWD tWP tWP WE tAA tAA tCAC tAA tCAC tOE tCAC tOE tOE OE tOEZ tOED tRAC OUT IN tOEZ tOED tDH tDH tDS tCLZ tCLZ I/O0-I/O15 tOEZ tOED tDS OUT IN tDH tCLZ OUT tDS IN Don’t Care 14 Integrated Circuit Solution Inc. DR005-0C IS41C16105 IS41LV16105 FAST PAGE MODE EARLY WRITE CYCLE tRASP tRP RAS tCAS tCRP tRHCP tRSH tCAS tPC tCAS tCSH tRCD tCP tCRP tCP UCAS/LCAS tAR tRAL tRAD tRAH tASC tASR ADDRESS Row tCAH tCAH tAR Column tASC Column Column tCWL tWCS tWCH tCAH tASC tCWL tWCH tWCS tWCS tWP tCWL tWP tWCH tWP WE tWCR OE tDHR tDS tDH tDS Valid DIN I/O0-I/O15 tDH Valid DIN tDS tDH Valid DIN Don’t Care AC WAVEFORMS 4)5 4)5-ONLY REFRESH CYCLE (OE, WE = DON'T CARE) tRC tRAS tRP RAS tCRP tRPC UCAS/LCAS tASR ADDRESS I/O tRAH Row Row Open Don’t Care Integrated Circuit Solution Inc. DR005-0C 15 IS41C16105 IS41LV16105 +*4 REFRESH CYCLE (Addresses; WE, OE = DON'T CARE) tRP tRAS tRP tRAS RAS tCHR tRPC tCP tCHR tRPC tCSR tCSR UCAS/LCAS Open I/O HIDDEN REFRESH CYCLE(1) (WE = HIGH; OE = LOW) tRAS tRP tRAS RAS tCRP tRCD tASR tRAD tRAH tASC tRSH tCHR UCAS/LCAS tAR ADDRESS Row tRAL tCAH Column tAA tRAC tOFF(2) tCAC tCLZ I/O Open Valid Data tOE Open tOD tORD OE Don’t Care Notes: 1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH. 2. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last. 16 Integrated Circuit Solution Inc. DR005-0C IS41C16105 IS41LV16105 ORDERING INFORMATION: 3.3V Commercial Range: 0°C to 70°C Speed (ns) 50 60 Order Part No. Package IS41LV16105-50K IS41LV16105-50T IS41LV16105-60K IS41LV16105-60T 400mil SOJ 400mil TSOP-2 400mil SOJ 400mil TSOP-2 ORDERING INFORMATION: 3.3V Industrial Temperature Range: 40°C to 85°C Speed (ns) 50 60 Order Part No. Package IS41LV16105-50KI IS41LV16105-50TI IS41LV16105-60KI IS41LV16105-60TI 400mil SOJ 400mil TSOP-2 400mil SOJ 400mil TSOP-2 ORDERING INFORMATION: 5V Commercial Range: 0°C to 70°C Speed (ns) 50 60 Order Part No. Package IS41C16105-50K IS41C16105-50T IS41C16105-60K IS41C16105-60T 400mil SOJ 400mil TSOP-2 400mil SOJ 400mil TSOP-2 ORDERING INFORMATION: 5V Industrial Temperature Range: 40°C to 85°C Speed (ns) 50 60 Integrated Circuit Solution Inc. DR005-0C Order Part No. Package IS41C16105-50KI IS41C16105-50TI IS41C16105-60KI IS41C16105-60TI 400mil SOJ 400mil TSOP-2 400mil SOJ 400mil TSOP-2 17 IS41C16105 IS41LV16105 Integrated Circuit Solution Inc. HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw 18 Integrated Circuit Solution Inc. DR005-0C