CDC1104 SCAS921 – SEPTEMBER 2011 www.ti.com 1 to 4 Configurable Clock Buffer for 3D Displays Check for Samples: CDC1104 FEATURES 1 4 GND 5 S4 6 S1 S2 3 2 1 12 Top View 11 10 7 8 9 OE S3 CLKIN RVK PACKAGE (TOP VIEW) CLKOUT4 • Input Reference Clock 120Hz–240Hz Output Clock (Fin/2) 60Hz–120Hz Output Buffer Drive Strength: 8mA 4 Clock Outputs 4 Control Pins Select Phases of Clock Outputs Supply Voltage: 3.8V–5.5V Operating Temperature Range: –40°C to 85°C ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-B) – 500-V Charged-Device Model (C101) Package Offerings – 12-pin QFN (3mm x 3mm) CLKOUT3 • • • • • • • • CLKOUT1 VDD CLKOUT2 DESCRIPTION The CDC1104 is a 1 to 4 configurable clock buffer. The device accepts an input reference clock and creates 4 buffered output clocks with an output frequency equal to one half the input clock frequency. Four control inputs, S1, S2, S3, S4 configurable phases of the clock outputs. ORDERING INFORMATION (1) PACKAGE (2) TA –40°C to 85°C (1) (2) RVK Tape and reel ORDERABLE PART NUMBER TOP-SIDE MARKING CDC1104RVKR ZT For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated CDC1104 SCAS921 – SEPTEMBER 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. PIN FUNCTIONS NO. (1) NAME TYPE (1) DESCRIPTION 1 S2 I Output clock select. Refer to Output Clock Selection Table 2 S1 I Output clock select. Refer to Output Clock Selection Table 3 CLKIN I Clock Input 4 S3 I Output clock select. Refer to Output Clock Selection Table 5 GND P Ground 6 S4 I Not internally connected 7 CLKOUT3 O Buffered CLK Output. Refer to Output Clock Selection Table 8 CLKOUT4 O Buffered CLK Output. Refer to Output Clock Selection Table 9 OE I Chip Enable 10 CLKOUT2 O Buffered CLK Output. Refer to Output Clock Selection Table 11 VDD P Inverted output. No counter delay 12 CLKOUT1 O Buffered CLK Output. Refer to Output Clock Selection Table G = Ground, I = Input, O = Output, P = Power TRUTH TABLE INPUTS 2 OUTPUTS OE CLKIN S4 S3 S2 S1 CLKOUT4 CLKOUT3 CLKOUT2 CLKOUT1 0 CLK X X X X L L L L 1 CLK 0 0 0 0 L L L L 1 CLK 0 0 0 1 CLK\ CLK\ CLK\ CLK 1 CLK 0 0 1 0 CLK\ CLK\ CLK CLK\ 1 CLK 0 0 1 1 CLK\ CLK\ CLK CLK 1 CLK 0 1 0 0 CLK\ CLK CLK\ CLK\ 1 CLK 0 1 0 1 CLK\ CLK CLK\ CLK 1 CLK 0 1 1 0 CLK\ CLK CLK CLK\ 1 CLK 0 1 1 1 CLK\ CLK CLK CLK 1 CLK 1 0 0 0 CLK CLK\ CLK\ CLK\ 1 CLK 1 0 0 1 CLK CLK\ CLK\ CLK 1 CLK 1 0 1 0 CLK CLK\ CLK CLK\ 1 CLK 1 0 1 1 CLK CLK\ CLK CLK 1 CLK 1 1 0 0 CLK CLK CLK\ CLK\ 1 CLK 1 1 0 1 CLK CLK CLK\ CLK 1 CLK 1 1 1 0 CLK CLK CLK CLK\ 1 CLK 1 1 1 1 CLK CLK CLK CLK Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :CDC1104 CDC1104 SCAS921 – SEPTEMBER 2011 www.ti.com Timing Diagram For Glitch Free Operation Transition of outputs from any state to any other state S4=1, S3=1, S2=1, S1=0 Change Area S4=1, S3=1, S2=0, S1=1 Change Area S4=0, S3=0, S2=1, S1=1 OE CLKIN CLKOUT1 CLKOUT2 CLKOUT3 CLKOUT4 NOTE: Transition to new state will happen after a latency of one output clock cycle after completing the present output clock cycle. Transition to new state will happen after a latency of up to 3 input clock cycles excluding the input cycle where the transition has occurred. Power Up 10 μS (min) OE CLKIN CLKOUT Sx in any stable state Valid Clock according to Sx NOTE: Transition to new state will happen after a latency of 2 input clock cycles excluding the input cycle where the transition has occurred. OE Operation 10 μS (min) OE CLKIN CLKOUT Sx in any stable state Valid Clock according to Sx NOTE: Transition to new state will happen after a latency of 2 input clock cycles excluding the input cycle where the transition has occurred. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :CDC1104 3 CDC1104 SCAS921 – SEPTEMBER 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range –0.3 6 V VI Input voltage range (2) –0.3 6 V VO Output voltage range in the high or low state (2) –0.3 6 IIK Input clamp current VI < 0 ±20 mA IOK Output clamp current VO < 0 ±20 mA IOL Continuous output Low current VO = 0 to VCC ±20 mA IOH Continuous output High current VO = 0 to VCC ±20 mA Tstg Storage temperature range 150 °C (1) (2) –65 V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. THERMAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) θJA (1) Package thermal impedance (1) RVK Package VALUE UNIT 72.2 °C/W The package thermal impedance is calculated in accordance with JESD 51-7. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range 3.8 5.5 V VIH High-Level Input Voltage 1.6 5.5 V VIL Low-Level Input Voltage 0 0.8 V IIH High-level input current 1 µA IIL Low-level input current 1 µA VI 0 5.5 V VO 0 VCC V IOH High-level output current -8 mA IOL Low-level output current 8 mA TA Operating free-air temperature 85 °C 4 –40 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :CDC1104 CDC1104 SCAS921 – SEPTEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –8 mA VOH VOL IOL = 8 mA Ii (CLKIN, OE, Sx) VI = GND to 4 V ICC (Disabled) VIO = 0 V or 5.5V, OE = Low IDD_ (Dynamic) TA = –40°C to 85°C VCC MIN 3.8 V Vcc-0.6 5V Vcc-0.4 TYP MAX UNIT V V 3.8 V 0.40 5V 0.40 V 1 µA 5.5 V V 3.8 V to 5.5 V 0.5 2 µA OE = 5.5 V; Sx = 0 V, 5.5 V; CLKIN = 0 V, 5.5 V 5.5 V 20 50 µA OE = 3.0 V; Sx = 0 V, 3.0 V; CLKIN = 0 V, 3.0 V 5.5 V 20 50 µA OE = 1.6 V; Sx = 0 V, 1.6 V; CLKIN = 0 V, 1.6 V 5.5 V 20 50 µA CI (CLKIN, OE, Sx) VI = VCC or GND 7 pF SWITCHING CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER FCLKIN FCLKOUT FROM (INPUT) TO(OUTPUT) VCC Input clock frequency Output clock frequency TA = –40°C to 85°C MIN TYP MAX UNIT 120 240 Hz FCLKIN /2 FCLKIN /2 Hz tRISE / tFALL Output rise/fall time 10 µs tRISE / tFALL Input rise/fall time 50 µs Input Duty Cycle Input duty cycle 49% 50% 51% Output Duty Cycle Output duty cycle 49% 50% 5%1 tSU Setup time on Sx 60 tH Hold time on Sx 60 tSKEW CLKOUTx skew µs µs 10 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :CDC1104 µs 5 CDC1104 SCAS921 – SEPTEMBER 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION Propagation Delays From Output Under Test VCC = 3.3 V ± 0.3 V 2 kΩ CL (See Note A) CL VM VI 15 pF VCC/2 VCC VI VM VM Input 0V tPLH tPHL VOH VM Output VM VOL tPHL tPLH VOH Output VM VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NON INVERTING OUTPUTS 6 A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, for propagation delays tr/tf = 3 ns, for setup and hold times and pulse width tr/tf = 1.2 ns. D. The outputs are measured on at a time, with on transition per measurement. E. tPLH and tPHL are the same a tpd. F. All parameters and waveforms are no applicable to all devices. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :CDC1104 PACKAGE OPTION ADDENDUM www.ti.com 16-Nov-2011 PACKAGING INFORMATION Orderable Device CDC1104RVKR Status (1) ACTIVE Package Type Package Drawing WQFN RVK Pins Package Qty 12 3000 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) CU NIPDAU Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device CDC1104RVKR Package Package Pins Type Drawing WQFN RVK 12 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 3000 330.0 12.4 Pack Materials-Page 1 3.3 B0 (mm) K0 (mm) P1 (mm) 3.3 1.1 8.0 W Pin1 (mm) Quadrant 12.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDC1104RVKR WQFN RVK 12 3000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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