IRF IR3508ZMTRPBF Xphase3tm phase ic Datasheet

IR3508Z
DATA SHEET
XPHASE3TM PHASE IC
DESCRIPTION
TM
The IR3508Z Phase IC combined with any IR XPhase3 Control IC provides a full featured and flexible way
to implement a power solution for the latest high performance CPUs and ASICs. The “Control” IC provides
overall system control and interfaces with any number of “Phase” ICs which each drive and monitor a single
TM
phase of a multiphase converter. The XPhase3 architecture results in a power supply that is smaller, less
expensive, and easier to design while providing higher efficiency than conventional approaches.
The IR3508Z disables its current sense amplifiers when entering power savings mode. The recommended
use for these Phase ICs is for applications without adaptive voltage positioning where two or more power
stages will be operating in power savings mode.
FEATURES IR3508Z PHASE IC
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
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•
Power State Indicator (PSI) interface provides the capability to maximize the efficiency at light loads.
Anti-bias circuitry
7V/2A gate drivers (4A GATEL sink current)
Support converter output voltage up to 5.1 V (Limited to VCCL-1.4V)
Loss-less inductor current sensing
Phase delay DFF bypassed during PSI assertion mode to improve output ripple performance
Over-current protection during PSI assertion mode operation
Feed-forward voltage mode control
Integrated boot-strap synchronous PFET
Only four external components per phase
3 wire analog bus connects Control and Phase ICs (VID, Error Amp, IOUT)
3 wire digital bus for accurate daisy-chain phase timing control without external components
Debugging function isolates phase IC from the converter
Self-calibration of PWM ramp, current sense amplifier, and current share amplifier
Single-wire bidirectional average current sharing
Small thermally enhanced 20L 4 X 4mm MLPQ package
RoHS compliant
APPLICATION CIRCUIT
Figure 1 Application Circuit
Page 1 of 19
Jan 09, 2009
IR3508Z
ORDERING INFORMATION
Part Number
IR3508ZMTRPBF
Package
20 Lead MLPQ
(4 x 4 mm body)
20 Lead MLPQ
(4 x 4 mm body)
* IR3508ZMPBF
Order Quantity
3000 per reel
100 piece strips
* Samples only
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. These are stress ratings only and functional operation of the device, at these or any other
conditions, beyond those indicated in the operational sections of the specifications are not implied.
o
Operating Junction Temperature…………….. 0 to 150 C
o
o
Storage Temperature Range………………….-65 C to 150 C
MSL Rating………………………………………2
o
Reflow Temperature…………………………….260 C
PIN #
PIN NAME
VMAX
VMIN
ISOURCE
ISINK
1
2
3
4
5
6
IOUT
PSI
DACIN
LGND
PHSIN
NC
8V
8V
3.3V
n/a
8V
n/a
-0.3V
-0.3V
-0.3V
n/a
-0.3V
n/a
1mA
1mA
1mA
n/a
1mA
n/a
1mA
1mA
1mA
n/a
1mA
n/a
7
8
9
PHSOUT
CLKIN
PGND
8V
8V
0.3V
-0.3V
-0.3V
-0.3V
2mA
1mA
n/a
10
GATEL
8V
11
NC
n/a
-0.3V DC, -5V for
100ns
n/a
2mA
1mA
5A for 100ns,
200mA DC
5A for 100ns,
200mA DC
n/a
12
VCCL
8V
-0.3V
n/a
13
BOOST
40V
-0.3V
14
GATEH
40V
15
SW
34V
-0.3V DC, -5V for
100ns
-0.3V DC, -5V for
100ns
-0.3V
-0.3V
-0.3V
-0.3V
n/a
1A for 100ns,
100mA DC
3A for 100ns,
100mA DC
3A for 100ns,
100mA DC
n/a
1mA
1mA
1mA
n/a
16
VCC
34V
17
CSIN+
8V
18
CSIN8V
19
EAIN
8V
20
NC
n/a
Note:
1. Maximum GATEH – SW = 8V
2. Maximum BOOST – GATEH = 8V
Page 2 of 19
5A for 100ns,
200mA DC
n/a
5A for 100ns,
200mA DC
3A for 100ns,
100mA DC
3A for 100ns,
100mA DC
n/a
10mA
1mA
1mA
1mA
n/a
Jan 09, 2009
IR3508Z
RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN
o
o
8.0V ≤ VCC ≤ 28V, 4.75V ≤ VCCL ≤ 7.5V, 0 C ≤ TJ ≤ 125 C. 0.5V ≤ V(DACIN) ≤ 1.6V, 500kHz ≤ CLKIN ≤ 9MHz, 250kHz
≤ PHSIN ≤1.5MHz.
ELECTRICAL CHARACTERISTICS
The electrical characteristics table lists the parametric range guaranteed to be within the recommended operating
conditions. Typical values represent the median values, which are related to 25°C.
CGATEH = 3.3nF, CGATEL = 6.8nF (unless otherwise specified)
PARAMETER
Gate Drivers
GATEH Source Resistance
GATEH Sink Resistance
GATEL Source Resistance
GATEL Sink Resistance
GATEH Source Current
GATEH Sink Current
GATEL Source Current
GATEL Sink Current
GATEH Rise Time
GATEH Fall Time
GATEL Rise Time
GATEL Fall Time
GATEL low to GATEH high
delay
GATEH low to GATEL high
delay
Disable Pull-Down
Resistance
Clock
CLKIN Threshold
CLKIN Bias Current
CLKIN Phase Delay
PHSIN Threshold
PHSOUT Propagation
Delay
PHSIN Pull-Down
Resistance
PHSOUT High Voltage
PHSOUT Low Voltage
Page 3 of 19
TEST CONDITION
BOOST – SW = 7V. Note 1
BOOST – SW = 7V. Note 1
VCCL – PGND = 7V. Note 1
VCCL – PGND = 7V. Note 1
BOOST=7V, GATEH=2.5V, SW=0V.
BOOST=7V, GATEH=2.5V, SW=0V.
VCCL=7V, GATEL=2.5V, PGND=0V.
VCCL=7V, GATEL=2.5V, PGND=0V.
BOOST – SW = 7V, measure 1V to 4V
transition time
BOOST – SW = 7V, measure 4V to 1V
transition time
VCCL – PGND = 7V, Measure 1V to 4V
transition time
VCCL – PGND = 7V, Measure 4V to 1V
transition time
BOOST = VCCL = 7V, SW = PGND = 0V,
measure time from GATEL falling to 1V to
GATEH rising to 1V
BOOST = VCCL = 7V, SW = PGND = 0V,
measure time from GATEH falling to 1V to
GATEL rising to 1V
Note 1
Compare to V(VCCL)
CLKIN = V(VCCL)
Measure time from CLKIN<1V to GATEH>1V
Compare to V(VCCL)
Measure time from CLKIN > (VCCL * 50% )
to PHSOUT > (VCCL *50%). 10pF Load @
o
125 C
I(PHSOUT) = -10mA, measure VCCL –
PHSOUT
I(PHSOUT) = 10mA
MIN
TYP
MAX
UNIT
1.0
1.0
1.0
0.4
2.0
2.0
2.0
4.0
5
2.5
2.5
2.5
1.0
10
Ω
Ω
Ω
Ω
A
A
A
A
ns
5
10
ns
10
20
ns
5
10
ns
10
20
40
ns
10
20
40
ns
30
80
130
kΩ
40
-0.5
40
35
4
45
0.0
75
50
15
57
0.5
125
55
35
%
µA
ns
%
ns
30
100
170
kΩ
1
0.6
0.4
V
1
Jan 09, 2009
V
IR3508Z
PARAMETER
PWM Comparator
PWM Ramp Slope
EAIN Bias Current
Minimum Pulse Width
Current Sense Amplifier
CSIN+/- Bias Current
CSIN+/- Bias Current
Mismatch
Input Offset Voltage
Gain
Unity Gain Bandwidth
Slew Rate
Differential Input Range
Differential Input Range
Common Mode Input Range
o
Rout at TJ = 25 C
o
Rout at TJ = 125 C
IOUT Source Current
IOUT Sink Current
Share Adjust Amplifier
Input Offset Voltage
Gain
Unity Gain Bandwidth
PWM Ramp Floor Voltage
Maximum PWM Ramp Floor
Voltage
Minimum PWM Ramp Floor
Voltage
PSI Comparator
Rising Threshold Voltage
Falling Threshold Voltage
Hysteresis
Resistance
Floating Voltage
Page 4 of 19
TEST CONDITION
MIN
TYP
MAX
UNIT
Vin=12V
42
52.5
57
0 ≤ EAIN ≤ 3V
Note 1
-5
-0.3
55
5
70
mV/
%DC
µA
ns
-200
-50
0
0
200
50
nA
nA
-1
0
1
mV
30.0
4.8
32.5
6.8
35.0
8.8
V/V
MHz
V/µs
mV
mV
V
kΩ
kΩ
mA
mA
Note 1
CSIN+ = CSIN- = DACIN. Measure
input referred offset from DACIN
0.5V ≤ V(DACIN) < 1.6V
C(IOUT)=10pF. Measure at IOUT.
Note 1
6
0.8V ≤ V(DACIN) ≤ 1.6V, Note 1
0.5V ≤ V(DACIN) < 0.8V, Note 1
Note 1
Note 1
-10
-5
0
2.3
3.6
0.5
0.5
3.0
4.7
1.6
1.4
50
50
Note2
3.7
5.4
2.9
2.9
Note 1
CSIN+ = CSIN- = DACIN. Note 1
Note 1
IOUT Open, Measure relative to DACIN
IOUT = DACIN – 200mV. Measure
relative to floor voltage.
IOUT = DACIN + 200mV. Measure
relative to floor voltage.
-3
4
4
-116
120
0
5.0
8.5
0
180
3
6
17
116
240
mV
V/V
kHz
mV
mV
-220
-160
-100
mV
Note 1
Note 1
Note 1
520
400
50
200
800
620
550
70
500
700
650
120
850
1150
mV
mV
mV
kΩ
mV
Jan 09, 2009
IR3508Z
PARAMETER
Body Brake Comparator
Threshold Voltage with EAIN
decreasing
Threshold Voltage with EAIN
increasing
Hysteresis
Propagation Delay
TEST CONDITION
MIN
TYP
MAX
UNIT
Measure relative to Floor Voltage
-300
-200
-110
mV
Measure relative to Floor Voltage
-200
-100
-10
mV
70
40
105
65
130
90
mV
ns
-1.0
-0.8
-0.4
V
15
40
70
ns
66
75
86
%
-16
100
0
200
16
400
mV
ns
360
520
960
mV
-250
-150
-50
mV
1.1
1.1
3.1
0.5
-1.5
0.1
4.0
2.0
8.0
1.5
-0.75
0.3
6.1
4
12.1
3
1
0.4
mA
mA
mA
mA
VCCL = 5V. Measure time from EAIN <
V(DACIN) (200mV overdrive) to GATEL
transition to < 4V.
OVP Comparator
OVP Threshold
Step V(IOUT) up until GATEL drives
high. Compare to V(VCCL)
Propagation Delay
V(VCCL)=5V, Step V(IOUT) up from
V(DACIN) to V(VCCL). Measure time to
V(GATEL)>4V.
Synchronous Rectification Disable Comparator
Threshold Voltage
The ratio of V(CSIN-) / V(DACIN), below
which V(GATEL) is always low.
Negative Current Comparator
Input Offset Voltage
Note1
Propagation Delay Time
Apply step voltage to V(CSIN+) –
V(CSIN-). Measure time to V(GATEL)<
1V.
Bootstrap Diode
Forward Voltage
I(BOOST) = 30mA, VCCL = 6.8V
Debug Comparator
Threshold Voltage
Compare to V(VCCL)
General
VCC Supply Current
8V ≤ V(VCC) < 10V
VCC Supply Current
10V ≤ V(VCC) ≤ 16V
VCCL Supply Current
BOOST Supply Current
4.75V ≤ V(BOOST)-V(SW )≤ 8V
DACIN Bias Current
SW Floating Voltage
Note 1: Guaranteed by design, but not tested in production
Note 2: VCCL-0.5V or VCC – 2.5V, whichever is lower
Page 5 of 19
Jan 09, 2009
µA
V
IR3508Z
PIN DESCRIPTION
PIN#
1
PIN SYMBOL
IOUT
2
3
PSI
DACIN
4
5
LGND
PHSIN
6
7
8
9
10
11
12
NC
PHSOUT
CLKIN
PGND
GATEL
NC
VCCL
13
BOOST
14
15
16
17
18
GATEH
SW
VCC
CSIN+
CSIN-
19
EAIN
20
NC
Page 6 of 19
PIN DESCRIPTION
Output of the Current Sense Amplifier is connected to this pin through a 3kΩ
resistor. Voltage on this pin is equal to V(DACIN) + 33 [V(CSIN+) – V(CSIN-)].
Connecting all IOUT pins together creates a share bus which provides an indication
of the average current being supplied by all the phases. The signal is used by the
Control IC for voltage positioning and over-current protection. OVP mode is initiated
if the voltage on this pin rises above V(VCCL)- 0.8V.
Logic low is an active low (i.e. low = low power state).
Reference voltage input from the Control IC. The Current Sense signal and PWM
ramp is referenced to the voltage on this pin.
Ground for internal IC circuits. IC substrate is connected to this pin.
Phase clock input.
No connection.
Phase clock output.
Clock input.
Return for low side driver and reference for GATEH non-overlap comparator.
Low-side driver output and input to GATEH non-overlap comparator.
No connection.
Supply for low-side driver. Internal bootstrap synchronous PFET is connected from
this pin to the BOOST pin.
Supply for high-side driver. Internal bootstrap synchronous PFET is connected
between this pin and the VCCL pin.
High-side driver output and input to GATEL non-overlap comparator.
Return for high-side driver and reference for GATEL non-overlap comparator.
Supply for internal IC circuits.
Non-Inverting input to the current sense amplifier, and input to debug comparator.
Inverting input to the current sense amplifier, and input to synchronous rectification
disable comparator.
PWM comparator input from the error amplifier output of Control IC. Body Braking
mode is initiated if the voltage on this pin is less than V(DACIN).
No connection.
Jan 09, 2009
IR3508Z
SYSTEM THEORY OF OPERATION
System Description
The system consists of one control IC and a scalable array of phase converters, each requiring one phase IC. The
control IC communicates with the phase ICs using three digital buses, i.e., CLOCK, PHSIN, PHSOUT and three analog
buses, i.e., DAC, EA, and IOUT. The digital buses are responsible for switching frequency determination and accurate
phase timing control without any external components. The analog buses are used for PWM control and current sharing
between interleaved phases. The control IC incorporates all the system functions, i.e., VID, CLOCK signals, error
amplifier, fault protections, current monitor, etc. The Phase IC implements the functions required by the converter of
each phase, i.e., the gate drivers, PWM comparator and latch, over-voltage protection, phase disable circuit, current
sensing and sharing, etc.
PWM Control Method
TM
The PWM block diagram of the XPhase3 architecture is shown in Figure 1. Feed-forward voltage mode control with
trailing edge modulation is used. A high-gain and wide-bandwidth voltage type error amplifier is implemented in the
controller’s design to achieve a fast voltage control loop. Input voltage is sensed by the phase ICs to provide feedforward control. The feed-forward control compensates the ramp slope based on the change in input voltage. The input
voltage can change due to variations in the silver box output voltage or due to the wire and PCB-trace voltage drop
related to changes in load current.
GATE DRIVE
VOLTAGE
CONTROL IC
VIN
PHSOUT
PHASE IC
CLOCK GENERATOR
CLKOUT
VCC
CLKIN
CLK Q
VCCH
D
PHSOUT
1
PHSIN
2
D
PWM
COMPARATOR
CBST
SW
OFF
CLK Q
VOUT
COUT
-
EAIN
VCCL
DFFRH
+
GND
PWM LATCH
GATEL
ENABLE
+
+
VID6
-
REMOTE SENSE
AMPLIFIER
BODY
BRAKING
COMPARATOR
VID6
-
PSI
PSI
SHARE ADJUST
ERROR AMPLIFIER
-
LGND
EAOUT
IOUT
CURRENT
SENSE
AMPLIFIER
VID6
VID6
-
+
RFB1
RFB
+
CCOMP
FB
RVSETPT
IROSC
CFB
CCS
RCS
CSIN-
DACIN
RDRP1
PHSOUT
PHASE IC
RDRP
VSETPT
IVSETPT
CSIN+
+
VID6
VID6 +
-
+
-
3K
RCOMP
ERROR
AMPLIFIER
-
VDAC
+
+
VOSNS-
-
VDAC
CDRP
IMON
VCC
CLK Q
CLKIN
D
VDAC
1
2
VCCH
RESET
DOMINANT
U248
PHSIN
GATEH
D
VDRP
VN
PWM
COMPARATOR
EAIN
CBST
Q
VID6
CLK Q
R
Thermal
Compensation
+
VDRP
AMP
PGND
OFF
+
RAMP
DISCHARGE
CLAMP
VO
VOSNS+
VID6
Q
R
PHSIN
GATEH
RESET
DOMINANT
SW
OFF
-
DFFRH
+
VCCL
PWM LATCH
-
RTHRM
ENABLE
IIN
+
VID6
-
RAMP
DISCHARGE
CLAMP
GATEL
BODY
BRAKING
COMPARATOR
VID6
PGND
OFF
-
+
PSI
PSI
SHARE ADJUST
ERROR AMPLIFIER
CURRENT
SENSE
AMPLIFIER
+
-
VID6
VID6
+
CSIN+
VID6
VID6 +
+
DACIN
CCS
RCS
-
-
3K
+
ISHARE
CSIN-
Figure 1: PWM Block Diagram
Page 7 of 19
Jan 09, 2009
IR3508Z
Frequency and Phase Timing Control
The oscillator is located in the Control IC and the system clock frequency is programmable from 250kHz to 9MHZ by an
external resistor. The control IC system clock signal (CLKOUT) is connected to CLKIN of all the phase ICs. The phase
timing of the phase ICs is controlled by the daisy chain loop, where the control IC phase clock output (PHSOUT) is
connected to the phase clock input (PHSIN) of the first phase IC, and PHSOUT of the first phase IC is connected to
PHSIN of the second phase IC, etc. The last phase IC is connected back to PHSIN of the control IC to complete the
daisy chain loop. During power up, the control IC sends out clock signals from both CLKOUT and PHSOUT pins and
detects the feedback at PHSIN pin to determine the phase number and monitor any fault in the daisy chain loop. When
the PSI is asserted (active low), the phases are effectively removed from the daisy chain loop. Figure 2 shows the
phase timing for a four phase converter. The switching frequency is set by the resistor ROSC. The clock frequency
equals the number of phase times the switching frequency.
Control IC CLKOUT
(Phase IC CLKIN)
Control IC PHSOUT
(Phase IC1 PHSIN)
Phase IC1
PWM Latch SET
Phase IC 1 PHSOUT
(Phase IC2 PHSIN)
Phase IC 2 PHSOUT
(Phase IC3 PHSIN)
Phase IC 3 PHSOUT
(Phase IC4 PHSIN)
Phase IC4 PHSOUT
(Control IC PHSIN)
Figure 2: Four Phase Oscillator Waveforms
PWM Operation
The PWM comparator is located in the phase IC. Upon receiving the falling edge of a clock pulse, the PWM latch is set
and the PWM ramp voltage begins to increase. In addition, the low side driver is turned off and the high side driver is
turned on after the non-overlap time expires (GATEL < 1V). When the PWM ramp voltage exceeds the error amplifier’s
output voltage, the PWM latch is reset and the internal ramp capacitor is quickly discharged to the output of the share
adjust amplifier and remains discharged until the next clock pulse. This reset latch additionally turns off the high side
driver and enables the low side driver after the non-overlap time concludes (Switch Node < 1V).
The PWM latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in
response to a load step decrease. Phases can overlap and go up to 100% duty cycle in response to a load step
increase with turn-on gated by the clock pulses. An error amplifier output voltage greater than the common mode input
range, of the PWM comparator, results in 100% duty cycle regardless of the voltage of the PWM ramp. This
arrangement guarantees that the error amplifier is always in control and can demand 0 to 100% duty cycle as required.
It also favors response to a load step decrease, which is appropriate, given that the low output to input voltage ratio of
most systems. The inductor current will increase much more rapidly than decrease in response to load transients.
This control method is designed to provide “single cycle transient response.” The inductor current will change in
response to load transients within a single switching cycle maximizing the effectiveness of the power train and
minimizing the output capacitor requirements. An additional advantage of the architecture is that differences in ground
or input voltage, at the phases, have no effect on operation since the PWM ramps are referenced to VDAC.
Figure 3 depicts PWM operating waveforms under various conditions.
Page 8 of 19
Jan 09, 2009
IR3508Z
PHASE IC
CLOCK
PULSE
EAIN
PWMRMP
VDAC
GATEH
GATEL
STEADY-STATE
OPERATION
DUTY CYCLE INCREASE
DUE TO LOAD
INCREASE
DUTY CYCLE DECREASE
DUE TO VIN INCREASE
(FEED-FORWARD)
DUTY CYCLE DECREASE DUE TO LOAD
DECREASE (BODY BRAKING) OR FAULT
(VCCLUV, OCP, VID=11111X)
STEADY-STATE
OPERATION
Figure 3: PWM Operating Waveforms
Body Braking
TM
In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in
response to a load step decrease is;
TSLEW =
L * ( I MAX − I MIN )
VO
The slew rate of the inductor current can be significantly increased by turning off the synchronous rectifier in response
to a load step decrease. The switch node voltage is then forced to decrease until conduction of the synchronous
rectifier’s body diode occurs. This increases the voltage across the inductor from Vout to Vout + VBODYDIODE. The
minimum time required to reduce the current in the inductor in response to a load transient decrease is now;
TSLEW =
L * ( I MAX − I MIN )
VO + VBODYDIODE
Since the voltage drop in the body diode is often comparable to the output voltage, the inductor current slew rate can be
increased significantly. This patented technique is referred to as “body braking” and is accomplished through the “body
braking comparator” located in the phase IC. If the error amplifier’s output voltage drops below the output voltage of the
share adjust amplifier in the phase IC, this comparator turns off the low side gate driver.
Lossless Average Inductor Current Sensing
Inductor current can be sensed by connecting a series resistor and a capacitor network in parallel with the inductor and
measuring the voltage across the capacitor, as shown in Figure 4. The equation of the sensing network is,
vC ( s ) = vL ( s )
Page 9 of 19
1
RL + sL
= iL ( s )
1 + sRCS CCS
1 + sRCS CCS
Jan 09, 2009
IR3508Z
Usually the resistor Rcs and capacitor Ccs are chosen so that the time constant of Rcs and Ccs equals the time
constant of the inductor which is the inductance L over the inductor DCR (RL). If the two time constants match, the
voltage across Ccs is proportional to the current through L, and the sense circuit can be treated as if only a sense
resistor with the value of RL was used. The mismatch of the time constants does not affect the measurement of inductor
DC current, but affects the AC component of the inductor current.
vL
iL
Current
Sense Amp
L
RL
RCS
CCS
VO
CO
c
vCS
CSOUT
Figure 4: Inductor Current Sensing and Current Sense Amplifier
The advantage of sensing the inductor current versus high side or low side sensing is that actual output current being
delivered to the load is obtained rather than peak or sampled information about the switch currents. The output voltage
can be positioned to meet a load line based on real time information. Except for a sense resistor in series with the
inductor, this is the only sense method that can support a single cycle transient response. Other methods provide no
information during either load increase (low side sensing) or load decrease (high side sensing).
An additional problem associated with peak or valley current mode control for voltage positioning is that they suffer from
peak-to-average errors. These errors will show in many ways but one example is the effect of frequency variation. If the
frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and the output impedance
of the converter will drop by about 10%. Variations in inductance, current sense amplifier bandwidth, PWM prop delay,
any added slope compensation, input voltage, and output voltage are all additional sources of peak-to-average errors.
Current Sense Amplifier
A high speed differential current sense amplifier is located in the phase IC, as shown in Figure 4. Its gain is nominally
32.5, and the 3850 ppm/ºC increase in inductor DCR should be compensated in the voltage loop feedback path.
The current sense amplifier can accept positive differential input up to 50mV and negative up to -10mV before clipping.
The output of the current sense amplifier is summed with the DAC voltage and sent to the control IC and other phases
through an on-chip 3KΩ resistor connected to the IOUT pin. The IOUT pins of all the phases are tied together and the
voltage on the share bus represents the average current through all the inductors and is used by the control IC for
voltage positioning and current limit protection. The input offset of this amplifier is calibrated to +/- 1mV in order to
reduce the current sense error.
The input offset voltage is the primary source of error for the current share loop. In order to achieve very small input
offset error and superior current sharing performance, the current sense amplifier continuously calibrates itself. This
calibration algorithm creates ripple on IOUT bus with a frequency of fsw/896 in a multiphase architecture.
Average Current Share Loop
Current sharing between phases of the converter is achieved by the average current share loop in each phase IC. The
output of the current sense amplifier is compared with the average current at the share bus. If current in a phase is
smaller than the average current, the share adjust amplifier of the phase will pull down the starting point of the PWM
ramp thereby increasing its duty cycle and output current; if current in a phase is larger than the average current, the
share adjust amplifier of the phase will pull up the starting point of the PWM ramp thereby decreasing its duty cycle and
output current. The current share amplifier is internally compensated so that the crossover frequency of the current
Page 10 of 19
Jan 09, 2009
IR3508Z
share loop is much slower than that of the voltage loop and the two loops do not interact. For proper current sharing the
output of current sense amplifier should not exceed (VCCL-1.4V) under all operating condition.
IR3508Z THEORY OF OPERATION
Block Diagram
The Block diagram of the IR3508Z is shown in Figure 5, and specific features are discussed in the following
sections.
PSI_SY NC
PHSOUT
CLKIN
CLK Q
.
.
D
.
PHSIN
PHASE DELAY DFF
D
CLK Q
PWM LATCH
PWM COMPARATOR
-
PWMQ
U183
D
Q
PWM_CLK
R
CLK Q
RESET
DOMINANT
GATEH NONGATEH NONOVERLAP
OVERLAP
LATCH
COMPARATOR
DFFRSH
Q
VCCL
RMPOUT
VCC
ANTI-BIAS
LATCH
PWM RAMP
GENERATOR
VCC
Q
R
CLK
Q
PSI_SY NC
BODY BRAKING
COMPARATOR
+
1V
GATEL NONOVERLAP
COMPARATOR
1V
GATEL NONOVERLAP
LATCH
D
CALIBRATION
DACIN-SHARE_ADJ
SW
-
S
SET R
DOMINANT
PWM RESET
PHSIN
GATEH
.
S
SET R
DOMINANT
-
+
BOOST
GATEH
DRIVER
.
.
.
.
+
EAIN
EAIN
EAIN
VCCL
GATEL
PGND
-
0.8V
Q
+
RESET
DOMINANT
DEBUG OFF
(LOW=OPEN)
IOUT
VCCL
PSI_SYNC
SHARE
ADJUST
AMPLIFIER
R
0.15V
SYNCHRONOUS RECTIFICATION
DISABLE COMPARATOR
S
-
NEGATIVE CURRENT
COMPARATOR
3K
CURRENT SENSE
AMPLIFIER
+
-
CSAOUT
+
IROSC
+
+
-
+
CALIBRATION
DACIN
DACIN
X
0.75
-
SHARE_ADJ
NEGATIVE
CURRENT
LATCH
+
DACIN +
GATEL
DRIVER
+
100mV
200mV
OVP
COMPARATOR
DEBUG
COMPARATOR
CSIN-
X32.5
+
CSIN+
CALIBRATION
LGND
1V
PSI_SY NC
D
R
CLK
VCCL
8CLK
Q
D
CLK
R
Q
PSI
COMPARATOR
VCCL
IROSC
PHSIN
(CLKIN for 1-PHASE)
-
500K
PSI
+
610mV
510mV
Figure 5: Block diagram
Tri-State Gate Drivers
The gate drivers are design to provide a 2A source and sink peak current (Bottom gate driver can sink 4A). An
adaptive non-overlap circuit monitors the voltage on the GATEH and GATEL pins to prevent MOSFET shootthrough current and minimizing body diode conduction. The non-overlap latch is added to eliminate erroneous
triggering caused by the switching noise. A fault condition is communicated to the phase IC via the control IC’s error
amplifier without an additional dedicated signal line. The error amplifier’s output is driven low in response to any
fault condition detected by the controller, such as VCCL under voltage or output overload, disabling the phase IC
TM
TM
and activating Body Braking . The IR3508Z Body Braking comparator detects the low signal at the EAIN and
drives the bottom gate output low. This tri-state operation prevents negative inductor current and negative output
voltage during power-down.
Page 11 of 19
Jan 09, 2009
IR3508Z
A synchronous rectification disable comparator is used to detect the converter’s CSIN- pin voltage, which
represents local converter output voltage. If the voltage is below 75% of VDAC and negative current is detected,
GATEL is driven low, which disables synchronous rectification and eliminates negative current during power-up.
The gate drivers are pulled low if the supply voltage falls below the normal operating range. An 80kΩ resistor is
connected across the GATEH/GATEL and PGND pins to prevent the GATEH/GATEL voltage from rising due to
leakage or other causes under these conditions.
PWM Ramp
Every time the phase IC is powered up, the PWM ramp magnitude is calibrated to generate a 52.5 mV/% ramp
(VCC=12V). For example, a 15 % duty ratio will generate a ramp amplitude of 787.5 mV (15 x 52.5 mV) with 12V
supply applied to VCC. Feed-forward control is achieved by varying the PWM ramp proportionally with VCC
voltage after calibration.
Power State Indicator (PSI) function
From a system perspective, the PSI input is controlled by the system and is forced low when the load current is
lower than a preset limit and forced high when load current is higher than the preset limit. IR3508Z can accept an
active low signal on its PSI input and force the drivers into tri-state, effectively, forcing the phase IC into an off
state. A PSI-assert signal activates three features in the Phase IC. First, it disconnects the IOUT pin from the
ISHARE bus (from a system perspective). ISHARE is used to report current and is used for over-current
protection. By disconnecting the disabled phase from the ISHARE bus, proper current reporting and over-current
protection level are ensured. Secondly, the D Flip-Flop (DFF) is disabled, bypassing the Phase IC from the daisy
chain loop. By removing the DFF from the daisy chain, the system ensures that proper phase delay is activated
among the active phases. Finally, the gate drivers are forced to tri-state, disabling the phase IC from the power
stage. Figure 6 shows the impact of PSI-assert on the gate drivers. After an 8 cycle PHSIN delay followed by a
CLK falling edge, the PSI_SYNC goes from 0 to 1. This disables the gate drives and the DFF.
PSI
8 PHSIN Delay
CLK
PSI_SYNC
D_PWM LATCH
Figure 6: PSI assertion.
Debugging Mode
If the CSIN+ pin is pulled up to VCCL voltage, IR3508Z enters into debugging mode. Both drivers are pulled low
and IOUT output is disconnected from the current share bus, which isolates this phase IC from other phases.
However, the phase timing from PHSIN to PHSOUT does not change.
Page 12 of 19
Jan 09, 2009
IR3508Z
Emulated Bootstrap Diode
IR3508Z integrates a PFET to emulate the bootstrap diode. If two or more top MOSFETs are to be driven at higher
switching frequency, an external bootstrap diode connected from VCCL pin to BOOST pin may be needed.
Over Voltage Protection (OVP)
The IR3508Z includes over-voltage protection that turns on the low side MOSFET to protect the load in the event of
a shorted high-side MOSFET, converter out of regulation, or connection of the converter output to an excessive
output voltage. As shown in Figure 7, if IOUT pin voltage is above V(VCCL) – 0.8V, which represents over-voltage
condition detected by control IC, the over-voltage latch is set. GATEL drives high and GATEH drives low. The OVP
circuit overrides the normal PWM operation and within approximately 150ns will fully turn-on the low side MOSFET,
which remains in conduction until IOUT drops below V(VCCL) – 0.8V when over voltage ends. The over voltage
fault is latched in control IC and can only be reset by cycling the power to control IC. The error amplifier output
(EAIN) is pulled down by control IC and will remain low. The lower MOSFETs alone can not clamp the output
voltage however a SCR or N-MOSFET could be triggered with the OVP output to prevent processor damage.
OUTPUT
VOLTAGE
(VO)
OVP
THRESHOLD
130mV
VCCL-800 mV
IOUT(ISHARE)
GATEH
(PHASE IC)
GATEL
(PHASE IC)
FAULT
LATCH
ERROR
AMPLIFIER
OUTPUT
(EAOUT)
VDAC
NORMAL OPERATION
OVP CONDITION
AFTER
OVP
Figure 7: Over-voltage protection waveforms
Operation at Higher Output Voltage
The proper operation of the phase IC is ensured for output voltage up to 5.1V. Similarly, the minimum VCC for
proper operation of the phase IC is 8 V. Operating below this minimum voltage, the current sharing performance of
the phase IC is affected.
Page 13 of 19
Jan 09, 2009
IR3508Z
DESIGN PROCEDURES - IR3508Z
Inductor Current Sensing Capacitor CCS and Resistor RCS
The DC resistance of the inductor is utilized to sense the inductor current. Usually the resistor RCS and capacitor CCS
in parallel with the inductor are chosen to match the time constant of the inductor, and therefore the voltage across
the capacitor CCS represents the inductor current. If the two time constants are not the same, the AC component of
the capacitor voltage is different from that of the real inductor current. The time constant mismatch does not affect the
average current sharing among the multiple phases, but does affect the current signal IOUT as well as the output
voltage during a load current transient if adaptive voltage positioning is being implemented.
Measure the inductance L and the inductor DC resistance RL. Pre-select the capacitor CCS and calculate RCS as
follows.
L RL
(1)
RCS =
C CS
Bootstrap Capacitor CBST
Depending on the duty cycle and gate drive current of the phase IC, a capacitor in the range of 0.1uF to 1uF is
needed for the bootstrap circuit.
Decoupling Capacitors for Phase IC
A 0.1uF-1uF decoupling capacitor is required at the VCCL pin.
CURRENT SHARE LOOP COMPENSATION
The internal compensation of current share loop ensures that crossover frequency of the current share loop is at least
one decade lower than that of the voltage loop so that the interaction between the two loops is eliminated. The
crossover frequency of current share loop is approximately 8 kHz.
Page 14 of 19
Jan 09, 2009
IR3508Z
LAYOUT GUIDELINES
The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB
layout; therefore, minimizing the noise coupled to the IC.
• Dedicate at least one middle layer for a ground plane, which is then split into signal ground plane (LGND) and
power ground plane (PGND).
• Separate analog bus (EAIN, DACIN, and IOUT) from digital bus (CLKIN, PSI, PHSIN, and PHSOUT) to reduce
the noise coupling.
• Connect PGND to LGND pins of each phase IC to the ground tab, which is tied to LGND and PGND planes
respectively through vias.
• Place current sense resistors and capacitors (RCS and CCS) close to phase IC. Use Kelvin connection for the
inductor current sense wires, but separate the two wires by ground polygon. The wire from the inductor
terminal to CSIN- should not cross over the fast transition nodes, i.e., switching nodes, gate drive outputs, and
bootstrap nodes.
• Place the decoupling capacitors CVCC and CVCCL as close as possible to VCC and VCCL pins of the phase IC
respectively.
• Place the phase IC as close as possible to the MOSFETs to reduce the parasitic resistance and inductance of
the gate drive paths.
• Place the input ceramic capacitors close to the drain of top MOSFET and the source of bottom MOSFET. Use
combination of different packages of ceramic capacitors.
• There are two switching power loops. One loop includes the input capacitors, top MOSFET, inductor, output
capacitors and the load; another loop consists of bottom MOSFET, inductor, output capacitors and the load.
Route the switching power paths using wide and short traces or polygons; use multiple vias for connections
between layers.
To Digital Bus
To Analog Bus
To Gate
Drive
Voltage
LGND
PLANE
IOUT
PSI
DACIN
LGND
PHSIN
To VIN
NC
NC
PHSOUT
CLKIN
CSIN CSIN+
Rcs
SW
GATEH
BOOST
VCC
VCCL
GATEL
NC
Cvccl
PGND
Ccs
EAIN
PGND
PLANE
Page 15 of 19
Cbst
Dbst
To Bottom
MOSFET
To Switching
Node
To Top
MOSFET
To LGND
Plane
Ground
Polygon
To Inductor Sense
Jan 09, 2009
IR3508Z
PCB Metal and Component Placement
• Lead land width should be equal to nominal part lead width. The minimum lead to lead spacing should be ≥
0.2mm to minimize shorting.
• Lead land length should be equal to maximum part lead length + 0.3 mm outboard extension + 0.05mm
inboard extension. The outboard extension ensures a large and inspectable toe fillet, and the inboard
extension will accommodate any part misalignment and ensure a fillet.
• Center pad land length and width should be equal to maximum part pad length and width. However, the
minimum metal to metal spacing should be ≥ 0.17mm for 2 oz. Copper (≥ 0.1mm for 1 oz. Copper and ≥
0.23mm for 3 oz. Copper)
• Four 0.3mm diameter vias shall be placed in the pad land spaced at 1.2mm, and connected to ground to
minimize the noise effect on the IC and to transfer heat to the PCB.
• No PCB traces should be routed nor vias placed under any of the 4 corners of the IC package. Doing so can
cause the IC to rise up from the PCB resulting in poor solder joints to the IC leads.
Page 16 of 19
Jan 09, 2009
IR3508Z
Solder Resist
• The solder resist should be pulled away from the metal lead lands and center pad by a minimum of 0.06mm.
The solder resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all
Non Solder Mask Defined (NSMD). Therefore, pulling the S/R 0.06mm will always ensure NSMD pads.
• The minimum solder resist width is 0.13mm. At the inside corner of the solder resist where the lead land
groups meet, it is recommended to provide a fillet so a solder resist width of ≥ 0.17mm remains.
• Ensure that the solder resist in-between the lead lands and the pad land is ≥ 0.15mm due to the high aspect
ratio of the solder resist strip separating the lead lands from the pad land.
• The 4 vias in the land pad should be tented with solder resist 0.4mm diameter, or 0.1mm larger than the
diameter of the via.
Page 17 of 19
Jan 09, 2009
IR3508Z
Stencil Design
• The stencil apertures for the lead lands should be approximately 80% of the area of the lead lands.
Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for 0.5mm pitch
devices the leads are only 0.25mm wide, the stencil apertures should not be made narrower; openings in
stencils < 0.25mm wide are difficult to maintain repeatable solder release.
• The stencil lead land apertures should therefore be shortened in length by 80% and centered on the lead
land.
• The land pad aperture should be striped with 0.25mm wide openings and spaces to deposit approximately
50% area of solder on the center pad. If too much solder is deposited on the center pad the part will float
and the lead lands will be open.
• The maximum length and width of the land pad stencil aperture should be equal to the solder resist opening
minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the lead lands
when the part is pushed into the solder paste.
Page 18 of 19
Jan 09, 2009
IR3508Z
PACKAGE INFORMATION
o
o
20L MLPQ (4 x 4 mm Body) – θJA = 32 C/W, θJC = 3 C/W
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.
Page 19 of 19
Jan 09, 2009
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