TI1 CD4051BQPWRQ1 Cmos analog multiplexers/demultiplexer Datasheet

CD4051B-Q1, CD4052B-Q1, CD4053B-Q1
CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS
WITH LOGIC−LEVEL CONVERSION
SCHS354A − AUGUST 2004 − REVISED JANUARY 2008
D Very Low Quiescent Power Dissipation
Features
D Qualified for Automotive Applications
D Wide Range of Digital and Analog Signal
D
D
D
D
Levels
− Digital: 3 V to 20 V
− Analog: 3 20 VP-P
Low ON Resistance, 125 Ω (Typ) Over
15 VP-P Signal Input Range
for VDD − VEE = 18 V
High OFF Resistance, Channel Leakage of
+100 pA (Typ) at VDD − VEE = 18 V
Logic-Level Conversion for Digital
Addressing Signals of 3 V to 20 V
(VDD − VSS = 3 V to 20 V) to Switch Analog
Signals to 20 VP-P (VDD − VEE = 20 V)
Matched Switching Characteristics,
ron = 5 Ω (Typ) for VDD − VEE = 15 V
D
D
D
D
D
Under All Digital-Control Input and Supply
Conditions, 0.2 µW (Typ)
at VDD − VSS = VDD − VEE = 10 V
Binary Address Decoding on Chip
5-V, 10-V, and 15-V Parametric Ratings
100% Tested for Quiescent Current at 20 V
Maximum Input Current of 1µA at 18 V Over
Full Package Temperature Range, 100 nA at
18 V and 25°C
Break-Before-Make Switching Eliminates
Channel Overlap
Applications
D Analog and Digital Multiplexing and
Demultiplexing
D Analog-to-Digital (A/D) and
D
Digital-to-Analog (D/A) Conversion
Signal Gating
description/ordering information
The CD4051B, CD4052B, and CD4053B analog multiplexers are digitally-controlled analog switches that have
low ON impedance and very low OFF leakage current. Control of analog signals up to 20 VP-P can be achieved
by digital signal amplitudes of 4.5 V to 20 V (If VDD − VSS = 3 V, a VDD − VEE of up to 13 V can be controlled;
for VDD − VEE level differences above 13 V, a VDD − VSS of at least 4.5 V is required). For example, if
VDD = 4.5 V, VSS = 0 V, and VEE = −13.5 V, analog signals from −13.5 V to 4.5 V can be controlled by digital
inputs of 0 V to 5 V. These multiplexer circuits dissipate extremely low quiescent power over the full VDD − VSS
and VDD − VEE supply-voltage ranges, independent of the logic state of the control signals. When a logic high
(H) is present at the inhibit (INH) input, all channels are off.
ORDERING INFORMATION†
PACKAGE‡
TA
40°C to 125°C
−40°C
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SOIC − M
Reel of 2500
CD4051BQM96Q1
CD4051Q
TSSOP − PW
Reel of 2000
CD4051BQPWRQ1
CM051BQ
SOIC − M
Reel of 2500
CD4052BQM96Q1§
CD4052Q
TSSOP − PW
Reel of 2000
CD4052BQPWRQ1§
CD4052Q
SOIC − M
Reel of 2500
CD4053BQM96Q1
CD4053Q
TSSOP − PW
Reel of 2000
CD4053BQPWRQ1§
CD4053Q
†
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI web site at http://www.ti.com.
‡ Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
§ Product Preview
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2008, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
CD4051B-Q1, CD4052B-Q1, CD4053B-Q1
CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS
WITH LOGIC−LEVEL CONVERSION
SCHS354A − AUGUST 2004 − REVISED JANUARY 2008
description/ordering information (continued)
The CD4051B is a single eight-channel multiplexer that has three binary control inputs (A, B, and C) and an
inhibit input. The three binary signals select one of eight channels to be turned on and connect one of the eight
inputs to the output.
The CD4052B is a differential four-channel multiplexer that has two binary control inputs (A and B) and an inhibit
input. The two binary input signals select one of four pairs of channels to be turned on and connect the analog
inputs to the outputs.
The CD4053B is a triple two-channel multiplexer with three separate digital control inputs (A, B, and C) and an
inhibit input. Each control input selects one of a pair of channels, which are connected in a single-pole,
double-throw configuration.
When these devices are used as demultiplexers, the CHANNEL IN/OUT terminals are the outputs, and the
common (COM OUT/IN) terminals are the inputs.
CD4051
M OR PW PACKAGE
(TOP VIEW)
CHANNEL I/O 4
CHANNEL I/O 6
COM OUT/IN
CHANNEL I/O 7
CHANNEL I/O 5
INH
VEE
VSS
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
CD4052
M OR PW PACKAGE
(TOP VIEW)
VDD
CHANNEL I/O 2
CHANNEL I/O 1
CHANNEL I/O 0
CHANNEL I/O 3
A
B
C
Y CHANNEL I/O 0
Y CHANNEL I/O 2
COM Y OUT/IN
Y CHANNEL I/O 3
Y CHANNEL I/O 1
INH
VEE
VSS
CD4053
M OR PW PACKAGE
(TOP VIEW)
IN/OUT by
IN/OUT bx
IN/OUT cy
OUT/IN CX OR CY
IN/OUT CX
INH
VEE
VSS
2
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
POST OFFICE BOX 655303
VDD
OUT/IN bx or by
OUT/IN ax or ay
IN/OUT ay
IN/OUT ax
A
B
C
• DALLAS, TEXAS 75265
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VDD
X CHANNEL I/O 2
X CHANNEL I/O 1
COM X OUT/IN
X CHANNEL I/O 0
X CHANNEL I/O 3
A
B
CD4051B-Q1, CD4052B-Q1, CD4053B-Q1
CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS
WITH LOGIC−LEVEL CONVERSION
SCHS354A − AUGUST 2004 − REVISED JANUARY 2008
Function Tables
CD4051
INPUTS
B
ON
CHANNEL
INH
C
L
L
L
L
0
L
L
L
H
1
L
L
H
L
2
L
L
H
H
3
L
H
L
L
4
L
H
L
H
5
L
H
H
L
6
L
H
H
H
7
H
X
X
X
None
A
X = don’t care
CD4052
INPUTS
INH
B
A
ON
CHANNEL
L
L
L
0x, 0y
L
L
H
1x, 2y
L
H
L
2x, 2y
L
H
H
3x, 3y
H
X
X
None
X = don’t care
CD4053
INPUTS
INH
A OR B OR C
ON
CHANNEL
L
L
ax or bx or cx
L
H
ay or by or cy
H
X
None
X = don’t care
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
CD4051B-Q1, CD4052B-Q1, CD4053B-Q1
CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS
WITH LOGIC−LEVEL CONVERSION
SCHS354A − AUGUST 2004 − REVISED JANUARY 2008
logic diagram (positive logic)
CD4051B
CHANNEL I/O
16 VDD
7
6
5
4
3
2
1
0
4
2
5
1
12
15
14
13
TG
TG
A† 11
TG
†
B
Binary
to
1-of-8
Decoder
With
Inhibit
10
Logic-Level
Conversion
C† 9
TG
3
COM
OUT/IN
TG
TG
TG
†
INH
6
TG
8
†
7
VSS
VEE
All inputs are protected by CMOS protection network.
CD4052B
X CHANNEL I/O
3
2
1
0
11
15
14
12
TG
VDD
16
TG
TG
A† 10
B†
9
†
6
INH
Binary
to
1-of-4
Decoder
With
Inhibit
Logic-Level
Conversion
TG
13 COM X
TG
3
TG
TG
TG
8
†
4
VSS
7
VEE
1
5
2
4
0
1
2
3
Y CHANNEL I/O
All inputs are protected by CMOS protection network.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
OUT/IN
COM Y
OUT/IN
CD4051B-Q1, CD4052B-Q1, CD4053B-Q1
CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS
WITH LOGIC−LEVEL CONVERSION
SCHS354A − AUGUST 2004 − REVISED JANUARY 2008
logic diagrams (positive logic) (continued)
CD4053B
IN/OUT
16 VDD
A† 11
cy
cx
by
bx
ay
ax
3
5
1
2
13
12
Binary to
1-of-2
Decoders
With
Inhibit
Logic-Level
Conversion
TG
COM OUT/IN
ac or ay
14
TG
TG
B† 10
COM OUT/IN
bc or by
15
TG
C†
TG
9
COM OUT/IN
xc or xy
4
TG
INH† 6
VDD
8 VSS
†
7
VEE
All inputs are protected by standard CMOS protection network.
absolute maximum ratings over operating free-air temperature (unless otherwise noted)‡
Supply voltage range, V+ to V− (voltages referenced to VSS terminal) . . . . . . . . . . . . . . . . . . . . . . −0.5 to 20 V
DC input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VDD + 0.5 V
DC input current, any one input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA
Package thermal impedance, θJA (see Note 1): M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Lead temperature (during soldering):
At distance 1/16 ± 1/32 inch (1,59 ± 0,79 mm) from case for 10 s max . . . . . . . . . . . . . . . . . . . . . . . 265°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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CD4051B-Q1, CD4052B-Q1, CD4053B-Q1
CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS
WITH LOGIC−LEVEL CONVERSION
SCHS354A − AUGUST 2004 − REVISED JANUARY 2008
recommended operating conditions
VDD
Supply voltage
TA
Operating free-air temperature
MIN
MAX
5
20
UNIT
V
−40
125
°C
electrical characteristics, VSUPPLY = ±5 V, AV = 1 V, RL = 100 Ω, unless otherwise noted
(see Note 2)
PARAMETER
IDD
VDD
(V)
TEST CONDITIONS
Quiescent device
current
LIMITS AT INDICATED
TEMPERATURES
UNIT
25°C
−40°C
40°C
125°C
5
5
150
0.04
5
10
10
300
0.04
10
15
20
600
0.04
20
20
100
3000
0.08
100
MIN
TYP
MAX
µA
A
Signal Input (Vis) and Output (Vos)
5
850
1300
470
1050
VEE = 0 V
V, VSS = 0 V,
V
VIS = 0 to VDD
10
330
550
180
400
15
210
320
125
240
ON-state resistance
difference between
any two switches
5
15
VEE = 0 V, VSS = 0 V
10
10
15
5
Input/output leakage
current (switch off)
Any channel OFF (MAX) or all channels
OFF (COM OUT/IN) (Max),
VEE = 0 V, VSS = 0 V, See Note 3
18
Cis
Input capacitance
VEE = −5 V, VSS = −5 V
5
Cos
Output capacitance
VEE = −5
5 V, VSS = −5
5V
ron
∆ron
Drain-to-source
D
i t
ON-state resistance
CD4051
CD4052
±1
±10−5
Ω
±0.1
5
pF
18
pF
9
Cios
Feedthrough
capacitance
VEE = −5 V, VSS = −5 V
5
0.2
Propagation delay
(signal input to
output)
5
30
60
tpd
VIS(p-p) = VDD, RL = 200 kΩ,
kΩ
CL = 50 pF
pF, tr, tf = 20 ns
10
15
30
15
10
20
NOTES: 2. Peak-to-peak voltage symmetrical about VDD − VEE
2
3. Determined by minimum feasible leakage measurement for automatic testing
POST OFFICE BOX 655303
µA
30
5
CD4053
6
±0.1
Ω
• DALLAS, TEXAS 75265
pF
ns
CD4051B-Q1, CD4052B-Q1, CD4053B-Q1
CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS
WITH LOGIC−LEVEL CONVERSION
SCHS354A − AUGUST 2004 − REVISED JANUARY 2008
electrical characteristics, VSUPPLY = ±5 V, AV = 1 V, RL = 100 Ω, unless otherwise noted
(see Note 2) (continued)
PARAMETER
TEST CONDITIONS
VEE
(V)
VDD
(V)
LIMITS AT INDICATED
TEMPERATURES
UNIT
25°C
−40°C
40°C
125°C
MIN
TYP
MAX
Control (Address or Inhibit), VC
VIL
VIH
IIN
tpd1
tpd2
tpd3
CIN
Input
p low voltage
g
Input
p high
g voltage
g
Input current
VIL = VDD through
g 1kΩ,,
VIH = VDD through 1kΩ,
RL = 1kΩ to VSS,
Iis < 2 µA on all OFF channels
VSS
5
1.5
1.5
1.5
VSS
10
3
3
3
VSS
15
4
4
4
VIL = VDD through
g 1kΩ,,
VIH = VDD through 1kΩ,
RL = 1kΩ to VSS,
Iis < 2 µA on all OFF channels
VSS
5
3.5
3.5
VSS
10
7
7
7
VSS
15
11
11
11
18
±0.1
±1
VIN = 0 V, 18 V
Address-to-signal
OUT (channels ON
p p g
or OFF)) propagation
delay
d l
tr, tf = 20 ns,
ns CL = 50 pF
pF,
RL = 10 kΩ, VSS = 0 V,
g
g
See Figure
10, Figure
11, and
Figure
14
Fi
Inhibit-to-signal
OUT (channel
g ON))
turning
propagation
ti delay
d l
tr, tf = 20 ns, CL = 50 pF,
RL = 1 kΩ,
kΩ VSS = 0 V,
V
See Figure 11
Inhibit-to-signal
OUT (channel
g OFF))
turning
propagation
ti delay
d l
tr, tf = 20 ns, CL = 50 pF,
RL = 10 kΩ,
kΩ VSS = 0 V,
V
See Figure 15
3.5
V
±10−5
±0.1
0
5
450
720
0
10
160
320
0
15
120
240
−5
5
225
450
0
5
400
720
0
10
160
320
0
15
120
240
−10
5
200
400
0
5
200
450
0
10
90
210
0
15
70
160
−10
5
130
300
5
7.5
Input capacitance,
any address or
inhibit input
V
µA
ns
ns
ns
pF
NOTES: 2: Peak-to-peak voltage symmetrical about VDD − VEE
2
3: Determined by minimum feasible leakage measurement for automatic testing
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CD4051B-Q1, CD4052B-Q1, CD4053B-Q1
CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS
WITH LOGIC−LEVEL CONVERSION
SCHS354A − AUGUST 2004 − REVISED JANUARY 2008
electrical specifications
PARAMETER
VIS
(V)
TEST CONDITIONS
VDD
(V)
LIMITS AT
INDICATED
TEMPERATURES
MIN
−3-dB cutoff
frequency
frequency,
channel ON
(sine-wave input)
THD
Total harmonic
distortion
RL = 1 kΩ,,
VOS at COM OUT/IN,
See Note 2,
2
VOS at COM OUT/IN
5
10
30
CD4052
5
10
25
CD4051
5
10
20
kΩ
RL = 10 kΩ,
See Note 2
2
5
3
10
0.2
5
15
0.12
5
10
8
CD4052
5
10
10
CD4051
5
10
12
VEE = VSS, 20log VOS/VIS = −40 dB,
VOS at any channel
Address or inhibit
to signal crosstalk
5
10
3
CD4052
10
MHz
VEE = VSS, 20log VOS/VIS = −40 dB,
Between any two sections,
In pin 2, Out pin 14
2.5
CD4053
6
RL = 10 kΩ, See Note 4
10
VEE = 0 V, VSS = 0 V, tr, tf = 20 ns,
VCC = VDD − VSS (square wave)
POST OFFICE BOX 655303
MHz
6
65
65
NOTES: 2. Peak-to-peak voltage symmetrical about VDD − VEE
2
4. Both ends of channel
8
%
8
VEE = VSS, 20log VOS/VIS = −40 dB,
Between sections, Measured on common
VEE = VSS, 20log VOS/VIS = −40 dB,
Between any two sections,
In pin 15, Out pin 14
0.3
CD4053
RL = 1 kΩ, between any two channels, See Note 2
−40-dB signal
g
crosstalk frequency
MHz
0.12
RL = 1 kΩ,
VOS at COM OUT/IN,
See Note 2
VEE = VSS, 20log VOS/VIS = −40 dB,
Between sections,
Measured on any channel
MAX
60
VEE = VSS, fis = 1-kHz sine wave
−40-dB
f dth
feedthrough
h
frequency
(all channels OFF)
TYP
CD4053
VEE = VSS, 20log VOS/VIS = −3 dB,
VOS at any channel
UNIT
25°C
• DALLAS, TEXAS 75265
mVPEAK
CD4051B-Q1, CD4052B-Q1, CD4053B-Q1
CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS
WITH LOGIC−LEVEL CONVERSION
SCHS354A − AUGUST 2004 − REVISED JANUARY 2008
TYPICAL CHARACTERISTICS
600
Supply Voltage (VDD − VEE) = 5 V
500
TA = 125°C
CHANNEL ON-STATE RESISTANCE
vs
INPUT SIGNAL VOLTAGE
400
300
25°C
200
−55°C
100
0
−4
−3
−2
−1
0
1
2
3
4
ron − Channel ON−State Resistance − W
ron − Channel ON−State Resistance − W
CHANNEL ON-STATE RESISTANCE
vs
INPUT SIGNAL VOLTAGE
300
Supply Voltage (VDD − VEE) = 10 V
250
TA = 125°C
200
25°C
150
−55°C
100
50
0
−10
−7.5
−5
Vis − Input Signal Voltage − V
−2.5
0
2.5
5
7.5
Vis − Input Signal Voltage − V
92CS-27326RI
92CS-27327RI
Figure 1
Figure 2
CHANNEL ON-STATE RESISTANCE
vs
INPUT SIGNAL VOLTAGE
TA = 25°C
300
Supply Voltage (VDD − VEE) = 5 V
200
150
100
10 V
15 V
50
0
−10
−7.5
−5
−2.5
0
2.5
5
7.5
Vis − Input Signal Voltage − V
10
92CS-27330RI
ron − Channel ON−State Resistance − W
ron − Channel ON−State Resistance − W
CHANNEL ON-STATE RESISTANCE
vs
INPUT SIGNAL VOLTAGE
250
10
Supply Voltage (VDD − VEE) = 15 V
300
250
200
TA = 125°C
150
25°C
100
−55°C
50
0
−10
−7.5
−5
−2.5
0
2.5
5
Vis − Input Signal Voltage − V
Figure 3
7.5
10
92CS-27329RI
Figure 4
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CD4051B-Q1, CD4052B-Q1, CD4053B-Q1
CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS
WITH LOGIC−LEVEL CONVERSION
SCHS354A − AUGUST 2004 − REVISED JANUARY 2008
TYPICAL CHARACTERISTICS
DYNAMIC POWER DISSIPATION
vs
SWITCHING FREQUENCY (CD4051B)
PD − Power Dissipation Per Package − mW
ON CHARACTERISTICS FOR
1-OF-8 CHANNELS (CD4051B)
Vos − Output Signal Voltage − V
6
VDD = 5 V
RL = 100 kW, RL = 10 kW
VSS = 0 V
4
1 kW
500 W
VEE = −5 V
100 W
TA = 255C
2
0
−2
−4
−6
−6
−4
−2
0
2
4
6
10 5
TA = 255C
Test Circuit
VDD
Alternating O
and I Pattern
10 4
VDD = 10 V
10 2
VDD = 5 V
100 Ω
10
1
10 2
10
VDD
VDD = 15 V
CD4029
B/D
A B
100 Ω
10 9
1
5
2
4 CD4052
10 3
VDD = 10 V
VDD = 5 V
6
7
3 CL
13
12
14
15
11
8
CL = 15 pF
Ι
10 3
10 4
10 5
PD − Power Dissipation Per Package − mW
f
100 Ω
PD − Power Dissipation Per Package − mW
CL = 50 pF
10 2
10 5
VDD = 15 V
TA = 255C
Alternating O
VDD = 10 V
and I Pattern
10 4
CL = 50 pF
VDD
CD4053
10
11
6
7
CL = 15 pF
CL
12
5
VDD = 5 V
10 2
4
9
3
100 W
Ι
13
2
1
15
14
8
10
1
10
10 2
10 3
f − Switching Frequency − kHz
Figure 7
Figure 8
POST OFFICE BOX 655303
Test Circuit
f
100 W
10 3
f − Switching Frequency − kHz
10
10 5
DYNAMIC POWER DISSIPATION
vs
SWITCHING FREQUENCY (CD4053B)
Test Circuit
and ÒIÓ Pattern
10
10 4
Figure 6
Alternating ÒOÓ
1
10 3
f − Switching Frequency − kHz
TA = 255C
10
Ι
CL = 15 pF
DYNAMIC POWER DISSIPATION
vs
SWITCHING FREQUENCY (CD4052B)
10 2
13
14
15
12 CD4051
1
5
3
2
4 8 7 6
CL
10 3
Figure 5
10 4
VDD
100 Ω 11 10 9
VDD = 15 V
Vis − Input Signal Voltage − V
10 5
B/D
CD4029
A B C
f
CL = 50 pF
• DALLAS, TEXAS 75265
10 4
10 5
CD4051B-Q1, CD4052B-Q1, CD4053B-Q1
CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS
WITH LOGIC−LEVEL CONVERSION
SCHS354A − AUGUST 2004 − REVISED JANUARY 2008
PARAMETER MEASUREMENT INFORMATION
VDD = 15 V
VDD = 7.5 V
VDD = 5 V
5V
7.5 V
16
VDD = 5 V
5V
16
16
16
VSS = 0 V
VSS = 0 V
VSS = 0 V
VEE = 0 V
7
8
VSS = 0 V
VEE = –7.5 V
7
8
VEE = –10 V
VEE = –5 V
7
8
(D)
(C)
(B)
(A)
7
8
NOTE: The A, B, C, and INH input logic levels are L = VSS and H = VDD. The analog signal (through the TG) may swing from VEE to VDD.
Figure 9. Typical Bias-Voltage Test Circuits
tr = 20 ns
90%
50%
90%
50%
10%
tr = 20 ns
tf = 20 ns
10%
90%
50%
10%
tf = 20 ns
90%
50%
10%
Turn-On Time
90%
50%
90%
10%
10%
10%
Turn-Off Time
Turn-Off Time
Turn-On Time
tPHZ
Figure 10. Channel Turned ON Waveforms
(RL = 1 kΩ)
POST OFFICE BOX 655303
Figure 11. Channel Turned OFF Waveforms
(RL = 1 kΩ)
• DALLAS, TEXAS 75265
11
CD4051B-Q1, CD4052B-Q1, CD4053B-Q1
CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS
WITH LOGIC−LEVEL CONVERSION
SCHS354A − AUGUST 2004 − REVISED JANUARY 2008
PARAMETER MEASUREMENT INFORMATION
1
2
3
4
5
6
7
16
15
14
13
12
11
10
8
9
VDD
VDD
VDD
1
2
3
4
5
6
7
8
IDD
CD4051
16
15
14
13
12
11
10
CD40529
1
2
3
4
5
6
7
8
IDD
16
15
14
13
12
11
10
9
IDD
CD4053
CD4052
Figure 12. OFF Channel Leakage Current, Any Channel OFF
VDD
1
2
3
4
5
6
7
8
IDD
VDD
VDD
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
IDD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CD4052
CD4051
16
15
14
13
12
11
10
9
IDD
CD4053
Figure 13. OFF Channel Leakage Current, All Channels OFF
VDD
VDD
1
2
3
4
5
6
7
VDD
VEE
16
15
14
13
12
11
10
8
Output
RL
Output
Output
CL
CL
RL
VDD
VEE
VDD
VSS
9
VEE
VEE
Clock
In
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
VEE
VDD
VSS
VSS
VSS
VSS
CD4051
CD4052
Clock
In
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RL
CL
VEE
VDD
VSS
Clock
In
VSS
CD4053
VSS
VSS
Figure 14. Propagation Delay, Address Input to Signal Output
VDD
Output
50 pF
RL
VEE
VDD
VSS
VDD
Clock
In
VEE
VSS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
tPHL and tPLH
VDD
Output
50 pF
RL
VEE
VDD
VDD
VSS
Clock
In
VEE
VSS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Output
RL
50 pF
VEE
VDD
VDD
VSS Clock
In
VEE
VSS
tPHL and tPLH VSS
VSS
CD4052
CD4051
Figure 15. Propagation Delay, Inhibit Input to Signal Output
12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
tPHL and tPLH VSS
CD4053
VDD
CD4051B-Q1, CD4052B-Q1, CD4053B-Q1
CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS
WITH LOGIC−LEVEL CONVERSION
SCHS354A − AUGUST 2004 − REVISED JANUARY 2008
PARAMETER MEASUREMENT INFORMATION
VDD
VDD
VDD
µA
VIH
1K
1K
VIH
VIL
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CD4051B
VIH
VIL
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1K
1K
µA
VIH
1K
VIL
VIH
16
15
14
13
12
11
10
9
1K
mA
VIH
VIL
CD4053B
CD4052B
VIL
1
2
3
4
5
6
7
8
VIL
Measure <2 mA on All OFF Channels (e.g., Channel 2x)
Measure <2 mA on All OFF Channels (e.g., Channel 6)
Measure <2 mA on All OFF Channels (e.g., Channel by)
Figure 16. Input-Voltage Test Circuit (Noise Immunity)
VDD
VDD
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Ι
CD4051
CD4053
Ι
16
15
14
13
12
11
10
9
CD4052
Figure 17. Quiescent Device Current
Keithley
610 Digital
Multimeter
VDD
TG
On
10 kW
1-kW
Range
Y
X−Y
Plotter
VSS
H.P.
Moseley
7030A
X
Figure 18. Channel ON-Resistance Test Circuit
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
CD4051B-Q1, CD4052B-Q1, CD4053B-Q1
CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS
WITH LOGIC−LEVEL CONVERSION
SCHS354A − AUGUST 2004 − REVISED JANUARY 2008
PARAMETER MEASUREMENT INFORMATION
VDD
1
2
3
4
5
6
7
8
VSS
VDD
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
VDD
Ι
VSS
CD4051
CD4053
VSS
NOTE: Measure inputs sequentially to both VDD and VSS.
Connect all unused inputs to either VDD or VSS.
16
15
14
13
12
11
10
9
VDD
Ι
VSS
CD4051
CD4053
NOTE: Measure inputs sequentially to both VDD and VSS.
Connect all unused inputs to either VDD or VSS.
Figure 19. Input Current
5 VP−P
Channel
ON
OFF
Channel
5 VP−P
Common
RF
VM
RL
1K
VDD
Channel
ON
RF
VM
Channel
OFF
6
7
8
Channel In Y
ON or OFF
Channel In X
ON or OFF
RF
VM
RL
Figure 22. Crosstalk Between Duals or Triplets (CD4052B, CD4053B)
CD4052
CD4052
Communications
Link
Differential
Amplifier/Line
Driver
.
Differential
Receiver
Differential
Multiplexing
Demultiplexing
Figure 23. Typical Time-Division Application of the CD4052B
14
RL
Figure 21. Crosstalk Between Any Two Channels
RL
Differential
Signals
RF
VM
RL
RL
Figure 20. Feedthrough
5 VP−P
Channel
OFF
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CD4051B-Q1, CD4052B-Q1, CD4053B-Q1
CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS
WITH LOGIC−LEVEL CONVERSION
SCHS354A − AUGUST 2004 − REVISED JANUARY 2008
APPLICATION INFORMATION
In applications where separate power sources drive VDD and the signal inputs, the VDD current capability should
exceed VDD/RL (RL = effective external load). This provision avoids permanent current flow or clamp action on the
VDD supply when power is applied or removed from the CD4051B, CD4052B, or CD4053B.
A
B
C
D
E
A
B
CD4051B
C
INH
Q0
A
B
E
1/2
CD4556
Q1
Q2
A
B
CD4051B
C
INH
Common
Output
A
B
CD4051B
C
INH
Figure 24. 24-to-1 Multiplexer Addressing
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CD4051BQPWRG4Q1
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
CM051BQ
CD4051BQPWRQ1
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
CM051BQ
CD4053BQM96G4Q1
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
CD4053Q
CD4053BQM96Q1
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
CD4053Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2014
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD4051B-Q1, CD4053B-Q1 :
• Catalog: CD4051B, CD4053B
• Military: CD4051B-MIL, CD4053B-MIL
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Mar-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CD4051BQPWRG4Q1
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
CD4051BQPWRQ1
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Mar-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CD4051BQPWRG4Q1
TSSOP
PW
16
2000
367.0
367.0
35.0
CD4051BQPWRQ1
TSSOP
PW
16
2000
367.0
367.0
35.0
Pack Materials-Page 2
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