AD HMC8410CHIPS-SX Low noise figure: 1.1 db typical Datasheet

FEATURES
FUNCTIONAL BLOCK DIAGRAM
Low noise figure: 1.1 dB typical
High gain: 19.5 dB typical
High output third-order intercept (IP3): 33 dBm typical
Die size: 0.95 mm × 0.61 × 0.102 mm
2
RFIN/VGG1
1
HMC8410CHIPS
APPLICATIONS
RFOUT/VDD
15093-001
Data Sheet
0.01 GHz to 10 GHz, GaAs, pHEMT, MMIC,
Low Noise Amplifier
HMC8410CHIPS
Figure 1.
Software defined radios
Electronics warfare
Radar applications
GENERAL DESCRIPTION
The HMC8410CHIPS is a gallium arsenide (GaAs), monolithic
microwave integrated circuit (MMIC), pseudomorphic high
electron mobility transistor (pHEMT), low noise wideband amplifier that operates from 0.01 GHz to 10 GHz. The HMC8410CHIPS
provides a typical gain of 19.5 dB, a 1.1 dB typical noise figure,
and a typical output IP3 of 33 dBm, requiring only 65 mA from
a 5 V supply voltage. The saturated output power (PSAT) of
Rev. 0
22.5 dBm enables the low noise amplifier (LNA) to function as a
local oscillator (LO) driver for many of Analog Devices, Inc.,
balanced, I/Q or image rejection mixers.
The HMC8410CHIPS also features inputs/outputs (I/Os) that are
internally matched to 50 Ω, making it ideal for surface-mounted
technology (SMT)-based, high capacity microwave radio
applications.
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HMC8410CHIPS
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Interface Schematics .....................................................................6
Applications ....................................................................................... 1
Typical Performance Characteristics ..............................................7
Functional Block Diagram .............................................................. 1
Theory of Operation ...................................................................... 12
General Description ......................................................................... 1
Applications Information .............................................................. 13
Revision History ............................................................................... 2
Recommended Bias Sequencing .............................................. 13
Electrical Specifications ................................................................... 3
0.01 GHz to 3 GHz Frequency Range........................................ 3
Mounting and Bonding Techniques for Millimeterwave GaAs
MMICs ......................................................................................... 13
3 GHz to 8 GHz Frequency Range ............................................. 3
Application Circuits ....................................................................... 15
8 GHz to 10 GHz Frequency Range ........................................... 4
Assembly Diagram ..................................................................... 15
Absolute Maximum Ratings............................................................ 5
Outline Dimensions ....................................................................... 16
ESD Caution .................................................................................. 5
Ordering Guide .......................................................................... 16
Pin Configuration and Function Descriptions ............................. 6
REVISION HISTORY
10/2016—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
Data Sheet
HMC8410CHIPS
SPECIFICATIONS
0.01 GHz TO 3 GHz FREQUENCY RANGE
TA = 25°C, VDD = 5 V, and IDQ = 65 mA, unless otherwise noted.
Table 1.
Parameter
FREQUENCY RANGE
GAIN
Gain Variation Over Temperature
NOISE FIGURE
RETURN LOSS
Input
Output
OUTPUT
Output Power for 1 dB Compression
Saturated Output Power
Output Third-Order Intercept
SUPPLY
Current
Voltage
Symbol
P1dB
PSAT
IP3
IDQ
VDD
Min
0.01
17.5
Typ
19.5
0.01
1.1
19.0
2
Max
3
1.6
Unit
GHz
dB
dB/°C
dB
15
24
dB
dB
21.0
22.5
33
dBm
dBm
dBm
Test Conditions/Comments
65
5
80
6
mA
V
Adjust VGG1 to achieve IDQ = 65 mA typical
Typ
Max
8
Unit
GHz
dB
dB/°C
dB
Test Conditions/Comments
3 GHz TO 8 GHz FREQUENCY RANGE
TA = 25°C, VDD = 5 V, and IDQ = 65 mA, unless otherwise noted.
Table 2.
Parameter
FREQUENCY RANGE
GAIN
Gain Variation Over Temperature
NOISE FIGURE
RETURN LOSS
Input
Output
OUTPUT
Output Power for 1 dB Compression
Saturated Output Power
Output Third-Order Intercept
SUPPLY
Current
Voltage
Symbol
P1dB
PSAT
IP3
IDQ
VDD
Min
3
15.5
17.5
2
18
0.01
1.4
1.9
12
12
dB
dB
20.5
22.5
31.5
dBm
dBm
dBm
65
5
80
6
Rev. 0 | Page 3 of 16
mA
V
Adjust VGG1 to achieve IDQ = 65 mA typical
HMC8410CHIPS
Data Sheet
8 GHz TO 10 GHz FREQUENCY RANGE
TA = 25°C, VDD = 5 V, and IDQ = 65 mA, unless otherwise noted.
Table 3.
Parameter
FREQUENCY RANGE
GAIN
Gain Variation Over Temperature
NOISE FIGURE
RETURN LOSS
Input
Output
OUTPUT
Output Power for 1 dB Compression
Saturated Output Power
Output Third-Order Intercept
SUPPLY
Current
Voltage
Symbol
P1dB
PSAT
IP3
IDQ
VDD
Min
8
13
17.5
2
Typ
16
0.01
1.7
Max
10
2.2
Unit
GHz
dB
dB/°C
dB
6
10
dB
dB
19.5
21.5
33
dBm
dBm
dBm
65
5
80
6
Rev. 0 | Page 4 of 16
mA
V
Test Conditions/Comments
Adjust VGG1 to achieve IDQ = 65 mA typical
Data Sheet
HMC8410CHIPS
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 4.
Parameter1
Drain Bias Voltage (VDD)
Radio Frequency (RF) Input Power (RFIN)
Continuous Power Dissipation (PDISS), T = 85°C
(Derate 13.23 mW/°C Above 85°C)
Channel Temperature
Storage Temperature Range
Operating Temperature Range
ESD Sensitivity
Human Body Model (HBM)
θJC is the junction to case thermal resistance, channel to bottom
of die.
Rating
7 V dc
20 dBm
1.2 W
Table 5. Thermal Resistance
175°C
−65°C to +150°C
−55°C to +85°C
Package Type
C-2-3
ESD CAUTION
Class 1B passed
500 V
When referring to a single function of a multifunction pin in the parameters,
only the portion of the pin name that is relevant to the specification is listed.
For the full pin names of multifunction pins, refer to the Pin Configuration
and Function Descriptions section.
2
See the Ordering Guide section for more information.
1
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. 0 | Page 5 of 16
θJC
75.57
Unit
°C/W
HMC8410CHIPS
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
HMC8410CHIPS
RFIN/VGG1
2
RFOUT/VDD
15093-002
TOP VIEW
(Not to Scale)
1
Figure 2. Pad Configuration
Table 6. Pad Function Descriptions
Pin No.
1
Mnemonic
RFIN/VGG1
2
RFOUT/VDD
Die Bottom
GND
Description
RF Input (RFIN). This pin is ac-coupled and matched to 50 Ω. See Figure 4 for the interface schematic.
Gate Bias of the Amplifier (VGG1). This pin is ac-coupled and matched to 50 Ω. See Figure 4 for the interface
schematic.
RF Output (RFOUT). This pin is ac-coupled and matched to 50 Ω. See Figure 5 for the interface schematic.
Drain Bias for Amplifier (VDD). This pin is ac-coupled and matched to 50 Ω. See Figure 5 for the interface
schematic.
Ground. Die bottom must be connected to RF/dc ground.
INTERFACE SCHEMATICS
15093-003
GND
15093-005
RFOUT/VDD
Figure 5. RFOUT/VDD Interface Schematic
RFIN/VGG1
15093-004
Figure 3. GND Interface Schematic
Figure 4. RFIN/VGG1 Interface Schematic
Rev. 0 | Page 6 of 16
Data Sheet
HMC8410CHIPS
TYPICAL PERFORMANCE CHARACTERISTICS
22
25
+85°C
+25°C
–55°C
20
15
10
18
GAIN (dB)
5
0
–5
16
14
–10
12
–15
–20
1
2
3
4
5
6
7
8
9
10
11
FREQUENCY (GHz)
8
0
4
5
6
7
8
9
10
11
+85°C
+25°C
–55°C
–5
OUTPUT RETURN LOSS (dB)
–6
–8
–10
–12
–14
–10
–15
–20
–25
–30
–18
1
2
3
4
5
6
7
8
9
10
11
FREQUENCY (GHz)
Figure 7. Input Return Loss vs. Frequency for Various Temperatures
4.0
–35
15093-007
0
1
2
3
4
5
6
7
8
9
10
11
FREQUENCY (GHz)
Figure 10. Output Return Loss vs. Frequency for Various Temperatures
15
+85°C
+25°C
–55°C
3.5
0
+85°C
+25°C
–55°C
14
13
12
3.0
NOISE FIGURE (dB)
11
2.5
2.0
1.5
10
9
8
7
6
5
4
1.0
3
2
0.5
0
1
2
3
4
5
6
7
8
9
10
11
FREQUENCY (GHz)
15093-008
1
0
Figure 8. Noise Figure vs. Frequency for Various Temperatures
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
FREQUENCY (GHz)
Figure 11. Noise Figure vs. Frequency for Various Temperatures,
10 MHz to 1 GHz
Rev. 0 | Page 7 of 16
15093-011
INPUT RETURN LOSS (dB)
3
0
+85°C
+25°C
–55°C
–16
NOISE FIGURE (dB)
2
Figure 9. Gain vs. Frequency for Various Temperatures
–4
–20
1
FREQUENCY (GHz)
Figure 6. Gain and Return Loss vs. Frequency
–2
0
15093-009
0
15093-010
–30
10
S11
S21
S22
–25
15093-006
GAIN (dB), RETURN LOSS (dB)
20
HMC8410CHIPS
Data Sheet
24
23
40
22
35
21
20
19
18
30
25
20
15
17
10
16
5
0
1
2
3
4
5
6
7
8
9
10
11
FREQUENCY (GHz)
0
15093-012
15
+85°C
+25°C
–55°C
45
OUTPUT IP2 (dBm)
P1dB (dBm)
50
+85°C
+25°C
–55°C
0
1
2
3
4
5
6
7
8
9
10
11
FREQUENCY (GHz)
15093-015
25
Figure 15. Output IP2 vs. Frequency for Various Temperatures at POUT/Tone =
5 dBm
Figure 12. P1dB vs. Frequency for Various Temperatures
0
25
24
+85°C
+25°C
–55°C
–5
REVERSE ISOLATION (dB)
23
PSAT (dBm)
22
21
20
19
18
–10
–15
–20
–25
17
1
2
3
4
5
6
7
8
9
10
11
FREQUENCY (GHz)
–35
2
3
4
5
6
7
8
9
10
11
Figure 16. Reverse Isolation vs. Frequency for Various Temperatures
40
35
35
30
30
OUTPUT IP3 (dBm)
40
25
20
15
10
25
20
15
10
0
1
2
3
4
5
6
7
8
9
10
0dBm
+85°C
5dBm
+25°C
10dBm
–55°C
5
11
FREQUENCY (GHz)
Figure 14. Output IP3 vs. Frequency for Various Temperatures,
Output Power (POUT)/Tone = 5 dBm
0
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY (GHz)
Figure 17. Output IP3 vs. Frequency for Various POUT/Tone
Rev. 0 | Page 8 of 16
11
15093-017
+85°C
+25°C
–55°C
5
15093-014
OUTPUT IP3 (dBm)
1
FREQUENCY (GHz)
Figure 13. PSAT vs. Frequency for Various Temperatures
0
0
15093-016
0
15093-013
15
–30
+85°C
+25°C
–55°C
16
Data Sheet
HMC8410CHIPS
55
GAIN
P1dB
PSAT
OUTPUT IP3
35
PSAT
PAE
50
45
PSAT (dBm), PAE (%)
GAIN (dB), P1dB (dBm), PSAT (dBm),
OUTPUT IP3 (dBm)
40
30
25
20
40
35
30
25
20
15
10
15
0.6
0.8
1.0
0
FREQUENCY (GHz)
0
1
POWER DISSIPATION (W)
P1dB (dBm), PAE (%)
20
15
10
5
7
8
9
1
2
3
4
5
6
7
8
9
10
11
0.25
0.20
0.15
0.10
1GHz
3GHz
5GHz
7GHz
9GHz
45
95
40
90
35
85
30
80
25
75
20
70
5
–5
0
5
0
2
4
6
8
10
12
14
5mA
15mA
25mA
35mA
45mA
65mA
70mA
80mA
18
16
14
12
60
10
55
50
10
INPUT POWER (dBm)
15093-020
POUT
GAIN
PAE
IDD
–2
20
65
10
–4
22
GAIN (dB)
100
–6
Figure 22. Power Dissipation vs. Input Power for Various Frequencies, TA = 85°C
IDD (mA)
50
–8
INPUT POWER (dBm)
Figure 19. P1dB and Power Added Efficiency (PAE) vs. Frequency
15
11
0.30
0
–10
15093-019
0
10
0.35
0.05
FREQUENCY (GHz)
POUT (dBm), GAIN (dB), PAE (%)
6
0.40
25
0
–10
5
0.45
30
0
4
Figure 21. PSAT and PAE vs. Frequency
P1dB
PAE
35
3
FREQUENCY (GHz)
Figure 18. Gain, P1dB, PSAT, and Output IP3 vs. Frequency
40
2
15093-022
0.4
Figure 20. POUT, Gain, PAE, and Supply Current with RF Applied (IDD) vs.
Input Power at 5 GHz
8
0
1
2
3
4
5
6
7
8
9
10
11
FREQUENCY (GHz)
Figure 23. Gain vs. Frequency for Various Supply Currents, VDD = 5 V
Rev. 0 | Page 9 of 16
15093-023
0.2
15093-018
0
15093-021
5
10
HMC8410CHIPS
3.0
2.5
35
30
OUTPUT IP3 (dBm)
3.5
2.0
1.5
25
20
15
1.0
10
0.5
5
0
0
1
2
3
4
5
6
7
8
9
10
11
FREQUENCY (GHz)
0
15093-024
NOISE FIGURE (dB)
40
5mA
15mA
25mA
35mA
45mA
65mA
70mA
75mA
Figure 24. Noise Figure vs. Frequency for Various Supply Currents (IDQ),
VDD = 5 V
5mA
25mA
45mA
70mA
0
1
2
15mA
35mA
65mA
75mA
3
4
5
6
7
8
9
10
11
FREQUENCY (GHz)
15093-027
4.0
Data Sheet
Figure 27. Output IP3 vs. Frequency for Various Supply Currents (IDQ),
POUT/Tone = 5 dBm, VDD = 5 V
22
25
3V
4V
5V
6V
7V
20
20
15
10
GAIN (dB)
P1dB (dBm)
18
5mA
15mA
25mA
35mA
45mA
65mA
70mA
75mA
80mA
16
14
12
5
1
2
3
4
5
6
7
8
9
10
11
FREQUENCY (GHz)
Figure 25. P1dB vs. Frequency for Various Supply Currents (IDQ), VDD = 5 V
1
2
3
4
5
6
7
8
9
24
3.5
NOISE FIGURE (dB)
21
5mA
15mA
25mA
35mA
45mA
65mA
70mA
75mA
80mA
19
0
1
2
3
4
5
6
7
FREQUENCY (GHz)
8
9
10
2.5
2.0
1.5
1.0
0.5
11
0
15093-026
20
11
3V
4V
5V
6V
7V
3.0
22
10
Figure 28. Gain vs. Frequency for Various Supply Voltages, IDQ = 65 mA
4.0
18
0
FREQUENCY (GHz)
25
23
PSAT (dBm)
8
Figure 26. PSAT vs. Frequency for Various Supply Currents (IDQ), VDD = 5 V
0
1
2
3
4
5
6
7
FREQUENCY (GHz)
8
9
10
11
15093-029
0
15093-025
0
15093-028
10
Figure 29. Noise Figure vs. Frequency for Various Supply Voltages, IDQ = 65 mA
Rev. 0 | Page 10 of 16
Data Sheet
HMC8410CHIPS
90
25
80
23
70
21
19
IDD (mA)
P1dB (dBm)
60
17
50
40
30
15
1
2
3
4
5
6
7
8
9
10
11
FREQUENCY (GHz)
0
–0.90 –0.85
–0.70 –0.65
–0.60 –0.55
Figure 33. Supply Current with RF Applied (IDD) vs. VGG1, VDD = 5 V,
Representative of a Typical Device
120
27
25
100
23
80
19
60
5mA
15mA
25mA
35mA
45mA
65mA
70mA
75mA
80mA
40
17
3V
4V
5V
6V
7V
0
2
4
6
8
20
10
FREQUENCY (GHz)
0
–10
15093-031
15
0
5
15
Figure 34. Supply Current with RF Applied (IDD) vs. Input Power for
Various Supply Currents (IDQ), VDD = 5 V
40
20
35
18
30
16
20
14
12
5mA
15mA
25mA
35mA
45mA
65mA
70mA
75mA
80mA
15
10
10
3V
4V
5V
6V
7V
0
1
2
3
4
5
6
7
8
9
10
8
11
FREQUENCY (GHz)
Figure 32. Output IP3 vs. Frequency for Various Supply Voltages,
POUT/Tone = 5 dBm
6
–10
15093-032
5
–5
0
5
INPUT POWER (dBm)
10
15
15093-035
GAIN (dB)
25
0
10
INPUT POWER (dBm)
Figure 31. PSAT vs. Frequency for Various Supply Voltages, IDQ = 65 mA
OUTPUT IP3 (dBm)
–5
15093-034
IDD (mA)
21
13
–0.50 –0.45
VGG1 (V)
Figure 30. P1dB vs. Frequency for Various Supply Voltages, IDQ = 65 mA
PSAT (dBm)
–0.80 –0.75
15093-033
0
10
15093-030
11
20
3V
4V
5V
6V
7V
13
Figure 35. Gain vs. Input Power for Various Supply Currents (IDQ) at 5 GHz,
VDD = 5 V
Rev. 0 | Page 11 of 16
HMC8410CHIPS
Data Sheet
THEORY OF OPERATION
The HMC8410CHIPS is a GaAs, MMIC, pHEMT, low noise
wideband amplifier.
The cascode amplifier uses a fundamental cell of two field effect
transistors (FETs) in series, source to drain. The basic schematic
for the cascode cell is shown in Figure 36, which forms a low
noise amplifier operating from 0.01 GHz to 10 GHz with excellent
noise figure performance.
The input and output impedances are sufficiently stable vs.
variations in temperature and supply voltage so that no impedance
matching compensation is required.
15093-036
RFOUT/VDD
RFIN/VGG1
The HMC8410CHIPS has single-ended input and output ports
whose impedances are nominally equal to 50 Ω over the 0.01 GHz
to 10 GHz frequency range. Consequently, it can directly insert
into a 50 Ω system with no required impedance matching
circuitry, which also means that multiple HMC8410CHIPS
amplifiers can be cascaded back to back without the need for
external matching circuitry.
To achieve optimal performance from the HMC8410CHIPS and
prevent damage to the device, do not exceed the absolute
maximum ratings.
Figure 36. Basic Schematic for the Cascode Cell
Rev. 0 | Page 12 of 16
Data Sheet
HMC8410CHIPS
APPLICATIONS INFORMATION
Figure 39 shows the basic connections for operating the
HMC8410CHIPS. The data taken herein used wideband bias
tees on the input and output ports to provide both ac coupling and
the necessary supply voltages to the RFIN/VGG1 and RFOUT/VDD
pins. A 5 V dc drain bias is supplied to the amplifier through
the choke inductor connected to the RFOUT/VDD pin, and the
−2 V gate bias voltage is supplied to the RFIN/VGG1 pin through
the choke inductor. The RF signal must be ac-coupled to prevent
disrupting the dc bias applied to RFIN/VGG1 and RFOUT/VDD.
The nonideal characteristics of ac coupling capacitors and
choke inductors (for example, self resonance) can introduce
performance trade-offs that must be considered when using a
single application circuit across a very wide frequency range.
RECOMMENDED BIAS SEQUENCING
The recommended bias sequence during power-up is as follows:
To bring the radio frequency to and from the chip, implementing
50 Ω transmission lines using a microstrip or coplanar waveguide
on 0.127 mm (5 mil) thick alumina, thin film substrates is recommended (see Figure 37). When using 0.254 mm (10 mil) thick
alumina, it is recommended that the die be raised to ensure that
the die and substrate surfaces are coplanar. Raise the die 0.150 mm
(6 mil) to ensure that the surface of the die is coplanar with the
surface of the substrate. To accomplish this, attach the 0.102 mm
(4 mil) thick die to a 0.150 mm (6 mil) thick, molybdenum (Mo)
heat spreader (moly tab), which can then be attached to the
ground plane (see Figure 37 and Figure 38).
Connect to GND.
Set RFIN/VGG1 to −2 V.
Set RFOUT/VDD to 5 V.
Increase RFIN/VGG1 to achieve a typical supply current
(IDQ) = 65 mA.
Apply the RF signal.
0.102mm (0.004") THICK GaAs MMIC
WIRE BOND
0.076mm
(0.003")
The recommended bias sequence during power-down is as
follows:
1.
2.
3.
4.
RF GROUND PLANE
Turn off the RF signal.
Decrease RFIN/VGG1 to −2 V to achieve a typical IDQ = 0 mA.
Decrease RFOUT/VDD to 0 V.
Increase RFIN/VGG1 to 0 V.
0.127mm (0.005") THICK ALUMINA
THIN FILM SUBSTRATE
15093-037
5.
Attach the die directly to the ground plane eutectically or with
conductive epoxy (see the Handling Precautions section).
Figure 37. Die Without the Moly Tab
The bias conditions previously listed (RFOUT/VDD = 5 V and
IDQ = 65 mA) are the recommended operating conditions to
achieve optimum performance. The data used in this data sheet
was taken with the recommended bias conditions. When using
the HMC8410CHIPS with different bias conditions, different
performance than that shown in the Typical Performance
Characteristics section may result.
0.102mm (0.004") THICK GaAs MMIC
WIRE BOND
0.076mm
(0.003")
Figure 29, Figure 30, and Figure 31 show that increasing the
voltage from 3 V to 7 V typically increases P1dB and PSAT at the
expense of power consumption with minor degradation on
noise figure (NF).
RF GROUND PLANE
0.150mm (0.005") THICK
MOLY TAB
0.254mm (0.010") THICK ALUMINA
THIN FILM SUBSTRATE
15093-038
1.
2.
3.
4.
MOUNTING AND BONDING TECHNIQUES FOR
MILLIMETERWAVE GaAs MMICS
Figure 38. Die With the Moly Tab
Place microstrip substrates as close to the die as possible to
minimize bond wire length. Typical die to substrate spacing is
0.076 mm to 0.152 mm (3 mil to 6 mil).
Rev. 0 | Page 13 of 16
HMC8410CHIPS
Data Sheet
Handling Precautions
To avoid permanent damage, follow these storage, cleanliness,
static sensitivity, transient, and general handling precautions:
•
•
Place all bare die in either waffle or gel-based ESD
protective containers and then seal the die in an ESD
protective bag for shipment. After the sealed ESD
protective bag is opened, store all die in a dry nitrogen
environment.
Handle the chips in a clean environment. Do not attempt
to clean the chip using liquid cleaning systems.
•
•
•
Rev. 0 | Page 14 of 16
Follow ESD precautions to protect against ESD strikes.
While bias is applied, suppress instrument and bias supply
transients. Use shielded signal and bias cables to minimize
inductive pickup.
Handle the chip along the edges with a vacuum collet or
with a sharp pair of bent tweezers. The surface of the chip
may have fragile air bridges and must not be touched with
a vacuum collet, tweezers, or fingers.
Data Sheet
HMC8410CHIPS
APPLICATION CIRCUIT
VDD
RFIN
1
EXTERNAL BIAS TEE
RFOUT
2
EXTERNAL BIAS TEE
15093-039
VGG1
Figure 39. Application Circuit
ASSEMBLY DIAGRAM
3mil NOMINAL GAP
RFOUT/VDD
RFIN/VGG1
Figure 40. Assembly Diagram
Rev. 0 | Page 15 of 16
15093-040
50Ω
TRANSMISSION
LINE
HMC8410CHIPS
Data Sheet
OUTLINE DIMENSIONS
0.950
0.159
0.630
ADI 2015
0.102
0.162
0.186
0.610
2
0.162
0.248
1
0.165
0.099
0.078
SIDE VIEW
10-20-2016-A
TOP VIEW
0.779
Figure 41. 2-Pad Bare Die [CHIP]
(C-2-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
HMC8410CHIPS
HMC8410CHIPS-SX
1
Temperature Range
−55°C to +85°C
−55°C to +85°C
Package Description
2-Pad Bare Die [CHIP]
2-Pad Bare Die [CHIP]
The HMC8410CHIPS and HMC8410CHIPS-SX are RoHS Compliant Parts.
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D15093-0-10/16(0)
Rev. 0 | Page 16 of 16
Package Option
C-2-3
C-2-3