Hanbit HDD64M72D18RPW Ddr sdram module 512mbyte (64mx72bit), based on 32mx8, 4banks, 8k ref., 184pin-dimm with pll & register Datasheet

HANBit
HDD64M72D18RPW
DDR SDRAM Module 512Mbyte (64Mx72bit), based on 32Mx8, 4Banks, 8K
Ref., 184Pin-DIMM with PLL & Register
Part No. HDD64M72D18RPW
GENERAL DESCRIPTION
The HDD64M72D18RPW is a 64M x 72 bit Double Data Rate(DDR) Synchronous Dynamic RAM high-density memory
module. The module consists of eighteen CMOS 32M x 8 bit with 4banks DDR SDRAMs in 66pin TSOP-II 400mil packages
and 2K EEPROM in 8-pin TSSOP package on a 184-pin glass-epoxy. Four 0.1uF decoupling capacitors are mounted on
the printed circuit board in parallel for each DDR SDRAM. The HDD64M72D18RPW is a DIMM( Dual in line Memory
Module) .Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible
on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allows the same device
to be useful for a variety of high bandwidth, high performance memory system applications. All module components may be
powered from a single 2.5V DC power supply and all inputs and outputs are SSTL_2 compatible.
FEATURES
• Part Identification
HDD64M72D18RPW – 10A :
100MHz (CL=2)
HDD64M72D18RPW – 13A : 133MHz (CL=2)
HDD64M72D18RPW – 13B :
133MHz (CL=2.5)
• 512MB(64Mx72) Registered DDR DIMM based on 32Mx8 DDR SDRAM
• 2.5V ± 0.2V VDD and VDDQ power supply
• Auto & self refresh capability (8K Cycles / 64ms)
• All input and output are compatible with SSTL_2 interface
• Data(DQ), Data strobes and write masks latched on the rising and falling edges of the clock
• All Addresses and control inputs except Data(DQ), Data strobes and Data masks latched on the rising edges of the clock
• MRS cycle with address key programs
- Latency (Access from column address) : 2, 2.5
- Burst length : 2, 4, 8
- Data scramble : Sequential & Interleave
• Data(DQ), Data strobes and write masks latched on the rising and falling edges of the clock
• All Addresses and control inputs except Data(DQ), Data strobes and Data masks latched on the rising edges of the clock
• The used device is 8M x 8bit x 4Banks DDR SDRAM
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REV 1.0 (August.2002)
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HDD64M72D18RPW
PIN ASSIGNMENT
PIN
Front
PIN
Back
PIN
Frontl
1
VREF
2
DQ0
32
A5
62
VDDQ
33
DQ24
63
/WE
3
VSS
34
VSS
64
DQ41
PIN
Back
PIN
Front
PIN
Back
93
VSS
124
VSS
154
/RAS
94
DQ4
125
A6
155
DQ45
95
DQ5
126
DQ28
156
VDDQ
4
DQ1
35
DQ25
65
/CAS
96
VDDQ
127
DQ29
157
/CS0
5
DQS0
36
DQS3
66
VSS
97
DM0
128
VDDQ
158
/CS1
6
DQ2
37
A4
67
DQS5
98
129
DM3
159
DM5
7
VDD
38
VDD
68
DQ42
99
DQ7
130
A3
160
VSS
8
DQ3
39
DQ26
69
DQ43
100
VSS
131
DQ30
161
DQ46
9
NC
40
DQ27
70
VDD
101
NC
132
VSS
162
DQ47
10
/RESET
41
A2
71
* /CS2
102
NC
133
DQ31
163
* /CS3
11
VSS
42
VSS
72
DQ48
103
*A13
134
CB4
164
VDDQ
12
DQ8
43
A1
73
DQ49
104
VDDQ
135
CB5
165
DQ52
13
DQ9
44
CB0
74
VSS
105
DQ12
136
VDDQ
166
DQ53
14
DQS1
45
CB1
75
* CK2
106
DQ13
137
CK0
167
NC
15
VDDQ
46
VDD
76
* /CK2
107
DM1
138
/CK0
168
VDD
DQ6
16
* CK1
47
DQS8
77
VDDQ
108
VDD
139
VSS
169
DM6
17
* /CK1
48
A0
78
DQS6
109
DQ14
140
DM8
170
DQ54
18
VSS
49
CB2
79
DQ50
110
DQ15
141
A10
171
DQ55
19
DQ10
50
VSS
80
DQ51
111
CKE1
142
CB6
172
VDDQ
20
DQ11
51
CB3
81
VSS
112
VDDQ
143
VDDQ
173
NC
21
CKE0
52
BA1
82
VDDID
113
* BA2
144
CB7
174
DQ60
22
VDDQ
83
DQ56
114
DQ20
175
DQ61
23
DQ16
53
DQ32
84
DQ57
115
A12
145
VSS
176
VSS
24
DQ17
54
VDDQ
85
VDD
116
VSS
146
DQ36
177
DM7
25
DQS2
55
DQ33
86
DQS7
117
DQ21
147
DQ37
178
DQ62
26
VSS
56
DQS4
87
DQ58
118
A11
148
VDD
179
DQ63
27
A9
57
DQ34
88
DQ59
119
DM2
149
DM4
180
VDDQ
28
DQ18
58
VSS
89
VSS
120
VDD
150
DQ38
181
SA0
KEY
KEY
29
A7
59
BA0
90
NC
121
DQ22
151
DQ39
182
SA1
30
VDDQ
60
DQ35
91
SDA
122
A8
152
VSS
183
SA2
31
DQ19
61
DQ40
92
SCL
123
DQ23
153
DQ44
184
VDDSPD
*These pins should be NC in the system which does not support SPD
PIN
PIN DESCRIPTION
PIN
PIN DESCRIPTION
A0~A12
Address input
VDD
Power supply(2.5V)
BA0~BA1
Bank Select Address
VDDQ
Power supply for DQs(2.5V)
DQ0~DQ63
Data input/output
VREF
Power supply for reference
Serial EEPROM Power supply(3.3)
CB0~CB7
Check Bit
VDDSPD
DQS0~DQS8
Data Strobe input/output
VSS
Ground
DM0~DM8
Data-in Mask
SA0~SA2
Address in EEPROM
CK0~/CK0
Clock input
SDA
Serial data I/O
CKE0~CKE1
Clock enable input
SCL
Serial clock
/CS0~/CS1
Chip Select input
VDDID
VDD identification flag
/RAS
Row Address strobe
NC
No connection
/CAS
Column Address strobe
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REV 1.0 (August.2002)
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HDD64M72D18RPW
FUNCTIONAL BLOCK DIAGRAM
/RCS1
/RCS0
Notes:
/RCS0
/RCS1
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REV 1.0 (August.2002)
1. DQ-to-I/O wiring may be changed within a byte.
2. DQ/DQS/DM/CKE/S relationships must be
maintained as shown.
3. DQ/DQS resistors should be 22 Ohms.
4. VDDID strap connections
(for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD ≠ VDDQ.
5. RS0 and RS1 alternate between the back and front
sides of the DIMM.
6.Address and control resistors should be 22 Ohms.
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HDD64M72D18RPW
PIN FUNCTION DESCRIPTION
Pin
CK, /CK
Name
Clock
Input Function
CK and CK are differential clock inputs. All address and control input signals are
sam-pled on the positive edge of CK and negative edge of CK. Output (read) data
is referenced to both edges of CK. Internal clock signals are derived from CK/CK.
CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device
input buffers and output drivers. Deactivating the clock provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE
POWER-DOWN(row ACTIVE in any bank). CKE is synchronous for all functions
CKE
Clock Enable
except for disabling outputs, which is achieved asynchronously. Input buffers,
excluding CK, CK and CKE are disabled during power-down and self refresh
modes, providing low standby power. CKE will recognizean LVCMOS LOW level
prior to VREF being stable on power-up.
CS enables(registered LOW) and disables(registered HIGH) the command
decoder.
/CS
Chip Select
All commands are masked when CS is registered HIGH. CS provides for external
bank selection on systems with multiple banks. CS is considered part of the
command code.
Row/column addresses are multiplexed on the same pins.
A0 ~ A12
Address
BA0 ~ BA1
Bank select address
Row address : RA0 ~ RA12, Column address : CA0 ~ CA9
BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRE-CHARGE
command is being applied.
Latches row addresses on the positive going edge of the CLK with /RAS low.
/RAS
Row address strobe
/CAS
Column address strobe
/WE
Write enable
DQS0~8
Data Strobe
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with /CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from /CAS, /WE active.
Output with read data, input with write data. Edge-aligned with read data, centered in write data. Used to capture write data.
DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH along with that input data during a WRITE access. DM is sampled
DM0~8
Input Data Mask
on both edges of DQS. DM pins include dummy loading internally, to matches the
DQ and DQS load-ing.
DQ0 ~ 63
Data input/output
Data inputs/outputs are multiplexed on the same pins.
CB0~CB7
Check Bit
Check Bit Input/Output pins
VDDQ
Supply
DQ Power Supply : +2.5V ± 0.2V.
VDD
Supply
Power Supply : +2.5V ± 0.2V (device specific).
VSS
Supply
DQ Ground.
VREF
Supply
SSTL_2 reference voltage.
VDDSPD
Supply
Serial EEPROM Power Supply : 3.3v
VDDID
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REV 1.0 (August.2002)
VDD identification Flag
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HDD64M72D18RPW
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNTE
VIN, VOUT
-0.5 ~ 3.6
V
Voltage on VDD supply relative to Vss
VDD
-1.0 ~ 3.6
V
Voltage on VDDQ supply relative to Vss
VDDQ
-0.5 ~ 3.6
V
Storage temperature
TSTG
-55 ~ +150
°C
PD
18
W
Voltage on any pin relative to Vss
Power dissipation
Short circuit current
IOS
50
Notes: Operation at above absolute maximum rating can adversely affect device reliability
mA
DC OPERATING CONDITIONS
(Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70°C) )
PARAMETER
Supply Voltage
I/O Supply Voltage
I/O Reference Voltage
SYMBOL
MIN
MAX
UNIT
NOTE
VDD
2.3
2.7
V
VDDQ
2.3
2.7
V
VREF
VDDQ/2 - 50mA
VDDQ/2 +
V
1
50mA
VTT
VREF – 0.04
VREF + 0.04
V
2
Input High Voltage
VIH (DC)
VREF + 0.15
VREF + 0.3
V
4
Input Low Voltage
VIL (DC)
-0.3
VREF - 0.15
V
4
Input Voltage Level, CK and /CK inputs
VIN (DC)
-0.3
VDDQ + 0.3
V
Input Differential Voltage, CK and /CK inputs
VID (DC)
0.3
VDDQ + 0.6
V
3
Input crossing point Voltage, CK and /CK
VIX (DC)
1.15
1.35
V
5
Input leakage current
I LI
-2
2
uA
Output leakage current
I OZ
-5
5
uA
Output High current (VOUT = 1.95V)
I OH
-16.8
mA
Output Low current (VOUT = 0.35V)
I OL
16.8
mA
I/O Termination Voltage(system)
inputs
Notes :
1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC
offset on VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and
internal DRAM noise coupled to VREF , both of which may result in VREF noise. VREF should be de-coupled with an
inductance of ≤ 3nH.
2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set
equal to VREF, and must track variations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the
pad in simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited
to 200MHZ.
5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of
the same.
6. These charactericteristics obey the SSTL-2 class II standards.
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REV 1.0 (August.2002)
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CAPACITANCE
HDD64M72D18RPW
(VDD = min to max, VDDQ = 2.5V to 2.7V, TA = 25°C, f = 100MHz)
DESCRIPTION
SYMBOL
MIN
MAX
UNITS
Input capacitance(A0~A12, BA0~BA1, /RAS, /CAS,/WE)
CIN1
-
12
pF
Input capacitance(CKE0,CKE1)
CIN2
-
12
pF
Input capacitance(/CS0,/CS1)
CIN3
-
11
pF
Input capacitance(CK0~/CK1)
CIN4
-
12
pF
Input capacitance(DM0~DM8)
CIN5
-
16
pF
16
pF
16
pF
Data & DQS input/output capacitance (DQ0 ~ DQ63,
COUT1
-
DQS0~DQS8)
Data input/output capacitance (CB0~CB7))
COUT2
-
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, VDD = 2.5V, T =25°C)
Symbo
TEST
l
Condition
Operating current
(One bank
active-Precharge)
IDD0
tRC ≥ tRC(min), tCK=100MHz for DDR200,133MHz for
DDR266A & DDR266B
DQ,DM and DQS inputs changing twice per clock
cycle Address and control inputs changing once per
clock cycle
Operating current
(One bankOperation)
IDD1
Precharge
powerdown
standby current
IDD2P
pARAMETER
Precharge Floating
standby current
IDD2F
Precharge Quiet
Standby current
IDD2Q
version
Unit
-10A
-13A
-13B
1515
1695
1695
mA
One bank open, BL=4,Reads-Refer to the following
page for detailed test condition
1605
1875
1875
mA
All banks idle, power-down mode
CKE ≤ VIL(max), tCK=100MHz for DDR200,133MHz for
DDR266A & DDR266B VIN = VREF for DQ,DQS and
DM
885
1020
1020
mA
1020
1155
1155
mA
975
1110
1110
/CS≥ VIH(min), All banks idle
CKE ≥ VIH(min), tCK=100MHz for DDR200,133MHz for
DDR266A & DDR266B
Address and control inputs changing once per clock
cycle VIN = VREF for DQ,DQS and DM
/CS≥ VIH(min), All banks idle
CKE ≥ VIH(min), tCK=100MHz for DDR200,133MHz for
DDR266A & DDR266B Address and other control
inputs stable with keeping≥ VIH(min) or ≤ VIL(max)
VIN = VREF for DQ,DQS and DM
Active power-down
Mode standby current
IDD3P
One bank active; power-down mode;
CKE ≤ VIL(max), tCK=100MHz for DDR200,133MHz for
DDR266A & DDR266B VIN = VREF for DQ,DQS and
DM.
1020
1155
1155
mA
IDD3N
CS# >= VIH(min), CKE>=VIH(min)
one bank active, active – precharge, tRC=tRASmax
tCK = 100Mhz for DDR200, 133Mhz for DDR266A
& DDR266B, DQ, DQS and DM inputs changing
twice per clock cycle Address and other control
inputs changing once per clock cycle
1110
1290
1290
mA
Active standby
current
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REV 1.0 (August.2002)
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HDD64M72D18RPW
Operating current
(burst read)
IDD4R
BL = 2, reads, continuous burst
One bank open, Address and control inputs
changing once per clock cycle, IOUT = 0mA
2055
2415
2415
mA
Operating current
(Bust write)
IDD4W
BL = 2, write, continuous burst
One bank open, Address and control inputs
changing once per clock cycle
2415
2955
2955
mA
Auto refresh current
IDD5
tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz,
distributed refresh
Self
refresh
current
IDD6
CKE =< 0.2V, External clock should be on
tCK = 100Mhz for DDR200, 133Mhz for DDR266A
& DDR266B
mA
2055
2415
2415
354
354
354
327
327
327
Four bank interleaving with BL=4
-Refer to the following page for detailed test
3315
condition
Notes: Operation at above absolute maximum rating can adversely affect device reliability
3945
3945
Normal
Low Power
Operating current
(Four bank operation)
IDD7A
mA
mA
AC OPERATING CONDITIONS
PARAMETER
STMBOL
MIN
Input High (Logic 1) Voltage, DQ, DQS and DM signals
VIH (AC)
VREF + 0.31
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
VIL (AC)
Input Differential Voltage, CK and CK inputs
VID (AC)
Input Crossing Point Voltage, CK and CK inputs
VIX (AC)
MAX
UNIT
NOTE
3
VREF - 0.31
V
3
0.7
VDDQ+0.6
V
1
0.5*VDDQ-0.2
0.5*VDDQ+0.2
V
2
Notes:
1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of VIX is expected to equal 0.5* VDDQ of the transmitting device and must track variations in the DC level
of the same
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the
pad in
simula-tion. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited
20MHz.
AC OPERATING TEST CONDITIONS
PARAMETER
VALUE
UNIT
Input reference voltage for Clock
0.5 * VDDQ
V
Input signal maximum peak swing
1.5
V
Input signal minimum slew rate
1.0
V
VREF+0.35/VREF
V
Input timing measurement reference level
VREF
V
Output timing measurement reference level
VTT
V
See Load Circuit
V
Input Levels(VIH/VIL)
Output load condition
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REV 1.0 (August.2002)
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HDD64M72D18RPW
AC CHARACTERISTICS (These AC charicteristics were tested on the Component)
PARAMETER
DDR200
DDR266A
DDR266B
-10A
-13A
-13B
SYMBOL
MIN
MAX
MIN
MAX
MIN
UNIT
NOTE
MAX
Row cycle time
tRC
70
65
65
ns
1
Refresh row cycle time
tRFC
80
75
75
ns
1,2
Row active time
tRAS
48
ns
1,2
/RAS to /CAS delay
tRCD
20
20
20
ns
3
Row precharge time
tRP
20
20
20
ns
3
Row active to Row active delay
tRRD
15
15
15
ns
3
Write recovery time
tWR
2
2
2
tCK
3
Last data in to Read command
tCDLR
1
1
1
tCK
2
Col. address to Col. address delay
tCCD
1
1
1
tCK
CL=2.0
Clock cycle time
120K
10
45
120K
45
120K
12
7.5
12
10
12
ns
12
7.5
12
7.5
12
ns
tCK
CL=2.5
Clock high level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Clock low level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
tDQSCK
-0.8
+0.8
-0.75
+0.75
-0.75
+0.75
ns
Output data access time from CK/CK
tAC
-0.8
+0.8
-0.75
+0.75
-0.75
+0.75
ns
Data strobe edge to ouput data edge
tDQSQ
-
+0.6
-
+0.5
-
+0.5
ns
Read Preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
tCK
Read Postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
DQS-out access time from CK/CK
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Data out high impedence time from
tHZQ
-0.8
+0.8
-0.75
+0.75
-0.75
+0.75
ns
CK to valid DQS-in
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
tCK
DQS-in setup time
tWPRES
0
0
0
ns
DQS-in hold time
tWPREH
0.25
0.25
0.25
tCK
tDSS
0.2
0.2
0.2
tCK
tDSH
0.2
0.2
0.2
tCK
DQS-in high level width
tDQSH
0.35
0.35
0.35
tCK
DQS-in low level width
tDQSL
0.35
0.35
0.35
tCK
DQS-in cycle time
tDSC
0.9
Address and Control Input setup time
tIS
1.1
0.9
0.9
ns
Address and Control Input hold time
tIH
1.1
0.9
0.9
ns
Mode register set cycle time
tMRD
16
15
15
ns
DQ & DM setup time to DQS
tDS
0.6
0.5
0.5
ns
DQ & DM hold time to DQS
tDH
0.6
0.5
0.5
ns
DQ & DM input pulse width
tDIPW
2
1.75
1.75
ns
Power down exit time
tPDEX
10
10
10
ns
Exit self refresh to write command
tXSW
116
95
tXSA
80
Exit self refresh to read command
tXSR
200
200
200
Cycle
Refresh interval time
TREF
7.8
7.8
7.8
us
Output DQS valid window
TQH
0.35
0.35
0.35
tCK
DQS write postamble time
TWPST
0.25
0.25
0.25
tCK
2
CK-/CK
3
DQS-in falling edge to CK rising-setup
time
DQS-in falling edge to CK rising hold
time
1.1
Exit self refresh to bank active
0.9
1.1
75
0.9
1.1
tCK
ns
75
ns
command
Notes :
1.
2.
Maximum burst refresh of 8.
tHZQ transitions occurs in the same assess time windows as valid data transitions. These parameters are not
referenced to a specific voltage level, but specify when the device output is no longer driving.
3.
The specific requirement is that DQS be valid(High-Low) on or before this CK edge. The case shown(DQS going
from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was
in progress, DQS could be High at this time, depending on tDQSS.
4.
The maximum limit for this parameter is not a device limit. The device will operate with a great value for this
parameter, but system performance (bus turnaround) will degrade accordingly.
URL : www.hbe.co.kr
REV 1.0 (August.2002)
9
HANBit Electronics Co.,Ltd.
1
4
HANBit
HDD64M72D18RPW
SIMPLIFIED TRUTH TABLE
COMMAND
CK
E
n-1
CK
E
n
/CS
/R
A
S
/C
A
S
/WE
DM
BA
0,1
A10/
AP
A11,A12
A9~A0
NOTE
Register
Extended MRS
H
X
L
L
L
L
X
OP code
1,2
Register
Mode register set
H
X
L
L
L
L
X
OP code
1,2
L
L
L
H
X
X
L
H
H
H
H
X
X
X
Auto refresh
Refresh
Self
refresh
Entry
Exit
Bank active & row addr.
Read &
Auto
column
disable
address
Auto precharge eable
Write &
column
address
H
H
L
L
H
H
X
L
L
H
H
X
V
H
X
L
H
L
H
X
V
disable
Auto precharge
H
H
X
L
H
L
Precharg
Bank selection
e
All banks
active power down
Precharge power
down mode
H
X
L
H
H
L
X
H
X
L
L
H
L
X
H
X
X
X
L
V
V
V
X
X
X
X
Entry
H
L
Exit
L
H
Entry
H
L
Exit
L
H
DM
H
No operation command
H
H
X
X
X
L
H
H
H
H
X
X
X
V
V
V
L
X
X
H
X
X
X
L
H
H
H
X
3
Row address
Column
L
Address
4
H
(A0 ~A9)
4
L
Column
4
H
(A0 ~ A9)
V
L
enable
Burst Stop
X
3
3
X
precharge
Auto precharge
Clock suspend or
X
3
Address
X
V
L
X
H
4,6
7
X
5
X
X
X
X
X
V
X
X
X
8
(V=Valid, X=Don't care, H=Logic high, L=Logic low)
Notes :
1. OP Code : Operand code
A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges
(Write DM latency is 0)
URL : www.hbe.co.kr
REV 1.0 (August.2002)
10
HANBit Electronics Co.,Ltd.
HANBit
HDD64M72D18RPW
PACKAGING INFORMATION
Unit : mm
<Front– Side >
133.35 ± 0.20
U11
U1
U2
U3
U5
U4
U6
U7
U8
U9
30.48± 0.20
U12
A
B
< Rear – Side >
133.35 ± 0.20
U13
U22
U21
U20
U19
U18
U1
U17
U16
U15
U14
30.48± 0.20
0
***
PCB 두 께
: 1.27 ± 0.08 mm
URL : www.hbe.co.kr
REV 1.0 (August.2002)
11
HANBit Electronics Co.,Ltd.
HANBit
HDD64M72D18RPW
ORDERING INFORMATION
Part Number
Density
Org.
Package
Ref.
Vcc
8K
2.5V
8K
2.5V
8K
2.5V
Low Profile
HDD64M72D18RWP-10A
512MByte
64M x 72
184PIN
DIMM
Low Profile
HDD64M72D18RW-13A
512MByte
64M x 72
184PIN
DIMM
Low Profile
HDD64M72D18RW-13B
512MByte
64M x 72
184PIN
DIMM
URL : www.hbe.co.kr
REV 1.0 (August.2002)
12
MODE
Registered
DDR
Registered
DDR
MAX.frq
100MHz/CL2
133MHz/CL2
Registered
133MHz/CL2
DDR
.5
HANBit Electronics Co.,Ltd.