Winbond ISD2532S Single-chip, multiple-messages, voice record/playback device 32-, 40-, 48-, and 64-second duration Datasheet

ISD2532/40/48/64
SINGLE-CHIP, MULTIPLE-MESSAGES,
VOICE RECORD/PLAYBACK DEVICE
32-, 40-, 48-, AND 64-SECOND DURATION
-1-
Publication Release Date: June 2003
Revision 1.0
ISD2532/40/48/64
1. GENERAL DESCRIPTION
Winbond’s ISD2500 ChipCorder® Series provide high-quality, single-chip, Record/Playback solutions
for 32- to 64-second messaging applications. The CMOS devices include an on-chip oscillator,
microphone preamplifier, automatic gain control, antialiasing filter, smoothing filter, speaker amplifier,
and high density multi-level storage array. In addition, the ISD2500 is microcontroller compatible,
allowing complex messaging and addressing to be achieved. Recordings are stored into on-chip
nonvolatile memory cells, providing zero-power message storage. This unique, single-chip solution is
made possible through Winbond’s patented multilevel storage technology. Voice and audio signals
are stored directly into memory in their natural form, providing high-quality, solid-state voice
reproduction.
2. FEATURES
•
Single 5 volt power supply
•
Single-chip with duration of 32, 40, 48, or 64 seconds.
•
Easy-to-use single-chip, voice record/playback solution
•
High-quality, natural voice/audio reproduction
•
Manual switch or microcontroller compatible
•
Playback can be edge- or level-activated
•
Directly cascadable for longer durations
•
Automatic power-down (push-button mode)
- Standby current 1 µA (typical)
•
Zero-power message storage
- Eliminates battery backup circuits
•
Fully addressable to handle multiple messages
•
100-year message retention (typical)
•
100,000 record cycles (typical)
•
On-chip clock source
•
Programmer support for play-only applications
•
Available in die form, PDIP, SOIC and TSOP packaging
•
Temperature options: die (0°C to +50°C) and package (0°C to +70°C)
-2-
ISD2532/40/48/64
3. BLOCK DIAGRAM
Internal Clock
Timing
XCLK
Sampling Clock
Amp
5-Pole Active
Antialiasing Filter
ANA OUT
MIC
MIC REF
Analog Transceivers
Decoders
ANA IN
PreAmp
256K Cell
Nonvolatile
Multilevel Storage
Array
5-Pole Active
Smoothing Filter
SP +
Mux
Automatic
Gain Control
(AGC)
AGC
Power Conditioning
VCCA
VSSA VSSD VCCD
Amp
SP -
Device Control
Address Buffers
A0 A1 A2 A3 A4 A5 A6 A7 A8
-3-
PD
OVF
P/R
CE
EOM
AUX IN
Publication Release Date: June 2003
Revision 1.0
ISD2532/40/48/64
4. TABLE OF CONTENTS
1. GENERAL DESCRIPTION.................................................................................................................. 2
2. FEATURES ......................................................................................................................................... 2
3. BLOCK DIAGRAM .............................................................................................................................. 3
4. TABLE OF CONTENTS ...................................................................................................................... 4
5. PIN CONFIGURATION ....................................................................................................................... 5
6. PIN DESCRIPTION ............................................................................................................................. 6
7. FUNCTIONAL DESCRIPTION.......................................................................................................... 10
7.1. Detailed Description.................................................................................................................... 10
7.2. Operational Modes ..................................................................................................................... 11
7.2.1. Operational Modes Description............................................................................................ 12
8. TIMING DIAGRAMS.......................................................................................................................... 16
9. ABSOLUTE MAXIMUM RATINGS.................................................................................................... 19
9.1 Operating Conditions ................................................................................................................... 20
10. ELECTRICAL CHARACTERISTICS ............................................................................................... 21
10.1. Parameters For Packaged Parts .............................................................................................. 21
10.1.1. Typical Parameter Variation with Voltage and Temperature - Packaged Parts ................ 24
10.2. Parameters For Die .................................................................................................................. 25
10.2.1. Typical Parameter Variation with Voltage and Temperature - Die .................................... 28
10.3. Parameters For Push-Button Mode.......................................................................................... 29
11. TYPICAL APPLICATION CIRCUIT ................................................................................................. 30
12. PACKAGE DRAWING AND DIMENSIONS .................................................................................... 35
12.1. 28-Lead 300-Mil Plastic Small Outline IC (SOIC)..................................................................... 35
12.2. 28-Lead 600-Mil Plastic Dual Inline Package (PDIP) ............................................................... 36
12.3. 28-Lead 8x13.4mm Plastic Thin Small Outline Package (TSOP) Type 1 ................................ 37
12.4. Die Bonding Physical Layout [1] ................................................................................................ 38
14. VERSION HISTORY ....................................................................................................................... 41
-4-
ISD2532/40/48/64
5. PIN CONFIGURATION
A0/M 0
1
28
V CCD
A1/M 1
2
27
P/R
A2/M 2
3
26
XCLK
A3/M 3
4
25
EOM
A4/M 4
5
24
PD
A5/M 5
6
23
CE
A6/M 6
7
22
OVF
NC
8
21
ANA OUT
A7
9
20
ANA IN
A8
10
19
AGC
AUX IN
11
18
M IC REF
V SSD
12
17
M IC
V SSA
13
16
V CCA
SP +
14
15
SP-
ISD2532
ISD2540
ISD2548
ISD2564
SOIC/PDIP
OVF
CE
PD
EOM
XCLK
P/R
V CCD
A0/M 0
A1/M 1
A2/M 2
A3/M 3
A4M 4
A5/M 5
A6/M 6
1
28
2
27
3
26
25
4
5
6
7
8
9
10
11
ISD2532
ISD2340
ISD2548
ISD2564
24
23
22
21
20
19
18
12
17
13
16
14
15
ANA OUT
ANA IN
AGC
M IC REF
M IC
V CCA
SPSP+
V SSA
V SSD
AUX IN
A8
A7
NC
TSOP
-5-
Publication Release Date: June 2003
Revision 1.0
ISD2532/40/48/64
6. PIN DESCRIPTION
PIN NO.
FUNCTION
PIN NAME
SOIC /
PDIP
A0, A1, A2,
A3, A4, A5,
A6, A7, A8
1, 2, 3, 8, 9, 10, Address/Mode Inputs: The Address/Mode Inputs have two functions
4, 5, 6, 11, 12, 13, depending on the level of the two Most Significant Bits (MSB) of the
7, 9, 10 14, 16, 17 address pins A7 and A8.
/ M0, M1,
M2, M3,
M4, M5, M6
/ 1, 2,
3, 4,
5, 6, 7
TSOP
/ 8, 9,
10, 11,
12, 13, 14
If either or both of the two MSBs are LOW, the inputs are all interpreted
as address bits and are used as the start address for the current record
or playback cycle. The address pins are inputs only and do not output
any internal address information during the operation. Address inputs
are latched by the falling edge of CE .
If both MSBs are HIGH, the Address/Mode inputs are interpreted as
Mode bits according to the Operational Mode table on page 12. There
are six operational modes (M0…M6) available as indicated in the table.
It is possible to use multiple operational modes simultaneously.
Operational Modes are sampled on each falling edge of CE , and thus
Operational Modes and direct addressing are mutually exclusive.
NC
8
15
No Connect.
AUX IN
11
18
Auxiliary Input: The Auxiliary Input is multiplexed through to the output
amplifier and speaker output pins when CE is HIGH, P/ R is HIGH,
and playback is currently not active or if the device is in playback
overflow. When cascading multiple ISD2500 devices, the AUX IN pin is
used to connect a playback signal from a following device to the
previous output speaker drivers. For noise considerations, it is
suggested that the auxiliary input not be driven when the storage array
is active.
VSSA, VSSD
13, 12
20, 19
Ground: The ISD2500 series of devices utilizes separate analog and
digital ground busses. These pins should be connected separately
through a low-impedance path to power supply ground.
SP+, SP-
14, 15
21, 22
Speaker Outputs: All devices in the ISD2500 series include an on-chip
differential speaker driver, capable of driving 50 mW into 16 Ω from
AUX IN (12.2mW from memory).
[1]
The speaker outputs are held at VSSA levels during record and power
down. It is therefore not possible to parallel speaker outputs of multiple
ISD2500 devices or the outputs of other speaker drivers.
[2]
A single-end output may be used (including a coupling capacitor
between the SP pin and the speaker). These outputs may be used
individually with the output signal taken from either pin. However, the
use of single-end output results in a 1 to 4 reduction in its output power.
[1]
[2]
Connection of speaker outputs in parallel may cause damage to the device.
Never ground or drive an unused speaker output.
-6-
ISD2532/40/48/64
PIN NO.
PIN NAME
SOIC/
PDIP
TSOP
FUNCTION
VCCA, VCCD
16, 28
23, 7
Supply Voltage: To minimize noise, the analog and digital circuits
in the ISD2500 series devices use separate power busses. These
voltage busses are brought out to separate pins and should be tied
together as close to the supply as possible. In addition, these
supplies should be decoupled as close to the package as possible.
MIC
17
24
Microphone: The microphone pin transfers input signal to the onchip preamplifier. A built-in Automatic Gain Control (AGC) circuit
controls the gain of this preamplifier from –15 to 24dB. An external
microphone should be AC coupled to this pin via a series capacitor.
The capacitor value, together with the internal 10 KΩ resistance on
this pin, determines the low-frequency cutoff for the ISD2500 series
passband. See Winbond’s Application Information for additional
information on low-frequency cutoff calculation.
MIC REF
18
25
Microphone Reference: The MIC REF input is the inverting input
to the microphone preamplifier. This provides a noise-canceling or
common-mode rejection input to the device when connected to a
differential microphone.
AGC
19
26
Automatic Gain Control: The AGC dynamically adjusts the gain of
the preamplifier to compensate for the wide range of microphone
input levels. The AGC allows the full range of whispers to loud
sounds to be recorded with minimal distortion. The “attack” time is
determined by the time constant of a 5 KΩ internal resistance and
an external capacitor (C2 on the schematic of Figure 5 in section
11) connected from the AGC pin to VSSA analog ground. The
“release” time is determined by the time constant of an external
resistor (R2) and an external capacitor (C2) connected in parallel
between the AGC pin and VSSA analog ground. Nominal values of
470 KΩ and 4.7 µF give satisfactory results in most cases.
ANA IN
20
27
Analog Input: The analog input transfers analog signal to the chip
for recording. For microphone inputs, the ANA OUT pin should be
connected via an external capacitor to the ANA IN pin. This
capacitor value, together with the 3.0 KΩ input impedance of ANA
IN, is selected to give additional cutoff at the low-frequency end of
the voice passband. If the desired input is derived from a source
other than a microphone, the signal can be fed, capacitively
coupled, into the ANA IN pin directly.
-7-
Publication Release Date: June 2003
Revision 1.0
ISD2532/40/48/64
PIN NO.
PIN NAME
SOIC/
PDIP
TSOP
FUNCTION
ANA OUT
21
28
Analog Output: This pin provides the preamplifier output to the
user. The voltage gain of the preamplifier is determined by the
voltage level at the AGC pin.
OVF
22
1
Overflow: This signal pulses LOW at the end of memory array,
indicating the device has been filled and the message has
overflowed. The OVF output then follows the CE input until a
PD pulse has reset the device. This pin can be used to cascade
several ISD2500 devices together to increase record/playback
durations.
CE
23
2
Chip Enable: The CE input pin is taken LOW to enable all
playback and record operations. The address pins and
playback/record pin (P/ R ) are latched by the falling edge of CE .
CE has additional functionality in the M6 (Push-Button)
Operational Mode as described in the Operational Mode section.
PD
24
3
Power Down: When neither record nor playback operation, the PD
pin should be pulled HIGH to place the part in standby mode (see
ISB specification). When overflow ( OVF ) pulses LOW for an
overflow condition, PD should be brought HIGH to reset the
address pointer back to the beginning of the memory array. The PD
pin has additional functionality in the M6 (Push-Button) Operation
Mode as described in the Operational Mode section.
EOM
25
4
End-Of-Message: A nonvolatile marker is automatically inserted at
the end of each recorded message. It remains there until the
message is recorded over. The EOM output pulses LOW for a
period of TEOM at the end of each message.
In addition, the ISD2500 series has an internal VCC detect circuit to
maintain message integrity should VCC fall below 3.5V. In this case,
EOM goes LOW and the device is fixed in Playback-only mode.
When the device is configured in Operational Mode M6 (PushButton Mode), this pin provides an active-HIGH signal, indicating
the device is currently recording or playing. This signal can
conveniently drive an LED for visual indicator of a record or
playback operation in process.
-8-
ISD2532/40/48/64
PIN NO.
PIN NAME
SOIC/
PDIP
TSOP
FUNCTION
XCLK
26
5
External Clock: The external clock input has an internal pull-down
device. The device is configured at the factory with an internal
sampling clock frequency centered to ±1 percent of specification.
The frequency is then maintained to a variation of ±2.25 percent
over the entire commercial temperature and operating voltage
ranges. If greater precision is required, the device can be clocked
through the XCLK pin as follows:
Part Number
Sample Rate
Required Clock
ISD2532
8.0 kHz
1024 kHz
ISD2540
6.4 kHz
819.2 kHz
ISD2548
5.3 kHz
682.7 kHz
ISD2564
4.0 kHz
512 kHz
These recommended clock rates should not be varied because the
antialiasing and smoothing filters are fixed, and aliasing problems
can occur if the sample rate differs from the one recommended.
The duty cycle on the input clock is not critical, as the clock is
immediately divided by two. If the XCLK is not used, this input
must be connected to ground.
P/ R
27
6
Playback/Record: The P/ R input pin is latched by the falling edge
of the CE pin. A HIGH level selects a playback cycle while a LOW
level selects a record cycle. For a record cycle, the address pins
provide the starting address and recording continues until PD or
CE is pulled HIGH or an overflow is detected (i.e. the chip is full).
When a record cycle is terminated by pulling PD or CE HIGH,
then End-Of-Message ( EOM ) marker is stored at the current
address in memory. For a playback cycle, the address inputs
provide the starting address and the device will play until an EOM
marker is encountered. The device can continue to pass an EOM
marker if CE is held LOW in address mode, or in an Operational
Mode. (See Operational Modes section)
-9-
Publication Release Date: June 2003
Revision 1.0
ISD2532/40/48/64
7. FUNCTIONAL DESCRIPTION
7.1. DETAILED DESCRIPTION
Speech/Sound Quality
The Winbond’s ISD2500 series includes devices offered at 4.0, 5.3, 6.4, and 8.0 kHz sampling
frequencies, allowing the user a choice of speech quality options. Increasing the duration within a
product series decreases the sampling frequency and bandwidth, which affects the sound quality.
Please refer to the ISD2532/40/48/64 Product Summary table below to compare the duration,
sampling frequency and filter pass band.
The speech samples are stored directly into the on-chip nonvolatile memory without any digitization
and compression associated like other solutions. Direct analog storage provides a very true, natural
sounding reproduction of voice, music, tones, and sound effects not available with most solid state
digital solutions.
Duration
To meet various system requirements, the ISD2532/40/48/64 products offer single-chip solutions at
32, 40, 48, and 64 seconds. Parts may also be cascaded together for longer durations.
TABLE 1: ISD2532/40/48/64 PRODUCT SUMMARY
Part Number
Duration
(Seconds)
Input Sample
Rate (kHz)
Typical Filter Pass
Band * (kHz)
ISD2532
32
8.0
3.4
ISD2540
40
6.4
2.7
ISD2548
48
5.3
2.3
ISD2564
64
4.0
1.7
*
3dB roll off point. This parameter is not checked during production testing and may vary due
to process variations and other factors. Therefore, customer should not rely on this value for
testing purposes.
EEPROM Storage
One of the benefits of Winbond’s ChipCorder® technology is the use of on-chip nonvolatile memory,
providing zero-power message storage. The message is retained for up to 100 years typically without
power. In addition, the device can be re-recorded typically over 100,000 times.
Microcontroller Interface
In addition to its simplicity and ease of use, the ISD2500 series includes all the interfaces necessary
for microcontroller-driven applications. The address and control lines can be interfaced to a
microcontroller and manipulated to perform a variety of tasks, including message assembly, message
concatenation, predefined fixed message segmentation, and message management.
- 10 -
ISD2532/40/48/64
Programming
The ISD2500 series is also ideal for playback-only applications, where single or multiple messages
are referenced through buttons, switches, or a microcontroller. Once the desired message
configuration is created, duplicates can easily be generated via a gang programmer.
7.2. OPERATIONAL MODES
The ISD2500 series is designed with several built-in Operational Modes that provide maximum
functionality with minimum external components. These modes are described in details as below. The
Operational Modes are accessed via the address pins and mapped beyond the normal message
address range. When the two Most Significant Bits (MSB), A7 and A8, are HIGH, the remaining
address signals are interpreted as mode bits and not as address bits. Therefore, Operational Modes
and direct addressing are not compatible and cannot be used simultaneously.
There are two important considerations for using Operational Modes. First, all operations begin initially
at address 0 of its memory. Later operations can begin at other address locations, depending on the
Operational Mode(s) chosen. In addition, the address pointer is reset to 0 when the device is changed
from record to playback, playback to record (except M6 mode), or when a Power-Down cycle is
executed.
Second, Operational Modes are executed when CE goes LOW. This Operational Mode remains in
effect until the next LOW-going CE signal, at which point the current mode(s) are sampled and
executed.
TABLE 2: OPERATIONAL MODES
Mode
[1]
Function
Jointly Compatible [2]
Typical Use
M0
Message cueing
Fast-forward through messages
M4, M5, M6
M1
Delete EOM markers
Position EOM marker at the end of
the last message
M3, M4, M5, M6
M2
Not applicable
Reserved
N/A
M3
Looping
Continuous playback from Address 0
M1, M5, M6
M4
Consecutive
addressing
Record/playback multiple
consecutive messages
M0, M1, M5
M5
CE level-activated
Allows message pausing
M0, M1, M3, M4
M6
Push-button control
Simplified device interface
M0, M1, M3
[1]
Besides mode pin needed to be “1”, A7 and A8 pin are also required to be “1” in order to enter into the related operational
mode.
[2]
Indicates additional Operational Modes which can be used simultaneously with the given mode.
- 11 -
Publication Release Date: June 2003
Revision 1.0
ISD2532/40/48/64
7.2.1. Operational Modes Description
The Operational Modes can be used in conjunction with a microcontroller, or they can be hardwired to
provide the desired system operation.
M0 – Message Cueing
Message Cueing allows the user to skip through messages, without knowing the actual physical
addresses of each message. Each CE LOW pulse causes the internal address pointer to skip to the
next message. This mode is used for playback only, and is typically used with the M4 Operational
Mode.
M1 – Delete EOM Markers
The M1 Operational Mode allows sequentially recorded messages to be combined into a single
message with only one EOM marker set at the end of the final message. When this Operational
Mode is configured, messages recorded sequentially are played back as one continuous message.
M2 – Unused
When Operational Modes are selected, the M2 pin should be LOW.
M3 – Message Looping
The M3 Operational Mode allows for the automatic, continuously repeated playback of the message
located at the beginning of the address space. A message can completely fill the ISD2500 device and
will loop from beginning to end without OVF going LOW.
M4 – Consecutive Addressing
During normal operation, the address pointer will reset when a message is played through an EOM
marker. The M4 Operational Mode inhibits the address pointer reset on EOM , allowing messages to
be played back consecutively.
M5 - CE -Level Activated
The default mode for ISD2500 devices is for CE to be edge-activated on playback and levelactivated on record. The M5 Operational Mode causes the CE pin to be interpreted as levelactivated as opposed to edge-activated during playback. This is especially useful for terminating
playback operations using the CE signal. In this mode, CE LOW begins a playback cycle, at the
beginning of the device memory. The playback cycle continues as long as CE is held LOW. When
CE goes HIGH, playback will immediately end. A new CE LOW will restart the message from the
beginning unless M4 is also HIGH.
- 12 -
ISD2532/40/48/64
M6 – Push-Button Mode
The ISD2500 series contain a Push-Button Operational Mode. The Push-Button Mode is used
primarily in very low-cost applications and is designed to minimize external circuitry and components,
thereby reducing system cost. In order to configure the device in Push-Button Operational Mode, the
two most significant address bits must be HIGH, and the M6 mode pin must also be HIGH. A device in
this mode always powers down at the end of each playback or record cycle after CE goes HIGH.
When this operational mode is implemented, three of the pins on the device have alternate
functionality as described in the table below.
TABLE 3: ALTERNATE FUNCTIONALITY IN PINS
Pin Name
Alternate Functionality in Push-Button Mode
CE
Start/Pause Push-Button (LOW pulse-activated)
PD
Stop/Reset Push-Button (HIGH pulse-activated)
EOM
Active-HIGH Run Indicator
CE (START/PAUSE)
In Push-Button Operational Mode, CE acts as a LOW-going pulse-activated START/PAUSE signal.
If no operation is currently in progress, a LOW-going pulse on this signal will initiate a playback or
record cycle according to the level on the P/ R pin. A subsequent pulse on the CE pin, before an
EOM is reached in playback or an overflow condition occurs, will pause the current operation, and
the address counter is not reset. Another CE pulse will cause the device to continue the operation
from the place where it is paused.
PD (STOP/RESET)
In Push-Button Operational Mode, PD acts as a HIGH-going pulse-activated STOP/RESET signal.
When a playback or record cycle is in progress and a HIGH-going pulse is observed on PD, the
current cycle is terminated and the address pointer is reset to address 0, the beginning of the
message space.
EOM (RUN)
In Push-Button Operational Mode, EOM becomes an active-HIGH RUN signal which can be used to
drive an LED or other external device. It is HIGH whenever a record or playback operation is in
progress.
Recording in Push-Button Mode
1. The PD pin should be LOW, usually using a pull-down resistor.
- 13 -
Publication Release Date: June 2003
Revision 1.0
ISD2532/40/48/64
2. The P/ R pin is taken LOW.
3. The CE pin is pulsed LOW. Recording starts, EOM goes HIGH to indicate an
operation in progress.
4. When the CE pin is pulsed LOW. Recording pauses, EOM goes back LOW. The
internal address pointers are not cleared, but the EOM marker is stored in memory to
indicate as the message end. The P/ R pin may be taken HIGH at this time. Any
subsequent CE would start a playback at address 0.
5. The CE pin is pulsed LOW. Recording starts at the next address after the previous set
EOM marker. EOM goes back HIGH.[3]
6. When the recording sequences are finished, the final CE pulse LOW will end the last
record cycle, leaving a set EOM marker at the message end. Recording may also be
terminated by a HIGH level on PD, which will leave a set EOM marker.
Playback in Push-Button Mode
1. The PD pin should be LOW.
2. The P/ R pin is taken HIGH.
3. The CE pin is pulsed LOW. Playback starts, EOM goes HIGH to indicate an operation
in progress.
4. If the CE pin is pulsed LOW or an EOM marker is encountered during an operation,
the part will pause. The internal address pointers are not cleared, and EOM goes back
LOW. The P/ R pin may be changed at this time. A subsequent record operation would
not reset the address pointers and the recording would begin where playback ended.
5.
CE is again pulsed LOW. Playback starts where it left off, with EOM going HIGH to
indicate an operation in progress.
6. Playback continues as in steps 4 and 5 until PD is pulsed HIGH or overflow occurs.
7. If in overflow, pulling CE LOW will reset the address pointer and start playback from the
beginning. After a PD pulse, the part is reset to address 0.
Note: Push-Button Mode can be used in conjunction with modes M0, M1, and M3.
[3]
If the M1 Operational Mode pin is also HIGH, the just previously written
address.
- 14 -
EOM
bit is erased, and recording starts at that
ISD2532/40/48/64
Good Audio Design Practices
Winbond ChipCorder products are very high-quality single-chip voice recording and playback
devices. To ensure the highest quality voice reproduction, it is important that good audio design
practices on layout and power supply decoupling are followed. Please refer to Application Information
Section of ChipCorder products in Winbond website (www.winbond-usa.com) for details.
Good Audio Design Practices (apin11.pdf)
Single-Chip Board Layout Diagrams (apin12.pdf)
- 15 -
Publication Release Date: June 2003
Revision 1.0
ISD2532/40/48/64
8. TIMING DIAGRAMS
TCE
CE
TSET
P/R
Don't Care
THOLD
PD
Don't Care
A0-A8
Don't Care
TPDH
TPDS
TPDR
TPDS
TPDP
Don't Care
TSET
MIC
ANA IN
TPUD
TOVF
OVF
FIGURE 1: RECORD
TCE
CE
TSET
Don't Care
P/R
THOLD
PD
Don't Care
A0-A8
Don't Care
TPDH
Don't Care
TSET
SP+/-
TOVF
OVF
EOM
TPUD
TEOM
FIGURE 2: PLAYBACK
- 16 -
ISD2532/40/48/64
Start
Pause
TCE
CE
Start
TCE
Stop
TCE
(Start/Pause)
TSET
TSET
TSET
P/R
TPD
TSET
PD
TSET
(Stop/Reset)
TSET
A0-A8
MIC ANA IN
OVF
TPAUSE
TRUN
EOM
(Run)
TDB
TPUD
Notes
(1)
(2)
(3)
TDB
(4, 5)
TDB
TPUD
(6, 7)
(8)
FIGURE 3: PUSH-BUTTON MODE RECORD
Start
Pause
TCE
CE
Start
Stop
TCE
(Start/Pause)
TSET
TSET
TSET
P/R
TPD
TSET
PD
TSET
(Stop/Reset)
TSET
A0-A8
SP+/OVF
TPAUSE
TRUN
EOM
(Run)
Notes
TPUD
(1)
(2)
(3)
TDB
TDB
(4, 5)
TPUD
TDB
(6, 7)
(8)
FIGURE 4: PUSH-BUTTON MODE PLAYBACK
- 17 -
Publication Release Date: June 2003
Revision 1.0
ISD2532/40/48/64
Notes for Push-Button modes:
1.
A8, A7, and A6 = 1 for push-button operation.
2.
3.
The first CE LOW pulse performs a start function.
The part will begin to play or record after a power-up delay TPUD.
4.
The part must have CE HIGH for a debounce period TDB before it will recognize another falling edge of
CE and pause.
5.
The second CE LOW pulse, and every even pulse thereafter, performs a Pause function.
6.
Again, the part must have CE HIGH for a debounce period TDB before it will recognize another falling
edge of CE , which would restart an operation. In addition, the part will not do an internal power down
until CE is HIGH for the TDB time.
7.
8.
The third CE LOW pulse, and every odd pulse thereafter, performs a Resume function.
At any time, a HIGH level on PD will stop the current function, reset the address counter, and power
down the device.
- 18 -
ISD2532/40/48/64
9. ABSOLUTE MAXIMUM RATINGS
TABLE 4: ABSOLUTE MAXIMUM RATINGS (DIE)
CONDITIONS
VALUES
Junction temperature
150°C
Storage temperature range
-65°C to +150°C
Voltage applied to any pad
(VSS –0.3V) to
(VCC +0.3V)
Voltage applied to any pad (Input current limited to ±20mA)
(VSS –1.0V) to
(VCC +1.0V)
VCC – VSS
-0.3V to +7.0V
TABLE 5: ABSOLUTE MAXIMUM RATINGS (PACKAGED PARTS)
CONDITIONS
VALUES
Junction temperature
150°C
Storage temperature range
-65°C to +150°C
Voltage applied to any pin
(VSS –0.3V) to
(VCC +0.3V)
Voltage applied to any pin (Input current limited to ±20 mA)
(VSS –1.0V) to
(VCC +1.0V)
Lead temperature (Soldering – 10sec)
300°C
VCC – VSS
-0.3V to +7.0V
Note:
Stresses above those listed may cause permanent damage to the device. Exposure to the
absolute maximum ratings may affect device reliability and performance. Functional
operation is not implied at these conditions.
- 19 -
Publication Release Date: June 2003
Revision 1.0
ISD2532/40/48/64
9.1 OPERATING CONDITIONS
TABLE 6: OPERATING CONDITIONS (DIE)
CONDITIONS
VALUES
Commercial operating temperature range
Supply voltage (VCC)
Ground voltage (VSS)
0°C to +50°C
[1]
+4.5V to +6.5V
[2]
0V
TABLE 7: OPERATING CONDITIONS (PACKAGED PARTS)
CONDITIONS
Commercial operating temperature range
Supply voltage (VCC)
Ground voltage (VSS)
VALUES
[3]
[1]
+4.5V to +5.5V
[2]
0V
Notes:
[1]
VCC = VCCA = VCCD
[2]
VSS = VSSA = VSSD
[3]
Case Temperature
0°C to +70°C
- 20 -
ISD2532/40/48/64
10. ELECTRICAL CHARACTERISTICS
10.1. PARAMETERS FOR PACKAGED PARTS
TABLE 8: DC PARAMETERS – Packaged Parts
PARAMETERS
SYMBOL
Input Low Voltage
VIL
Input High Voltage
VIH
Output Low Voltage
VOL
Output High Voltage
VOH
OVF Output High Voltage
MIN [2]
TYP [1]
MAX [2]
UNITS
0.8
V
2.0
CONDITIONS
V
0.4
V
IOL = 4.0 mA
VCC - 0.4
V
IOH = -10 µA
VOH1
2.4
V
IOH = -1.6 mA
EOM Output High Voltage
VOH2
VCC – 1.0
V
IOH = -3.2 mA
VCC Current (Operating)
ICC
25
30
mA
REXT = ∞ [3]
VCC Current (Standby)
ISB
1
10
µA
[3]
Input Leakage Current
IIL
±1
µA
Input Current HIGH w/Pull
Down
IILPD
130
µA
Force VCC [4]
Output Load Impedance
REXT
16
Ω
Speaker Load
Preamp Input Resistance
RMIC
4
9
15
KΩ
MIC and MIC
REF Pins
AUX IN Input Resistance
RAUX
5
11
20
KΩ
ANA IN Input Resistance
RANA IN
2.3
3
5
KΩ
Preamp Gain 1
APRE1
21
24
26
dB
AGC = 0.0V
Preamp Gain 2
APRE2
-15
5
dB
AGC = 2.5V
AUX IN/SP+ Gain
AAUX
0.98
1.0
V/V
ANA IN to SP+/- Gain
AARP
21
23
26
dB
AGC Output Resistance
RAGC
2.5
5
9.5
KΩ
VCC - 0.8
Notes:
[1]
Typical values @ TA = 25º and VCC = 5.0V.
[2]
All Min/Max limits are guaranteed by Winbond via electrical testing or characterization. Not all specifications are 100
percent tested.
[3]
VCCA and VCCD connected together.
[4]
XCLK pin only.
- 21 -
Publication Release Date: June 2003
Revision 1.0
ISD2532/40/48/64
TABLE 9: AC PARAMETERS – Packaged Parts
CHARACTERISTIC
Sampling Frequency
SYMBOL
MIN[2]
TYP[1]
MAX[2]
UNITS
CONDITIONS
FS
ISD2532
8.0
kHz
[7]
ISD2540
6.4
kHz
[7]
ISD2548
5.3
kHz
[7]
ISD2564
4.0
kHz
[7]
ISD2532
3.4
kHz
3 dB Roll-Off Point [3][8]
ISD2540
2.7
kHz
3 dB Roll-Off Point [3][8]
ISD2548
2.3
kHz
3 dB Roll-Off Point [3][8]
ISD2564
1.7
kHz
3 dB Roll-Off Point [3][8]
ISD2532
32
sec
[7]
ISD2540
40
sec
[7]
ISD2548
48
sec
[7]
ISD2564
64
sec
[7]
ISD2532
32
sec
[7]
ISD2540
40
sec
[7]
ISD2548
48
sec
[7]
ISD2564
64
sec
[7]
Filter Pass Band
Record Duration
Playback Duration
FCF
TREC
TPLAY
CE Pulse Width
TCE
100
nsec
Control/Address Setup Time
TSET
300
nsec
Control/Address Hold Time
THOLD
0
nsec
Power-Up Delay
TPUD
ISD2532
25.0
msec
ISD2540
31.0
msec
ISD2548
37.0
msec
ISD2564
50.0
msec
- 22 -
ISD2532/40/48/64
TABLE 9: AC PARAMETERS – Packaged Parts (Cont’d)
CHARACTERISTIC
PD Pulse Width (record)
SYMBOL
MIN[2]
TYP[1]
MAX[2]
UNITS
TPDR
ISD2532
25.0
msec
ISD2540
31.25
msec
ISD2548
37.5
msec
ISD2564
50.0
msec
ISD2532
12.5
msec
ISD2540
15.625
msec
ISD2548
18.75
msec
ISD2564
25.0
msec
PD Pulse Width (Play)
TPDP
PD Pulse Width (Static)
TPDS
100
nsec
Power Down Hold
TPDH
0
nsec
12.5
msec
15.625
msec
18.75
msec
25.0
msec
µsec
EOM Pulse Width
CONDITIONS
[6]
TEOM
ISD2532
ISD2540
ISD2548
ISD2564
Overflow Pulse Width
TOVF
6.5
Total Harmonic Distortion
THD
1
2
%
Speaker Output Power
POUT
12.2
50
mW
Voltage Across Speaker Pins
VOUT
2.5
V p-p
MIC Input Voltage
VIN1
20
mV
Peak-to-Peak
ANA IN Input Voltage
VIN2
50
mV
Peak-to-Peak
AUX Input Voltage
VIN3
1.25
V
@ 1 kHz
REXT = 16 Ω
[4]
REXT = 600 Ω, Aux In=1.25Vp-p
[5]
Peak-to-Peak; REXT = 16 Ω
Notes:
[1]
Typical values @ TA = 25ºC, VCC = 5.0V and timing measured at 50% levels.
[2]
All Min/Max limits are guaranteed by Winbond via electrical testing or characterization. Not all specifications are 100 percent tested.
[3]
Low-frequency cutoff depends upon the value of external capacitors (see Pin Descriptions)
[4]
From AUX IN; if ANA IN is driven at 50 mV p-p, the POUT = 12.2 mW, typical.
[5]
With 5.1 K Ω series resistor at ANA IN.
[6]
TPDS is required during a static condition, typically overflow.
[7]
Sampling Frequency and Duration can vary as much as ±2.25 percent over the commercial temperature range. For greater stability, an
external clock can be utilized (see Pin Descriptions)
[8]
Filter specification applies to the antialiasing filter and the smoothing filter. Therefore, from input to output, expect a 6 dB drop by nature of
passing through both filters.
- 23 -
Publication Release Date: June 2003
Revision 1.0
ISD2532/40/48/64
10.1.1. Typical Parameter Variation with Voltage and Temperature - Packaged Parts
Chart 3: Standby Current (ISB)
1.2
Standby Current (mA)
Operating Current (mA)
25
Chart 1: Record Mode Operating
Current (ICC)
20
15
10
5
0
1.0
0.8
0.6
0.4
0.2
0
-40
25
70
85
-40
Temperature (C)
5.5 Volts
4.5 Volts
5.5 Volts
Chart 2: Total Harmonic Distortion
70
85
4.5 Volts
Chart 4: Oscillator Stability
0.7
0.4
0.6
0.2
Percent Change (%)
Percent Distortion (%)
25
Temperature (C)
0.5
0.4
0.3
0.2
0.1
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-40
25
70
85
-40
Temperature (C)
5.5 Volts
25
70
Temperature (C)
4.5 Volts
5.5 Volts
- 24 -
4.5 Volts
85
ISD2532/40/48/64
10.2. PARAMETERS FOR DIE
TABLE 10: DC PARAMETERS – Die
PARAMETERS
SYMBOL
Input Low Voltage
VIL
Input High Voltage
VIH
Output Low Voltage
VOL
Output High Voltage
VOH
OVF Output High Voltage
MIN[2]
TYP[1]
MAX[2]
UNITS
0.8
V
2.0
CONDITIONS
V
0.4
V
IOL = 4.0 mA
VCC - 0.4
V
IOH = -10 µA
VOH1
2.4
V
IOH = -1.6 mA
EOM Output High Voltage
VOH2
VCC – 1.0
V
IOH = -3.2 mA
VCC Current (Operating)
ICC
25
30
mA
REXT = ∞ [3]
VCC Current (Standby)
ISB
1
10
µA
[2]
Input Leakage Current
IIL
±1
µA
Input Current HIGH w/Pull
Down
IILPD
130
µA
Force VCC [4]
Output Load Impedance
REXT
16
Ω
Speaker Load
Preamp IN Input
Resistance
RMIC
4
9
15
KΩ
MIC and MIC
REF Pads
AUX IN Input Resistance
RAUX
5
11
20
KΩ
ANA IN Input Resistance
RANA IN
2.3
3
5
KΩ
Preamp Gain 1
APRE1
21
24
26
dB
AGC = 0.0V
Preamp Gain 2
APRE2
-15
5
dB
AGC = 2.5V
AUX IN/SP+ Gain
AAUX
0.98
1.0
V/V
ANA IN to SP+/- Gain
AARP
21
23
26
dB
AGC Output Resistance
RAGC
2.5
5
9.5
KΩ
VCC 0.8
Notes:
[1]
Typical values @ TA = 25°C and VCC = 5.0V.
[2]
All Min/Max limits are guaranteed by Winbond via electrical testing or characterization. Not all specifications are 100
percent tested.
[3]
VCCA and VCCD connected together.
[4]
XCLK pad only.
- 25 -
Publication Release Date: June 2003
Revision 1.0
ISD2532/40/48/64
TABLE 11: AC PARAMETERS – Die
CHARACTERISTIC
Sampling Frequency
SYMBOL
MIN[2]
TYP[1]
MAX[2]
UNITS
CONDITIONS
FS
ISD2532
8.0
kHz
[7]
ISD2540
6.4
kHz
[7]
ISD2548
5.3
kHz
[7]
ISD2564
4.0
kHz
[7]
ISD2532
3.4
kHz
3 dB Roll-Off Point [3][8]
ISD2540
2.7
kHz
3 dB Roll-Off Point [3][8]
ISD2548
2.3
kHz
3 dB Roll-Off Point [3][8]
ISD2564
1.7
kHz
3 dB Roll-Off Point [3][8]
ISD2532
32
sec
[7]
ISD2540
40
sec
[7]
ISD2548
48
sec
[7]
ISD2564
64
sec
[7]
ISD2532
32
sec
[7]
ISD2540
40
sec
[7]
ISD2548
48
sec
[7]
ISD2564
64
sec
[7]
Filter Pass Band
Record Duration
Playback Duration
FCF
TREC
TPLAY
CE Pulse Width
TCE
100
nsec
Control/Address Setup Time
TSET
300
nsec
Control/Address Hold Time
THOLD
0
nsec
Power-Up Delay
TPUD
ISD2532
25.0
msec
ISD2540
31.3
msec
ISD2548
37.5
msec
ISD2564
50.0
msec
- 26 -
ISD2532/40/48/64
TABLE 11: AC PARAMETERS – Die (Cont’d)
CHARACTERISTIC
PD Pulse Width (Record)
SYMBOL
MIN[2]
TYP[1]
MAX[2]
UNITS
TPDR
ISD2532
25.0
msec
ISD2540
31.25
msec
ISD2548
37.5
msec
ISD2564
50.0
msec
ISD2532
12.5
msec
ISD2540
15.625
msec
ISD2548
18.75
msec
ISD2564
25.0
msec
PD Pulse Width (Play)
TPDP
PD Pulse Width (Static)
TPDS
100
nsec
Power Down Hold
TPDH
0
nsec
12.5
msec
15.625
msec
18.75
msec
25.0
msec
µsec
EOM Pulse Width
CONDITIONS
[6]
TEOM
ISD2532
ISD2540
ISD2548
ISD2564
Overflow Pulse Width
TOVF
6.5
Total Harmonic Distortion
THD
1
2
%
Speaker Output Power
POUT
12.2
50
mW
Voltage Across Speaker Pins
VOUT
2.5
V p-p
MIC Input Voltage
VIN1
20
mV
Peak-to-Peak
ANA IN Input Voltage
VIN2
50
mV
Peak-to-Peak
AUX Input Voltage
VIN3
1.25
V
@ 1 kHz
REXT = 16 Ω
[4]
REXT=600 Ω, Aux In=1.25Vp-p
[5]
Peak-to-Peak; REXT = 16 Ω
Notes:
[1]
Typical values @ TA = 25°C, VCC = 5.0V and timing measured at 50% levels.
[2]
All Min/Max limits are guaranteed by Winbond via electrical testing or characterization. Not all specifications are 100 percent tested.
[3]
Low-frequency cutoff depends upon the value of external capacitors (see Pin Descriptions)
[4]
From AUX IN; if ANA IN is driven at 50 mV p-p, the POUT = 12.2 mW, typical.
[5]
With 5.1 K Ω series resistor at ANA IN.
[6]
TPDS is required during a static condition, typically overflow.
[7]
Sampling Frequency and playback Duration can vary as much as ±2.25 percent over the commercial temperature range. For greater stability,
an external clock can be utilized (see Pin Descriptions)
[8]
Filter specification applies to the antialiasing filter and the smoothing filter. Therefore, from input to output, expect a 6 dB drop by nature of
passing through both filters.
- 27 -
Publication Release Date: June 2003
Revision 1.0
ISD2532/40/48/64
10.2.1. Typical Parameter Variation with Voltage and Temperature - Die
Chart 7: Standby Current (ISB)
1.0
25
Standby Current (mA)
Operating Current (mA)
30
Chart 5: Record Mode Operating
Current (ICC)
20
15
10
5
0
0.8
0.6
0.4
0.2
0
-40
25
50
-40
Temperature (C)
6.5 Volts
5.5 Volts
4.5 Volts
6.5 Volts
Chart 6: Total Harmonic Distortion
50
5.5 Volts
4.5 Volts
Chart 8: Oscillator Stability
0.7
0.2
0.6
0
Percent Change (%)
Percent Distortion (%)
25
Temperature (C)
0.5
0.4
0.3
0.2
0.1
0
-0.2
-0.4
-0.6
-0.8
-1.0
-40
25
50
-40
Temperature (C)
6.5 Volts
5.5 Volts
25
50
Temperature (C)
4.5 Volts
6.5 Volts
- 28 -
5.5 Volts
4.5 Volts
ISD2532/40/48/64
10.3. PARAMETERS FOR PUSH-BUTTON MODE
TABLE 12: PARAMETERS FOR PUSH-BUTTON MODE
PARAMETERS
SYMBOL
MIN[2]
TYP[1]
MAX[2]
UNITS
CE Pulse Width
(Start/Pause)
TCE
300
nsec
Control/Address Setup Time
TSET
300
nsec
Power-Up Delay
TPUD
ISD2532
25.0
msec
ISD2540
31.25
msec
ISD2548
37.25
msec
ISD2564
50.0
msec
300
nsec
PD Pulse Width (Stop/Restart)
TPD
CE to EOM HIGH
TRUN
25
400
nsec
CE to EOM LOW
TPAUSE
50
400
nsec
CE HIGH Debounce
TDB
70
105
msec
85
135
msec
105
160
msec
135
215
msec
ISD2532
ISD2540
ISD2548
ISD2564
CONDITIONS
Notes:
[1]
Typical values @ TA = 25°C, VCC = 5.0V and timing measured at 50% levels.
[2]
All Min/Max limits are guaranteed by Winbond via electrical testing or characterization. Not all specifications are 100
percent tested.
- 29 -
Publication Release Date: June 2003
Revision 1.0
ISD2532/40/48/64
11. TYPICAL APPLICATION CIRCUIT
VCC
ISD2532/40/48/64
VCC
VSS
CHIP ENABLE
R4
100 K Ω
POWER DOWN
PLAYBACK/RECORD
1 A0
2 A1
VCCD 28
VCCA 16
3 A2
4 A3
C6
0.1 µ F
VSSD 12
5 A4
6 A5
VSSA 13
7 A6
SP+ 14
SP- 15
9 A7
10 A8
AUX IN 11
ANA IN 20
23 CE
24 PD
ANA OUT 21
27 P/R
25 OEM
MIC REF 18
MIC 17
22 OVF
26 XCLK
C7
0.1 µ F
µF
16 Ω
SPEAKER
R6
5.1 K Ω
C3
0.1 µ F
(Note)
C1
0.1 µ F
VCC
AGC 19
R1
1 KΩ
R2
470 KΩ
C8
22
C2
4.7 µ F
C5
0.1 µ F
R3
10 KΩ
C4
220
µF
ELECTRET
MICROPHONE
R5
10 KΩ
FIGURE 5: DESIGN SCHEMATIC
Note: If desired, pin 18 (PDIP package) may be left unconnected (microphone preamplifier noise will be higher). In
this case, pin 18 must not be tied to any other signal or voltage. Additional design example schematics are
provided below.
- 30 -
ISD2532/40/48/64
TABLE 13: APPLICATION EXAMPLE – BASIC DEVICE CONTROL
Control Step
Function
Action
1
Power up chip and select Record/Playback Mode
1. PD = LOW, 2. P/ R = As desired
2
Set message address for record/playback
Set addresses A0-A8
3A
Begin playback
P/ R = HIGH, CE = Pulse LOW
3B
Begin record
P/ R = LOW, CE = LOW
4A
End playback
Automatic
4B
End record
PD or CE = HIGH
TABLE 14: APPLICATION EXAMPLE – PASSIVE COMPONENT FUNCTIONS
Parts
Function
Comments
R1
Microphone power supply decoupling
Reduces power supply noise
R2
Release time constant
Sets release time for AGC
R3, R5
Microphone biasing resistors
Provides biasing for microphone operation
R4
Series limiting resistor
Reduces level to prevent distortion at
higher supply voltages
R6
Series limiting resistor
Reduces level to high supply voltages
C1, C5
Microphone DC-blocking capacitor Lowfrequency cutoff
Decouples microphone bias from chip.
Provides single-pole low-frequency cutoff
and command mode noise rejection.
C2
Attack/Release time constant
Sets attack/release time for AGC
C3
Low-frequency cutoff capacitor
Provides additional pole for low-frequency
cutoff
C4
Microphone power supply decoupling
Reduces power supply noise
C6, C7, C8
Power supply capacitors
Filter and bypass of power supply
- 31 -
Publication Release Date: June 2003
Revision 1.0
ISD2532/40/48/64
VCC
MC68HC705K1A
OSC1
PB0
OSC2
PB1
S2
S3
RECORD
PLAY
MSG#
ISD2532/40/48/64
R1
TBD
PA0
RESET
IRQ
PA1
U1
D1
RUN
S1
PA2
1 A0
2 A1
VCCD 28
VCCA 16
3 A2
4 A3
VSSD 12
VSSA 13
PA4
5 A4
6 A5
VDD
PA5
7 A6
VSS
PA6
PA7
SP+ 14
SP- 15
PA3
9 A7
10 A8
23 CE
24 PD
27 P/R
25 OEM
22 OVF
26 XCLK
U2
AUX IN 11
ANA IN 20
ANA OUT 21
MIC REF 18
MIC 17
AGC 19
FIGURE 6: ISD2532/40/48/64 APPLICATION EXAMPLE – MICROCONTROLLER/ISD2500
INTERFACE
In this simplified block diagram of a microcontroller application, the Push-Button Mode and message
cueing are used. The microcontroller is a 16-pin version with enough port pins for buttons, an LED,
and the ISD2500 series device. The software can be written to use three buttons: one each for play
and record, and one for message selection. Because the microcontroller is interpreting the buttons
and commanding the ISD2500 device, software can be written for any function desired in a particular
application.
Note: Winbond does not recommend connecting address lines directly to a microprocessor bus.
Address lines should be externally latched.
- 32 -
ISD2532/40/48/64
VCC
ISD2532/40/48/64
VCC
VSS
VCC
R6
100 K Ω
START/PAUSE
STOP/RESET
R7
100 K
VCC
VCCA 16
3 A2
4 A3
C4
0.1 µ F
VSSD 12
5 A4
6 A5
VSSA 13
7 A6
SP+ 14
SP- 15
9 A7
10 A8
AUX IN 11
ANA IN 20
23 CE
24 PD
ANA OUT 21
27 P/R
25 OEM
PLAYBACK/RECORD
VCCD 28
1 A0
2 A1
R4
5.1 K Ω
µF
C3
0.1 µ F
(Note)
C1
0.1 µ F
VCC
AGC 19
R1
1 KΩ
R2
470 KΩ
C5
22
16 Ω
SPEAKER
MIC REF 18
MIC 17
22 OVF
26 XCLK
C1
0.1 µ F
C2
4.7
µF
C5
0.1 µ F
R3
10 KΩ
C4
220
µF
ELECTRET
MICROPHONE
R5
10 KΩ
FIGURE 7: ISD2532/40/48/64 APPLICATION EXAMPLE – PUSH-BUTTON
Note: Please refer to page 13 for more details.
- 33 -
Publication Release Date: June 2003
Revision 1.0
ISD2532/40/48/64
TABLE 15: APPLICATION EXAMPLE – PUSH-BUTTON CONTROL
Control Step
Function
Action
1
Select Record/Playback Mode
P/ R = As desired
2A
Begin playback
P/ R = HIGH, CE = Pulse LOW
2B
Begin record
P/ R = LOW, CE = Pulse LOW
3
Pause record or playback
CE = Pulsed LOW
4A
End playback
Automatic at EOM marker or PD = Pulsed HIGH
4B
End record
PD = Pulsed HIGH
TABLE 16: APPLICATION EXAMPLE – PASSIVE COMPONENT FUNCTIONS
Parts
Function
Comments
R2
Release time constant
Sets release time for AGC
R4
Series limiting resistor
Reduces level to prevent distortion at
higher supply voltages
R6, R7
Pull-up and pull-down resistors
Defines static state of inputs
C1, C4, C5
Power supply capacitors
Filters and bypass of power supply
C2
Attack/Release time constant
Sets attack/release time for AGC
C3
Low-frequency cutoff capacitor
Provides additional pole for low-frequency
cutoff
- 34 -
ISD2532/40/48/64
12. PACKAGE DRAWING AND DIMENSIONS
12.1. 28-LEAD 300-MIL PLASTIC SMALL OUTLINE IC (SOIC)
28 27 26 25 24 23 22 21 20 19 18 17 16 15
1
2 3 4 5
6 7 8 9 10 11 12 13 14
A
G
C
B
D
E
H
F
INCHES
MILLIMETERS
Min
Nom
Max
Min
Nom
Max
A
0.701
0.706
0.711
17.81
17.93
18.06
B
0.097
0.101
0.104
2.46
2.56
2.64
C
0.292
0.296
0.299
7.42
7.52
7.59
D
0.005
0.009
0.0115
0.127
0.22
0.29
E
0.014
0.016
0.019
0.35
0.41
0.48
F
0.050
1.27
G
0.400
0.406
0.410
10.16
10.31
10.41
H
0.024
0.032
0.040
0.61
0.81
1.02
Note: Lead coplanarity to be within 0.004 inches.
- 35 -
Publication Release Date: June 2003
Revision 1.0
ISD2532/40/48/64
12.2. 28-LEAD 600-MIL PLASTIC DUAL INLINE PACKAGE (PDIP)
INCHES
A
MILLIMETERS
Min
Nom
Max
Min
Nom
Max
1.445
1.450
1.455
36.70
36.83
36.96
B1
0.150
B2
0.065
C1
0.600
C2
0.530
0.070
0.540
D
3.81
0.075
1.65
0.625
15.24
0.550
13.46
1.78
15.88
13.72
0.19
D1
0.015
E
0.125
F
0.015
G
0.055
H
1.91
13.97
4.83
0.38
0.135
3.18
0.018
0.022
0.38
0.46
0.56
0.060
0.065
1.40
1.52
1.62
0.100
3.43
2.54
J
0.008
0.010
0.012
0.20
0.25
0.30
S
0.070
0.075
0.080
1.78
1.91
2.03
q
0°
15°
0°
- 36 -
15°
ISD2532/40/48/64
12.3. 28-LEAD 8X13.4MM PLASTIC THIN SMALL OUTLINE PACKAGE (TSOP) TYPE 1
A
A
B
B
G
G
1
22
33
44
55
66
77
88
99
10
10
11
11
12
12
13
13
14
14
28
28
27
27
26
26
25
25
24
24
23
23
22
22
21
21
20
20
19
19
18
18
17
17
16
16
15
15
F
C
E
E
D
JJ
H
H
I
Plastic Thin Small Outline Package (TSOP) Type 1 Dimensions
INCHES
M ILLIM ETERS
M in
Nom
M ax
M in
Nom
M ax
A
0.520
0.528
0.535
13.20
13.40
13.60
B
0.461
0.465
0.469
11.70
11.80
11.90
C
0.311
0.315
0.319
7.90
8.00
8.10
D
0.002
0.006
0.05
E
0.007
0.011
0.17
G
0.037
H
I
0
0.020
J
0.004
Note:
0.009
0.0217
F
0
0.039
0
3
0.022
0.15
0.22
0.27
0.55
0.041
0
0.95
0
6
0.028
0
0.50
0.008
0.10
1.00
0
3
0.55
1.05
0
6
0.70
0.21
Lead coplanarity to be within 0.004 inches.
- 37 -
Publication Release Date: June 2003
Revision 1.0
ISD2532/40/48/64
12.4. DIE BONDING PHYSICAL LAYOUT [1]
A3
ISD2532/40/48/64
o
Die Dimensions
A0
XCLK
P/R
EOM
PD
A4
X: 149.6 + 1 mils
CE
A5
Y: 206.3 + 1 mils
o
VCCD
A1
A2
OVF
A6
ISD2532/40/48/64
Die Thickness [2]
11.8 + .4 mils
o
Pad Opening
111 microns (4.4 mils)
≈
≈
NC
ANA OUT
A7
ANA IN
A8
AUX IN
VSSD
VSSA
SP+
SP-
MIC
AGC
VCCA MIC REF
Notes:
[1]
The backside of die is internally connected to VSS. It MUST NOT be connected to any other potential or damage may
occur.
[2]
Die thickness is subject to change, please contact Winbond factory for status and availability.
- 38 -
ISD2532/40/48/64
ISD2532/40/48/64 PRODUCT PAD DESIGNATIONS
(with respect to die center)
Pad
Pad Name
X Axis (µm)
Y Axis (µm)
OVF
Overflow Output
1675.95
1779.38
CE
Chip Enable Input
1728.08
2114.25
PD
Power Down Input
1731.83
2383.88
EOM
End of Message
1342.20
2411.63
XCLK
No Connect (optional)
987.83
2450.63
P/ R
Playback/Record
808.58
2453.25
VCCD
VCC Digital Power Supply
546.08
2449.13
A0
Address 0
-896.55
2425.13
A1
Address 1
-1114.05
2425.13
A2
Address 2
-1329.68
2425.13
A3
Address 3
-1542.68
2425.13
A4
Address 4
-1639.05
2178.75
A5
Address 5
-1696.80
1960.88
A6
Address 6
-1696.80
1731.38
NC
NC
-1729.80
-1875.75
A7
Address 7
-1729.80
-2061.00
A8
Address 8
-1729.80
-2343.38
AUX IN
Auxiliary Input
-1408.80
-2408.25
VSSD
VSS Digital Power Supply
-1111.43
-2388.75
VSSA
VSS Analog Power Supply
-406.43
-2431.13
SP+
Speaker Output +
-46.05
-2360.25
SP-
Speaker Output -
388.20
-2360.25
VCCA
VCC Analog Power Supply
747.83
-2403.00
MIC
Microphone Input
1102.58
-2438.63
MIC REF
Microphone Reference
1296.08
-2438.63
AGC
Automatic Gain Control
1667.70
-2422.88
ANA IN
Analog Input
1729.95
-1946.63
ANA OUT
Analog Output
1702.20
-1703.63
- 39 -
Publication Release Date: June 2003
Revision 1.0
ISD2532/40/48/64
13. ORDERING INFORMATION
Product Number Descriptor Key
ISD2 5
Special Temperature Field:
Blank = Commercial Packaged (0˚C to +70˚C)
ISD2500 Series
Duration:
or Commercial Die (0˚C to +50˚C)
32
=
32 seconds
40
=
40 seconds
48
=
48 seconds
64
=
64 seconds
Package Type:
P =
28-Lead 600mil Plastic Dual Inline
Package (PDIP)
S =
28-Lead 300mil Small Outline
Integrated Circuit (SOIC)
E =
28-Lead 8x13.4 mm Thin Small
Outline Package (TSOP) Type 1
X = Die
When ordering ISD2532/40/48/64 products refer to the following part numbers which are supported in
volume for this product series. Consult the local Winbond Sales Representative or Distributor for
availability information.
Part Number
Part Number
Part Number
Part Number
ISD2532P
ISD2540P
ISD2548P
ISD2564P
ISD2532S
ISD2540S
ISD2532E
ISD2540E
ISD2548E
ISD2532X
ISD2540X
ISD2548X
ISD2564X
For the latest product information, access Winbond’s worldwide website at
http://www.winbond-usa.com
- 40 -
ISD2532/40/48/64
14. VERSION HISTORY
VERSION
DATE
DESCRIPTION
0
Apr. 1998
Preliminary Specifications.
1.0
Jun. 2003
Reformat the document.
Update TSOP description in pin configuration section.
Revise Table 1: Product Summary.
Update TSOP and SOIC package option.
Remove industrial temperature option.
- 41 -
Publication Release Date: June 2003
Revision 1.0
ISD2532/40/48/64
The contents of this document are provided only as a guide for the applications of Winbond products. Winbond
makes no representation or warranties with respect to the accuracy or completeness of the contents of this
publication and reserves the right to discontinue or make changes to specifications and product descriptions at
any time without notice. No license, whether express or implied, to any intellectual property or other right of
Winbond or others is granted by this publication. Except as set forth in Winbond's Standard Terms and
Conditions of Sale, Winbond assumes no liability whatsoever and disclaims any express or implied warranty of
merchantability, fitness for a particular purpose or infringement of any Intellectual property.
Winbond products are not designed, intended, authorized or warranted for use as components in systems or
equipments intended for surgical implantation, atomic energy control instruments, airplane or spaceship
instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other
applications intended to support or sustain life. Further more, Winbond products are not intended for applications
wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe
property or environmental injury could occur.
Application examples and alternative uses of any integrated circuit contained in this publication are for illustration
only and Winbond makes no representation or warranty that such applications shall be suitable for the use
specified.
ISD® and ChipCorder® are trademarks of Winbond Electronics Corporation.
The 100-year retention and 100K record cycle projections are based upon accelerated reliability tests, as
published in the Winbond Reliability Report, and are neither warranted nor guaranteed by Winbond.
®
®
Information contained in this ISD ChipCorder data sheet supersedes all data for the ISD ChipCorder products
®
published by ISD prior to August, 1998.
®
®
This data sheet and any future addendum to this data sheet is(are) the complete and controlling ISD ChipCorder
product specifications. In the event any inconsistencies exist between the information in this and other product
documentation, or in the event that other product documentation contains information in addition to the information
in this, the information contained herein supersedes and governs such other information in its entirety.
Copyright© 2003, Winbond Electronics Corporation. All rights reserved. ISD® is a registered trademark of
Winbond. ChipCorder® is a trademark of Winbond. All other trademarks are properties of their respective
owners.
Headquarters
Winbond Electronics Corporation America
Winbond Electronics (Shanghai) Ltd.
No. 4, Creation Rd. III
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5665577
http://www.winbond.com.tw/
2727 North First Street, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-5441797
http://www.winbond-usa.com/
27F, 299 Yan An W. Rd. Shanghai,
200336 China
TEL: 86-21-62365999
FAX: 86-21-62356998
Taipei Office
Winbond Electronics Corporation Japan
Winbond Electronics (H.K.) Ltd.
9F, No. 480, Pueiguang Rd.
Neihu District
Taipei, 114 Taiwan
TEL: 886-2-81777168
FAX: 886-2-87153579
7F Daini-ueno BLDG. 3-7-18
Shinyokohama Kohokuku,
Yokohama, 222-0033
TEL: 81-45-4781881
FAX: 81-45-4781800
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Please note that all data and specifications are subject to change without notice.
All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.
- 42 -