Holt HI-15530CDM Manchester encoder / decoder Datasheet

HI-15530
Manchester Encoder / Decoder
July 2001
GENERAL DESCRIPTION
FEATURES
The HI-15530 is a high performance CMOS integrated
circuit designed to meet the requirements of Mil-Std-1553
and similar Manchester II encoded, time division
multiplexed serial data protocols. The HI-15530 contains
both an Encoder and Decoder, which operate
independently.
! Mil-Std-1553 compatible
The device generates Mil-Std-1553 sync pulses, parity bits
as well as the Manchester II encoding of the data bits. The
decoder recognizes and identifies sync pulses, decodes
data bits, and performs parity checking.
! Direct replacement for:
Harris HD15530
GEC Plessey Semiconductors MAS15530
Aeroflex ACT15530
The HI-15530 supports the 1Mbit/s data rate of Mil-Std1553 over the full temperature and voltage range.
! 1.25 Mbit/s Data Rate
For applications requiring small footprints and low cost, the
HI-15530 is available in a 24-pin plastic SOIC package.
Ceramic DIP and LCC packages are also available to
achieve the highest level of reliability and to provide drop-in
replacement for obsolete parts from other manufacturers.
! Interfaces to HI-1567 Transceiver
! Small footprint 24-pin plastic SOIC package
option
! Manchester II Encode and Decode
! Sync identification and Lock-in
! Clock recovery
PIN CONFIGURATION (Top View)
VALID WORD
APPLICATIONS
1
24 VDD
ENCODER SHIFT CLK
2
23 ENCODER CLK
TAKE DATA
3
22 SEND CLK IN
HI-15530PSI
! Mil-Std-1553 Interfaces
SERIAL DATA OUT
DECODER CLK
5
20 SYNC SELECT
! ARINC 708A Interfaces
BIPOLAR ZERO IN
6
19 ENCODER ENABLE
BIPOLAR ONE IN
7
18 SERIAL DATA IN
UNIPOLAR DATA IN
8
17 BIPOLAR ONE OUT
DECODER SHIFT CLK
9
16 OUTPUT INHIBIT
! Smart Munitions
! Stores management
! Sensor interfaces
4
COMMAND / DATA SYNC 10
DECODER RESET 11
GND 12
21 SEND DATA
15 BIPOLAR ZERO OUT
14 ÷ 6 OUT
13 MASTER RESET
! Instrumentation
24 Pin SOIC package
HOLT INTEGRATED CIRCUITS
(DS15530 Rev. A)
07/01
HI-15530
PIN DESCRIPTIONS
SIGNAL
FUNCTION
VALID WORD
ENCODER SHIFT CLOCK
TAKE DATA
OUTPUT
OUTPUT
OUTPUT
SERIAL DATA OUT
DECODER CLOCK
OUTPUT
INPUT
BIPOLAR ZERO IN
INPUT
BIPOLAR ONE IN
INPUT
UNIPOLAR DATA IN
INPUT
DECODER SHIFT CLOCK
OUTPUT
COMMAND / DATA SYNC
OUTPUT
DECODER RESET
INPUT
GND
MASTER RESET
POWER
INPUT
÷6 OUT
BIPOLAR ZERO OUT
OUTPUT
OUTPUT
OUTPUT INHIBIT
INPUT
BIPOLAR ONE OUT
OUTPUT
SERIAL DATA IN
ENCODER ENABLE
INPUT
INPUT
SYNC SELECT
INPUT
SEND DATA
OUTPUT
SEND CLOCK IN
ENCODER CLOCK
VDD
INPUT
INPUT
POWER
DESCRIPTION
A high output signals the receipt of a valid word
Shifts data into the encoder on a low to high transition
Output is high during receipt of data after identification of a Sync
Pulse and two valid Manchester data bits.
Received Data output in NRZ format
12x the data rate. Clock for the transition finder and synchronizer,
which generates the internal clock for the remainder of the decoder
A high input indicates the 1553 bus is in its negative state.
This pin must be held high when the Unipolar input is used
A high input indicates the 1553 bus is in the positive state.
This pin must be held low when the Unipolar input is used
Input for unipolar data to the transition finder. Must be held low when
not in use
Provides the DECODER CLOCK divided by 12, synchronized by the
recovered serial data
A high on this pin occurs during the output of decoded data which
was preceded by a Command (or Status) synchronizing character. A
low output indicates a Data synchronizing character
A high applied to this pin during a DECODER SHIFT CLOCK rising
edge resets the bit counter
0V supply
A high on this pin clears 2:1 counters in both Encoder and Decoder,
and resets the divide-by-6 circuit
Provides ENCODER CLOCK divided by 6
An active low output intended to drive the zero or negative sense of a
MIL-STD-1553 Line Driver
A low inhibits the BIPOLAR ZERO OUT and BIPOLAR ONE OUT by
forcing them to inactive high states
An active low output intended to drive the one or positive sense on a
MIL-STD-1553 Line Driver
Receiver serial data at the rate of the ENCODER SHIFT CLOCK
A high on this pin initiates the encode cycle. (Subject to the
preceeding cycle being complete)
Actuates a Command Sync for an input high and a Data Sync for a
low
An active high output which enables the external source of serial
Data
Clock input at 2 times the Data rate, usualy driven by ÷6 OUT
Input to the divide by 6 circuit. Normal frequency is Data rate x12
5V +/- 10%
HOLT INTEGRATED CIRCUITS
2
HI-15530
ENCODER OPERATION
The encoder requires a single clock with a frequency of
twice the desired rate applied at the SEND CLOCK input.
An auxiliary divide by six counter is provided on chip which
can be utilized to produce the SEND CLOCK by dividing
the ENCODER CLOCK.
To abort the Encoder transmission a positive pulse must be
applied at MASTER RESET. Anytime after or during this
pulse, a low to high transition on SEND CLOCK clears the
internal counters and initializes the Encoder for a new
word.
The Encoder's cycle begins when ENCODER ENABLE is
high during a falling edge of ENCODER SHIFT CLOCK (1).
This cycle lasts for one word length or twenty ENCODER
SHIFT CLOCK periods. At the next low-to-high transition of
the ENCODER SHIFT CLOCK, a high at SYNC SELECT
input actuates a command sync or a low will produce a
data sync for that word (2). When the Encoder is ready to
accept data, the SEND DATA output will go high and
remain high for sixteen ENCODER SHIFT CLOCK periods
(3). During these sixteen periods the data should be
clocked into the SERIAL DATA input with every low-to-high
transition of the ENCODER SHIFT CLOCK (3) - (4). After
the sync and the Manchester II coded data are transmitted
through the BIPOLAR ONE and BIPOLAR ZERO outputs,
the Encoder adds on an additional bit which is the parity for
that word (5). If ENCODER ENABLE is held high continuously, consecutive words will be encoded without an
interframe gap. ENCODER ENABLE must go low by time
(5) as shown to prevent a consecutive word from being
encoded. At any time a low on the OUTPUT INHIBIT input
will force both bipolar outputs to a high state but will not
affect the Encoder in any other way.
0
TIMING
1
2
3
4
MASTER RESET
OUTPUT
INHIBIT
SEND CLK IN
BIPOLAR
ONE OUT
÷ 6 OUT
÷2
Character
Former
÷6
BIPOLAR
ZERO OUT
ENCODER CLK
Bit
Counter
SYNC
SELECT
SEND
DATA
ENCODER
SHIFT
CLK
5
6
7
15
16
17
SERIAL
DATA
IN
ENCODER
ENABLE
18
19
SEND CLK
ENCODER
SHIFT CLK
ENCODER
ENABLE
SYNC SELECT
DON’T CARE
VALID
DON’T CARE
SEND DATA
SERIAL
DATA IN
15
14
13
12
11
10
3
2
1
0
BIPOLAR
ONE OUT
SYNC
SYNC
15
14
13
12
11
3
2
1
0
P
BIPLOAR
ZERO OUT
SYNC
SYNC
15
14
13
12
11
3
2
1
0
P
(1) (2)
(3)
HOLT INTEGRATED CIRCUITS
3
(4) (5)
HI-15530
DECODER OPERATION
The Decoder requires a single clock with a frequency of 12
times the desired data rate applied at the DECODER
CLOCK input. The Manchester II coded data can be
presented to the Decoder in one of two ways. The
BIPOLAR ONE and BIPOLAR ZERO inputs will accept
data from a comparator sensed transformer coupled bus as
specified in MIL-STD-1553. The UNIPOLAR DATA input
can only accept non-inverted Manchester II coded data
(e.g. from BIPOLAR ZERO OUT of an Encoder). The
Decoder is free running and continuously monitors its data
input lines for a valid sync character and two valid
Manchester data bits to start an output cycle. When a valid
sync is recognized (1), the type of sync is indicated on
COMMAND/DATA SYNC output. If the sync character was
a command sync, this output will go high (2) and remain
high for sixteen DECODER SHIFT CLOCK periods (3),
otherwise it will remain low. The TAKE DATA output will go
high and remain high (2) - (3) while the Decoder is
transmitting the decoded data through SERIAL DATA OUT.
The decoded data available at SERIAL DATA OUT is in a
NRZ format. The DECODER SHIFT CLOCK is provided so
that the decoded bits can be shifted into an external register
on every low-to-high transition of this clock (2) - (3). After all
sixteen decoded bits have been transmitted (3) the data is
checked for odd parity. A high on VALID WORD output (4)
indicates a successful reception of a word without any
Manchester or parity errors. At this time the Decoder is
TIMING
0
1
looking for a new sync character to start another output
sequence. VALID WORD will go low approximately 20
DECODER SHIFT CLOCK periods after it goes high if not
reset low sooner by a valid sync and two valid Manchester
bits as shown (1). At any time in the above sequence, a
high input on DECODER RESET during a low-to-high
transition of DECODER SHIFT CLOCK will abort
transmission and initialize the Decoder to start looking for a
new sync character.
TAKE DATA
UNIPOLAR
DATA IN
BIPOLAR
ONE IN
TRANSITION
FINDER
CHARACTER
IDENTIFIER
COMMAND/DATA
SYNC
BIPOLAR
ZERO IN
SERIAL DATA
OUT
DECODER
CLK
BIT
RATE
CLK
SYNCHRONIZER
PARITY
CHECK
DECODER
SHIFT CLK
MASTER
RESET
DECODER
RESET
2
3
4
5
6
7
8
16
17
18
19
BIT
COUNTER
DECODER
SHIFT CLK
BIPOLAR
ONE IN
SYNC
SYNC
15
14
13
12
11
10
2
1
0
P
BIPLOAR
ZERO IN
SYNC
SYNC
15
14
13
12
11
10
2
1
0
P
TAKE DATA
COMMAND /
DATA SYNC
SERIAL
DATA OUT
VALID WORD
UNDEFINED
15
14
13
12
4
3
2
1
0
May be high from previous reception
(1)(2)
HOLT INTEGRATED CIRCUITS
4
VALID
WORD
(3)
(4)
HI-15530
SEND CLK
t E1
ENCODER
SHIFT CLK
t E2
SERIAL DATA IN
t E3
VALID
VALID
SEND CLK
ENCODER
SHIFT CLK
t E1
t E4
ENCODER ENABLE
t E6
t E5
VALID
SYNC SELECT
t E7
ENCODER
SHIFT CLK
t E8
SEND DATA
SEND CLK
t E9
BIPOLAR ONE OUT or
BIPOLAR ZERO OUT
DECODER SHIFT CLK
t D6
COMMAND / DATA SYNC
t D7
TAKE DATA
DECODER SHIFT CLK
t D8
DATA BIT
SERIAL DATA OUT
DECODER SHIFT CLK
t D9
COMMAND / DATA SYNC
t D10
TAKE DATA
t D11
VALID WORD
DECODER SHIFT CLK
t DRH
DECODER RESET
t DR
t DRS
HOLT INTEGRATED CIRCUITS
5
HI-15530
BIT PERIOD
BIPOLAR ONE IN
BIT PERIOD
t D1
t D3
t D2
BIPOLAR ZERO IN
BIT PERIOD
t D3
t D1
t D2
COMMAND SYNC
BIPOLAR ONE IN
t D1
t D3
t D3
BIPOLAR ZERO IN
t D1
t D2
BIPOLAR ONE IN
t D3
t D2
DATA SYNC
t D1
t D1
t D3
BIPOLAR ZERO IN
t D3
t D3
t D1
t D3
t D1
t D4
t D5
t D5
ONE
t D4
ZERO
ONE
t D2
UNIPOLAR IN
t D2
COMMAND SYNC
t D2
UNIPOLAR IN
t D2
DATA SYNC
t D5
UNIPOLAR IN
t D4
t D4
t D5
ONE
Bit Period
Command Word
Data Word
Status Word
0
1
2
SYNC
ZERO
3
4
5
6
7
TERMINAL ADDRESS
8
R/T
SYNC
SYNC
9
t D4
ONE
10
11 12 13 14 15 16 17 18 19
SUBADDRESS
/ MODE
DATA WORD
COUNT
P
P
DATA WORD
SYNC
SYNC
TERMINAL ADDRESS
ME
CODE FOR FAILURE MODES
SYNC
HOLT INTEGRATED CIRCUITS
6
TF
P
HI-15530
Supply Voltage VDD
-0.3V to +7V
Voltage at any pin
-0.3V to Vcc +0.3V
Power Dissipation at 25C
Plastic SOIC
Ceramic DIP
1.5 W, derate10mW/°C
1.0 W, derate 7mW/°C
DC Current Drain per pin
±10mA
Storage Temperature Range:
Operating Temperature Range:
(Industrial)
(Military)
-65°C to +150°C
-40°C to +85°C
-55°C to +125°C
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings
only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
VDD = 5V ±10%, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
Input Voltage
Clock Input Voltage
Input Leakage Current
Output Voltage
SYMBOL
CONDITIONS
VIH
VIL
70% VDD
Input Voltage HI
Input Voltage LO
VIHC
VILC
VDD-0.5
Input Sink
Input Source
Logic “1” Output Voltage
Logic “0” Output Voltage
IIH
IIL
TYP
MAX
V
V
0.5V
V
V
1.0
IDDSB
Operating Supply Current
IDD
Input Capacitance
UNIT
30% VDD
-1.0
IOH=-3mA
IOL=1.8mA
Output Capacitance
MIN
Input Voltage HI
Input Voltage LO
VOH
VOL
Standby Supply Current
LIMITS
0.4
V
V
VIN=VDD, Outputs Open
2.0
mA
f=1MHz, Outputs Open
10.0
mA
CIN
7.0
pF
COUT
10.0
pF
HOLT INTEGRATED CIRCUITS
7
2.4
µA
µA
HI-15530
VDD = 5V±10%, GND = 0V, TA = Operating Temperature Range, CL=50pF
PARAMETER
SYMBOL
LIMITS
MIN
TYP
MAX
UNITS
Encoder Timing
Encoder Clock Frequency
fEC
0
15
MHz
Send Clock Frequency
fESC
0
2.5
MHz
Encoder Clock Rise Time
tECR
8
ns
Encoder Clock Fall Time
tECF
8
ns
1.25
MHz
125
ns
Encoder Data Rate
fED
0
Master Reset Pulse Width
tMR
150
Shift Clock Delay
tE1
Serial Data Setup Time
tE2
75
Serial Data Hold Time
tE3
75
ns
Enable Setup Time
tE4
90
ns
ns
ns
Enable Pulse Width
tE5
80
ns
Sync Setup Time
tE6
55
ns
Sync Pulse Width
tE7
150
Send Data Delay
tE8
0
ns
50
ns
130
ns
Bipolar Output Delay
tE9
Enable Hold Time
tE10
10
ns
Sync Hold Time
tE11
95
ns
Decoder Clock Frequency
fDC
0
Decoder Clock Rise Time
tDCR
8
ns
Decoder Clock Fall Time
tDCF
8
ns
1.25
MHz
Decoder Timing
15
MHz
Decoder Data Rate
fDD
0
Decoder Reset Pulse Width
tDR
150
ns
Decoder Reset Setup Time
tDRS
75
ns
Decoder Reset Hold Time
tDRH
10
ns
Master Reset Pulse Width
tMR
150
ns
Bipolar Data Pulse Width
tD1
tDC+10
Sync Transition Span
tD2
One-Zero Overlap
tD3
Short Data Transition Span
tD4
6tDC
Long Data Transition Span
tD5
12tDC
Sync Delay (On)
tD6
-20
110
Take Data Delay (On)
tD7
0
110
ns
Serial Data Out Delay
tD8
80
ns
ns
18tDC
ns
tDC-10
ns
ns
ns
ns
Sync Delay (Off)
tD9
0
110
ns
Take Data Delay (Off)
tD10
0
110
ns
Valid Word Delay
tD11
0
110
ns
HOLT INTEGRATED CIRCUITS
8
HI-15530
VALID WORD 1
ENCODER SHIFT CLK 2
TAKE DATA 3
SERIAL DATA OUT 4
DECODER CLK 5
BIPOLAR ZERO IN 6
BIPOLAR ONE IN 7
UNIPOLAR DATA IN 8
DECODER SHIFT CLK 9
COMMAND / DATA SYNC 10
DECODER RESET 11
GND 12
HI-15530CDI
HI-15530CDT
HI-15530CDM
24
23
22
21
20
19
18
17
16
15
VDD
ENCODER CLK
SEND CLK IN
SEND DATA
SYNC SELECT
ENCODER ENABLE
SERIAL DATA IN
BIPOLAR ONE OUT
OUTPUT INHIBIT
BIPOLAR ZERO OUT
4
3
2
1 28 27 26
DECODER CLK
5
25
SEND DATA
N/C
6
24
N/C
N/C
7
23
N/C
BIPOLAR ZERO IN
8
22
SYNC SELECT
BIPOLAR ONE IN
9
21
ENCODER ENABLE
UNIPOLAR DATA IN
10
20
SERIAL DATA IN
DECODER SHIFT CLOCK
11
19
12 13 14 15 16 17 18
HI-15530CLI
HI-15530CLT
HI-15530CLM
BIPOLAR ONE OUT
14 ÷ 6 OUT
13 MASTER RESET
24 - Pin Ceramic Side-Brazed DIP
28 - Pin Ceramic LCC
PART
NUMBER
PACKAGE
DESCRIPTION
TEMPERATURE
RANGE
HI-15530CDI
HI-15530CDT
24 PIN CERAMIC SIDE BRAZED DIP
24 PIN CERAMIC SIDE BRAZED DIP
-40°C TO +85°C
-55°C TO +125°C
I
T
NO
NO
GOLD
GOLD
HI-15530CDM
24 PIN CERAMIC SIDE BRAZED DIP
-55°C TO +125°C
M
YES
SOLDER
HI-15530PSI
HI-15530PST
HI-15530CLI
HI-15530CLT
HI-15530CLM
24 PIN PLASTIC SOIC
24 PIN PLASTIC SOIC
24 PIN CERAMIC LEADLESS CHIP CARRIER
24 PIN CERAMIC LEADLESS CHIP CARRIER
24 PIN CERAMIC LEADLESS CHIP CARRIER
-40°C TO +85°C
-55°C TO +125°C
-40°C TO +85°C
-55°C TO +125°C
-55°C TO +125°C
I
T
I
T
M
NO
NO
NO
NO
YES
SOLDER
SOLDER
GOLD
GOLD
SOLDER
HOLT INTEGRATED CIRCUITS
9
FLOW BURN
IN
LEAD
FINISH
HI-15530
24-PIN PLASTIC SSOP
Package Type: 24HS
.323 ± .012
(8.20 ± .30)
.006
TYP
(.15)
.209 ± .012
(5.30 ± .30)
.307 ± .016
(7.80 ± .40)
SEE DETAIL A
.012
TYP
(.30)
.095 ± .005
(2.413 ± .127)
0° to 8°
.026
TYP
(.65)
.005 ± .001
(.13 ± .08)
.030 ± .008
(.75 ± .20)
DETAIL A
24-PIN CERAMIC SIDE-BRAZED DIP
Package Type: 24C
1.220 MAX
(30.988 MAX)
.595 ± .010
(15.113 ± .254)
.610 ± .010
(15.494 ± .254)
.225 MAX
(5.715 MAX)
.050 TYP
(1.270 TYP)
.125 MIN
(3.175 MIN)
.085 ± .009
(2.159 ± .229)
.100 BSC
(2.540 BSC)
.018 TYP
(.457 TYP)
HOLT INTEGRATED CIRCUITS
10
.600 ± .010
(15.240 ± .254)
.010 + .002/−.001
(.254 + .051/−.025)
HI-15530
28-PIN CERAMIC LEADLESS CHIP CARRIER
Package Type: 28S
.020 INDEX
(.508 INDEX)
.080 ± .020
(2.032 ± .508)
PIN 1
PIN 1
.050 ± .005
(1.270 ± .127)
.451 ± .009
(11.455 ± .229)
SQ.
.050 BSC
(1.270 BSC)
.008R ± .006
(.203R ± .152)
.040 x 45° 3PLS
(1.016 x 45° 3PLS)
HOLT INTEGRATED CIRCUITS
11
.025 ± .003
(.635 ± .076)
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