Section I. Arria GX Device
Data Sheet
This section provides designers with the data sheet specifications for
Arria™ GX devices. They contain feature definitions of the transceivers,
internal architecture, configuration, and JTAG boundary-scan testing
information, DC operating conditions, AC timing parameters, a reference
to power consumption, and ordering information for Arria GX devices.
This section includes the following chapters:
Revision History
Altera Corporation
■
Chapter 1, Arria GX Device Family Overview
■
Chapter 2, Arria GX Architecture
■
Chapter 3, Configuration and Testing
■
Chapter 4, DC and Switching Characteristics
■
Chapter 5, Reference and Ordering Information
Refer to each chapter for its own specific revision history. For information
on when each chapter was updated, refer to the Chapter Revision Dates
section, which appears in the full handbook.
Section I–1
Arria GX Device Data Sheet
Section I–2
Arria GX Device Handbook, Volume 1
Altera Corporation
1. Arria GX Device Family
Overview
AGX51001-1.2
Introduction
The ArriaTM GX family of devices combines 3.125 gigabits per second
(Gbps) serial transceivers with reliable packaging technology and a
proven logic array. Arria GX devices include 4 to 12 high-speed
transceiver channels, each incorporating clock/data recovery (CDR)
technology and embedded SERDES circuitry designed to support
PCI-Express, Gigabit Ethernet, SDI, SerialLite II, XAUI, and
Serial RapidIO protocols, along with the ability to develop proprietary,
serial-based IP using its Basic mode. The transceivers build upon the
success of Stratix® II GX family. The Arria GX FPGA technology offers a
1.2-V logic array with the right level of performance and dependability
needed to support these mainstream protocols.
Features
The key device features for the Arria GX include:
■
Altera Corporation
May 2008
Transceiver block features
●
High-speed serial transceiver channels with clock/data
recovery support up to 3.125 Gbps.
●
Devices available with 4, 8, or 12 high-speed full-duplex serial
transceiver channels
●
Support for the following CDR-based bus standards — PCI
Express, Gigabit Ethernet, SDI, SerialLite II, XAUI, and Serial
RapidIO, along with the ability to develop proprietary,
serial-based IP using its Basic mode
●
Individual transmitter and receiver channel power-down
capability for reduced power consumption during
non-operation
●
1.2- and 1.5-V pseudo current mode logic (PCML) support on
transmitter output buffers
●
Receiver indicator for loss of signal (available only in PCI
Express (PIPE) mode)
●
Hot socketing feature for hot plug-in or hot swap and power
sequencing support without the use of external devices
●
Dedicated circuitry that is compliant with PIPE, XAUI, GIGE,
SDI, and Serial RapidIO
●
8B/10B encoder/decoder performs 8-bit to 10-bit encoding and
10-bit to 8-bit decoding
●
Phase compensation FIFO buffer performs clock domain
translation between the transceiver block and the logic array
●
Channel aligner compliant with XAUI
1–1
Arria GX Device Family Overview
■
Main device features:
●
TriMatrix memory consisting of three RAM block sizes to
implement true dual-port memory and first-in first-out (FIFO)
buffers with performance up to 380 MHz
●
Up to 16 global clock networks with up to 32 regional clock
networks per device
●
High-speed DSP blocks provide dedicated implementation of
multipliers, multiply-accumulate functions, and finite impulse
response (FIR) filters
●
Up to four enhanced PLLs per device provide spread spectrum,
programmable bandwidth, clock switch-over, and advanced
multiplication and phase shifting
●
Support for numerous single-ended and differential I/O
standards
●
High-speed source-synchronous differential I/O support on up
to 47 channels
●
Support for source-synchronous bus standards, including SPI-4
Phase 2 (POS-PHY Level 4), SFI-4.1, XSBI, UTOPIA IV, NPSI,
and CSIX-L1
●
Support for high-speed external memory including double data
rate (DDR and DDR2) SDRAM, and single data rate (SDR)
SDRAM
●
Support for multiple intellectual property megafunctions from
Altera® MegaCore® functions and Altera Megafunction Partners
Program (AMPPSM)
●
Support for remote configuration updates
Table 1–1 lists Arria GX device features for FineLine BGA (FBGA) with
flip-chip packages.
Table 1–1. Arria GX Device Features (Part 1 of 2)
EP1AGX20C
EP1AGX35C/D
EP1AGX50C/D
EP1AGX60C/D/E
EP1AGX90E
Feature
Package
C
C
D
C
D
C
D
E
E
484-pin,
780-pin (Flipchip)
484-pin
(Flipchip)
780-pin
(Flipchip)
484-pin
(Flipchip)
780-pin,
1152-pin
(Flipchip)
484pin
(Flipchip)
780pin
(Flipchip)
1152pin
(Flipchip)
1152-pin
(Flip-chip)
ALMs
8,632
13,408
20,064
24,040
36,088
Equivalent
LEs
21,580
33,520
50,160
60,100
90,220
Transceiver
channels
4
Transceiver
data rate
600 Mbps to
3.125 Gbps
4
8
600 Mbps to 3.125
Gbps
1–2
Arria GX Device Handbook, Volume 1
4
8
600 Mbps to 3.125
Gbps
4
8
12
600 Mbps to 3.125
Gbps
12
600 Mbps to
3.125 Gbps
Altera Corporation
May 2008
Features
Table 1–1. Arria GX Device Features (Part 2 of 2)
EP1AGX20C
EP1AGX35C/D
EP1AGX50C/D
EP1AGX60C/D/E
EP1AGX90E
Feature
C
C
D
C
D
C
D
E
E
Sourcesynchronous
receive
channels
31
31
31
31
31, 42
31
31
42
47
Sourcesynchronous
transmit
channels
29
29
29
29
29, 42
29
29
42
45
M512 RAM
blocks (32 ×
18 bits)
166
197
313
326
478
M4K RAM
blocks (128 ×
36 bits)
118
140
242
252
400
M-RAM
blocks (4096
× 144 bits)
1
1
2
2
4
Total RAM
bits
1,229,184
1,348,416
2,475,072
2,528,640
4,477,824
Embedded
multipliers
(18 × 18)
40
56
104
128
176
DSP blocks
10
14
PLLs
4
4
Maximum
user I/O pins
230, 341
230
26
341
32
4
4, 8
4
229
350, 514
229
350
44
8
8
514
538
Arria GX devices are available in space-saving FBGA packages (refer to
Table 1–2). All Arria GX devices support vertical migration within the
same package. With vertical migration support, designers can migrate to
devices whose dedicated pins, configuration pins, and power pins are the
same for a given package across device densities. For I/O pin migration
Altera Corporation
May 2008
1–3
Arria GX Device Handbook, Volume 1
Arria GX Device Family Overview
across densities, the designer must cross-reference the available I/O pins
using the device pin-outs for all planned densities of a given package type
to identify which I/O pins are migratable.
Table 1–2. Arria GX Package Options (Pin Counts and Transceiver Channels)
Device
Transceiver
Channels
Source-Synchronous
Channels
Maximum User I/O Pin Count
Receive
Transmit
484-Pin FBGA
(23 mm)
780-Pin FBGA 1152-Pin FBGA
(29 mm)
(35 mm)
EP1AGX20C
4
31
29
230
341
—
EP1AGX35C
4
31
29
230
—
—
EP1AGX50C
4
31
29
229
—
—
EP1AGX60C
4
31
29
229
—
—
EP1AGX35D
8
31
29
—
341
—
EP1AGX50D
8
31, 42
29, 42
—
350
514
EP1AGX60D
8
31
29
—
350
—
EP1AGX60E
12
42
42
—
—
514
EP1AGX90E
12
47
45
—
—
538
Table 1–3 lists the Arria GX device package sizes.
Table 1–3. Arria GX FBGA Package Sizes
Dimension
484 Pins
780 Pins
Pitch (mm)
1.00
1.00
1.00
(mm2)
529
841
1225
23 × 23
29 × 29
35 × 35
Area
Length × width
(mm × mm)
1–4
Arria GX Device Handbook, Volume 1
1152 Pins
Altera Corporation
May 2008
Document Revision History
Document
Revision History
Table 1–4 shows the revision history for this chapter.
Table 1–4. Document Revision History
Date and
Document
Version
Changes Made
Summary of Changes
Included support for SDI, SerialLite II, and
XAUI.
—
June 2007, v1.1
Included GIGE information.
—
May 2007, v1.0
Initial Release
—
May 2008, v1.2
Altera Corporation
May 2008
1–5
Arria GX Device Handbook, Volume 1
Arria GX Device Family Overview
1–6
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
2. Arria GX Architecture
AGX51002-1.3
Transceivers
Arria™ GX devices incorporate up to 12 high-speed serial transceiver
channels that build on the success of the Stratix® II GX device family.
Arria GX transceivers are structured into full-duplex (transmitter and
receiver) four-channel groups called transceiver blocks located on the
right side of the device. The transceiver blocks can be configured to
support the following serial connectivity protocols (functional modes):
■
■
■
■
■
■
PCI Express (PIPE)
Gigabit Ethernet (GIGE)
XAUI
Basic (600 Mbps to 3.125 Gbps)
SDI (HD, 3G)
Serial RapidIO (1.25 Gbps, 2.5 Gbps, 3.125 Gbps)
Transceivers within each block are independent and have their own set of
dividers. Therefore, each transceiver can operate at different frequencies.
Each block can select from two reference clocks to provide two clock
domains that each transceiver can select from.
Table 2–1 shows the number of transceiver channels for each member of
the Arria GX family.
Table 2–1. Arria GX Transceiver Channels
Altera Corporation
May 2008
Device
Number of Transceiver Channels
EP1AGX20C
4
EP1AGX35C
4
EP1AGX35D
8
EP1AGX50C
4
EP1AGX50D
8
EP1AGX60C
4
EP1AGX60D
8
EP1AGX60E
12
EP1AGX90E
12
2–1
Transceivers
Figure 2–1 shows a high-level diagram of the transceiver block
architecture divided into four channels.
Figure 2–1. Transceiver Block
Transceiver Block
RX1
Channel 1
TX1
RX0
Channel 0
Arria GX
Logic Array
TX0
Supporting Blocks
(PLLs, State Machines,
Programming)
REFCLK_1
REFCLK_0
RX2
Channel 2
TX2
RX3
Channel 3
TX3
Each transceiver block has:
■
■
■
■
Four transceiver channels with dedicated physical coding sublayer
(PCS) and physical media attachment (PMA) circuitry
One transmitter PLL that takes in a reference clock and generates
high-speed serial clock depending on the functional mode
Four receiver PLLs and clock recovery unit (CRU) to recover clock
and data from the received serial data stream
State machines and other logic to implement special features
required to support each protocol
2–2
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
Arria GX Architecture
Figure 2–2 shows functional blocks that make up a transceiver channel.
Figure 2–2. Arria GX Transceiver Channel Block Diagram
PMA Analog Section
PCS Digital Section
n
Deserializer
(1)
FPGA Fabric
Word
Aligner
Rate
Matcher
Clock
Recovery
Unit
Reference
Clock
Receiver
PLL
Reference
Clock
Transmitter
PLL
XAUI
Lane
Deskew
8B/10B
Decoder
Byte
Deserializer
Phase
Compensation
FIFO Buffer
m
(2)
n
Serializer
(1)
8B/10B
Encoder
Phase
Compensation
FIFO Buffer
Byte
Serializer
m
(2)
Notes to Figure 2–2:
(1)
(2)
“n” represents the number of bits in each word that must be serialized by the transmitter portion of the PMA.
n = 8 or 10.
“m” represents the number of bits in the word that passes between the FPGA logic and the PCS portion of the
transceiver. m = 8, 10, 16, or 20.
Each transceiver channel is full-duplex and consists of a transmitter
channel and a receiver channel.
The transmitter channel contains the following sub-blocks:
■
■
■
■
■
Transmitter phase compensation first-in first-out (FIFO) buffer
Byte serializer (optional)
8B/10B encoder (optional)
Serializer (parallel-to-serial converter)
Transmitter differential output buffer
The receiver channel contains the following:
■
■
■
■
■
■
■
■
■
■
■
Altera Corporation
May 2008
Receiver differential input buffer
Receiver lock detector and run length checker
Clock recovery unit (CRU)
Deserializer
Pattern detector
Word aligner
Lane deskew
Rate matcher (optional)
8B/10B decoder (optional)
Byte deserializer (optional)
Receiver phase compensation FIFO buffer
2–3
Arria GX Device Handbook, Volume 1
Transceivers
You can configure the transceiver channels to the desired functional
modes usingthe ALT2GXB MegaCore instance in the Quartus® II
MegaWizard® Plug-in Manager for the Arria GX device family.
Depending on the selected functional mode, the Quartus II software
automatically configures the transceiver channels to employ a subset of
the sub-blocks listed above.
Transmitter Path
This section describes the data path through the Arria GX transmitter. The
sub-blocks are described in order from the PLD-transmitter parallel
interface to the serial transmitter buffer.
Clock Multiplier Unit
Each transceiver block has a clock multiplier unit (CMU) that takes in a
reference clock and synthesizes two clocks: a high-speed serial clock to
serialize the data and a low-speed parallel clock to clock the transmitter
digital logic (PCS).
The CMU is further divided into three sub-blocks:
■
■
■
One transmitter PLL
One central clock divider block
Four local clock divider blocks (one per channel)
2–4
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
Arria GX Architecture
Figure 2–3 shows the block diagram of the clock multiplier unit.
Figure 2–3. Clock Multiplier Unit
CMU Block
Transmitter High-Speed Serial
and Low-Speed Parallel Clocks
Transmitter Channels [3:2]
Local
Clock
TX Clock
Divider Block
Gen Block
Reference Clock
from REFCLKs,
Global Clock (1),
Inter-Transceiver
Lines
Transmitter
PLL
Central Clock
Divider
Block
Transmitter High-Speed Serial
and Low-Speed Parallel Clocks
Local
Clock
TX Clock
Divider Block
Transmitter Channels [1:0]
Gen Block
The transmitter PLL multiplies the input reference clock to generate the
high-speed serial clock required to support the intended protocol. It
implements a half-rate voltage controlled oscillator (VCO) that generates
a clock at half the frequency of the serial data rate for which it is
configured.
Altera Corporation
May 2008
2–5
Arria GX Device Handbook, Volume 1
Transceivers
Figure 2–4 shows the block diagram of the transmitter PLL.
Figure 2–4. Transmitter PLL
Transmitter PLL
/M
To
Inter-Transceiver Lines
Dedicated
REFCLK0
Dedicated
REFCLK1
/2
Phase
Frequency
Detector
INCLK
/2
(1)
up
down
Charge
Pump + Loop
Filter
Voltage
Controlled
Oscillator
/L(1)
High Speed
Serial Clock
Inter-Transceiver Lines[2:0]
Global Clock (2)
Notes to Figure 2–4:
(1)
(2)
You only need to select the protocol and the available input reference clock frequency in the ALTGXB MegaWizard
Plug-In Manager. Based on your selections, the MegaWizard Plug-In Manager automatically selects the necessary
/M and /L dividers (clock multiplication factors).
The global clock line must be driven from an input pin only.
The reference clock input to the transmitter PLL can be derived from:
■
■
■
One of two available dedicated reference clock input pins (REFCLK0
or REFCLK1) of the associated transceiver block
PLD global clock network (must be driven directly from an input
clock pin and cannot be driven by user logic or enhanced PLL)
Inter-transceiver block lines driven by reference clock input pins of
other transceiver blocks
1
Altera® recommends using the dedicated reference clock input
pins (REFCLK0 or REFCLK1) to provide reference clock for the
transmitter PLL.
Table 2–2 lists the adjustable parameters in the transmitter PLL.
Table 2–2. Transmitter PLL Specifications
Parameter
Input reference frequency range
Data rate support
Bandwidth
2–6
Arria GX Device Handbook, Volume 1
Specifications
50 MHz to 622.08 MHz
600 Mbps to 3.125 Gbps
Low, medium, or high
Altera Corporation
May 2008
Arria GX Architecture
The transmitter PLL output feeds the central clock divider block and the
local clock divider blocks. These clock divider blocks divide the
high-speed serial clock to generate the low-speed parallel clock for the
transceiver PCS logic and PLD-transceiver interface clock.
Transmitter Phase Compensation FIFO Buffer
A transmitter phase compensation FIFO is located at each transmitter
channel’s logic array interface. It compensates for the phase difference
between the transmitter PCS clock and the local PLD clock. The
transmitter phase compensation FIFO is used in all supported functional
modes. The transmitter phase compensation FIFO buffer is eight words
deep in PCI Express (PIPE) mode and four words deep in all other modes.
f
For more details about architecture and clocking, refer to the Arria GX
Transceiver Architecture chapter in volume 2 of the Arria GX Device
Handbook.
Byte Serializer
The byte serializer takes in two-byte wide data from the transmitter phase
compensation FIFO buffer and serializes it into a one-byte wide data at
twice the speed. The transmit data path after the byte serializer is 8 or 10
bits. This allows clocking the PLD-transceiver interface at half the speed
as compared to the transmitter PCS logic. The byte serializer is bypassed
in GIGE mode. After serialization, the byte serializer transmits the least
significant byte (LSByte) first and the most significant byte (MSByte) last.
Figure 2–5 shows byte serializer input and output. datain[15:0] is the
input to the byte serializer from the transmitter phase compensation
FIFO; dataout[7:0] is the output of the byte serializer.
Figure 2–5. Byte Serializer Operation Note (1)
D1
datain[15:0]
D2
{8'h00,8'h01}
D1LSByte
dataout[7:0]
xxxxxxxxxx
xxxxxxxxxx
D3
{8'h02,8'h03}
8'h01
D1MSByte
8'h00
xxxx
D2LSByte
8'h03
D2MSByte
8'h02
Note to Figure 2–5:
(1)
datain may be 16 or 20 bits. dataout may be 8 or 10 bits.
Altera Corporation
May 2008
2–7
Arria GX Device Handbook, Volume 1
Transceivers
8B/10B Encoder
The 8B/10B encoder block is used in all supported functional modes. The
8B/10B encoder block takes in 8-bit data from the byte serializer or the
transmitter phase compensation FIFO buffer. It generates a 10-bit code
group with proper running disparity from the 8-bit character and a 1-bit
control identifier (tx_ctrlenable). When tx_ctrlenable is low, the
8-bit character is encoded as data code group (Dx.y). When
tx_ctrlenable is high, the 8-bit character is encoded as a control code
group (Kx.y). The 10-bit code group is fed to the serializer. The 8B/10B
encoder conforms to the IEEE 802.3 1998 edition standard.
Figure 2–6 shows the 8B/10B conversion format.
f
For additional information regarding 8B/10B encoding rules, refer to the
Specifications and Additional Information chapter in volume 2 of the
Arria GX Device Handbook.
Figure 2–6. 8B/10B Encoder
7
6
5
4
3
2
1
0
H
G
F
E
D
C
B
A
Ctrl
8B-10B Conversion
j
h
g
f
i
e
d
c
b
a
9
8
7
6
5
4
3
2
1
0
MSB
LSB
During reset (tx_digitalreset), the running disparity and data
registers are cleared and the 8B/10B encoder outputs a K28.5 pattern
from the RD- column continuously. Once out of reset, the 8B/10B encoder
starts with a negative disparity (RD-) and transmits three K28.5 code
groups for synchronizing before it starts encoding the input data or
control character.
Transmit State Machine
The transmit state machine operates in either PCI Express (PIPE) mode,
XAUI mode, or GIGE mode, depending on the protocol used.
2–8
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Altera Corporation
May 2008
Arria GX Architecture
GIGE Mode
In GIGE mode, the transmit state machine converts all idle ordered sets
(/K28.5/, /Dx.y/) to either /I1/ or /I2/ ordered sets. The /I1/ set
consists of a negative-ending disparity /K28.5/ (denoted by /K28.5/-),
followed by a neutral /D5.6/. The /I2/ set consists of a positive-ending
disparity /K28.5/ (denoted by /K28.5/+) and a negative-ending
disparity /D16.2/ (denoted by /D16.2/-). The transmit state machines do
not convert any of the ordered sets to match /C1/ or /C2/, which are the
configuration ordered sets. (/C1/ and /C2/ are defined by [/K28.5/,
/D21.5/] and [/K28.5/, /D2.2/], respectively). Both the /I1/ and /I2/
ordered sets guarantee a negative-ending disparity after each ordered set.
XAUI Mode
The transmit state machine translates the XAUI XGMII code group to the
XAUI PCS code group. Table 2–3 shows the code conversion.
Table 2–3. On-Chip Termination Support by I/O Banks
XGMII TXC
XGMII TXD
PCS Code-Group
Description
0
00 through FF
Dxx.y
Normal data
1
07
K28.0 or K28.3 or K28.5
Idle in ||I||
1
07
K28.5
Idle in ||T||
1
9C
K28.4
Sequence
1
FB
K27.7
Start
1
FD
K29.7
Terminate
1
FE
K30.7
Error
1
See IEEE 802.3 reserved
code groups
See IEEE 802.3 reserved code groups
Reserved code groups
1
Other value
K30.7
Invalid XGMII character
The XAUI PCS idle code groups, /K28.0/ (/R/) and /K28.5/ (/K/), are
automatically randomized based on a PRBS7 pattern with an ×7 + ×6 + 1
polynomial. The /K28.3/ (/A/) code group is automatically generated
between 16 and 31 idle code groups. The idle randomization on the /A/,
/K/, and /R/ code groups is done automatically by the transmit state
machine.
Altera Corporation
May 2008
2–9
Arria GX Device Handbook, Volume 1
Transceivers
Serializer (Parallel-to-Serial Converter)
The serializer block clocks in 8- or 10-bit encoded data from the 8B/10B
encoder using the low-speed parallel clock and clocks out serial data
using the high-speed serial clock from the central or local clock divider
blocks. The serializer feeds the data LSB to MSB to the transmitter output
buffer.
Figure 2–7 shows the serializer block diagram.
Figure 2–7. Serializer
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
10
From 8B/10B
Encoder
To Transmitter
Output Buffer
Low-speed parallel clock
CMU
Central /
Local Clock
High-speed serial clock
Divider
Transmitter Buffer
The Arria GX transceiver buffers support the 1.2- and 1.5-V PCML I/O
standard at rates up to 3.125 Gbps. The common mode voltage (VCM) of
the output driver may be set to 600 or 700 mV.
f
Refer to the Arria GX Transceiver Architecture chapter in volume 2 of the
Arria GX Device Handbook.
The output buffer, as shown in Figure 2–8, is directly driven by the
high-speed data serializer and consists of a programmable output driver,
a programmable pre-emphasis circuit, and OCT circuitry.
2–10
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
Arria GX Architecture
Figure 2–8. Output Buffer
Serializer
Output Buffer
Programmable
Pre-Emphasis
Programmable
Output
Driver
Output
Pins
Programmable Output Driver
The programmable output driver can be set to drive out differentially 400
to 1200 mV. The differential output voltage (VOD) can be statically set by
using the ALTGXB megafunction.
The output driver may be configured using 100 Ω on-chip termination or
external termination.
Differential signaling conventions are shown in Figure 2–9. The
differential amplitude represents the value of the voltage between the
true and complement signals. Peak-to-peak differential voltage is defined
as 2 (VHIGH – VLOW) = 2 single-ended voltage swing. The common mode
voltage is the average of VHIGH and VLOW.
Altera Corporation
May 2008
2–11
Arria GX Device Handbook, Volume 1
Transceivers
Figure 2–9. Differential Signaling
Single-Ended Waveform
Vhigh
True
+VOD
Complement
Vlow
Differential Waveform
+400
+VOD
0-V Differential
2 * VOD
VOD (Differential)
-VOD
−400
= Vhigh − Vlow
Programmable Pre-Emphasis
The programmable pre-emphasis module controls the output driver to
boost high frequency components and compensate for losses in the
transmission medium, as shown in Figure 2–10. Pre-emphasis is set
statically using the ALTGXB megafunction.
Figure 2–10. Pre-Emphasis Signaling
VMAX
Pre-Emphasis % = (
VMIN
VMAX
− 1) × 100
VMIN
Pre-emphasis percentage is defined as (VMAX/VMIN – 1) × 100, where
VMAX is the differential emphasized voltage (peak-to-peak) and VMIN is
the differential steady-state voltage (peak-to-peak).
2–12
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
Arria GX Architecture
PCI Express (PIPE) Receiver Detect
The Arria GX transmitter buffer has a built-in receiver detection circuit
for use in PCI Express (PIPE) mode. This circuit provides the ability to
detect if there is a receiver downstream by sending out a pulse on the
channel and monitoring the reflection. This mode requires a tri-stated
transmitter buffer (in electrical idle mode).
PCI Express (PIPE) Electric Idles (or Individual Transmitter Tri-State)
The Arria GX transmitter buffer supports PCI Express (PIPE) electrical
idles. This feature is only active in PCI Express (PIPE) mode. The
tx_forceelecidle port puts the transmitter buffer in electrical idle
mode. This port is available in all PCI Express (PIPE) power-down modes
and has specific usage in each mode.
Receiver Path
This section describes the data path through the Arria GX receiver. The
sub-blocks are described in order from the receiver buffer to the
PLD-receiver parallel interface.
Receiver Buffer
The Arria GX receiver input buffer supports the 1.2 V and 1.5 V PCML
I/O standard at rates up to 3.125 Gbps. The common mode voltage of the
receiver input buffer is programmable between 0.85 V and 1.2 V. You
must select the 0.85 V common mode voltage for AC- and DC-coupled
PCML links and 1.2 V common mode voltage for DC-coupled LVDS links.
The receiver has on-chip 100 Ω differential termination for different
protocols, as shown in Figure 2–11. The receiver’s internal termination
can be disabled if external terminations and biasing are provided. The
receiver and transmitter differential termination method can be set
independently of each other.
Figure 2–11. Receiver Input Buffer
100 Ω
Termination
Input
Pins
Programmable
Equalizer
Differential
Input
Buffer
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May 2008
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Transceivers
If a design uses external termination, the receiver must be externally
terminated and biased to 0.85 V or 1.2 V. Figure 2–12 shows an example
of an external termination and biasing circuit.
Figure 2–12. External Termination and Biasing Circuit
Receiver External Termination
and Biasing
Arria GX Device
VDD
50-Ω
Termination
Resistance
R1
C1
Receiver
R1/R2 = 1K
VDD × {R2/(R1 + R 2)} = 0.85/1.2 V
RXIP
R2
RXIN
Receiver External Termination
and Biasing
Transmission
Line
Programmable Equalizer
The Arria GX receivers provide a programmable receiver equalization
feature to compensate for the effects of channel attenuation for highspeed signaling. PCB traces carrying these high-speed signals have lowpass filter characteristics. Impedance mismatch boundaries can also
cause signal degradation. Equalization in the receiver diminishes the
lossy attenuation effects of the PCB at high frequencies.
The receiver equalization circuit is comprised of a programmable
amplifier. Each stage is a peaking equalizer with a different center
frequency and programmable gain. This allows varying amounts of gain
to be applied, depending on the overall frequency response of the channel
loss. Channel loss is defined as the summation of all losses through the
PCB traces, vias, connectors, and cables present in the physical link. The
Quartus II software allows five equalization settings for Arria GX devices.
Receiver PLL and Clock Recovery Unit (CRU)
Each transceiver block has four receiver PLLs and CRU units, each of
which is dedicated to a receiver channel. The receiver PLL is fed by an
input reference clock. The receiver PLL, in conjunction with the CRU,
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May 2008
Arria GX Architecture
generates two clocks: a high-speed serial recovered clock that clocks the
deserializer and a low-speed parallel recovered clock that clocks the
receiver's digital logic.
Figure 2–13 shows a block diagram of the receiver PLL and CRU circuits.
Figure 2–13. Receiver PLL and Clock Recovery Unit
/M
Dedicated
REFCLK0
rx_pll_locked
/2
PFD
Dedicated
/2
REFCLK1
Inter-Transceiver Lines [2:0]
rx_cruclk
up
dn
up
dn
CP+ LF
VCO
/L
Global Clock (2)
rx_freqlocked
rx_locktorefclk
rx_locktodata
Clock Recovery Unit (CRU) Control
rx_datain
High-speed serial recovered clk
Low-speed parallel recovered clk
Notes to Figure 2–13:
(1)
(2)
You only need to select the protocol and the available input reference clock frequency in the ALTGXB MegaWizard
Plug-In Manager. Based on your selections, the ALTGXB MegaWizard Plug-In Manager automatically selects the
necessary /M and /L dividers.
The global clock line must be driven from an input pin only.
The reference clock input to the receiver PLL can be derived from:
■
■
■
One of the two available dedicated reference clock input pins
(REFCLK0 or REFCLK1) of the associated transceiver block
PLD global clock network (must be driven directly from an input
clock pin and cannot be driven by user logic or enhanced PLL)
Inter-transceiver block lines driven by reference clock input pins of
other transceiver blocks
All the parameters listed are programmable in the Quartus II software.
The receiver PLL has the following features:
■
■
■
■
■
■
■
Altera Corporation
May 2008
Operates from 600 Mbps to 3.125 Gbps.
Uses a reference clock between 50 MHz and 622.08 MHz.
Programmable bandwidth settings: low, medium, and high.
Programmable rx_locktorefclk (forces the receiver PLL to lock
to reference clock) and rx_locktodata (forces the receiver PLL to
lock to data).
The voltage-controlled oscillator (VCO) operates at half rate.
Programmable frequency multiplication W of 1, 4, 5, 8, 10, 16, 20, and
25. Not all settings are supported for any particular frequency.
Two lock indication signals are provided. They are found in PFD
mode (lock-to-reference clock), and PD (lock-to-data).
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The clock recovery unit controls whether the receiver PLL locks to the
input reference clock (lock-to-reference mode) or the incoming serial data
(lock-to data mode). You can set the CRU to switch between lock-to-data
and lock-to-reference modes automatically or manually. In automatic
lock mode, the phase detector and dedicated parts per million (PPM)
detector within each receiver channel control the switch between
lock-to-data and lock-to-reference modes based on some pre-set
conditions. In manual lock mode, you control the switch manually using
the rx_locktorefclk and rx_locktodata signals.
f
For more details, refer to the Clock Recovery Unit section in the Arria GX
Transceiver Protocol Support and Additional Features chapter in volume 2 of
the Arria GX Device Handbook.
Table 2–4 show the behavior of THE CRU block with respect to the
rx_locktorefclk and rx_locktodata signals.
Table 2–4. CRU Manual Lock Signals
rx_locktorefclk
rx_locktodata
CRU Mode
1
0
Lock-to-reference clock
x
1
Lock-to-data
0
0
Automatic
If the rx_locktorefclk and rx_locktodata ports are not used, the
default is automatic lock mode.
Deserializer
The deserializer block clocks in serial input data from the receiver buffer
using the high-speed serial recovered clock and deserializes into 8- or
10-bit parallel data using the low-speed parallel recovered clock. The
serial data is assumed to be received with LSB first, followed by MSB. It
feeds the deserialized 8- or 10-bit data to the word aligner, as shown in
Figure 2–14.
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Arria GX Architecture
Figure 2–14. Deserializer Note (1)
Received Data
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
10
To Word
Aligner
Clock
High-speed serial recovered clock
Recovery
Unit
Low -speed parallel recovered clock
Note to Figure 2–14:
(1)
This is a 10-bit deserializer. The deserializer can also convert 8 bits of data.
Word Aligner
The deserializer block creates 8- or 10-bit parallel data. The deserializer
ignores protocol symbol boundaries when converting this data.
Therefore, the boundaries of the transferred words are arbitrary. The
word aligner aligns the incoming data based on specific byte or word
boundaries. The word alignment module is clocked by the local receiver
recovered clock during normal operation. All the data and programmed
patterns are defined as “big-endian” (most significant word followed by
least significant word). Most-significant-bit-first protocols should reverse
the bit order of word align patterns programmed.
This module detects word boundaries for 8B/10B-based protocols. This
module is also used to align to specific programmable patterns in
PRBS7/23 test mode.
Pattern Detection
The programmable pattern detection logic can be programmed to align
word boundaries using a single 7- or 10-bit pattern. The pattern detector
can either do an exact match, or match the exact pattern and the
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May 2008
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Transceivers
complement of a given pattern. Once the programmed pattern is found,
the data stream is aligned to have the pattern on the LSB portion of the
data output bus.
XAUI, GIGE, PCI Express (PIPE), and Serial RapidIO standards have
embedded state machines for symbol boundary synchronization. These
standards use K28.5 as their 10-bit programmed comma pattern. Each of
these standards uses different algorithms before signaling symbol
boundary acquisition to the FPGA.
pattern detection logic searches from the LSB to the most significant bit
(MSB). If multiple patterns are found within the search window, the
pattern in the lower portion of the data stream (corresponding to the
pattern received earlier) is aligned and the rest of the matching patterns
are ignored.
Once a pattern is detected and the data bus is aligned, the word boundary
is locked. The two detection status signals (rx_syncstatus and
rx_patterndetect) indicate that an alignment is complete.
Figure 2–15 is a block diagram of the word aligner.
Figure 2–15. Word Aligner
datain
bitslip
Word
Aligner
enapatternalign
dataout
syncstatus
patterndetect
clock
Control and Status Signals
The rx_enapatternalign signal is the FPGA control signal that
enables word alignment in non-automatic modes. The
rx_enapatternalign signal is not used in automatic modes (PCI
Express [PIPE], XAUI, GIGE, and Serial RapidIO).
In manual alignment mode, after the rx_enapatternalign signal is
activated, the rx_syncstatus signal goes high for one parallel clock
cycle to indicate that the alignment pattern has been detected and the
word boundary has been locked. If rx_enapatternalign is
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Arria GX Architecture
deactivated, the rx_syncstatus signal acts as a re-synchronization
signal to signify that the alignment pattern has been detected but not
locked on a different word boundary.
When using the synchronization state machine, the rx_syncstatus
signal indicates the link status. If the rx_syncstatus signal is high, link
synchronization is achieved. If the rx_syncstatus signal is low, link
synchronization has not yet been achieved, or there were enough code
group errors to lose synchronization.
f
For more information about manual alignment modes, refer to the
Arria GX Device Handbook.
The rx_patterndetect signal pulses high during a new alignment
and whenever the alignment pattern occurs on the current word
boundary.
Programmable Run Length Violation
The word aligner supports a programmable run length violation counter.
Whenever the number of the continuous ‘0’ (or ‘1’) exceeds a user
programmable value, the rx_rlv signal goes high for a minimum pulse
width of two recovered clock cycles. The maximum run values supported
are 128 UI for 8-bit serialization or 160 UI for 10-bit serialization.
Running Disparity Check
The running disparity error rx_disperr and running disparity value
rx_runningdisp are sent along with aligned data from the 8B/10B
decoder to the FPGA. You can ignore or act on the reported running
disparity value and running disparity error signals.
Bit-Slip Mode
The word aligner can operate in either pattern detection mode or in
bit-slip mode.
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May 2008
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Transceivers
The Bit-slip mode provides the option to manually shift the word
boundary through the FPGA. This feature is useful for:
■
■
■
Longer synchronization patterns than the pattern detector can
accommodate
Scrambled data stream
Input stream consisting of over-sampled data
The word aligner outputs a word boundary as it is received from the
analog receiver after reset. You can examine the word and search its
boundary in the FPGA. To do so, assert the rx_bitslip signal. The
rx_bitslip signal should be toggled and held constant for at least two
FPGA clock cycles.
For every rising edge of the rx_bitslip signal, the current word
boundary is slipped by one bit. Every time a bit is slipped, the bit received
earliest is lost. If bit slipping shifts a complete round of bus width, the
word boundary is back to the original boundary.
The rx_syncstatus signal is not available in bit-slipping mode.
Channel Aligner
The channel aligner is available only in XAUI mode and aligns the signals
of all four channels within a transceiver. The channel aligner follows the
IEEE 802.3ae, clause 48 specification for channel bonding.
The channel aligner is a 16-word FIFO buffer with a state machine
controlling the channel bonding process. The state machine looks for an
/A/ (/K28.3/) in each channel and aligns all the /A/ code groups in the
transceiver. When four columns of /A/ (denoted by //A//) are
detected, the rx_channelaligned signal goes high, signifying that all
the channels in the transceiver have been aligned. The reception of four
consecutive misaligned /A/ code groups restarts the channel alignment
sequence and sends the rx_channelaligned signal low.
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Arria GX Architecture
Figure 2–16 shows misaligned channels before the channel aligner and
the aligned channels after the channel aligner.
Figure 2–16. Before and After the Channel Aligner
Before
Lane 3
K
K
A
K
R
R
K
K
R
K
R
K
K
R
A
K
R
R
K
K
R
K
K
R
A
K
R
R
K
K
R
K
R
Lane 2
Lane 1
K
Lane 0
After
R
K
K
R
A
K
R
R
K
K
R
K
Lane 3
K
K
R
A
K
R
R
K
K
R
K
R
Lane 2
K
K
R
A
K
R
R
K
K
R
K
R
Lane 1
K
K
R
A
K
R
R
K
K
R
K
R
Lane 0
K
K
R
A
K
R
R
K
K
R
K
R
R
R
Rate Matcher
In asynchronous systems, the upstream transmitter and local receiver
may be clocked with independent reference clock sources. Frequency
differences in the order of a few hundred PPM can potentially corrupt the
data at the receiver.
The rate matcher compensates for small clock frequency differences
between the upstream transmitter and the local receiver clocks by
inserting or removing skip characters from the inter packet gap (IPG) or
idle streams. It inserts a skip character if the local receiver is running a
faster clock than the upstream transmitter. It deletes a skip character if the
local receiver is running a slower clock than the upstream transmitter. The
Quartus II software automatically configures the appropriate skip
character as specified in the IEEE 802.3 for GIGE mode and PCI-Express
Base Specification for PCI Express (PIPE) mode. The rate matcher is
bypassed in Serial RapidIO and must be implemented in the PLD logic
array or external circuits depending on your system design.
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May 2008
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Transceivers
Table 2–5 shows the maximum frequency difference that the rate matcher
can tolerate in XAUI, PCI Express (PIPE), GIGE, and Basic functional
modes.
Table 2–5. Rate Matcher PPM Tolerance
Function Mode
PPM
XAUI
± 100
PCI Express (PIPE)
± 300
GIGE
± 100
Basic
± 300
XAUI Mode
In XAUI mode, the rate matcher adheres to clause 48 of the IEEE 802.3ae
specification for clock rate compensation. The rate matcher performs
clock compensation on columns of /R/ (/K28.0/), denoted by //R//.
An //R// is added or deleted automatically based on the number of
words in the FIFO buffer.
PCI Express (PIPE) Mode Rate Matcher
In PCI Express (PIPE) mode, the rate matcher can compensate up to
± 300 PPM (600 PPM total) frequency difference between the upstream
transmitter and the receiver. The rate matcher logic looks for skip ordered
sets (SOS), which contains a /K28.5/ comma followed by three /K28.0/
skip characters. The rate matcher logic deletes or inserts /K28.0/ skip
characters as necessary from/to the rate matcher FIFO.
The rate matcher in PCI Express (PIPE) mode has a FIFO buffer overflow
and underflow protection. In the event of a FIFO buffer overflow, the rate
matcher deletes any data after detecting the overflow condition to
prevent FIFO pointer corruption until the rate matcher is not full. In an
underflow condition, the rate matcher inserts 9'h1FE (/K30.7/) until the
FIFO buffer is not empty. These measures ensure that the FIFO buffer can
gracefully exit the overflow and underflow condition without requiring a
FIFO reset. The rate matcher FIFO overflow and underflow condition is
indicated on the pipestatus port.
You can bypass the rate matcher in PCI Express (PIPE) mode if you have
a synchronous system where the upstream transmitter and local receiver
derive their reference clocks from the same source.
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GIGE Mode Rate Matcher
In GIGE mode, the rate matcher can compensate up to ± 100 PPM
(200 PPM total) frequency difference between the upstream transmitter
and the receiver. The rate matcher logic inserts or deletes /I2/ idle
ordered sets to/from the rate matcher FIFO during the inter-frame or
inter-packet gap (IFG or IPG). /I2/ is selected as the rate matching
ordered set since it maintains the running disparity, unlike /I1/ that
alters the running disparity. Since the /I2/ ordered-set contains two
10-bit code groups (/K28.5/, /D16.2/), 20 bits are inserted or deleted at a
time for rate matching.
1
The rate matcher logic has the capability to insert or delete /C1/
or /C2/ configuration ordered sets when ‘GIGE Enhanced’
mode is chosen as the sub-protocol in the MegaWizard Plug-In
Manager.
If the frequency PPM difference between the upstream transmitter and
the local receiver is high, or if the packet size is too large, the rate matcher
FIFO buffer can face an overflow or underflow situation.
Basic Mode
In Basic mode, you can program the skip and control pattern for rate
matching. There is no restriction on the deletion of a skip character in a
cluster. The rate matcher deletes the skip characters as long as they are
available. For insertion, the rate matcher inserts skip characters such that
the number of skip characters at the output of rate matcher does not
exceed five.
8B/10B Decoder
The 8B/10B decoder is used in all supported functional modes. The
8B/10B decoder takes in 10-bit data from the rate matcher and decodes it
into 8-bit data + 1-bit control identifier, thereby restoring the original
transmitted data at the receiver. The 8B/10B decoder indicates whether
the received 10-bit character is a data or control code through the
rx_ctrldetect port. If the received 10-bit code group is a control
character (Kx.y), the rx_ctrldetect signal is driven high and if it is a
data character (Dx.y), the rx_ctrldetect signal is driven low.
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May 2008
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Transceivers
Figure 2–17 shows a 10-bit code group decoded to an 8-bit data and a 1-bit
control indicator.
Figure 2–17. 10-Bit to 8-Bit Conversion
j
h
g
f
i
e
d
c
b
a
9
8
7
6
5
4
3
2
1
0
MSB Received Last
LSB Received First
8B/10B Conversion
ctrl
7
6
5
4
3
2
1
0
H
G
F
E
D
C
B
A
Parallel Data
If the received 10-bit code is not a part of valid Dx.y or Kx.y code groups,
the 8B/10B decoder block asserts an error flag on the rx_errdetect
port. If the received 10-bit code is detected with incorrect running
disparity, the 8B/10B decoder block asserts an error flag on the
rx_disperr and rx_errdetect ports. The error flag signals
(rx_errdetect and rx_disperr) have the same data path delay from
the 8B/10B decoder to the PLD-transceiver interface as the bad code
group.
Receiver State Machine
The receiver state machine operates in Basic, GIGE, PCI Express (PIPE),
and XAUI modes. In GIGE mode, the receiver state machine replaces
invalid code groups with K30.7. In XAUI mode, the receiver state
machine translates the XAUI PCS code group to the XAUI XGMII code
group.
Byte Deserializer
Byte deserializer takes in one-byte wide data from the 8B/10B decoder
and deserializes it into a two-byte wide data at half the speed. This allows
clocking the PLD-receiver interface at half the speed as compared to the
receiver PCS logic. The byte deserializer is bypassed in GIGE mode.
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Arria GX Architecture
The byte ordering at the receiver output might be different than what was
transmitted. This is a non-deterministic swap, because it depends on PLL
lock times and link delay. If required, you must implement byte ordering
logic in the PLD to correct this situation.
f
For more details, refer to the Arria GX Transceiver Architecture chapter in
volume 2 of Arria GX Device Handbook.
Receiver Phase Compensation FIFO Buffer
A receiver phase compensation FIFO buffer is located at each receiver
channel’s logic array interface. It compensates for the phase difference
between the receiver PCS clock and the local PLD receiver clock. The
receiver phase compensation FIFO is used in all supported functional
modes. The receiver phase compensation FIFO buffer is eight words deep
in PCI Express (PIPE) mode and four words deep in all other modes.
f
For more details about architecture and clocking, refer to the Arria GX
Transceiver Architecture chapter in volume 2 of Arria GX Device Handbook.
Loopback Modes
Arria GX transceivers support the following loopback configurations for
diagnostic purposes:
■
■
■
■
Altera Corporation
May 2008
Serial loopback
Reverse serial loopback
Reverse serial loopback (pre-CDR)
PCI Express (PIPE) reverse parallel loopback (available only in
[PIPE] mode)
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Serial Loopback
Figure 2–18 shows the transceiver data path in serial loopback.
Figure 2–18. Transceiver Data Path in Serial Loopback
Transmitter PCS
TX Phase
Compensation
FIFO
Byte
Serializer
Transmitter PMA
8B/10B
Encoder
Serializer
PLD
Logic
Array
Serial Loopback
Receiver PCS
RX Phase
Compensation
FIFO
Byte
DeSerializer
8B/10B
Decoder
Rate
Match
FIFO
Word
Aligner
Receiver PMA
DeSerializer
Clock
Recovery
Unit
In GIGE and Serial RapidIO modes, you can dynamically put each
transceiver channel individually in serial loopback by controlling the
rx_seriallpbken port. A high on the rx_seriallpbken port puts
the transceiver into serial loopback and a low takes the transceiver out of
serial loopback.
As seen in Figure 2–18, the serial data output from the transmitter
serializer is looped back to the receiver CRU in serial loopback. The
transmitter data path from the PLD interface to the serializer in serial
loopback is the same as in non-loopback mode. The receiver data path
from the clock recovery unit to the PLD interface in serial loopback is the
same as in non-loopback mode. Since the entire transceiver data path is
available in serial loopback, this option is often used to diagnose the data
path as a probable cause of link errors.
1
When serial loopback is enabled, the transmitter output buffer is
still active and drives the serial data out on the tx_dataout
port.
Reverse Serial Loopback
Reverse serial loopback mode uses the analog portion of the transceiver.
An external source (pattern generator or transceiver) generates the source
data. The high-speed serial source data arrives at the high-speed
differential receiver input buffer, passes through the CRU unit and the
retimed serial data is looped back, and is transmitted though the
high-speed differential transmitter output buffer.
Figure 2–19 shows the data path in reverse serial loopback mode.
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Arria GX Architecture
Figure 2–19. Arria GX Block in Reverse Serial Loopback Mode
Transmitter Digital Logic
Analog Receiver and
Transmitter Logic
BIST
PRBS
Generator
BIST
Incremental
Generator
TX Phase
Compensation
FIFO
Byte
Serializer
8B/10B
20 Encoder
Serializer
FPGA
Logic
Array
Reverse
Serial
Loopback
BIST
Incremental
Verify
RX Phase
Compensation
FIFO
BIST
PRBS
Verify
Byte
Deserializer
8B/10B
Decoder
Rate
Match
FIFO
Deskew
FIFO
Word
Aligner
Deserializer
Clock
Recovery
Unit
Receiver Digital Logic
Reverse Serial Pre-CDR Loopback
Reverse serial pre-CDR loopback mode uses the analog portion of the
transceiver. An external source (pattern generator or transceiver)
generates the source data. The high-speed serial source data arrives at the
high-speed differential receiver input buffer, loops back before the CRU
unit, and is transmitted though the high-speed differential transmitter
output buffer. It is for test or verification use only to verify the signal
being received after the gain and equalization improvements of the input
buffer. The signal at the output is not exactly what is received since the
signal goes through the output buffer and the VOD is changed to the VOD
setting level. Pre-emphasis settings have no effect.
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Transceivers
Figure 2–20 show the Arria GX block in reverse serial pre-CDR loopback
mode.
Figure 2–20. Arria GX Block in Reverse Serial Pre-CDR Loopback Mode
Transmitter Digital Logic
Analog Receiver and
Transmitter Logic
BIST
PRBS
Generator
BIST
Incremental
Generator
TX Phase
Compensation
FIFO
Byte
Serializer
8B/10B
20 Encoder
Serializer
FPGA
Logic
Array
BIST
Incremental
Verify
Reverse
Serial
Pre-CDR
Loopback
BIST
PRBS
Verify
Byte
Deserializer
RX Phase
Compensation
FIFO
8B/10B
Decoder
Rate
Match
FIFO
Deskew
FIFO
Word
Aligner
Deserializer
Clock
Recovery
Unit
Receiver Digital Logic
PCI Express (PIPE) Reverse Parallel Loopback
Figure 2–21 shows the data path for PCI Express (PIPE) reverse parallel
loopback. The reverse parallel loopback configuration is compliant with
the PCI Express (PIPE) specification and is available only on PCI Express
(PIPE) mode.
Figure 2–21. PCI Express (PIPE) Reverse Parallel Loopback
Transmitter PCS
TX Phase
Compensation
FIFO
Byte
Serializer
Transmitter PMA
8B/10B
Encoder
PIPE
Interface
Serializer
PIPE Reverse
Parallel Loopback
Receiver PCS
RX Phase
Compensation
FIFO
Byte
DeSerializer
8B/10B
Decoder
Rate
Match
FIFO
Word
Aligner
Receiver PMA
DeSerializer
Clock
Recovery
Unit
You can dynamically put the PCI Express (PIPE) mode transceiver in
reverse parallel loopback by controlling the tx_detectrxloopback
port instantiated in the MegaWizard Plug-In Manager. A high on the
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tx_detectrxloopback port in P0 power state puts the transceiver in
reverse parallel loopback. A high on the tx_detectrxloopback port in
any other power state does not put the transceiver in reverse parallel
loopback.
As seen in Figure 2–21, the serial data received on the rx_datain port in
reverse parallel loopback goes through the CRU, deserializer, word
aligner, and the rate matcher blocks. The parallel data at the output of the
receiver rate matcher block is looped back to the input of the transmitter
serializer block. The serializer converts the parallel data to serial data and
feeds it to the transmitter output buffer that drives the data out on the
tx_dataout port. The data at the output of the rate matcher also goes
through the 8B/10B decoder, byte deserializer, and receiver phase
compensation FIFO before being fed to the PLD on the rx_dataout port.
Reset and Powerdown
Arria GX transceivers offer a power saving advantage with their ability to
shut off functions that are not needed.
The following three reset signals are available per transceiver channel
and can be used to individually reset the digital and analog portions
within each channel:
■
■
■
tx_digitalreset
rx_analogreset
rx_digitalreset
The following two powerdown signals are available per transceiver block
and can be used to shut down an entire transceiver block that is not being
used:
■
■
Altera Corporation
May 2008
gxb_powerdown
gxb_enable
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Arria GX Device Handbook, Volume 1
Transceivers
Table 2–6 shows the reset signals available in Arria GX devices and the
transceiver circuitry affected by each signal.
v
rx_digitalreset
v
v
v
v
rx_analogreset
tx_digitalreset
v
v
gxb_powerdown
v
v
v
v
gxb_enable
v
v
v
v
v
Receiver Analog Circuits
BIST Verifiers
Receiver XAUI State Machine
Receiver PLL / CRU
Receiver Phase Comp FIFO Module/ Byte Deserializer
Receiver 8B/10B Decoder
Receiver Rate Matcher
Receiver Deskew FIFO Module
Receiver Word Aligner
Receiver Deserializer
BIST Generators
Transmitter XAUI State Machine
Transmitter PLL
Transmitter Analog Circuits
Transmitter Serializer
Transmitter 8B/10B Encoder
Reset Signal
Transmitter Phase Compensation FIFO Module/ Byte Serializer
Table 2–6. Reset Signal Map to Arria GX Blocks
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Calibration Block
Arria GX devices use the calibration block to calibrate on-chip
termination for the PLLs and their associated output buffers and the
terminating resistors on the transceivers. The calibration block counters
the effects of process, voltage, and temperature (PVT). The calibration
block references a derived voltage across an external reference resistor to
calibrate the on-chip termination resistors on Arria GX devices. The
calibration block can be powered down. However, powering down the
calibration block during operations may yield transmit and receive data
errors.
2–30
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May 2008
Arria GX Architecture
Transceiver Clocking
This section describes the clock distribution within an Arria GX
transceiver channel and the PLD clock resource utilization by the
transceiver blocks.
Transceiver Channel Clock Distribution
Each transceiver block has one transmitter PLL and four receiver PLLs.
The transmitter PLL multiplies the input reference clock to generate a
high-speed serial clock at a frequency that is half the data rate of the
configured functional mode. This high-speed serial clock (or its
divide-by-two version if the functional mode uses byte serializer) is fed
to the CMU clock divider block. Depending on the configured functional
mode, the CMU clock divider block divides the high-speed serial clock to
generate the low-speed parallel clock that clocks the transceiver PCS logic
in the associated channel. The low-speed parallel clock is also forwarded
to the PLD logic array on the tx_clkout or coreclkout ports.
The receiver PLL in each channel is also fed by an input reference clock.
The receiver PLL along with the clock recovery unit generates a
high-speed serial recovered clock and a low-speed parallel recovered
clock. The low-speed parallel recovered clock feeds the receiver PCS logic
until the rate matcher. The CMU low-speed parallel clock clocks the rest
of the logic from the rate matcher until the receiver phase compensation
FIFO. In modes that do not use a rate matcher, the receiver PCS logic is
clocked by the recovered clock until the receiver phase compensation
FIFO.
The input reference clock to the transmitter and receiver PLLs can be
derived from:
■
■
■
Altera Corporation
May 2008
One of two available dedicated reference clock input pins (REFCLK0
or REFCLK1) of the associated transceiver block
PLD clock network (must be driven directly from an input clock pin
and cannot be driven by user logic or enhanced PLL)
Inter-transceiver block lines driven by reference clock input pins of
other transceiver blocks
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Arria GX Device Handbook, Volume 1
Transceivers
Figure 2–22 shows the input reference clock sources for the transmitter
and receiver PLL.
Figure 2–22. Input Reference Clock Sources
Inter-Transceiver Lines [2]
Transceiver Block 2
Inter-Transceiver Lines [1]
Transceiver Block 1
Transceiver Block 0
Inter-Transceiver Lines [0]
Dedicated
REFCLK0
/2
Dedicated
REFCLK1
/2
Transmitter
PLL
Inter-Transceiver Lines [2:0]
Global Clock (1)
Four
Receiver
PLLs
Global Clock (1)
f
For detailed transceiver clocking in all supported functional modes, refer
to the Arria GX Transceiver Architecture chapter in volume 2 of the
Arria GX Device Handbook.
PLD Clock Utilization by Transceiver Blocks
Arria GX devices have up to 16 global clock (GCLK) lines and 16 regional
clock (RCLK) lines that are used to route the transceiver clocks. The
following transceiver clocks utilize the available global and regional clock
resources:
■
■
■
■
pll_inclk (if driven from an FPGA input pin)
rx_cruclk (if driven from an FPGA input pin)
tx_clkout/coreclkout (CMU low-speed parallel clock
forwarded to the PLD)
Recovered clock from each channel (rx_clkout) in non-rate
matcher mode
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Altera Corporation
May 2008
Arria GX Architecture
■
■
Calibration clock (cal_blk_clk)
Fixed clock (fixedclk used for receiver detect circuitry in PCI
Express [PIPE] mode only)
Figures 2–23 and 2–24 show the available global and regional clock
resources in Arria GX devices.
Figure 2–23. Global Clock Resources in Arria GX Devices
CLK[15..12]
11 5
7
Arria GX
Transceiver
Block
GCLK[15..12]
CLK[3..0]
1
2
GCLK[11..8]
GCLK[3..0]
GCLK[4..7]
Arria GX
Transceiver
Block
8
12 6
CLK[7..4]
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May 2008
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Arria GX Device Handbook, Volume 1
Transceivers
Figure 2–24. Regional Clock Resources in Arria GX Devices
CLK[15..12]
11 5
7
CLK[3..0]
RCLK
[31..28]
RCLK
[27..24]
RCLK
[3..0]
RCLK
[23..20]
RCLK
[7..4]
RCLK
[19..16]
Arria GX
Transceiver
Block
1
2
8
RCLK
[11..8]
Arria GX
Transceiver
Block
RCLK
[15..12]
12 6
CLK[7..4]
For the regional or global clock network to route into the transceiver, a
local route input output (LRIO) channel is required. Each LRIO clock
region has up to eight clock paths and each transceiver block has a
maximum of eight clock paths for connecting with LRIO clocks. These
resources are limited and determine the number of clocks that can be used
between the PLD and transceiver blocks. Tables 2–7 and 2–8 give the
number of LRIO resources available for Arria GX devices with different
number of transceiver blocks.
Table 2–7. Available Clocking Connections for Transceivers in EP1AGX35D,
EP1AGX50D, and EP1AGX60D
Clock Resource
Source
Global Clock
Regional
Clock
Bank13
8 Clock I/O
v
Region0
8 LRIO clock
v
RCLK 20-27
Region1
8 LRIO clock
v
RCLK 12-19
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Arria GX Device Handbook, Volume 1
Transceiver
Bank14
8 Clock I/O
v
Altera Corporation
May 2008
Arria GX Architecture
Table 2–8. Available Clocking Connections for Transceivers in EP1AGX60E and EP1AGX90E
Clock Resource
Source
Global Clock
Transceiver
Regional
Clock
Bank13
8 Clock I/O
Region0
8 LRIO clock
v
RCLK 20-27
v
Region1
8 LRIO clock
v
RCLK 20-27
v
Region2
8 LRIO clock
v
RCLK 12-19
Region3
8 LRIO clock
v
RCLK 12-19
Logic Array
Blocks
Bank14
8 Clock I/O
Bank15
8 Clock I/O
v
v
v
v
Each logic array block (LAB) consists of eight adaptive logic modules
(ALMs), carry chains, shared arithmetic chains, LAB control signals, local
interconnects, and register chain connection lines. The local interconnect
transfers signals between ALMs in the same LAB. Register chain
connections transfer the output of an ALM register to the adjacent ALM
register in a LAB. The Quartus II Compiler places associated logic in a
LAB or adjacent LABs, allowing the use of local, shared arithmetic chain,
and register chain connections for performance and area efficiency.
Table 2–9 shows Arria GX device resources. Figure 2–25 shows the
Arria GX LAB structure.
Table 2–9. Arria GX Device Resources
Device
Altera Corporation
May 2008
M512 RAM
M4K RAM
Columns/Blocks Columns/Blocks
M-RAM
Blocks
DSP Block
Columns/Blocks
EP1AGX20
166
118
1
10
EP1AGX35
197
140
1
14
EP1AGX50
313
242
2
26
EP1AGX60
326
252
2
32
EP1AGX90
478
400
4
44
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Arria GX Device Handbook, Volume 1
Logic Array Blocks
Figure 2–25. Arria GX LAB Structure
Row Interconnects of
Variable Speed & Length
ALMs
Direct link
interconnect from
adjacent block
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
Direct link
interconnect to
adjacent block
Local Interconnect
LAB
Local Interconnect is Driven
from Either Side by Columns & LABs,
& from Above by Rows
Column Interconnects of
Variable Speed & Length
LAB Interconnects
The LAB local interconnect can drive all eight ALMs in the same LAB. It
is driven by column and row interconnects and ALM outputs in the same
LAB. Neighboring LABs, M512 RAM blocks, M4K RAM blocks, M-RAM
blocks, or digital signal processing (DSP) blocks from the left and right
can also drive a LAB's local interconnect through the direct link
connection. The direct link connection feature minimizes the use of row
and column interconnects, providing higher performance and flexibility.
Each ALM can drive 24 ALMs through fast local and direct link
interconnects.
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May 2008
Arria GX Architecture
Figure 2–26 shows the direct link connection.
Figure 2–26. Direct Link Connection
Direct link interconnect from
left LAB, TriMatrixTM memory
block, DSP block, or
input/output element (IOE)
Direct link interconnect from
right LAB, TriMatrix memory
block, DSP block, or IOE output
ALMs
Direct link
interconnect
to right
Direct link
interconnect
to left
Local
Interconnect
LAB
LAB Control Signals
Each LAB contains dedicated logic for driving control signals to its ALMs.
The control signals include three clocks, three clock enables, two
asynchronous clears, synchronous clear, asynchronous preset/load, and
synchronous load control signals, providing a maximum of 11 control
signals at a time. Although synchronous load and clear signals are
generally used when implementing counters, they can also be used with
other functions.
Each LAB can use three clocks and three clock enable signals. However,
there can only be up to two unique clocks per LAB, as shown in the LAB
control signal generation circuit in Figure 2–27. Each LAB’s clock and
clock enable signals are linked. For example, any ALM in a particular
LAB using the labclk1 signal also uses labclkena1. If the LAB uses
both the rising and falling edges of a clock, it also uses two LAB-wide
clock signals. De-asserting the clock enable signal turns off the
corresponding LAB-wide clock. Each LAB can use two asynchronous
clear signals and an asynchronous load/preset signal. The asynchronous
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May 2008
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Arria GX Device Handbook, Volume 1
Adaptive Logic Modules
load acts as a preset when the asynchronous load data input is tied high.
When the asynchronous load/preset signal is used, the labclkena0
signal is no longer available.
The LAB row clocks [5..0] and LAB local interconnect generate the
LAB-wide control signals. The MultiTrack interconnects have inherently
low skew. This low skew allows the MultiTrack interconnects to
distribute clock and control signals in addition to data.
Figure 2–27 shows the LAB control signal generation circuit.
Figure 2–27. LAB-Wide Control Signals
There are two unique
clock signals per LAB.
6
Dedicated Row LAB Clocks
6
6
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
labclk0
Adaptive Logic
Modules
labclk2
labclk1
labclkena0
or asyncload
or labpreset
labclkena1
labclkena2
labclr1
syncload
labclr0
synclr
The basic building block of logic in the Arria GX architecture is the ALM.
The ALM provides advanced features with efficient logic utilization. Each
ALM contains a variety of look-up table (LUT)-based resources that can
be divided between two adaptive LUTs (ALUTs). With up to eight inputs
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May 2008
Arria GX Architecture
to the two ALUTs, one ALM can implement various combinations of two
functions. This adaptability allows the ALM to be completely backwardcompatible with four-input LUT architectures. One ALM can also
implement any function of up to six inputs and certain seven-input
functions.
In addition to the adaptive LUT-based resources, each ALM contains two
programmable registers, two dedicated full adders, a carry chain, a
shared arithmetic chain, and a register chain. Through these dedicated
resources, the ALM can efficiently implement various arithmetic
functions and shift registers. Each ALM drives all types of interconnects:
local, row, column, carry chain, shared arithmetic chain, register chain,
and direct link interconnects. Figure 2–28 shows a high-level block
diagram of the Arria GX ALM while Figure 2–29 shows a detailed view
of all the connections in the ALM.
Figure 2–28. High-Level Block Diagram of the Arria GX ALM
carry_in
shared_arith_in
reg_chain_in
To general or
local routing
dataf0
adder0
datae0
D
dataa
datab
datac
datad
Q
To general or
local routing
reg0
Combinational
Logic
adder1
D
Q
datae1
To general or
local routing
reg1
dataf1
To general or
local routing
carry_out
shared_arith_out
Altera Corporation
May 2008
reg_chain_out
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Arria GX Device Handbook, Volume 1
datae0
Local
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Arria GX Device Handbook, Volume 1
dataa
datab
Local
Interconnect
Local
Local
Interconnect
dataf1
datae1
Local
Interconnect
datad
Local
Interconnect
Interconnect
datac
Local
Interconnect
Interconnect
dataf0
Local
Interconnect
LUT
3-Input
3-Input
LUT
4-Input
LUT
LUT
3-Input
LUT
3-Input
LUT
4-Input
shared_arith_out
shared_arith_in
carry_out
carry_in
VCC
sclr
syncload
reg_chain_out
reg_chain_in
clk[2..0]
aclr[1..0]
ENA
CLRN
PRN/ALD
D
Q
ADATA
ENA
CLRN
PRN/ALD
D
Q
ADATA
asyncload
ena[2..0]
Local
Interconnect
Row, column &
direct link routing
Row, column &
direct link routing
Local
Interconnect
Row, column &
direct link routing
Row, column &
direct link routing
Adaptive Logic Modules
Figure 2–29. Arria GX ALM Details
Altera Corporation
May 2008
Arria GX Architecture
One ALM contains two programmable registers. Each register has data,
clock, clock enable, synchronous and asynchronous clear, asynchronous
load data, and synchronous and asynchronous load/preset inputs.
Global signals, general-purpose I/O pins, or any internal logic can drive
the register's clock and clear control signals. Either general-purpose I/O
pins or internal logic can drive the clock enable, preset, asynchronous
load, and asynchronous load data. The asynchronous load data input
comes from the datae or dataf input of the ALM, which are the same
inputs that can be used for register packing. For combinational functions,
the register is bypassed and the output of the LUT drives directly to the
outputs of the ALM.
Each ALM has two sets of outputs that drive the local, row, and column
routing resources. The LUT, adder, or register output can drive these
output drivers independently (see Figure 2–29). For each set of output
drivers, two ALM outputs can drive column, row, or direct link routing
connections. One of these ALM outputs can also drive local interconnect
resources. This allows the LUT or adder to drive one output while the
register drives another output. This feature, called register packing,
improves device utilization because the device can use the register and
combinational logic for unrelated functions. Another special packing
mode allows the register output to feed back into the LUT of the same
ALM so that the register is packed with its own fan-out LUT. This feature
provides another mechanism for improved fitting. The ALM can also
drive out registered and unregistered versions of the LUT or adder
output.
ALM Operating Modes
The Arria GX ALM can operate in one of the following modes:
■
■
■
■
Normal mode
Extended LUT mode
Arithmetic mode
Shared arithmetic mode
Each mode uses ALM resources differently. Each mode has 11 available
inputs to the ALM (see Figure 2–28) ⎯the eight data inputs from the LAB
local interconnect; carry-in from the previous ALM or LAB; the shared
arithmetic chain connection from the previous ALM or LAB; and the
register chain connection ⎯are directed to different destinations to
implement the desired logic function. LAB-wide signals provide clock,
asynchronous clear, asynchronous preset/load, synchronous clear,
synchronous load, and clock enable control for the register. These
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May 2008
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Arria GX Device Handbook, Volume 1
Adaptive Logic Modules
LAB-wide signals are available in all ALM modes. Refer to “LAB Control
Signals” on page 2–37 for more information about LAB-wide control
signals.
The Quartus II software and supported third-party synthesis tools, in
conjunction with parameterized functions such as library of
parameterized modules (LPM) functions, automatically choose the
appropriate mode for common functions such as counters, adders,
subtractors, and arithmetic functions. If required, you can also create
special-purpose functions that specify which ALM operating mode to use
for optimal performance.
Normal Mode
Normal mode is suitable for general logic applications and combinational
functions. In this mode, up to eight data inputs from the LAB local
interconnect are inputs to the combinational logic. Normal mode allows
two functions to be implemented in one Arria GX ALM, or an ALM to
implement a single function of up to six inputs. The ALM can support
certain combinations of completely independent functions and various
combinations of functions which have common inputs. Figure 2–30
shows the supported LUT combinations in normal mode.
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Altera Corporation
May 2008
Arria GX Architecture
Figure 2–30. ALM in Normal Mode Note (1)
dataf0
datae0
datac
dataa
4-Input
LUT
combout0
datab
datad
datae1
dataf1
4-Input
LUT
combout1
dataf0
datae0
datac
dataa
datab
5-Input
LUT
combout0
datad
datae1
dataf1
dataf0
datae0
datac
dataa
datab
datad
datae1
dataf1
3-Input
LUT
5-Input
LUT
combout0
5-Input
LUT
combout1
dataf0
datae0
dataa
datab
datac
datad
6-Input
LUT
combout0
dataf0
datae0
dataa
datab
datac
datad
6-Input
LUT
combout0
6-Input
LUT
combout1
datad
datae1
dataf1
combout1
5-Input
LUT
4-Input
LUT
dataf0
datae0
datac
dataa
datab
combout0
combout1
datae1
dataf1
Note to Figure 2–30:
(1)
Combinations of functions with less inputs than those shown are also supported. For example, combinations of
functions with the following number of inputs are supported: 4 and 3, 3 and 3, 3 and 2, 5 and 2, etc.
Normal mode provides complete backward compatibility with
four-input LUT architectures. Two independent functions of four inputs
or less can be implemented in one Arria GX ALM. In addition, a
five-input function and an independent three-input function can be
implemented without sharing inputs.
Altera Corporation
May 2008
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Adaptive Logic Modules
To pack two five-input functions into one ALM, the functions must have
at least two common inputs. The common inputs are dataa and datab.
The combination of a four-input function with a five-input function
requires one common input (either dataa or datab).
To implement two six-input functions in one ALM, four inputs must be
shared and the combinational function must be the same. For example, a
4 × 2 crossbar switch (two 4-to-1 multiplexers with common inputs and
unique select lines) can be implemented in one ALM, as shown in
Figure 2–31. The shared inputs are dataa, datab, datac, and datad,
while the unique select lines are datae0 and dataf0 for function0,
and datae1 and dataf1 for function1. This crossbar switch
consumes four LUTs in a four-input LUT-based architecture.
Figure 2–31. 4 × 2 Crossbar Switch Example
4 × 2 Crossbar Switch
sel0[1..0]
inputa
inputb
out0
inputc
inputd
Implementation in 1 ALM
dataf0
datae0
dataa
datab
datac
datad
Six-Input
LUT
(Function0)
combout0
Six-Input
LUT
(Function1)
combout1
out1
sel1[1..0]
datae1
dataf1
In a sparsely used device, functions that could be placed into one ALM
can be implemented in separate ALMs. The Quartus II Compiler spreads
a design out to achieve the best possible performance. As a device begins
to fill up, the Quartus II software automatically utilizes the full potential
of the Arria GX ALM. The Quartus II Compiler automatically searches for
functions of common inputs or completely independent functions to be
placed into one ALM and to make efficient use of the device resources. In
addition, you can manually control resource usage by setting location
assignments. Any six-input function can be implemented utilizing inputs
dataa, datab, datac, datad, and either datae0 and dataf0 or
datae1 and dataf1. If datae0 and dataf0 are utilized, the output is
driven to register0, and/or register0 is bypassed and the data
drives out to the interconnect using the top set of output drivers (see
Figure 2–32). If datae1 and dataf1 are utilized, the output drives to
register1 and/or bypasses register1 and drives to the interconnect
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May 2008
Arria GX Architecture
using the bottom set of output drivers. The Quartus II Compiler
automatically selects the inputs to the LUT. Asynchronous load data for
the register comes from the datae or dataf input of the ALM. ALMs in
normal mode support register packing.
Figure 2–32. Six-Input Function in Normal Mode Notes (1), (2)
dataf0
datae0
dataa
datab
datac
datad
To general or
local routing
6-Input
LUT
D
Q
To general or
local routing
reg0
datae1
dataf1
(2)
D
These inputs are available for register packing.
Q
To general or
local routing
reg1
Notes to Figure 2–32:
(1)
(2)
If datae1 and dataf1 are used as inputs to the six-input function, datae0 and
dataf0 are available for register packing.
The dataf1 input is available for register packing only if the six-input function is
un-registered.
Extended LUT Mode
Extended LUT mode is used to implement a specific set of seven-input
functions. The set must be a 2-to-1 multiplexer fed by two arbitrary fiveinput functions sharing four inputs. Figure 2–33 shows the template of
supported seven-input functions utilizing extended LUT mode. In this
mode, if the seven-input function is unregistered, the unused eighth
input is available for register packing. Functions that fit into the template
shown in Figure 2–33 occur naturally in designs. These functions often
appear in designs as “if-else” statements in Verilog HDL or VHDL code.
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May 2008
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Arria GX Device Handbook, Volume 1
Adaptive Logic Modules
Figure 2–33. Template for Supported Seven-Input Functions in Extended LUT Mode
datae0
datac
dataa
datab
datad
dataf0
5-Input
LUT
To general or
local routing
combout0
D
5-Input
LUT
Q
To general or
local routing
reg0
datae1
dataf1
(1)
This input is available
for register packing.
Note to Figure 2–33:
(1)
If the seven-input function is unregistered, the unused eighth input is available for register packing. The second
register, reg1, is not available.
Arithmetic Mode
Arithmetic mode is ideal for implementing adders, counters,
accumulators, wide parity functions, and comparators. An ALM in
arithmetic mode uses two sets of 2 four-input LUTs along with two
dedicated full adders. The dedicated adders allow the LUTs to be
available to perform pre-adder logic; therefore, each adder can add the
output of two four-input functions. The four LUTs share the dataa and
datab inputs. As shown in Figure 2–34, the carry-in signal feeds to
adder0, and the carry-out from adder0 feeds to carry-in of adder1. The
carry-out from adder1 drives to adder0 of the next ALM in the LAB.
ALMs in arithmetic mode can drive out registered and/or unregistered
versions of the adder outputs.
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May 2008
Arria GX Architecture
Figure 2–34. ALM in Arithmetic Mode
carry_in
adder0
datae0
4-Input
LUT
To general or
local routing
D
dataf0
datac
datab
dataa
Q
To general or
local routing
reg0
4-Input
LUT
adder1
datad
datae1
4-Input
LUT
To general or
local routing
D
4-Input
LUT
Q
To general or
local routing
reg1
dataf1
carry_out
While operating in arithmetic mode, the ALM can support simultaneous
use of the adder’s carry output along with combinational logic outputs.
In this operation, adder output is ignored. This usage of the adder with
the combinational logic output provides resource savings of up to 50% for
functions that can use this ability. An example of such functionality is a
conditional operation, such as the one shown in Figure 2–35. The
equation for this example is:
R = (X < Y) ? Y : X
To implement this function, the adder is used to subtract ‘Y’ from ‘X.’ If
‘X’ is less than ‘Y,’ the carry_out signal will be ‘1.’ The carry_out
signal is fed to an adder where it drives out to the LAB local interconnect.
It then feeds to the LAB-wide syncload signal. When asserted,
syncload selects the syncdata input. In this case, the data ‘Y’ drives
the syncdata inputs to the registers. If ‘X’ is greater than or equal to ‘Y,’
the syncload signal is de-asserted and ‘X’ drives the data port of the
registers.
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May 2008
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Adaptive Logic Modules
Figure 2–35. Conditional Operation Example
Adder output
is not used.
ALM 1
X[0]
Comb &
Adder
Logic
Y[0]
X[0]
D
R[0]
To general or
local routing
R[1]
To general or
local routing
R[2]
To general or
local routing
Q
reg0
syncdata
syncload
X[1]
Comb &
Adder
Logic
Y[1]
X[1]
D
Q
reg1
syncload
Carry Chain
ALM 2
X[2]
Y[2]
Comb &
Adder
Logic
X[2]
D
Q
reg0
syncload
Comb &
Adder
Logic
carry_out
To local routing &
then to LAB-wide
syncload
Arithmetic mode also offers clock enable, counter enable, synchronous
up/down control, add/subtract control, synchronous clear, and
synchronous load. The LAB local interconnect data inputs generate the
clock enable, counter enable, synchronous up/down and add/subtract
control signals. These control signals may be used for the inputs that are
shared between the four LUTs in the ALM. The synchronous clear and
synchronous load options are LAB-wide signals that affect all registers in
the LAB. The Quartus II software automatically places any registers that
are not used by the counter into other LABs.
Carry Chain
Carry chain provides a fast carry function between the dedicated adders
in arithmetic or shared arithmetic mode. Carry chains can begin in either
the first ALM or the fifth ALM in a LAB. The final carry-out signal is
routed to an ALM, where it is fed to local, row, or column interconnects.
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Arria GX Architecture
The Quartus II Compiler automatically creates carry chain logic during
compilation, or you can create it manually during design entry.
Parameterized functions such as LPM functions automatically take
advantage of carry chains for the appropriate functions. The Quartus II
Compiler creates carry chains longer than 16 (8 ALMs in arithmetic or
shared arithmetic mode) by linking LABs together automatically. For
enhanced fitting, a long carry chain runs vertically allowing fast
horizontal connections to TriMatrix memory and DSP blocks. A carry
chain can continue as far as a full column. To avoid routing congestion in
one small area of the device when a high fan-in arithmetic function is
implemented, the LAB can support carry chains that only utilize either
the top half or bottom half of the LAB before connecting to the next LAB.
The other half of the ALMs in the LAB is available for implementing
narrower fan-in functions in normal mode. Carry chains that use the top
four ALMs in the first LAB carries into the top half of the ALMs in the
next LAB within the column. Carry chains that use the bottom four ALMs
in the first LAB carries into the bottom half of the ALMs in the next LAB
within the column. Every other column of the LABs are top-half
bypassable, while the other LAB columns are bottom-half bypassable.
Refer to “MultiTrack Interconnect” on page 2–54 for more information
about carry chain interconnect.
Shared Arithmetic Mode
In shared arithmetic mode, the ALM can implement a three-input add. In
this mode, the ALM is configured with four 4-input LUTs. Each LUT
either computes the sum of three inputs or the carry of three inputs. The
output of the carry computation is fed to the next adder (either to adder1
in the same ALM or to adder0 of the next ALM in the LAB) using a
dedicated connection called the shared arithmetic chain. This shared
arithmetic chain can significantly improve the performance of an adder
tree by reducing the number of summation stages required to implement
an adder tree. Figure 2–36 shows the ALM in shared arithmetic mode.
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May 2008
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Adaptive Logic Modules
Figure 2–36. ALM in Shared Arithmetic Mode
shared_arith_in
carry_in
4-Input
LUT
To general or
local routing
D
datae0
datac
datab
dataa
datad
datae1
Q
To general or
local routing
reg0
4-Input
LUT
4-Input
LUT
To general or
local routing
D
4-Input
LUT
Q
To general or
local routing
reg1
carry_out
shared_arith_out
Note to Figure 2–36:
(1)
Inputs dataf0 and dataf1 are available for register packing in shared arithmetic mode.
Adder trees are used in many different applications. For example, the
summation of partial products in a logic-based multiplier can be
implemented in a tree structure. Another example is a correlator function
that can use a large adder tree to sum filtered data samples in a given time
frame to recover or to de-spread data which was transmitted utilizing
spread spectrum technology. An example of a three-bit add operation
utilizing the shared arithmetic mode is shown in Figure 2–37. The partial
sum (S[2..0]) and the partial carry (C[2..0]) is obtained using LUTs,
while the result (R[2..0]) is computed using dedicated adders.
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Arria GX Architecture
Figure 2–37. Example of a 3-Bit Add Utilizing Shared Arithmetic Mode
shared_arith_in = '0'
carry_in = '0'
3-Bit Add Example
ALM Implementation
ALM 1
1st stage add is
implemented in LUTs.
X2 X1 X0
Y2 Y1 Y0
+ Z2 Z1 Z0
2nd stage add is
implemented in adders.
S2 S1 S0
+ C2 C1 C0
R3 R2 R1 R0
Binary Add
Decimal
Equivalents
1 1 0
1 0 1
+ 0 1 0
6
5
+ 2
0 0 1
+ 1 1 0
1
+ 2x6
1 1 0 1
13
3-Input
LUT
S0
R0
X0
Y0
Z0
3-Input
LUT
C0
X1
Y1
Z1
3-Input
LUT
S1
R1
3-Input
LUT
C1
3-Input
LUT
S2
ALM 2
R2
X2
Y2
Z2
3-Input
LUT
C2
3-Input
LUT
'0'
R3
3-Input
LUT
Shared Arithmetic Chain
In addition to dedicated carry chain routing, the shared arithmetic chain
available in shared arithmetic mode allows the ALM to implement a
three-input add, which significantly reduces the resources necessary to
implement large adder trees or correlator functions. Shared arithmetic
chains can begin in either the first or fifth ALM in a LAB. The Quartus II
Compiler automatically links LABs to create shared arithmetic chains
longer than 16 (8 ALMs in arithmetic or shared arithmetic mode). For
enhanced fitting, a long shared arithmetic chain runs vertically allowing
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Adaptive Logic Modules
fast horizontal connections to TriMatrix memory and DSP blocks. A
shared arithmetic chain can continue as far as a full column. Similar to
carry chains, shared arithmetic chains are also top- or bottom-half
bypassable. This capability allows the shared arithmetic chain to cascade
through half of the ALMs in a LAB while leaving the other half available
for narrower fan-in functionality. Every other LAB column is top-half
bypassable, while the other LAB columns are bottom-half bypassable.
Refer to “MultiTrack Interconnect” on page 2–54 for more information
about shared arithmetic chain interconnect.
Register Chain
In addition to the general routing outputs, the ALMs in a LAB have
register chain outputs. Register chain routing allows registers in the same
LAB to be cascaded together. The register chain interconnect allows a
LAB to use LUTs for a single combinational function and the registers to
be used for an unrelated shift register implementation. These resources
speed up connections between ALMs while saving local interconnect
resources (see Figure 2–38). The Quartus II Compiler automatically takes
advantage of these resources to improve utilization and performance.
Refer to “MultiTrack Interconnect” on page 2–54 for more information
about register chain interconnect.
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Arria GX Architecture
Figure 2–38. Register Chain within a LAB Note (1)
From Previous ALM
Within The LAB
reg_chain_in
To general or
local routing
adder0
D
Q
To general or
local routing
reg0
Combinational
Logic
adder1
D
Q
To general or
local routing
reg1
To general or
local routing
To general or
local routing
adder0
D
Q
To general or
local routing
reg0
Combinational
Logic
adder1
D
Q
To general or
local routing
reg1
To general or
local routing
reg_chain_out
To Next ALM
within the LAB
Note to Figure 2–38:
(1)
The combinational or adder logic can be utilized to implement an unrelated, un-registered function.
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MultiTrack Interconnect
Clear and Preset Logic Control
LAB-wide signals control the logic for the register’s clear and load/preset
signals. The ALM directly supports an asynchronous clear and preset
function. The register preset is achieved through the asynchronous load
of a logic high. The direct asynchronous preset does not require a NOT
gate push-back technique. Arria GX devices support simultaneous
asynchronous load/preset and clear signals. An asynchronous clear
signal takes precedence if both signals are asserted simultaneously. Each
LAB supports up to two clears and one load/preset signal.
In addition to the clear and load/preset ports, Arria GX devices provide
a device-wide reset pin (DEV_CLRn) that resets all registers in the device.
An option set before compilation in the Quartus II software controls this
pin. This device-wide reset overrides all other control signals.
MultiTrack
Interconnect
In Arria GX architecture, the MultiTrack interconnect structure with
DirectDrive technology provides connections between ALMs, TriMatrix
memory, DSP blocks, and device I/O pins. The MultiTrack interconnect
consists of continuous, performance-optimized routing lines of different
lengths and speeds used for inter- and intra-design block connectivity.
The Quartus II Compiler automatically places critical design paths on
faster interconnects to improve design performance.
DirectDrive technology is a deterministic routing technology that ensures
identical routing resource usage for any function regardless of placement
in the device. The MultiTrack interconnect and DirectDrive technology
simplify the integration stage of block-based designing by eliminating the
re-optimization cycles that typically follow design changes and
additions.
The MultiTrack interconnect consists of row and column interconnects
that span fixed distances. A routing structure with fixed length resources
for all devices allows predictable and repeatable performance when
migrating through different device densities. Dedicated row
interconnects route signals to and from LABs, DSP blocks, and TriMatrix
memory in the same row.
These row resources include:
■
■
■
Direct link interconnects between LABs and adjacent blocks
R4 interconnects traversing four blocks to the right or left
R24 row interconnects for high-speed access across the length of the
device
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Arria GX Architecture
The direct link interconnect allows a LAB, DSP block, or TriMatrix
memory block to drive into the local interconnect of its left and right
neighbors and then back into itself, providing fast communication
between adjacent LABs and/or blocks without using row interconnect
resources.
The R4 interconnects span four LABs, three LABs and one M512 RAM
block, two LABs and one M4K RAM block, or two LABs and one DSP
block to the right or left of a source LAB. These resources are used for fast
row connections in a four-LAB region. Every LAB has its own set of R4
interconnects to drive either left or right. Figure 2–39 shows R4
interconnect connections from a LAB.
R4 interconnects can drive and be driven by DSP blocks and RAM blocks
and row IOEs. For LAB interfacing, a primary LAB or LAB neighbor can
drive a given R4 interconnect. For R4 interconnects that drive to the right,
the primary LAB and right neighbor can drive onto the interconnect. For
R4 interconnects that drive to the left, the primary LAB and its left
neighbor can drive onto the interconnect. R4 interconnects can drive
other R4 interconnects to extend the range of LABs they can drive. R4
interconnects can also drive C4 and C16 interconnects for connections
from one row to another. Additionally, R4 interconnects can drive R24
interconnects.
Figure 2–39. R4 Interconnect Connections Notes (1), (2), (3)
Adjacent LAB can
Drive onto Another
LAB's R4 Interconnect
C4 and C16
Column Interconnects (1)
R4 Interconnect
Driving Right
R4 Interconnect
Driving Left
LAB
Neighbor
Primary
LAB (2)
LAB
Neighbor
Notes to Figure 2–39:
(1)
(2)
(3)
C4 and C16 interconnects can drive R4 interconnects.
This pattern is repeated for every LAB in the LAB row.
The LABs in Figure 2–39 show the 16 possible logical outputs per LAB.
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May 2008
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MultiTrack Interconnect
R24 row interconnects span 24 LABs and provide the fastest resource for
long row connections between LABs, TriMatrix memory, DSP blocks, and
row IOEs. The R24 row interconnects can cross M-RAM blocks. R24 row
interconnects drive to other row or column interconnects at every fourth
LAB and do not drive directly to LAB local interconnects. R24 row
interconnects drive LAB local interconnects via R4 and C4 interconnects.
R24 interconnects can drive R24, R4, C16, and C4 interconnects. The
column interconnect operates similarly to the row interconnect and
vertically routes signals to and from LABs, TriMatrix memory, DSP
blocks, and IOEs. Each column of LABs is served by a dedicated column
interconnect.
These column resources include:
■
■
■
■
■
Shared arithmetic chain interconnects in a LAB
Carry chain interconnects in a LAB and from LAB to LAB
Register chain interconnects in a LAB
C4 interconnects traversing a distance of four blocks in up and down
direction
C16 column interconnects for high-speed vertical routing through
the device
Arria GX devices include an enhanced interconnect structure in LABs for
routing shared arithmetic chains and carry chains for efficient arithmetic
functions. The register chain connection allows the register output of one
ALM to connect directly to the register input of the next ALM in the LAB
for fast shift registers. These ALM-to-ALM connections bypass the local
interconnect. The Quartus II Compiler automatically takes advantage of
these resources to improve utilization and performance. Figure 2–40
shows shared arithmetic chain, carry chain, and register chain
interconnects.
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Arria GX Architecture
Figure 2–40. Shared Arithmetic Chain, Carry Chain and Register Chain Interconnects
Local Interconnect
Routing Among ALMs
in the LAB
Carry Chain & Shared
Arithmetic Chain
Routing to Adjacent ALM
ALM 1
Register Chain
Routing to Adjacent
ALM's Register Input
ALM 2
Local
Interconnect
ALM 3
ALM 4
ALM 5
ALM 6
ALM 7
ALM 8
C4 interconnects span four LABs, M512, or M4K blocks up or down from
a source LAB. Every LAB has its own set of C4 interconnects to drive
either up or down. Figure 2–41 shows the C4 interconnect connections
from a LAB in a column. C4 interconnects can drive and be driven by all
types of architecture blocks, including DSP blocks, TriMatrix memory
blocks, and column and row IOEs. For LAB interconnection, a primary
LAB or its LAB neighbor can drive a given C4 interconnect. C4
interconnects can drive each other to extend their range as well as drive
row interconnects for column-to-column connections.
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May 2008
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MultiTrack Interconnect
Figure 2–41. C4 Interconnect Connections Note (1)
C4 Interconnect
Drives Local and R4
Interconnects
up to Four Rows
C4 Interconnect
Driving Up
LAB
Row
Interconnect
Adjacent LAB can
drive onto neighboring
LAB's C4 interconnect
Local
Interconnect
C4 Interconnect
Driving Down
Note to Figure 2–41:
(1)
Each C4 interconnect can drive either up or down four rows.
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Arria GX Architecture
C16 column interconnects span a length of 16 LABs and provide the
fastest resource for long column connections between LABs, TriMatrix
memory blocks, DSP blocks, and IOEs. C16 interconnects can cross
M-RAM blocks and also drive to row and column interconnects at every
fourth LAB. C16 interconnects drive LAB local interconnects via C4 and
R4 interconnects and do not drive LAB local interconnects directly. All
embedded blocks communicate with the logic array similar to
LAB-to-LAB interfaces. Each block (that is, TriMatrix memory and DSP
blocks) connects to row and column interconnects and has local
interconnect regions driven by row and column interconnects. These
blocks also have direct link interconnects for fast connections to and from
a neighboring LAB. All blocks are fed by the row LAB clocks,
labclk[5..0].
Table 2–10 shows the Arria GX device’s routing scheme.
Table 2–10. Arria GX Device Routing Scheme (Part 1 of 2)
Shared arithmetic chain
v
Carry chain
v
Register chain
v
Direct link interconnect
v
R4 interconnect
v
v
v
v
M512 RAM block
v v v
v
M4K RAM block
v v v
v
M-RAM block
v v v v
DSP blocks
v v
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May 2008
Row IOE
Column IOE
DSP Blocks
v
v v v v
v v v v v v
ALM
M-RAM Block
v v v v
v v v v
R24 interconnect
C16 interconnect
M4K RAM Block
v v v v v v v
Local interconnect
C4 interconnect
M512 RAM Block
ALM
C16 Interconnect
C4 Interconnect
R24 Interconnect
R4 Interconnect
Direct Link Interconnect
Local Interconnect
Register Chain
Carry Chain
Source
Shared Arithmetic Chain
Destination
v
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TriMatrix Memory
Table 2–10. Arria GX Device Routing Scheme (Part 2 of 2)
Column IOE
v
Row IOE
v v v v
TriMatrix
Memory
Row IOE
Column IOE
DSP Blocks
M-RAM Block
M4K RAM Block
M512 RAM Block
ALM
C16 Interconnect
C4 Interconnect
R24 Interconnect
R4 Interconnect
Direct Link Interconnect
Local Interconnect
Register Chain
Carry Chain
Source
Shared Arithmetic Chain
Destination
v v
TriMatrix memory consists of three types of RAM blocks: M512, M4K,
and M-RAM. Although these memory blocks are different, they can all
implement various types of memory with or without parity, including
true dual-port, simple dual-port, and single-port RAM, ROM, and first-in
first-out (FIFO) buffers. Table 2–11 shows the size and features of the
different RAM blocks.
Table 2–11. TriMatrix Memory Features (Part 1 of 2)
Memory Feature
Maximum performance
M512 RAM Block
(32 × 18 Bits)
M4K RAM Block
(128 × 36 Bits)
M-RAM Block
(4K × 144 Bits)
345 MHz
380 MHz
290 MHz
v
v
True dual-port memory
Simple dual-port memory
v
v
v
Single-port memory
v
v
v
Shift register
v
v
ROM
v
v
FIFO buffer
v
v
v
v
v
Pack mode
Byte enable
v
Address clock enable
v
v
v
v
Parity bits
v
v
v
Mixed clock mode
v
v
v
Memory initialization (.mif)
v
v
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Arria GX Architecture
Table 2–11. TriMatrix Memory Features (Part 2 of 2)
Memory Feature
Simple dual-port memory
mixed width support
M512 RAM Block
(32 × 18 Bits)
M4K RAM Block
(128 × 36 Bits)
M-RAM Block
(4K × 144 Bits)
v
v
v
v
v
Outputs cleared
Outputs cleared
Outputs unknown
Output registers
Output registers
True dual-port memory
mixed width support
Power-up conditions
Register clears
Mixed-port read-during-write
Unknown output/old data Unknown output/old data
Configurations
512 × 1
256 × 2
128 × 4
64 × 8
64 × 9
32 × 16
32 × 18
4K × 1
2K × 2
1K × 4
512 × 8
512 × 9
256 × 16
256 × 18
128 × 32
128 × 36
Output registers
Unknown output
64K × 8
64K × 9
32K × 16
32K × 18
16K × 32
16K × 36
8K × 64
8K × 72
4K × 128
4K × 144
TriMatrix memory provides three different memory sizes for efficient
application support. The Quartus II software automatically partitions the
user-defined memory into the embedded memory blocks using the most
efficient size combinations. You can also manually assign the memory to
a specific block size or a mixture of block sizes.
M512 RAM Block
The M512 RAM block is a simple dual-port memory block and is useful
for implementing small FIFO buffers, DSP, and clock domain transfer
applications. Each block contains 576 RAM bits (including parity bits).
M512 RAM blocks can be configured in the following modes:
■
■
■
■
■
Simple dual-port RAM
Single-port RAM
FIFO
ROM
Shift register
When configured as RAM or ROM, you can use an initialization file to
pre-load the memory contents.
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M512 RAM blocks can have different clocks on its inputs and outputs.
The wren, datain, and write address registers are all clocked together
from one of the two clocks feeding the block. The read address, rden, and
output registers can be clocked by either of the two clocks driving the
block, allowing the RAM block to operate in read and write or input and
output clock modes. Only the output register can be bypassed. The six
labclk signals or local interconnect can drive the inclock, outclock,
wren, rden, and outclr signals. Because of the advanced interconnect
between the LAB and M512 RAM blocks, ALMs can also control the wren
and rden signals and the RAM clock, clock enable, and asynchronous
clear signals. Figure 2–42 shows the M512 RAM block control signal
generation logic.
Figure 2–42. M512 RAM Block Control Signals
Dedicated
Row LAB
Clocks
6
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
outclocken
inclocken
Local
Interconnect
inclock
outclock
wren
rden
outclr
The RAM blocks in Arria GX devices have local interconnects to allow
ALMs and interconnects to drive into RAM blocks. The M512 RAM block
local interconnect is driven by the R4, C4, and direct link interconnects
from adjacent LABs. The M512 RAM blocks can communicate with LABs
on either the left or right side through these row interconnects or with
LAB columns on the left or right side with the column interconnects. The
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Arria GX Architecture
M512 RAM block has up to 16 direct link input connections from the left
adjacent LABs and another 16 from the right adjacent LAB. M512 RAM
outputs can also connect to left and right LABs through direct link
interconnect. The M512 RAM block has equal opportunity for access and
performance to and from LABs on either its left or right side. Figure 2–43
shows the M512 RAM block to logic array interface.
Figure 2–43. M512 RAM Block LAB Row Interface
C4 Interconnect
Direct link
interconnect
to adjacent LAB
R4 Interconnect
16
Direct link
interconnect
to adjacent LAB
36
dataout
M4K RAM
Block
Direct link
interconnect
from adjacent LAB
Direct link
interconnect
from adjacent LAB
datain
control
signals
byte
enable
clocks
address
6
M4K RAM Block Local
Interconnect Region
LAB Row Clocks
M4K RAM Blocks
The M4K RAM block includes support for true dual-port RAM. The M4K
RAM block is used to implement buffers for a wide variety of applications
such as storing processor code, implementing lookup schemes, and
implementing larger memory applications. Each block contains
4,608 RAM bits (including parity bits). M4K RAM blocks can be
configured in the following modes:
■
■
■
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May 2008
True dual-port RAM
Simple dual-port RAM
Single-port RAM
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■
■
■
FIFO
ROM
Shift register
When configured as RAM or ROM, you can use an initialization file to
pre-load the memory contents.
M4K RAM blocks allow for different clocks on their inputs and outputs.
Either of the two clocks feeding the block can clock M4K RAM block
registers (renwe, address, byte enable, datain, and output
registers). Only the output register can be bypassed. The six labclk
signals or local interconnects can drive the control signals for the A and B
ports of the M4K RAM block. ALMs can also control the clock_a,
clock_b, renwe_a, renwe_b, clr_a, clr_b, clocken_a, and
clocken_b signals, as shown in Figure 2–44.
Figure 2–44. M4K RAM Block Control Signals
Dedicated
Row LAB
Clocks
6
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
clocken_b
clock_b
clock_a
clocken_a
renwe_b
renwe_a
aclr_b
aclr_a
The R4, C4, and direct link interconnects from adjacent LABs drive the
M4K RAM block local interconnect. The M4K RAM blocks can
communicate with LABs on either the left or right side through these row
resources or with LAB columns on either the right or left with the column
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resources. Up to 16 direct link input connections to the M4K RAM block
are possible from the left adjacent LABs and another 16 are possible from
the right adjacent LAB. M4K RAM block outputs can also connect to left
and right LABs through direct link interconnect. Figure 2–45 shows the
M4K RAM block to logic array interface.
Figure 2–45. M4K RAM Block LAB Row Interface
C4 Interconnect
Direct link
interconnect
to adjacent LAB
R4 Interconnect
16
Direct link
interconnect
to adjacent LAB
36
dataout
M4K RAM
Block
Direct link
interconnect
from adjacent LAB
Direct link
interconnect
from adjacent LAB
datain
control
signals
byte
enable
clocks
address
6
M4K RAM Block Local
Interconnect Region
LAB Row Clocks
M-RAM Block
The largest TriMatrix memory block, the M-RAM block, is useful for
applications where a large volume of data must be stored on-chip. Each
block contains 589,824 RAM bits (including parity bits). The M-RAM
block can be configured in the following modes:
■
■
■
■
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May 2008
True dual-port RAM
Simple dual-port RAM
Single-port RAM
FIFO
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You cannot use an initialization file to initialize the contents of a M-RAM
block. All M-RAM block contents power up to an undefined value. Only
synchronous operation is supported in the M-RAM block, so all inputs
are registered. Output registers can be bypassed.
Similar to all RAM blocks, M-RAM blocks can have different clocks on
their inputs and outputs. Either of the two clocks feeding the block can
clock M-RAM block registers (renwe, address, byte enable, datain,
and output registers). The output register can be bypassed. The six
labclk signals or local interconnect can drive the control signals for the
A and B ports of the M-RAM block. ALMs can also control the clock_a,
clock_b, renwe_a, renwe_b, clr_a, clr_b, clocken_a, and
clocken_b signals, as shown in Figure 2–46.
Figure 2–46. M-RAM Block Control Signals
Dedicated
Row LAB
Clocks
6
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
clocken_a
Local
Interconnect
clock_a
renwe_a
aclr_a
clock_b
aclr_b
renwe_b
Local
Interconnect
clocken_b
The R4, R24, C4, and direct link interconnects from adjacent LABs on
either the right or left side drive the M-RAM block local interconnect. Up
to 16 direct link input connections to the M-RAM block are possible from
the left adjacent LABs and another 16 are possible from the right adjacent
LAB. M-RAM block outputs can also connect to left and right LABs
through direct link interconnect. Figure 2–47 shows an example floorplan
for the EP1AGX90 device and the location of the M-RAM interfaces.
Figures 2–48 and 2–49 show the interface between the M-RAM block and
the logic array.
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Arria GX Architecture
Figure 2–47. EP1AGX90 Device with M-RAM Interface Locations
Note (1)
M-RAM blocks interface to
LABs on right and left sides for
easy access to horizontal I/O pins
M4K
Blocks
M-RAM
Block
M-RAM
Block
M-RAM
Block
M-RAM
Block
M512
Blocks
DSP
Blocks
LABs
DSP
Blocks
Note to Figure 2–47:
(1)
The device shown is an EP1AGX90 device. The number and position of M-RAM blocks vary in other devices.
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May 2008
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TriMatrix Memory
Figure 2–48. M-RAM Block LAB Row Interface Note (1)
Row Unit Interface Allows LAB
Rows to Drive Port A Datain,
Dataout, Address and Control
Signals to and from M-RAM Block
Row Unit Interface Allows LAB
Rows to Drive Port B Datain,
Dataout, Address and Control
Signals to and from M-RAM Block
L0
R0
L1
R1
M-RAM Block
L2
Port A
Port B R2
L3
R3
L4
R4
L5
R5
LAB Interface
Blocks
LABs in Row
M-RAM Boundary
LABs in Row
M-RAM Boundary
Note to Figure 2–48:
(1)
Only R24 and C16 interconnects cross the M-RAM block boundaries.
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Arria GX Architecture
Figure 2–49. M-RAM Row Unit Interface to Interconnect
C4 Interconnect
R4 and R24 Interconnects
M-RAM Block
LAB
Up to 16
dataout_a[ ]
16
Up to 28
Direct Link
Interconnects
datain_a[ ]
addressa[ ]
addr_ena_a
renwe_a
byteenaA[ ]
clocken_a
clock_a
aclr_a
Row Interface Block
M-RAM Block to
LAB Row Interface
Block Interconnect Region
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May 2008
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TriMatrix Memory
Table 2–12 shows the input and output data signal connections along
with the address and control signal input connections to the row unit
interfaces (L0 to L5 and R0 to R5).
Table 2–12. M-RAM Row Interface Unit Signals
Unit Interface Block
f
Input Signals
Output Signals
L0
datain_a[14..0]
byteena_a[1..0]
dataout_a[11..0]
L1
datain_a[29..15]
byteena_a[3..2]
dataout_a[23..12]
L2
datain_a[35..30]
addressa[4..0]
addr_ena_a
clock_a
clocken_a
renwe_a
aclr_a
dataout_a[35..24]
L3
addressa[15..5]
datain_a[41..36]
dataout_a[47..36]
L4
datain_a[56..42]
byteena_a[5..4]
dataout_a[59..48]
L5
datain_a[71..57]
byteena_a[7..6]
dataout_a[71..60]
R0
datain_b[14..0]
byteena_b[1..0]
dataout_b[11..0]
R1
datain_b[29..15]
byteena_b[3..2]
dataout_b[23..12]
R2
datain_b[35..30]
addressb[4..0]
addr_ena_b
clock_b
clocken_b
renwe_b
aclr_b
dataout_b[35..24]
R3
addressb[15..5]
datain_b[41..36]
dataout_b[47..36]
R4
datain_b[56..42]
byteena_b[5..4]
dataout_b[59..48]
R5
datain_b[71..57]
byteena_b[7..6]
dataout_b[71..60]
For more information about TriMatrix memory, refer to the TriMatrix
Embedded Memory Blocks in Arria GX Devices chapter in volume 2 of the
Arria GX Device Handbook.
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Arria GX Architecture
Digital Signal
Processing
Block
The most commonly used DSP functions are finite impulse response (FIR)
filters, complex FIR filters, infinite impulse response (IIR) filters, fast
Fourier transform (FFT) functions, direct cosine transform (DCT)
functions, and correlators. All of these use the multiplier as the
fundamental building block. Additionally, some applications need
specialized operations such as multiply-add and multiply-accumulate
operations. Arria GX devices provide DSP blocks to meet the arithmetic
requirements of these functions.
Each Arria GX device has two to four columns of DSP blocks to efficiently
implement DSP functions faster than ALM-based implementations. Each
DSP block can be configured to support up to:
■
■
■
Eight 9 × 9-bit multipliers
Four 18 × 18-bit multipliers
One 36 × 36-bit multiplier
As indicated, the Arria GX DSP block can support one 36 × 36-bit
multiplier in a single DSP block and is true for any combination of signed,
unsigned, or mixed sign multiplications.
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Digital Signal Processing Block
Figures 2–50 shows one of the columns with surrounding LAB rows.
Figure 2–50. DSP Blocks Arranged in Columns
DSP Block
Column
4 LAB
Rows
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DSP Block
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May 2008
Arria GX Architecture
Table 2–13 shows the number of DSP blocks in each Arria GX device. DSP
block multipliers can optionally feed an adder/subtractor or accumulator
in the block depending on the configuration, which makes routing to
ALMs easier, saves ALM routing resources, and increases performance
because all connections and blocks are in the DSP block.
Table 2–13. DSP Blocks in Arria GX Devices Note (1)
Device
DSP Blocks
Total 9 × 9
Multipliers
Total 18 × 18
Multipliers
Total 36 × 36
Multipliers
10
80
40
10
EP1AGX20
EP1AGX35
14
112
56
14
EP1AGX50
26
208
104
26
EP1AGX60
32
256
128
32
EP1AGX90
44
352
176
44
Note to Table 2–13:
(1)
This list only shows functions that can fit into a single DSP block. Multiple DSP
blocks can support larger multiplication functions.
Additionally, DSP block input registers can efficiently implement shift
registers for FIR filter applications. DSP blocks support Q1.15 format
rounding and saturation. Figure 2–51 shows a top-level diagram of the
DSP block configured for 18 × 18-bit multiplier mode.
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Digital Signal Processing Block
Figure 2–51. DSP Block Diagram for 18 × 18-Bit Configuration
Optional Serial Shift Register
Inputs from Previous
DSP Block
Multiplier Stage
D
Optional Stage Configurable
as Accumulator or Dynamic
Adder/Subtractor
Q
ENA
CLRN
D
D
ENA
CLRN
Q
Output Selection
Multiplexer
Q
ENA
CLRN
Adder/
Subtractor/
Accumulator
1
D
Q
ENA
CLRN
D
D
ENA
CLRN
Q
Q
ENA
CLRN
Summation
D
Q
ENA
CLRN
D
D
ENA
CLRN
Q
Q
Summation Stage
for Adding Four
Multipliers Together
Optional Output
Register Stage
ENA
CLRN
Adder/
Subtractor/
Accumulator
2
D
Optional Serial
Shift Register
Outputs to
Next DSP Block
in the Column
Q
ENA
CLRN
D
D
ENA
CLRN
Q
ENA
CLRN
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Q
Optional Pipeline
Register Stage
Optional Input Register
Stage with Parallel Input or
Shift Register Configuration
to MultiTrack
Interconnect
Altera Corporation
May 2008
Arria GX Architecture
Modes of Operation
The adder, subtractor, and accumulate functions of a DSP block have four
modes of operation:
■
■
■
■
Simple multiplier
Multiply-accumulator
Two-multipliers adder
Four-multipliers adder
Table 2–14 shows the different number of multipliers possible in each
DSP block mode according to size. These modes allow the DSP blocks to
implement numerous applications for DSP including FFTs, complex FIR,
FIR, 2D FIR filters, equalizers, IIR, correlators, matrix multiplication, and
many other functions. DSP blocks also support mixed modes and mixed
multiplier sizes in the same block. For example, half of one DSP block can
implement one 18 × 18-bit multiplier in multiply-accumulator mode,
while the other half of the DSP block implements four 9 × 9-bit multipliers
in simple multiplier mode.
Table 2–14. Multiplier Size and Configurations per DSP Block
DSP Block Mode
Multiplier
9×9
Eight multipliers with
eight product outputs
Multiply-accumulator
—
Two-multipliers adder
Four-multipliers adder
18 × 18
Four multipliers with four
product outputs
36 × 36
One multiplier with one
product output
Two 52-bit multiplyaccumulate blocks
—
Four two-multiplier adder
(two 9 × 9 complex
multiply)
Two two-multiplier adder
(one 18 × 18 complex
multiply)
—
Two four-multiplier adder
One four-multiplier adder
—
DSP Block Interface
The Arria GX device DSP block input registers can generate a shift
register that can cascade down in the same DSP block column. Dedicated
connections between DSP blocks provide fast connections between shift
register inputs to cascade shift register chains. You can cascade registers
within multiple DSP blocks for 9 × 9- or 18 × 18-bit FIR filters larger than
four taps, with additional adder stages implemented in ALMs. If the DSP
block is configured as 36 × 36 bits, the adder, subtractor, or accumulator
stages are implemented in ALMs. Each DSP block can route the shift
register chain out of the block to cascade multiple columns of DSP blocks.
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Digital Signal Processing Block
The DSP block is divided into four block units that interface with four
LAB rows on the left and right. Each block unit can be considered one
complete 18 × 18-bit multiplier with 36 inputs and 36 outputs. A local
interconnect region is associated with each DSP block. Like a LAB, this
interconnect region can be fed with 16 direct link interconnects from the
LAB to the left or right of the DSP block in the same row. R4 and C4
routing resources can access the DSP block’s local interconnect region.
The outputs also work similarly to LAB outputs as well. Eighteen outputs
from the DSP block can drive to the left LAB through direct link
interconnects and 18 can drive to the right LAB though direct link
interconnects. All 36 outputs can drive to R4 and C4 routing
interconnects. Outputs can drive right- or left-column routing.
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Arria GX Architecture
Figures 2–52 and 2–53 show the DSP block interfaces to LAB rows.
Figure 2–52. DSP Block Interconnect Interface
DSP Block
R4, C4 & Direct
Link Interconnects
OA[17..0]
OB[17..0]
R4, C4 & Direct
Link Interconnects
A1[17..0]
B1[17..0]
OC[17..0]
OD[17..0]
A2[17..0]
B2[17..0]
OE[17..0]
OF[17..0]
A3[17..0]
B3[17..0]
OG[17..0]
OH[17..0]
A4[17..0]
B4[17..0]
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May 2008
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Figure 2–53. DSP Block Interface to Interconnect
Direct Link Interconnect
from Adjacent LAB
C4 Interconnect
R4 Interconnect
Direct Link Outputs
to Adjacent LABs
Direct Link Interconnect
from Adjacent LAB
36
DSP Block
Row Structure
36
LAB
LAB
18
16
16
12
Control
36
A[17..0]
B[17..0]
OA[17..0]
OB[17..0]
36
Row Interface
Block
DSP Block to
LAB Row Interface
Block Interconnect Region
36 Inputs per Row
36 Outputs per Row
A bus of 44 control signals feeds the entire DSP block. These signals
include clocks, asynchronous clears, clock enables, signed and unsigned
control signals, addition and subtraction control signals, rounding and
saturation control signals, and accumulator synchronous loads. The clock
signals are routed from LAB row clocks and are generated from specific
LAB rows at the DSP block interface. The LAB row source for control
signals, data inputs, and outputs is shown in Table 2–15.
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Arria GX Architecture
f
For more information about DSP blocks, refer to the DSP Blocks in Arria
GX Devices chapter in volume 2 of the Arria GX Device Handbook.
Table 2–15. DSP Block Signal Sources and Destinations
LAB Row at
Interface
Altera Corporation
May 2008
Control Signals Generated
Data Inputs
Data Outputs
0
clock0
aclr0
ena0
mult01_saturate
addnsub1_round/
accum_round
addnsub1
signa
sourcea
sourceb
A1[17..0]
B1[17..0]
OA[17..0]
OB[17..0]
1
clock1
aclr1
ena1
accum_saturate
mult01_round
accum_sload
sourcea
sourceb
mode0
A2[17..0]
B2[17..0]
OC[17..0]
OD[17..0]
2
clock2
aclr2
ena2
mult23_saturate
addnsub3_round/
accum_round
addnsub3
sign_b
sourcea
sourceb
A3[17..0]
B3[17..0]
OE[17..0]
OF[17..0]
3
clock3
aclr3
ena3
accum_saturate
mult23_round
accum_sload
sourcea
sourceb
mode1
A4[17..0]
B4[17..0]
OG[17..0]
OH[17..0]
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PLLs and Clock Networks
PLLs and Clock
Networks
Arria GX devices provide a hierarchical clock structure and multiple
phase-locked loops (PLLs) with advanced features. The large number of
clocking resources in combination with the clock synthesis precision
provided by enhanced and fast PLLs provides a complete clock
management solution.
Global and Hierarchical Clocking
Arria GX devices provide 16 dedicated global clock networks and
32 regional clock networks (eight per device quadrant). These clocks are
organized into a hierarchical clock structure that allows for up to 24 clocks
per device region with low skew and delay. This hierarchical clocking
scheme provides up to 48 unique clock domains in Arria GX devices.
There are 12 dedicated clock pins (CLK[15..12] and CLK[7..0]) to
drive either the global or regional clock networks. Four clock pins drive
each side of the device except the right side, as shown in Figures 2–54 and
2–55. Internal logic and enhanced and fast PLL outputs can also drive the
global and regional clock networks. Each global and regional clock has a
clock control block, which controls the selection of the clock source and
dynamically enables or disables the clock to reduce power consumption.
Table 2–16 shows the global and regional clock features.
Table 2–16. Global and Regional Clock Features
Feature
Global Clocks
Regional Clocks
Number per device
16
32
Number available per
quadrant
16
8
Clock pins, PLL outputs,
core routings,
inter-transceiver clocks
Clock pins, PLL outputs,
core routings,
inter-transceiver clocks
Sources
Dynamic clock source
selection
v
Dynamic enable/disable
v
v
Global Clock Network
These clocks drive throughout the entire device, feeding all device
quadrants. Global clock networks can be used as clock sources for all
resources in the device IOEs, ALMs, DSP blocks, and all memory blocks.
These resources can also be used for control signals, such as clock enables
and synchronous or asynchronous clears fed from the external pin. The
global clock networks can also be driven by internal logic for internally
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Arria GX Architecture
generated global clocks and asynchronous clears, clock enables, or other
control signals with large fanout. Figure 2–54 shows the 12 dedicated CLK
pins driving global clock networks.
Figure 2–54. Global Clocking
CLK[15..12]
Global Clock [15..0]
CLK[3..0]
Global Clock [15..0]
CLK[7..4]
Regional Clock Network
There are eight regional clock networks (RCLK[7..0]) in each quadrant
of the Arria GX device that are driven by the dedicated
CLK[15..12]and CLK[7..0] input pins, by PLL outputs, or by internal
logic. The regional clock networks provide the lowest clock delay and
skew for logic contained in a single quadrant. The CLK pins
symmetrically drive the RCLK networks in a particular quadrant, as
shown in Figure 2–55.
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May 2008
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PLLs and Clock Networks
Figure 2–55. Regional Clocks
CLK[15..12]
11 5
7
CLK[3..0]
RCLK
[31..28]
RCLK
[27..24]
RCLK
[3..0]
RCLK
[23..20]
RCLK
[7..4]
RCLK
[19..16]
Arria GX
Transceiver
Block
1
2
RCLK
[11..8]
8
Arria GX
Transceiver
Block
RCLK
[15..12]
12 6
CLK[7..4]
Dual-Regional Clock Network
A single source (CLK pin or PLL output) can generate a dual-regional
clock by driving two regional clock network lines in adjacent quadrants
(one from each quadrant), which allows logic that spans multiple
quadrants to utilize the same low skew clock. The routing of this clock
signal on an entire side has approximately the same speed but slightly
higher clock skew when compared with a clock signal that drives a single
quadrant. Internal logic-array routing can also drive a dual-regional
clock. Clock pins and enhanced PLL outputs on the top and bottom can
drive horizontal dual-regional clocks. Clock pins and fast PLL outputs on
the left and right can drive vertical dual-regional clocks, as shown in
Figure 2–56. Corner PLLs cannot drive dual-regional clocks.
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Arria GX Architecture
Figure 2–56. Dual-Regional Clocks
Clock Pins or PLL Clock Outputs
Can Drive Dual-Regional Network
CLK[15..12]
CLK[3..0]
Clock Pins or PLL Clock
Outputs Can Drive
Dual-Regional Network
CLK[15..12]
CLK[3..0]
PLLs
PLLs
CLK[7..4]
CLK[7..4]
Combined Resources
Within each quadrant, there are 24 distinct dedicated clocking resources
consisting of 16 global clock lines and eight regional clock lines.
Multiplexers are used with these clocks to form buses to drive LAB row
clocks, column IOE clocks, or row IOE clocks. Another multiplexer is
used at the LAB level to select three of the six row clocks to feed the ALM
registers in the LAB (see Figure 2–57).
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May 2008
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PLLs and Clock Networks
Figure 2–57. Hierarchical Clock Networks Per Quadrant
Clocks Available
to a Quadrant
or Half-Quadrant
Column I/O Cell
IO_CLK[7..0]
Global Clock Network [15..0]
Clock [23..0]
Lab Row Clock [5..0]
Regional Clock Network [7..0]
Row I/O Cell
IO_CLK[7..0]
You can use the Quartus II software to control whether a clock input pin
drives either a global, regional, or dual-regional clock network. The
Quartus II software automatically selects the clocking resources if not
specified.
Clock Control Block
Each global clock, regional clock, and PLL external clock output has its
own clock control block. The control block has two functions:
■
■
Clock source selection (dynamic selection for global clocks)
Clock power-down (dynamic clock enable or disable)
Figures 2–58 through 2–60 show the clock control block for the global
clock, regional clock, and PLL external clock output, respectively.
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Arria GX Architecture
Figure 2–58. Global Clock Control Blocks
CLKp
Pins
PLL Counter
Outputs
CLKSELECT[1..0]
(1)
2
2
CLKn
Pin
2
Internal
Logic
Static Clock Select (2)
This multiplexer supports
User-Controllable
Dynamic Switching
Enable/
Disable
Internal
Logic
GCLK
Notes to Figure 2–58:
(1)
(2)
These clock select signals can be dynamically controlled through internal logic when the device is operating in user
mode.
These clock select signals can only be set through a configuration file (SRAM Object File [.sof] or Programmer Object
File [.pof]) and cannot be dynamically controlled during user mode operation.
Figure 2–59. Regional Clock Control Blocks
CLKp
Pin
PLL Counter
Outputs
CLKn
Pin (2)
2
Internal
Logic
Static Clock Select (1)
Enable/
Disable
Internal
Logic
RCLK
Notes to Figure 2–59:
(1)
(2)
These clock select signals can only be set through a configuration file (SOF or POF) and cannot be dynamically
controlled during user mode operation.
Only the CLKn pins on the top and bottom of the device feed to regional clock select.
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May 2008
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PLLs and Clock Networks
Figure 2–60. External PLL Output Clock Control Blocks
PLL Counter
Outputs (c[5..0])
6
Static Clock Select (1)
Enable/
Disable
Internal
Logic
IOE (2)
Internal
Logic
Static Clock
Select (1)
PLL_OUT
Pin
Notes to Figure 2–60:
(1)
(2)
These clock select signals can only be set through a configuration file (SOF or POF) and cannot be dynamically
controlled during user mode operation.
The clock control block feeds to a multiplexer within the PLL_OUT pin’s IOE. The PLL_OUT pin is a dual-purpose
pin. Therefore, this multiplexer selects either an internal signal or the output of the clock control block.
For the global clock control block, clock source selection can be controlled
either statically or dynamically. You has the option of statically selecting
the clock source by using the Quartus II software to set specific
configuration bits in the configuration file (SOF or POF) or you can control
the selection dynamically by using internal logic to drive the multiplexer
select inputs. When selecting statically, the clock source can be set to any
of the inputs to the select multiplexer. When selecting the clock source
dynamically, you can either select between two PLL outputs (such as the
C0 or C1 outputs from one PLL), between two PLLs (such as the C0/C1
clock output of one PLL or the C0/C1 c1ock output of the other PLL),
between two clock pins (such as CLK0 or CLK1), or between a
combination of clock pins or PLL outputs.
For the regional and PLL_OUT clock control block, clock source selection
can only be controlled statically using configuration bits. Any of the
inputs to the clock select multiplexer can be set as the clock source.
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Arria GX Architecture
Arria GX clock networks can be disabled (powered down) by both static
and dynamic approaches. When a clock net is powered down, all the logic
fed by the clock net is in an off-state thereby reducing the overall power
consumption of the device. Global and regional clock networks can be
powered down statically through a setting in the configuration file (SOF
or POF). Clock networks that are not used are automatically powered
down through configuration bit settings in the configuration file
generated by the Quartus II software. The dynamic clock enable or
disable feature allows the internal logic to control power up/down
synchronously on GCLK and RCLK nets and PLL_OUT pins. This function
is independent of the PLL and is applied directly on the clock network or
PLL_OUT pin, as shown in Figures 2–58 through 2–60.
Enhanced and Fast PLLs
Arria GX devices provide robust clock management and synthesis using
up to four enhanced PLLs and four fast PLLs. These PLLs increase
performance and provide advanced clock interfacing and clock frequency
synthesis. With features such as clock switchover, spread spectrum
clocking, reconfigurable bandwidth, phase control, and reconfigurable
phase shifting, the Arria GX device’s enhanced PLLs provide you with
complete control of your clocks and system timing. The fast PLLs provide
general purpose clocking with multiplication and phase shifting as well
as high-speed outputs for high-speed differential I/O support. Enhanced
and fast PLLs work together with the Aria GX high-speed I/O and
advanced clock architecture to provide significant improvements in
system performance and bandwidth.
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May 2008
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PLLs and Clock Networks
The Quartus II software enables the PLLs and their features without
requiring any external devices. Table 2–17 shows the PLLs available for
each Arria GX device and their type.
Table 2–17. Arria GX Device PLL Availability Notes (1), (2)
Fast PLLs
Enhanced PLLs
Device
1
2
3 (3) 4 (3)
7
8
EP1AGX20
v
v
EP1AGX35
v
v
EP1AGX50 (4)
v
v
v
v
EP1AGX60(5)
v
v
v
EP1AGX90
v
v
v
9 (3)
10 (3)
5
6
11
12
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Notes to Table 2–17:
(1)
(2)
(3)
(4)
(5)
The global or regional clocks in a fast PLL's transceiver block can drive the fast PLL input. A pin or other PLL must
drive the global or regional source. The source cannot be driven by internally generated logic before driving the fast
PLL.
EP1AGX20C, EP1AGX35C/D, EP1AGX50C and EP1AGX60C/D devices only have two fast PLLs (PLLs 1 and 2), but
the connectivity from these two PLLs to the global and regional clock networks remains the same as shown in this
table.
PLLs 3, 4, 9, and 10 are not available in Arria GX devices.
4 or 8 PLLs are available depending on C or D device and the package option.
4or 8 PLLs are available depending on C, D, or E device option.
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Arria GX Architecture
Table 2–18 shows the enhanced PLL and fast PLL features in Arria GX
devices.
Table 2–18. Arria GX PLL Features
Feature
Enhanced PLL
Fast PLL
Clock multiplication and division
m/(n × post-scale counter) (1)
m/(n × post-scale counter) (2)
Down to 125-ps increments (3), (4)
Down to 125-ps increments (3), (4)
Clock switchover
v
v (5)
PLL reconfiguration
v
v
Reconfigurable bandwidth
v
v
Spread spectrum clocking
v
Programmable duty cycle
v
v
Number of internal clock outputs
6
4
Number of external clock outputs
Three differential/six single-ended
(6)
Number of feedback clock inputs
One single-ended or differential
(7), (8)
Phase shift
Notes to Table 2–18:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
For enhanced PLLs, m, n range from 1 to 256 and post-scale counters range from 1 to 512 with 50% duty cycle.
For fast PLLs, m, and post-scale counters range from 1 to 32. The n counter ranges from 1 to 4.
The smallest phase shift is determined by the voltage controlled oscillator (VC O ) period divided by 8.
For degree increments, Arria GX devices can shift all output frequencies in increments of at least 45. Smaller degree
increments are possible depending on the frequency and divide parameters.
Arria GX fast PLLs only support manual clock switchover.
Fast PLLs can drive to any I/O pin as an external clock. For high-speed differential I/O pins, the device uses a data
channel to generate txclkout.
If the feedback input is used, you will lose one (or two, if fBIN is differential) external clock output pin.
Every Arria GX device has at least two enhanced PLLs with one single-ended or differential external feedback
input per PLL.
Altera Corporation
May 2008
2–89
Arria GX Device Handbook, Volume 1
PLLs and Clock Networks
Figure 2–61 shows a top-level diagram of the Arria GX device and PLL
floorplan.
Figure 2–61. PLL Locations
CLK[15..12]
FPLL7CLK
7
CLK[3..0]
1
2
11
5
12
6
PLLs
FPLL8CLK
8
CLK[7..4]
Figures 2–62 and 2–63 shows global and regional clocking from the fast
PLL outputs and side clock pins. The connections to the global and
regional clocks from the fast PLL outputs, internal drivers, and CLK pins
on the left side of the device are shown in Table 2–19.
2–90
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
Arria GX Architecture
Figure 2–62. Global and Regional Clock Connections from Center Clock Pins and Fast PLL Outputs Note (1)
C0
CLK0
CLK1
Fast
PLL 1
C1
C2
C3
Logic Array
Signal Input
To Clock
Network
C0
CLK2
CLK3
Fast
PLL 2
C1
C2
C3
RCLK0
RCLK2
RCLK1
RCLK4
RCLK3
RCLK6
RCLK5
RCLK7
GCLK0
GCLK1
GCLK2
GCLK3
Note to Figure 2–62:
(1)
The global or regional clocks in a fast PLL's quadrant can drive the fast PLL input. A dedicated clock input pin or
other PLL must drive the global or regional source. The source cannot be driven by internally generated logic before
driving the fast PLL.
Altera Corporation
May 2008
2–91
Arria GX Device Handbook, Volume 1
PLLs and Clock Networks
Figure 2–63. Global and Regional Clock Connections from Corner Clock Pins and Fast PLL Outputs Note (1)
RCLK1
RCLK3
RCLK0
RCLK2
RCLK4
RCLK6
C0
Fast
PLL 7
C1
C2
C3
C0
Fast
PLL 8
C1
C2
C3
RCLK5
GCLK0
RCLK7
GCLK2
GCLK1
GCLK3
Note to Figure 2–63:
(1)
The global or regional clocks in a fast PLL's quadrant can drive the fast PLL input. A dedicated clock input pin or
other PLL must drive the global or regional source. The source cannot be driven by internally generated logic before
driving the fast PLL.
RCLK7
RCLK6
RCLK5
v
RCLK4
v
RCLK3
CLK1p
RCLK2
v
RCLK1
v
RCLK0
CLK1
CLK0p
CLK3
CLK0
Left Side Global & Regional Clock
Network Connectivity
CLK2
Table 2–19. Global and Regional Clock Connections from Left Side Clock Pins and Fast PLL Outputs
(Part 1 of 3)
Clock Pins
v
v
v
CLK2p
v
v
CLK3p
v
v
v
v
v
v
v
Drivers from Internal Logic
2–92
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
Arria GX Architecture
v
v
v
RCLKDRV1
v
v
RCLKDRV2
v
v
RCLKDRV3
v
RCLKDRV4
v
v
v
RCLKDRV5
RCLK7
v
RCLK6
v
RCLKDRV0
RCLK5
v
RCLK4
v
GCLKDRV3
RCLK3
v
RCLK2
v
GCLKDRV2
RCLK1
v
RCLK0
v
GCLKDRV1
CLK3
CLK1
GCLKDRV0
CLK2
Left Side Global & Regional Clock
Network Connectivity
CLK0
Table 2–19. Global and Regional Clock Connections from Left Side Clock Pins and Fast PLL Outputs
(Part 2 of 3)
v
v
RCLKDRV6
v
v
RCLKDRV7
v
PLL 1 Outputs
c0
v
v
c1
v
v
v
v
v
c2
v
v
c3
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
PLL 2 Outputs
c0
v
v
c1
v
v
v
c2
v
v
c3
v
v
c0
v
v
c1
v
v
v
v
v
v
v
v
v
v
v
v
v
PLL 7 Outputs
c2
v
v
c3
v
v
v
v
v
v
v
v
v
v
PLL 8 Outputs
Altera Corporation
May 2008
2–93
Arria GX Device Handbook, Volume 1
PLLs and Clock Networks
v
v
c3
v
v
2–94
Arria GX Device Handbook, Volume 1
v
RCLK7
RCLK6
RCLK5
v
RCLK4
v
c2
RCLK3
v
RCLK2
v
c1
RCLK1
CLK3
c0
RCLK0
CLK2
CLK1
Left Side Global & Regional Clock
Network Connectivity
CLK0
Table 2–19. Global and Regional Clock Connections from Left Side Clock Pins and Fast PLL Outputs
(Part 3 of 3)
v
v
v
v
v
v
v
Altera Corporation
May 2008
Arria GX Architecture
Figure 2–64 shows the global and regional clocking from enhanced PLL
outputs and top and bottom CLK pins.
Figure 2–64. Global and Regional Clock Connections from Top and Bottom Clock Pins and Enhanced PLL
Outputs Note (1)
CLK15
CLK13
CLK12
CLK14
PLL5_FB
PLL11_FB
PLL 11
PLL 5
c0 c1 c2 c3 c4 c5
c0 c1 c2 c3 c4 c5
PLL5_OUT[2..0]p
PLL5_OUT[2..0]n
RCLK31
RCLK30
RCLK29
RCLK28
PLL11_OUT[2..0]p
PLL11_OUT[2..0]n
Regional
Clocks
RCLK27
RCLK26
RCLK25
RCLK24
G15
G14
G13
G12
Global
Clocks
Regional
Clocks
G4
G5
G6
G7
RCLK8
RCLK9
RCLK10
RCLK11
RCLK12
RCLK13
RCLK14
RCLK15
PLL6_OUT[2..0]p
PLL6_OUT[2..0]n
PLL12_OUT[2..0]p
PLL12_OUT[2..0]n
c0 c1 c2 c3 c4 c5
c0 c1 c2 c3 c4 c5
PLL 12
PLL 6
PLL12_FB
PLL6_FB
CLK6
CLK4
CLK5
CLK7
Note to Figure 2–64:
(1)
If the design uses the feedback input, you will lose one (or two if FBIN is differential) external clock output pin.
Altera Corporation
May 2008
2–95
Arria GX Device Handbook, Volume 1
PLLs and Clock Networks
The connections to the global and regional clocks from the top clock pins
and enhanced PLL outputs are shown in Table 2–20. The connections to
the clocks from the bottom clock pins are shown in Table 2–21.
CLK14p
v
v
v
CLK15p
v
v
v
RCLK31
v
RCLK30
v
RCLK29
v
RCLK28
CLK13p
RCLK27
v
RCLK26
v
RCLK25
CLK13
v
CLK15
CLK12
CLK12p
CLK14
DLLCLK
Top Side Global and
Regional Clock Network
Connectivity
RCLK24
Table 2–20. Global and Regional Clock Connections from Top Clock Pins and Enhanced PLL Outputs
(Part 1 of 2)
Clock pins
v
v
v
CLK12n
v
v
v
v
v
v
CLK13n
v
v
v
v
CLK14n
v
v
v
v
CLK15n
v
v
v
Drivers from internal logic
v
GCLKDRV0
v
GCLKDRV1
v
GCLKDRV2
v
GCLKDRV3
v
RCLKDRV0
v
v
RCLKDRV1
v
v
RCLKDRV2
v
v
RCLKDRV3
v
RCLKDRV4
v
v
v
RCLKDRV5
v
v
RCLKDRV6
v
v
RCLKDRV7
v
Enhanced PLL5 outputs
c0
v
v
v
c1
v
v
v
2–96
Arria GX Device Handbook, Volume 1
v
v
v
v
Altera Corporation
May 2008
Arria GX Architecture
v
c4
v
c5
v
v
v
v
v
v
RCLK31
v
v
RCLK30
v
RCLK29
c3
RCLK28
v
RCLK27
v
RCLK26
v
RCLK25
CLK15
c2
RCLK24
CLK14
CLK13
CLK12
Top Side Global and
Regional Clock Network
Connectivity
DLLCLK
Table 2–20. Global and Regional Clock Connections from Top Clock Pins and Enhanced PLL Outputs
(Part 2 of 2)
v
v
v
v
v
v
Enhanced PLL 11 outputs
c0
v
v
c1
v
v
v
v
v
c2
v
v
c3
v
v
v
v
v
v
c4
v
v
v
c5
v
v
v
v
v
v
v
v
v
v
v
RCLK15
v
CLK7p
RCLK14
v
RCLK13
v
RCLK12
v
CLK6p
RCLK11
v
RCLK10
v
RCLK9
CLK5
v
CLK5p
CLK7
CLK4
CLK4p
CLK6
DLLCLK
Bottom Side Global and
Regional Clock Network
Connectivity
RCLK8
Table 2–21. Global and Regional Clock Connections from Bottom Clock Pins and Enhanced PLL
Outputs
(Part 1 of 2)
Clock pins
CLK4n
v
v
v
v
v
v
v
v
v
CLK5n
v
v
v
v
CLK7n
v
v
v
CLK6n
v
v
v
v
Drivers from internal logic
GCLKDRV0
GCLKDRV1
Altera Corporation
May 2008
v
v
2–97
Arria GX Device Handbook, Volume 1
PLLs and Clock Networks
RCLK15
RCLK14
RCLK13
RCLK12
RCLK11
RCLK10
RCLK9
RCLK8
CLK7
CLK6
CLK5
CLK4
Bottom Side Global and
Regional Clock Network
Connectivity
DLLCLK
Table 2–21. Global and Regional Clock Connections from Bottom Clock Pins and Enhanced PLL
Outputs
(Part 2 of 2)
v
GCLKDRV2
v
GCLKDRV3
v
RCLKDRV0
v
v
RCLKDRV1
v
v
RCLKDRV2
v
v
RCLKDRV3
v
RCLKDRV4
v
v
v
RCLKDRV5
v
v
RCLKDRV6
v
v
RCLKDRV7
v
Enhanced PLL 6 outputs
c0
v
v
v
v
c1
v
v
v
c2
v
v
v
c3
v
v
v
c4
v
c5
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Enhanced PLL 12 outputs
c0
v
v
c1
v
v
v
v
c2
v
v
c3
v
v
c4
c5
2–98
Arria GX Device Handbook, Volume 1
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Altera Corporation
May 2008
Arria GX Architecture
Enhanced PLLs
Arria GX devices contain up to four enhanced PLLs with advanced clock
management features. These features include support for external clock
feedback mode, spread-spectrum clocking, and counter cascading.
Figure 2–65 shows a diagram of the enhanced PLL.
Figure 2–65. Arria GX Enhanced PLL Note (1)
From Adjacent PLL
VCO Phase Selection
Selectable at Each
PLL Output Port
Clock
Switchover
Circuitry
Post-Scale
Counters
Spread
Spectrum
Phase Frequency
Detector
/c0
INCLK[3..0]
/c1
4
/n
PFD
Charge
Pump
Loop
Filter
8
VCO
Global or
Regional
Clock
4
Global
Clocks
8
Regional
Clocks
/c2
6
/c3
6
/m
I/O Buffers (3)
/c4
(2)
/c5
Lock Detect
& Filter
FBIN
to I/O or general
routing
VCO Phase Selection
Affecting All Outputs
Shaded Portions of the
PLL are Reconfigurable
Notes to Figure 2–65:
(1)
(2)
(3)
(4)
Each clock source can come from any of the four clock pins that are physically located on the same side of the device
as the PLL.
If the feedback input is used, you will lose one (or two, if FBIN is differential) external clock output pin.
Each enhanced PLL has three differential external clock outputs or six single-ended external clock outputs.
The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or
regional clock, or through a clock control block provided the clock control block is fed by an output from another
PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL.
Fast PLLs
Arria GX devices contain up to four fast PLLs with high-speed serial
interfacing ability. Fast PLLs offer high-speed outputs to manage the
high-speed differential I/O interfaces. Figure 2–66 shows a diagram of
the fast PLL.
Altera Corporation
May 2008
2–99
Arria GX Device Handbook, Volume 1
I/O Structure
Figure 2–66. Arria GX Device Fast PLL
Clock
Switchover
Circuitry (4)
Global or
regional clock (1)
Clock
Input
VCO Phase Selection
Selectable at each PLL
Output Port
Phase
Frequency
Detector
Post-Scale
Counters
diffioclk0 (2)
load_en0 (3)
÷c0
÷n
4
PFD
Charge
Pump
Loop
Filter
VCO
÷k
8
load_en1 (3)
÷c1
diffioclk1 (2)
4
Global clocks
÷c2
4
Global or
regional clock (1)
8
Regional clocks
÷c3
÷m
8
to DPA block
Shaded Portions of the
PLL are Reconfigurable
Notes to Figure 2–66:
(1)
(2)
(3)
(4)
The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or
regional clock, or through a clock control block provided the clock control block is fed by an output from another
PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL.
In high-speed differential I/O support mode, this high-speed PLL clock feeds the serializer/deserializer (SERDES)
circuitry. Arria GX devices only support one rate of data transfer per fast PLL in high-speed differential I/O support
mode.
This signal is a differential I/O SERDES control signal.
Arria GX fast PLLs only support manual clock switchover.
f
I/O Structure
For more information about enhanced and fast PLLs, refer to the PLLs in
Arria GX Devices chapter in volume 2 of the Arria GX Device Handbook.
Refer to “High-Speed Differential I/O with DPA Support” on page 2–124
for more information about high-speed differential I/O support.
The Arria GX IOEs provide many features, including:
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Dedicated differential and single-ended I/O buffers
3.3-V, 64-bit, 66-MHz PCI compliance
3.3-V, 64-bit, 133-MHz PCI-X 1.0 compliance
Joint Test Action Group (JTAG) boundary-scan test (BST) support
On-chip driver series termination
On-chip termination for differential standards
Programmable pull-up during configuration
Output drive strength control
Tri-state buffers
Bus-hold circuitry
Programmable pull-up resistors
Programmable input and output delays
Open-drain outputs
DQ and DQS I/O pins
Double data rate (DDR) registers
2–100
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
Arria GX Architecture
The IOE in Arria GX devices contains a bidirectional I/O buffer, six
registers, and a latch for a complete embedded bidirectional single data
rate or DDR transfer. Figure 2–67 shows the Arria GX IOE structure. The
IOE contains two input registers (plus a latch), two output registers, and
two output enable registers. The design can use both input registers and
the latch to capture DDR input and both output registers to drive DDR
outputs. Additionally, the design can use the output enable (OE) register
for fast clock-to-output enable timing. The negative edge-clocked OE
register is used for DDR SDRAM interfacing. The Quartus II software
automatically duplicates a single OE register that controls multiple
output or bidirectional pins.
Altera Corporation
May 2008
2–101
Arria GX Device Handbook, Volume 1
I/O Structure
Figure 2–67. Arria GX IOE Structure
Logic Array
OE Register
OE
D
Q
OE Register
D
Q
Output Register
Output A
D
Q
CLK
Output Register
Output B
D
Q
Input Register
D
Q
Input A
Input B
Input Register
D
Q
Input Latch
D
Q
ENA
The IOEs are located in I/O blocks around the periphery of the Arria GX
device. There are up to four IOEs per row I/O block and four IOEs per
column I/O block. Row I/O blocks drive row, column, or direct link
interconnects. Column I/O blocks drive column interconnects.
2–102
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
Arria GX Architecture
Figure 2–68 shows how a row I/O block connects to the logic array.
Figure 2–68. Row I/O Block Connection to the Interconnect
R4 & R24
Interconnects
C4 Interconnect
I/O Block Local
Interconnect
32 Data & Control
Signals from
Logic Array (1)
32
LAB
Horizontal
I/O Block
io_dataina[3..0]
io_datainb[3..0]
Direct Link
Interconnect
to Adjacent LAB
Direct Link
Interconnect
to Adjacent LAB
io_clk[7:0]
LAB Local
Interconnect
Horizontal I/O
Block Contains
up to Four IOEs
Note to Figure 2–68:
(1)
The 32 data and control signals consist of eight data out lines: four lines each for DDR applications
io_dataouta[3..0] and io_dataoutb[3..0], four output enables io_oe[3..0], four input clock enables
io_ce_in[3..0], four output clock enables io_ce_out[3..0], four clocks io_clk[3..0], four asynchronous
clear and preset signals io_aclr/apreset[3..0], and four synchronous clear and preset signals
io_sclr/spreset[3..0].
Altera Corporation
May 2008
2–103
Arria GX Device Handbook, Volume 1
I/O Structure
Figure 2–69 shows how a column I/O block connects to the logic array.
Figure 2–69. Column I/O Block Connection to the Interconnect
32 Data &
Control Signals
from Logic Array (1)
Vertical I/O
Block Contains
up to Four IOEs
Vertical I/O Block
32
IO_dataina[3..0]
IO_datainb[3..0]
io_clk[7..0]
I/O Block
Local Interconnect
R4 & R24
Interconnects
LAB
LAB Local
Interconnect
LAB
LAB
C4 & C16
Interconnects
Note to Figure 2–69:
(1)
The 32 data and control signals consist of eight data out lines: four lines each for DDR applications
io_dataouta[3..0] and io_dataoutb[3..0], four output enables io_oe[3..0], four input clock enables
io_ce_in[3..0], four output clock enables io_ce_out[3..0], four clocks io_clk[3..0], four asynchronous
clear and preset signals io_aclr/apreset[3..0], and four synchronous clear and preset signals
io_sclr/spreset[3..0].
2–104
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
Arria GX Architecture
There are 32 control and data signals that feed each row or column I/O
block. These control and data signals are driven from the logic array. The
row or column IOE clocks, io_clk[7..0], provide a dedicated routing
resource for low-skew, high-speed clocks. I/O clocks are generated from
global or regional clocks (refer to “PLLs and Clock Networks” on
page 2–80).
Figure 2–70 illustrates the signal paths through the I/O block.
Figure 2–70. Signal Path Through the I/O Block
Row or Column
io_clk[7..0]
To Logic
Array
To Other
IOEs
io_dataina
io_datainb
oe
ce_in
io_oe
ce_out
io_ce_in
io_ce_out
Control
Signal
Selection
aclr/apreset
IOE
sclr/spreset
io_aclr
From Logic
Array
clk_in
io_sclr
clk_out
io_clk
io_dataouta
io_dataoutb
Each IOE contains its own control signal selection for the following
control signals: oe, ce_in, ce_out, aclr/apreset, sclr/spreset,
clk_in, and clk_out. Figure 2–71 illustrates the control signal
selection.
Altera Corporation
May 2008
2–105
Arria GX Device Handbook, Volume 1
I/O Structure
Figure 2–71. Control Signal Selection per IOE Note (1)
Dedicated I/O
Clock [7..0]
Local
Interconnect
io_oe
Local
Interconnect
io_sclr
Local
Interconnect
io_aclr
Local
Interconnect
io_ce_out
Local
Interconnect
io_ce_in
Local
Interconnect
io_clk
ce_out
clk_out
clk_in
ce_in
sclr/spreset
aclr/apreset
oe
Notes to Figure 2–71:
(1)
Control signals ce_in, ce_out, aclr/apreset, sclr/spreset, and oe can be global signals even though their
control selection multiplexers are not directly fed by the ioe_clk[7..0] signals. The ioe_clk signals can drive
the I/O local interconnect, which then drives the control selection multiplexers.
In normal bidirectional operation, you can use the input register for input
data requiring fast setup times. The input register can have its own clock
input and clock enable separate from the OE and output registers. The
output register can be used for data requiring fast clock-to-output
performance. You can use the OE register for fast clock-to-output enable
timing. The OE and output register share the same clock source and the
same clock enable source from the local interconnect in the associated
LAB, dedicated I/O clocks, and the column and row interconnects.
Figure 2–72 shows the IOE in bidirectional configuration.
2–106
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
Arria GX Architecture
Figure 2–72. Arria GX IOE in Bidirectional I/O Configuration Note (1)
ioe_clk[7..0]
Column, Row,
or Local
Interconnect
oe
OE Register
D
Q
clkout
ENA
CLRN/PRN
ce_out
OE Register
tCO Delay
VCCIO
PCI Clamp (2)
VCCIO
Programmable
Pull-Up
Resistor
aclr/apreset
Chip-Wide Reset
Output Register
D
sclr/spreset
Q
Output
Pin Delay
On-Chip
Termination
Drive Strength Control
ENA
Open-Drain Output
CLRN/PRN
Input Pin to
Logic Array Delay
Input Register
clkin
ce_in
D
Input Pin to
Input Register Delay
Bus-Hold
Circuit
Q
ENA
CLRN/PRN
Notes to Figure 2–72:
(1)
(2)
All input signals to the IOE can be inverted at the IOE.
The optional PCI clamp is only available on column I/O pins.
The Arria GX device IOE includes programmable delays that can be
activated to ensure input IOE register-to-logic array register transfers,
input pin-to-logic array register transfers, or output IOE register-to-pin
transfers.
Altera Corporation
May 2008
2–107
Arria GX Device Handbook, Volume 1
I/O Structure
A path in which a pin directly drives a register can require the delay to
ensure zero hold time, whereas a path in which a pin drives a register
through combinational logic may not require the delay. Programmable
delays exist for decreasing input-pin-to-logic-array and IOE input
register delays. The Quartus II Compiler can program these delays to
automatically minimize setup time while providing a zero hold time.
Programmable delays can increase the register-to-pin delays for output
and/or output enable registers. Programmable delays are no longer
required to ensure zero hold times for logic array register-to-IOE register
transfers. The Quartus II Compiler can create zero hold time for these
transfers. Table 2–22 shows the programmable delays for Arria GX
devices.
Table 2–22. Arria GX Devices Programmable Delay Chain
Programmable Delays
Quartus II Logic Option
Input pin to logic array delay
Input delay from pin to internal cells
Input pin to input register delay
Input delay from pin to input register
Output pin delay
Delay from output register to output pin
Output enable register tCO delay
Delay to output enable pin
IOE registers in Arria GX devices share the same source for clear or
preset. You can program preset or clear for each individual IOE. You can
also program the registers to power up high or low after configuration is
complete. If programmed to power up low, an asynchronous clear can
control the registers. If programmed to power up high, an asynchronous
preset can control the registers. This feature prevents the inadvertent
activation of another device’s active-low input upon power-up. If one
register in an IOE uses a preset or clear signal, all registers in the IOE must
use that same signal if they require preset or clear. Additionally, a
synchronous reset signal is available for the IOE registers.
Double Data Rate I/O Pins
Arria GX devices have six registers in the IOE, which support DDR
interfacing by clocking data on both positive and negative clock edges.
The IOEs in Arria GX devices support DDR inputs, DDR outputs, and
bidirectional DDR modes. When using the IOE for DDR inputs, the two
input registers clock double rate input data on alternating edges. An
input latch is also used in the IOE for DDR input acquisition. The latch
holds the data that is present during the clock high times, allowing both
bits of data to be synchronous with the same clock edge (either rising or
falling). Figure 2–73 shows an IOE configured for DDR input. Figure 2–74
shows the DDR input timing diagram.
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Arria GX Architecture
Figure 2–73. Arria GX IOE in DDR Input I/O Configuration Note (1)
ioe_clk[7..0]
Column, Row,
or Local
Interconnect
VCCIO
To DQS Logic
Block (3)
DQS Local
Bus (2)
PCI Clamp (4)
VCCIO
Programmable
Pull-Up
Resistor
On-Chip
Termination
Input Pin to
Input RegisterDelay
sclr/spreset
Input Register
D
Q
clkin
ce_in
ENA
CLRN/PRN
Bus-Hold
Circuit
aclr/apreset
Chip-Wide Reset
Latch
Input Register
D
Q
ENA
CLRN/PRN
D
Q
ENA
CLRN/PRN
Notes to Figure 2–73:
(1)
(2)
(3)
(4)
All input signals to the IOE can be inverted at the IOE.
This signal connection is only allowed on dedicated DQ function pins.
This signal is for dedicated DQS function pins only.
The optional PCI clamp is only available on column I/O pins.
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May 2008
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I/O Structure
Figure 2–74. Input Timing Diagram in DDR Mode
Data at
input pin
B0
A0
B1
A1
B2
A2
B3
A3
B4
CLK
A0
A1
A2
A3
B0
B1
B2
B3
Input To
Logic Array
When using the IOE for DDR outputs, the two output registers are
configured to clock two data paths from ALMs on rising clock edges.
These output registers are multiplexed by the clock to drive the output
pin at a ×2 rate. One output register clocks the first bit out on the clock
high time, while the other output register clocks the second bit out on the
clock low time. Figure 2–75 shows the IOE configured for DDR output.
Figure 2–76 shows the DDR output timing diagram.
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May 2008
Arria GX Architecture
Figure 2–75. Arria GX IOE in DDR Output I/O Configuration Notes (1), (2)
ioe_clk[7..0]
Column, Row,
or Local
Interconnect
oe
OE Register
D
Q
clkout
ENA
CLRN/PRN
OE Register
tCO Delay
ce_out
aclr/apreset
VCCIO
PCI Clamp (3)
Chip-Wide Reset
OE Register
D
VCCIO
Q
sclr/spreset
ENA
CLRN/PRN
Used for
DDR, DDR2
SDRAM
Programmable
Pull-Up
Resistor
Output Register
D
Q
ENA
CLRN/PRN
Output Register
D
Output
Pin Delay
On-Chip
Termination
clk
Drive Strength
Control
Open-Drain Output
Q
ENA
CLRN/PRN
Bus-Hold
Circuit
Notes to Figure 2–75:
(1)
(2)
(3)
All input signals to the IOE can be inverted at the IOE.
The tri-state buffer is active low. The DDIO megafunction represents the tri-state buffer as active-high with an
inverter at the OE register data port.
The optional PCI clamp is only available on column I/O pins.
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May 2008
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I/O Structure
Figure 2–76. Output Timing Diagram in DDR Mode
CLK
A1
A2
A3
A4
B1
B2
B3
B4
From Internal
Registers
DDR output
B1
A1
B2
A2
B3
A3
B4
A4
The Arria GX IOE operates in bidirectional DDR mode by combining the
DDR input and DDR output configurations. The negative-edge-clocked
OE register holds the OE signal inactive until the falling edge of the clock
to meet DDR SDRAM timing requirements.
External RAM Interfacing
In addition to the six I/O registers in each IOE, Arria GX devices also
have dedicated phase-shift circuitry for interfacing with external memory
interfaces, including DDR, DDR2 SDRAM, and SDR SDRAM. In every
Arria GX device, the I/O banks at the top (Banks 3 and 4) and bottom
(Banks 7 and 8) of the device support DQ and DQS signals with DQ bus
modes of ×4, ×8/×9, ×16/×18, or ×32/×36. Table 2–23 shows the number
of DQ and DQS buses that are supported per device.
Table 2–23. DQS and DQ Bus Mode Support (Part 1 of 2) Note (1)
Device
Package
Number of
×4 Groups
Number of
×8/×9 Groups
Number of
×16/×18
Groups
Number of
×32/×36
Groups
2
0
0
0
EP1AGX20
484-pin FineLine BGA
EP1AGX35
484-pin FineLine BGA
2
0
0
0
780-pin FineLine BGA
18
8
4
0
EP1AGX50/60
484-pin FineLine BGA
2
0
0
0
780-pin FineLine BGA
18
8
4
0
1,152-pin FineLine BGA
36
18
8
4
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Arria GX Architecture
Table 2–23. DQS and DQ Bus Mode Support (Part 2 of 2) Note (1)
Device
EP1AGX90
Package
Number of
×4 Groups
Number of
×8/×9 Groups
Number of
×16/×18
Groups
Number of
×32/×36
Groups
36
18
8
4
1,152-pin FineLine BGA
Note to Table 2–23:
(1)
Numbers are preliminary until devices are available.
A compensated delay element on each DQS pin automatically aligns
input DQS synchronization signals with the data window of their
corresponding DQ data signals. The DQS signals drive a local DQS bus in
the top and bottom I/O banks. This DQS bus is an additional resource to
the I/O clocks and is used to clock DQ input registers with the DQS
signal.
The Arria GX device has two phase-shifting reference circuits, one on the
top and one on the bottom of the device. The circuit on the top controls
the compensated delay elements for all DQS pins on the top. The circuit
on the bottom controls the compensated delay elements for all DQS pins
on the bottom.
Each phase-shifting reference circuit is driven by a system reference clock,
which must have the same frequency as the DQS signal. Clock pins
CLK[15..12]p feed phase circuitry on the top of the device and clock
pins CLK[7..4]p feed phase circuitry on the bottom of the device. In
addition, PLL clock outputs can also feed the phase-shifting reference
circuits. Figure 2–77 shows the phase-shift reference circuit control of
each DQS delay shift on the top of the device. This same circuit is
duplicated on the bottom of the device.
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May 2008
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I/O Structure
Figure 2–77. DQS Phase-Shift Circuitry Notes (1), (2)
From PLL 5 (4)
DQS
Pin
DQS
Pin
Δt
Δt
to IOE
to IOE
CLK[15..12]p (3)
DQS
Pin
DQS
Pin
Δt
Δt
to IOE
to IOE
DQS
Phase-Shift
Circuitry
Notes to Figure 2–77:
(1)
(2)
(3)
(4)
There are up to 18 pairs of DQS pins available on the top or bottom of the Arria GX device. There are up to 10 pairs
on the right side and 8 pairs on the left side of the DQS phase-shift circuitry.
The “t” module represents the DQS logic block.
Clock pins CLK[15..12]p feed phase-shift circuitry on the top of the device and clock pins CLK[7..4]p feed the
phase circuitry on the bottom of the device. You can also use a PLL clock output as a reference clock to phase shift
circuitry.
You can only use PLL 5 to feed the DQS phase-shift circuitry on the top of the device and PLL 6 to feed the DQS
phase-shift circuitry on the bottom of the device.
These dedicated circuits combined with enhanced PLL clocking and
phase-shift ability provide a complete hardware solution for interfacing
to high-speed memory.
f
For more information about external memory interfaces, refer to the
External Memory Interfaces in Arria GX Devices chapter in volume 2 of the
Arria GX Device Handbook.
Programmable Drive Strength
The output buffer for each Arria GX device I/O pin has a programmable
drive strength control for certain I/O standards. The LVTTL, LVCMOS,
SSTL, and HSTL standards have several levels of drive strength that the
you can control. The default setting used in the Quartus II software is the
maximum current strength setting that is used to achieve maximum I/O
performance. For all I/O standards, the minimum setting is the lowest
drive strength that guarantees the IOH/IOL of the standard. Using
minimum settings provides signal slew rate control to reduce system
noise and signal overshoot.
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Arria GX Architecture
Table 2–24 shows the possible settings for I/O standards with drive
strength control.
Table 2–24. Programmable Drive Strength Note (1)
IOH / IOL Current Strength
Setting (mA) for Column
I/O Pins
IOH / IOL Current Strength
Setting (mA) for Row I/O
Pins
3.3-V LVTTL
24, 20, 16, 12, 8, 4
12, 8, 4
3.3-V LVCMOS
I/O Standard
24, 20, 16, 12, 8, 4
8, 4
2.5-V LVTTL/LVCMOS
16, 12, 8, 4
12, 8, 4
1.8-V LVTTL/LVCMOS
12, 10, 8, 6, 4, 2
8, 6, 4, 2
8, 6, 4, 2
4, 2
SSTL-2 Class I
12, 8
12, 8
SSTL-2 Class II
24, 20, 16
16
SSTL-18 Class I
12, 10, 8, 6, 4
10, 8, 6, 4
SSTL-18 Class II
20, 18, 16, 8
—
HSTL-18 Class I
12, 10, 8, 6, 4
12, 10, 8, 6, 4
HSTL-18 Class II
20, 18, 16
—
HSTL-15 Class I
12, 10, 8, 6, 4
8, 6, 4
HSTL-15 Class II
20, 18, 16
—
1.5-V LVCMOS
Note to Table 2–24:
(1)
The Quartus II software default current setting is the maximum setting for each
I/O standard.
Open-Drain Output
Arria GX devices provide an optional open-drain (equivalent to an open
collector) output for each I/O pin. This open-drain output enables the
device to provide system-level control signals (for example, interrupt and
write enable signals) that can be asserted by any of several devices.
Bus Hold
Each Arria GX device I/O pin provides an optional bus-hold feature.
Bus-hold circuitry can hold the signal on an I/O pin at its last-driven
state. Since the bus-hold feature holds the last-driven state of the pin until
the next input signal is present, an external pull-up or pull-down resistor
is not needed to hold a signal level when the bus is tri-stated.
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May 2008
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I/O Structure
Bus-hold circuitry also pulls undriven pins away from the input
threshold voltage where noise can cause unintended high-frequency
switching. You can select this feature individually for each I/O pin. The
bus-hold output drives no higher than VCCIO to prevent overdriving
signals. If the bus-hold feature is enabled, the programmable pull-up
option cannot be used. Disable the bus-hold feature when the I/O pin has
been configured for differential signals.
Bus-hold circuitry uses a resistor with a nominal resistance (RBH) of
approximately 7 kΩ to pull the signal level to the last-driven state. This
information is provided for each VCCIO voltage level. Bus-hold circuitry is
active only after configuration. When going into user mode, the bus-hold
circuit captures the value on the pin present at the end of configuration.
f
For the specific sustaining current driven through this resistor and
overdrive current used to identify the next-driven input level, refer to
the DC & Switching Characteristics chapter in volume 1 of the Arria GX
Device Handbook.
Programmable Pull-Up Resistor
Each Arria GX device I/O pin provides an optional programmable
pull-up resistor during user mode. If you enable this feature for an I/O
pin, the pull-up resistor (typically 25 kΩ) holds the output to the VCCIO
level of the output pin’s bank.
Advanced I/O Standard Support
Arria GX device IOEs support the following I/O standards:
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
3.3-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
3.3-V PCI
3.3-V PCI-X mode 1
LVDS
LVPECL (on input and output clocks only)
Differential 1.5-V HSTL class I and II
Differential 1.8-V HSTL class I and II
Differential SSTL-18 class I and II
Differential SSTL-2 class I and II
1.2-V HSTL class I and II
1.5-V HSTL class I and II
1.8-V HSTL class I and II
SSTL-2 class I and II
SSTL-18 class I and II
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Arria GX Architecture
Table 2–25 describes the I/O standards supported by Arria GX devices.
Table 2–25. Arria GX Devices Supported I/O Standards
I/O Standard
Type
Input Reference
Output Supply
Board Termination
Voltage (VREF) (V) Voltage (VCCIO) (V) Voltage (VTT) (V)
LVTTL
Single-ended
-
3.3
-
LVCMOS
Single-ended
-
3.3
-
2.5 V
Single-ended
-
2.5
-
1.8 V
Single-ended
-
1.8
-
1.5-V LVCMOS
Single-ended
-
1.5
-
3.3-V PCI
Single-ended
-
3.3
-
3.3-V PCI-X mode 1
Single-ended
-
3.3
-
LVDS
Differential
-
2.5 (3)
-
LVPECL (1)
Differential
-
3.3
-
HyperTransport technology Differential
-
2.5 (3)
-
Differential 1.5-V HSTL
class I and II (2)
Differential
0.75
1.5
0.75
Differential 1.8-V HSTL
class I and II (2)
Differential
0.90
1.8
0.90
Differential SSTL-18 class I Differential
and II (2)
0.90
1.8
0.90
Differential SSTL-2 class I
and II (2)
1.25
2.5
1.25
Differential
1.2-V HSTL(4)
Voltage-referenced
0.6
1.2
0.6
1.5-V HSTL class I and II
Voltage-referenced
0.75
1.5
0.75
1.8-V HSTL class I and II
Voltage-referenced
0.9
1.8
0.9
SSTL-18 class I and II
Voltage-referenced
0.90
1.8
0.90
SSTL-2 class I and II
Voltage-referenced
1.25
2.5
1.25
Notes to Table 2–25:
(1)
(2)
(3)
(4)
This I/O standard is only available on input and output column clock pins.
This I/O standard is only available on input clock pins and DQS pins in I/O banks 3, 4, 7, and 8, and output clock
pins in I/O banks 9, 10, 11, and 12.
VCCIO is 3.3 V when using this I/O standard in input and output column clock pins (in I/O banks 3, 4, 7, 8, 9, 10,
11, and 12).
1.2-V HSTL is only supported in I/O banks 4, 7, and 8.
f
Altera Corporation
May 2008
For more information about the I/O standards supported by Arria GX
I/O banks, refer to the Selectable I/O Standards in Arria GX Devices chapter
in volume 2 of the Arria GX Device Handbook.
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I/O Structure
Arria GX devices contain six I/O banks and four enhanced PLL external
clock output banks, as shown in Figure 2–78. The two I/O banks on the
left of the device contain circuitry to support source-synchronous,
high-speed differential I/O for LVDS inputs and outputs. These banks
support all Arria GX I/O standards except PCI or PCI-X I/O pins, and
SSTL-18 class II and HSTL outputs. The top and bottom I/O banks
support all single-ended I/O standards. Additionally, enhanced PLL
external clock output banks allow clock output capabilities such as
differential support for SSTL and HSTL.
Figure 2–78. Arria GX I/O Banks Notes (1), (2)
DQS ×8
PLL7
DQS ×8
DQS ×8
DQS ×8
VREF0B3 VREF1B3 VREF2B3 VREF3B3 VREF4B3
Bank 2
VREF0B2 VREF1B2
VREF2B2
VREF3B2 VREF4B2
Bank 3
Bank 11
VREF3B1 VREF4B1
Bank 1
VREF2B1
DQS ×8
DQS ×8
DQS ×8
DQS ×8
DQS ×8
VREF0B4 VREF1B4 VREF2B4 VREF3B4 VREF4B4
Bank 4
Bank 9
This I/O bank supports LVDS
and LVPECL standards for input clock
operation. Differential HSTL and
differential SSTL standards are
supported for both input and output
operations. (3)
I/O banks 1 & 2 support LVTTL, LVCMOS,
2.5 V, 1.8 V, 1.5 V, SSTL-2, SSTL-18 class I,
LVDS, pseudo-differential SSTL-2 and pseudo-differential
SSTL-18 class I standards for both input and output
operations. HSTL, SSTL-18 class II,
pseudo-differential HSTL and pseudo-differential
SSTL-18 class II standards are only supported for
input operations. (4)
PLL2
VREF0B1 VREF1B1
PLL5
This I/O bank supports LVDS
and LVPECL standards
for input clock operations. Differential HSTL
and differential SSTL standards
are supported for both input
and output operations. (3)
I/O Banks 3, 4, 9, and 11 support all single-ended
I/O standards for both input and output operations.
All differential I/O standards are supported for both
input and output operations at I/O banks 9 and 11.
PLL1
VREF4B8 VREF3B8 VREF2B8 VREF1B8 VREF0B8
DQS ×8
DQS ×8
DQS ×8
DQS ×8
Bank 12
Bank 10
PLL12
PLL6
Transmitter: Bank 13
Receiver: Bank 13
REFCLK: Bank 13
Transmitter: Bank 14
Receiver: Bank 14
REFCLK: Bank 14
I/O banks 7, 8, 10 and 12 support all single-ended I/O
standards for both input and output operations. All differential
I/O standards are supported for both input and output operations
at I/O banks 10 and 12.
This I/O bank supports LVDS
This I/O bank supports LVDS
and LVPECL standards for input clock operation.
and LVPECL standards for input clock
Differential HSTL and differential
operation. Differential HSTL and differential
SSTL standards are supported
SSTL standards are supported
for both input and output operations. (3)
for both input and output operations. (3)
Bank 8
PLL8
PLL11
Transmitter: Bank 15
Receiver: Bank 15
REFCLK: Bank 15
Bank 7
VREF4B7 VREF3B7 VREF2B7 VREF1B7 VREF0B7
DQS ×8
DQS ×8
DQS ×8
DQS ×8
DQS ×8
Notes to Figure 2–78:
(1)
(2)
(3)
(4)
Figure 2–78 is a top view of the silicon die that corresponds to a reverse view for flip chip packages. It is a graphical
representation only.
Depending on the size of the device, different device members have different numbers of VREF groups. Refer to the
pin list and the Quartus II software for exact locations.
Banks 9 through 12 are enhanced PLL external clock output banks.
Horizontal I/O banks feature SERDES and DPA circuitry for high-speed differential I/O standards. For more
information about differential I/O standards, refer to the High-Speed Differential I/O Interfaces in Arria GX Devices
chapter in volume 2 of the Arria GX Device Handbook.
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Arria GX Architecture
Each I/O bank has its own VCCIO pins. A single device can support
1.5-, 1.8-, 2.5-, and 3.3-V interfaces; each bank can support a different
VCCIO level independently. Each bank also has dedicated VREF pins to
support the voltage-referenced standards (such as SSTL-2).
Each I/O bank can support multiple standards with the same VCCIO for
input and output pins. Each bank can support one VREF voltage level. For
example, when VCCIO is 3.3 V, a bank can support LVTTL, LVCMOS, and
3.3-V PCI for inputs and outputs.
On-Chip Termination
Arria GX devices provide differential (for the LVDS technology I/O
standard) and series on-chip termination to reduce reflections and
maintain signal integrity. There is no calibration support for these on-chip
termination resistors. On-chip termination simplifies board design by
minimizing the number of external termination resistors required.
Termination can be placed inside the package, eliminating small stubs
that can still lead to reflections.
Arria GX devices provide two types of termination:
■
■
Altera Corporation
May 2008
Differential termination (RD)
Series termination (RS)
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I/O Structure
Table 2–26 shows the Arria GX on-chip termination support per I/O
bank.
Table 2–26. On-Chip Termination Support by I/O Banks
On-Chip Termination Support
Series termination
Differential termination (1)
Top and Bottom Banks
(3, 4, 7, 8)
Left Bank (1, 2)
3.3-V LVTTL
v
v
3.3-V LVCMOS
v
v
2.5-V LVTTL
v
v
2.5-V LVCMOS
v
v
1.8-V LVTTL
v
v
1.8-V LVCMOS
v
v
1.5-V LVTTL
v
v
1.5-V LVCMOS
v
v
SSTL-2 class I and II
v
v
SSTL-18 class I
v
v
SSTL-18 class II
v
1.8-V HSTL class I
v
1.8-V HSTL class II
v
1.5-V HSTL class I
v
1.2-V HSTL
v
I/O Standard Support
v
v
LVDS
v
HyperTransport technology
v
Note to Table 2–26:
(1)
Clock pins CLK1 and CLK3, and pins FPLL[7..8]CLK do not support differential on-chip termination. Clock pins
CLK0 and CLK2, do support differential on-chip termination. Clock pins in the top and bottom banks (CLK[4..7,
12..15]) do not support differential on-chip termination.
Differential On-Chip Termination
Arria GX devices support internal differential termination with a nominal
resistance value of 100 Ω for LVDS input receiver buffers. LVPECL input
signals (supported on clock pins only) require an external termination
resistor. Differential on-chip termination is supported across the full
range of supported differential data rates as shown in the High-Speed I/O
Specifications section of the DC & Switching Characteristics chapter in
volume 1 of the Arria GX Device Handbook.
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Arria GX Architecture
f
For more information about differential on-chip termination, refer to the
High-Speed Differential I/O Interfaces with DPA in Arria GX Devices chapter
in volume 2 of the Arria GX Device Handbook.
For more information about tolerance specifications for differential
on-chip termination, refer to the DC & Switching Characteristics chapter in
volume 1 of the Arria GX Device Handbook.
On-Chip Series Termination
Arria GX devices support driver impedance matching to provide the I/O
driver with controlled output impedance that closely matches the
impedance of the transmission line. As a result, reflections can be
significantly reduced. Arria GX devices support on-chip series
termination for single-ended I/O standards with typical RS values of 25
and 50 Ω . Once matching impedance is selected, current drive strength is
no longer selectable. Table 2–26 shows the list of output standards that
support on-chip series termination.
f
For more information about series on-chip termination supported by
Arria GX devices, refer to the Selectable I/O Standards in Arria GX Devices
chapter in volume 2 of the Arria GX Device Handbook.
f
For more information about tolerance specifications for on-chip
termination without calibration, refer to the DC & Switching
Characteristics chapter in volume 1 of the Arria GX Device Handbook.
MultiVolt I/O Interface
The Arria GX architecture supports the MultiVolt I/O interface feature
that allows Arria GX devices in all packages to interface with systems of
different supply voltages. Arria GX VCCINT pins must always be
connected to a 1.2-V power supply. With a 1.2-V VCCINT level, input pins
are 1.2-, 1.5-, 1.8-, 2.5-, and 3.3-V tolerant. The VCCIO pins can be
connected to either a 1.2-, 1.5-, 1.8-, 2.5-, or 3.3-V power supply,
depending on the output requirements. The output levels are compatible
with systems of the same voltage as the power supply (for example, when
VCCIO pins are connected to a 1.5-V power supply, the output levels are
compatible with 1.5-V systems). Arria GX VCCPD power pins must be
connected to a 3.3-V power supply. These power pins are used to supply
the pre-driver power to the output buffers, which increases the
performance of the output pins. The VCCPD pins also power
configuration input pins and JTAG input pins.
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May 2008
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I/O Structure
Table 2–27 summarizes Arria GX MultiVolt I/O support.
Table 2–27. Arria GX MultiVolt I/O Support Note (1)
Input Signal (V)
VCCIO (V)
1.2
Output Signal (V)
1.2
1.5
1.8
2.5
3.3
1.2
(4)
v (2)
v (2)
v (2)
v (2)
v (4)
1.5
1.8
2.5
1.5
(4)
v
v
v (2)
v (2)
v (3)
1.8
(4)
v
v
v (2)
v (2)
v (3) v (3)
2.5
(4)
v
v
v (3) v (3) v (3)
v
3.3
(4)
v
v
v (3) v (3) v (3)
v (3)
3.3 5.0
v
v
v
v
Notes to Table 2–27:
(1)
(2)
(3)
(4)
To drive inputs higher than VCCIO but less than 4.0 V, disable the PCI clamping diode and select
the Allow LVTTL and LVCMOS input levels to overdrive input buffer option in the Quartus II
software.
The pin current may be slightly higher than the default value. You must verify that the driving
device’s VO L maximum and VO H minimum voltages do not violate the applicable Arria GX VI L
maximum and VI H minimum voltage specifications.
Although VCCIO specifies the voltage necessary for the Arria GX device to drive out, a receiving
device powered at a different level can still interface with the Arria GX device if it has inputs that
tolerate the VCCIO value.
Arria GX devices support 1.2-V HSTL. They do not support 1.2-V LVTTL and 1.2-V LVCMOS.
The TDO and nCEO pins are powered by VCCIO of the bank that they reside.
TDO is in I/O bank 4 and nCEO is in I/O Bank 7. Ideally, the VCC supplies
for the I/O buffers of any two connected pins are at the same voltage
level. This may not always be possible depending on the VCCIO level of
TDO and nCEO pins on master devices and the configuration voltage level
chosen by VCCSEL on slave devices. Master and slave devices can be in any
position in the chain. Master indicates that it is driving out TDO or nCEO
to a slave device. For multi-device passive configuration schemes, the
nCEO pin of the master device will be driving the nCE pin of the slave
device. The VCCSEL pin on the slave device selects which input buffer is
used for nCE. When VCCSEL is logic high, it selects the 1.8-V/1.5-V buffer
powered by VCCIO. When VCCSEL is logic low it selects the 3.3-V/2.5-V
input buffer powered by VCCPD. The ideal case is to have the VCCIO of the
nCEO bank in a master device match the VCCSEL settings for the nCE input
buffer of the slave device it is connected to, but that may not be possible
depending on the application.
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Altera Corporation
May 2008
Arria GX Architecture
Table 2–28 contains board design recommendations to ensure that nCEO
can successfully drive nCE for all power supply combinations.
Table 2–28. Board Design Recommendations for nCEO and nCE Input Buffer Power
nCE Input Buffer Power in
I/O Bank 3
Arria GX nCEO VCCIO Voltage Level in I/O Bank 7
VC C I O = 3.3 V VC C I O = 2.5 V
VC C I O = 1.8 V VC C I O = 1.5 V VC C I O = 1.2 V
VCCSEL high
(VC C I O Bank 3 = 1.5 V)
v(1), (2)
v (3), (4)
v (5)
v
v
VCCSEL high
(VC C I O Bank 3 = 1.8 V)
v (1), (2)
v (3), (4)
v
v
Level shifter
required
v
v (4)
v (6)
Level shifter
required
Level shifter
required
VCCSEL low (nCE powered
by VC C P D = 3.3 V)
Notes to Table 2–28:
(1)
(2)
(3)
(4)
(5)
(6)
Input buffer is 3.3-V tolerant.
The nCEO output buffer meets VO H (MIN) = 2.4 V.
Input buffer is 2.5-V tolerant.
The nCEO output buffer meets VOH (MIN) = 2.0 V.
Input buffer is 1.8-V tolerant.
An external 250-Ω pull-up resistor is not required, but recommended if signal levels on the
board are not optimal.
For JTAG chains, the TDO pin of the first device will be driving the TDI
pin of the second device in the chain. The VCCSEL input on JTAG input I/O
cells (TCK, TMS, TDI, and TRST) is internally hardwired to GND selecting
the 3.3-V/2.5-V input buffer powered by VCCPD. The ideal case is to have
the VCCIO of the TDO bank from the first device to match the VCCSEL
settings for TDI on the second device, but that may not be possible
depending on the application. Table 2–29 contains board design
recommendations to ensure proper JTAG chain operation.
Table 2–29. Supported TDO/TDI Voltage Combinations (Part 1 of 2)
Device
Arria GX
TDI Input
Buffer Power
Always
VC C P D (3.3 V)
Altera Corporation
May 2008
Arria GX TDO VC C I O Voltage Level in I/O Bank 4
VC C I O = 3.3 V
VC C I O = 2.5 V
v (1)
v (2)
VC C I O = 1.8 V VC C I O = 1.5 V VC C I O = 1.2 V
v (3)
Level shifter
required
Level shifter
required
2–123
Arria GX Device Handbook, Volume 1
High-Speed Differential I/O with DPA Support
Table 2–29. Supported TDO/TDI Voltage Combinations (Part 2 of 2)
Device
NonArria GX
TDI Input
Buffer Power
Arria GX TDO VC C I O Voltage Level in I/O Bank 4
VC C I O = 3.3 V
VC C I O = 2.5 V
VC C I O = 1.8 V VC C I O = 1.5 V VC C I O = 1.2 V
VCC = 3.3 V
v (1)
v (2)
v (3)
Level shifter
required
Level shifter
required
VCC = 2.5 V
v (1), (4)
v (2)
v (3)
Level shifter
required
Level shifter
required
VCC = 1.8 V
v (1), (4)
v (2), (5)
v
Level shifter
required
Level shifter
required
VCC = 1.5 V
v (1), (4)
v (2), (5)
v (6)
v
v
Notes to Table 2–29:
(1)
(2)
(3)
(4)
(5)
(6)
The TDO output buffer meets VOH (MIN) = 2.4 V.
The TDO output buffer meets VOH (MIN) = 2.0 V.
An external 250-Ω pull-up resistor is not required, but recommended if signal levels on the board
are not optimal.
Input buffer must be 3.3-V tolerant.
Input buffer must be 2.5-V tolerant.
Input buffer must be 1.8-V tolerant.
High-Speed
Differential I/O
with DPA
Support
Arria GX devices contain dedicated circuitry for supporting differential
standards at speeds up to 840 Mbps. LVDS differential I/O standards are
supported in the Arria GX device. In addition, the LVPECL I/O standard
is supported on input and output clock pins on the top and bottom I/O
banks.
The high-speed differential I/O circuitry supports the following
high-speed I/O interconnect standards and applications:
■
■
■
SPI-4 Phase 2 (POS-PHY Level 4)
SFI-4
Parallel RapidIO standard
There are two dedicated high-speed PLLs (PLL1 and PLL2) in the
EP1AGX20 and EP1AGX35 devices and up to four dedicated high-speed
PLLs (PLL1, PLL2, PLL7, and PLL8) in the EP1AGX50, EP1AGX60, and
EP1AGX90 devices to multiply reference clocks and drive high-speed
differential SERDES channels in I/O banks 1 and 2.
Tables 2–30 through 2–34 show the number of channels that each fast PLL
can clock in each of the Arria GX devices. In Tables 2–30 through 2–34 the
first row for each transmitter or receiver provides the maximum number
of channels that each fast PLL can drive in its adjacent I/O bank (I/O
Bank 1 or I/O Bank 2). The second row shows the maximum number of
2–124
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Altera Corporation
May 2008
Arria GX Architecture
channels that each fast PLL can drive in both I/O banks (I/O Bank 1 and
I/O Bank 2). For example, in the 780-pin FineLine BGA EP1AGX20
device, PLL 1 can drive a maximum of 16 transmitter channels in I/O
Bank 2 or a maximum of 29 transmitter channels in I/O Banks 1 and 2.
The Quartus II software can also merge receiver and transmitter PLLs
when a receiver is driving a transmitter. In this case, one fast PLL can
drive both the maximum numbers of receiver and transmitter channels.
1
For more details, refer to the Differential Pin Placement
Guidelines section in the High-Speed Differential I/O Interfaces
with DPA in Arria GX Devices chapter in volume 2 of the Arria GX
Device Handbook.
Table 2–30. EP1AGX20 Device Differential Channels Note (1)
Center Fast PLLs
Package
484-pin FineLine BGA
780-pin FineLine GBA
Transmitter/Receiver
Total Channels
Transmitter
29
Receiver
31
Transmitter
29
Receiver
31
PLL1
PLL2
16
13
13
16
17
14
14
17
16
13
13
16
17
14
14
17
Note to Table 2–30:
(1)
The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used
as data channels.
Table 2–31. EP1AGX35 Device Differential Channels Note (1)
Center Fast PLLs
Package
484-pin FineLine BGA
Altera Corporation
May 2008
Transmitter/Receiver
Total Channels
PLL1
PLL2
13
Transmitter
29
16
13
16
Receiver
31
17
14
14
17
2–125
Arria GX Device Handbook, Volume 1
High-Speed Differential I/O with DPA Support
Table 2–31. EP1AGX35 Device Differential Channels Note (1)
Center Fast PLLs
Package
Transmitter/Receiver
Total Channels
Transmitter
780-pin FineLine BGA
29
Receiver
31
PLL1
PLL2
16
13
13
16
17
14
14
17
Note to Table 2–31:
(1)
The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used
as data channels.
Table 2–32. EP1AGX50 Device Differential Channels Note (1)
Package
Transmitter/Receiver
Transmitter
484-pin FineLine BGA
Receiver
Transmitter
780-pin FineLine BGA
Receiver
Transmitter
1,152-pin FineLine BGA
Receiver
Total
Channels
Center Fast PLLs
Corner Fast PLLs
PLL1
PLL2
PLL7
PLL8
29
16
13
—
—
13
16
—
—
31
29
31
42
42
17
14
—
—
14
17
—
—
16
13
—
—
13
16
—
—
17
14
—
—
14
17
—
—
21
21
21
21
21
21
—
—
21
21
21
21
21
21
—
—
Note to Table 2–32:
(1)
The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used
as data channels.
2–126
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
Arria GX Architecture
Table 2–33. EP1AGX60 Device Differential Channels Note (1)
Package
Transmitter/Receiver
Transmitter
484-pin FineLine BGA
Receiver
Transmitter
780-pin FineLine BGA
Receiver
Transmitter
1,152-pin FineLine
BGA
Receiver
Total
Channels
Center Fast PLLs
Corner Fast PLLs
PLL1
PLL2
PLL7
PLL8
16
13
—
—
13
16
—
—
17
14
—
—
14
17
—
—
29
31
29
31
42
42
16
13
—
—
13
16
—
—
17
14
—
—
14
17
—
—
21
21
21
21
21
21
—
—
21
21
21
21
21
21
—
—
Note to Table 2–33:
(1)
The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used
as data channels.
Table 2–34. EP1AGX90 Device Differential Channels Note (1)
Package
Transmitter/Receiver
Transmitter
1,152-pin FineLine
BGA
Receiver
Total
Channels
45
47
Center Fast PLLs
Corner Fast PLLs
PLL1
PLL2
PLL7
PLL8
23
22
23
22
22
23
—
—
23
24
23
24
24
23
—
—
Note to Table 2–34:
(1)
The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used
as data channels.
Dedicated Circuitry with DPA Support
Arria GX devices support source-synchronous interfacing with LVDS
signaling at up to 840 Mbps. Arria GX devices can transmit or receive
serial channels along with a low-speed or high-speed clock.
Altera Corporation
May 2008
2–127
Arria GX Device Handbook, Volume 1
High-Speed Differential I/O with DPA Support
The receiving device PLL multiplies the clock by an integer factor W = 1
through 32. The SERDES factor J determines the parallel data width to
deserialize from receivers or to serialize for transmitters. The SERDES
factor J can be set to 4, 5, 6, 7, 8, 9, or 10 and does not have to equal the PLL
clock-multiplication W value. A design using the dynamic phase aligner
also supports all of these J factor values. For a J factor of 1, the Arria GX
device bypasses the SERDES block. For a J factor of 2, the Arria GX device
bypasses the SERDES block, and the DDR input and output registers are
used in the IOE. Figure 2–79 shows the block diagram of the Arria GX
transmitter channel.
Figure 2–79. Arria GX Transmitter Channel
Data from R4, R24, C4, or
direct link interconnect
+
–
10
Local
Interconnect
Up to 840 Mbps
10
Dedicated
Transmitter
Interface
diffioclk
refclk
Fast
PLL
load_en
Regional or
global clock
Each Arria GX receiver channel features a DPA block for phase detection
and selection, a SERDES, a synchronizer, and a data realigner circuit. You
can bypass the dynamic phase aligner without affecting the basic
source-synchronous operation of the channel. In addition, you can
dynamically switch between using the DPA block or bypassing the block
via a control signal from the logic array.
2–128
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Altera Corporation
May 2008
Arria GX Architecture
Figure 2–80 shows the block diagram of the Arria GX receiver channel.
Figure 2–80. GX Receiver Channel
Data to R4, R24, C4, or
direct link interconnect
Up to 840 Mbps
+
–
D
Q
Data Realignment
Circuitry
10
data
retimed_data
DPA
Synchronizer
Dedicated
Receiver
Interface
DPA_clk
Eight Phase Clocks
8
diffioclk
refclk
Fast
PLL
load_en
Regional or
global clock
An external pin or global or regional clock can drive the fast PLLs, which
can output up to three clocks: two multiplied high-speed clocks to drive
the SERDES block and/or external pin, and a low-speed clock to drive the
logic array. In addition, eight phase-shifted clocks from the VCO can feed
to the DPA circuitry.
f
For more information about fast PLL, see the PLLs in Arria GX Devices
chapter in volume 2 of the Arria GX Device Handbook.
The eight phase-shifted clocks from the fast PLL feed to the DPA block.
The DPA block selects the closest phase to the center of the serial data eye
to sample the incoming data. This allows the source-synchronous
circuitry to capture incoming data correctly regardless of
channel-to-channel or clock-to-channel skew. The DPA block locks to a
phase closest to the serial data phase. The phase-aligned DPA clock is
used to write the data into the synchronizer.
The synchronizer sits between the DPA block and the data realignment
and SERDES circuitry. Since every channel utilizing the DPA block can
have a different phase selected to sample the data, the synchronizer is
needed to synchronize the data to the high-speed clock domain of the
data realignment and the SERDES circuitry.
Altera Corporation
May 2008
2–129
Arria GX Device Handbook, Volume 1
High-Speed Differential I/O with DPA Support
For high-speed source synchronous interfaces such as POS-PHY 4 and the
Parallel RapidIO standard, the source synchronous clock rate is not a
byte- or SERDES-rate multiple of the data rate. Byte alignment is
necessary for these protocols since the source synchronous clock does not
provide a byte or word boundary since the clock is one half the data rate,
not one eighth. The Arria GX device’s high-speed differential I/O
circuitry provides dedicated data realignment circuitry for
user-controlled byte boundary shifting. This simplifies designs while
saving ALM resources. You can use an ALM-based state machine to
signal the shift of receiver byte boundaries until a specified pattern is
detected to indicate byte alignment.
Fast PLL and Channel Layout
The receiver and transmitter channels are interleaved such that each I/O
bank on the left side of the device has one receiver channel and one
transmitter channel per LAB row. Figure 2–81 shows the fast PLL and
channel layout in the EP1AGX20C, EP1AGX35C/D, EP1AGX50C/D and
EP1AGX60C/D devices. Figure 2–82 shows the fast PLL and channel
layout in EP1AGX60E and EP1AGX90E devices.
Figure 2–81. Fast PLL and Channel Layout in the EP1AGX20C, EP1AGX35C/D, EP1AGX50C/D, EP1AGX60C/D
Devices Note (1)
4
LVDS
Clock
DPA
Clock
Quadrant
Quadrant
Quadrant
Quadrant
4
2
Fast
PLL 1
Fast
PLL 2
2
4
LVDS
Clock
DPA
Clock
Note to Figure 2–81:
(1)
See Table 2–30 for the number of channels each device supports.
2–130
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
Arria GX Architecture
Figure 2–82. Fast PLL and Channel Layout in the EP1AGX60E and EP1AGX90E Devices Note (1)
Fast
PLL 7
2
4
LVDS
Clock
DPA
Clock
Quadrant
Quadrant
DPA
Clock
Quadrant
Quadrant
4
2
Fast
PLL 1
Fast
PLL 2
2
4
LVDS
Clock
2
Fast
PLL 8
Note to Figure 2–82:
(1)
See Tables 2–30 through 2–34 for the number of channels each device supports.
Referenced
Documents
This chapter references the following documents:
■
■
■
■
■
■
■
Altera Corporation
May 2008
Arria GX Transceiver Architecture chapter in volume 2 of the Arria GX
Device Handbook
Arria GX Transceiver Protocol Support and Additional Features chapter
in volume 2 of the Arria GX Device Handbook
DC & Switching Characteristics chapter in volume 1 of the Arria GX
Device Handbook
DSP Blocks in Arria GX Devices chapter in volume 2 of the Arria GX
Device Handbook
External Memory Interfaces in Arria GX Devices chapter in volume 2 of
the Arria GX Device Handbook
High-Speed Differential I/O Interfaces with DPA in Arria GX Devices
chapter in volume 2 of the Arria GX Device Handbook
PLLs in Arria GX Devices chapter in volume 2 of the Arria GX Device
Handbook
2–131
Arria GX Device Handbook, Volume 1
Document Revision History
■
■
■
Document
Revision History
Selectable I/O Standards in Arria GX Devices chapter in volume 2 of the
Arria GX Device Handbook
Specifications and Additional Information chapter in volume 2 of the
Arria GX Device Handbook
TriMatrix Embedded Memory Blocks in Arria GX Devices chapter in
volume 2 of the Arria GX Device Handbook
Table 2–35 shows the revision history for this chapter.
Table 2–35. Document Revision History
Date and Document Version
Changes Made
Summary of Changes
May 2008, v1.3
Added “Reverse Serial Pre-CDR Loopback” and
“Calibration Block” sub-sections to “Transmitter
Path” section.
—
August 2007, v1.2
Added “Referenced Documents” section.
—
June 2007, v1.1
Added GIGE information.
—
May 2007 v1.0
Initial release.
—
2–132
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
3. Configuration and Testing
AGX51003-1.3
Introduction
All ArriaTM GX devices provide Joint Test Action Group (JTAG)
boundary-scan test (BST) circuitry that complies with the IEEE Std.
1149.1. You can perform JTAG boundary-scan testing either before or
after, but not during configuration. Arria GX devices can also use the
JTAG port for configuration with the Quartus® II software or hardware
using either jam files (.jam) or jam byte-code files (.jbc).
This chapter contains the following sections:
■
■
■
■
■
IEEE Std. 1149.1
JTAG BoundaryScan Support
“IEEE Std. 1149.1 JTAG Boundary-Scan Support” on page 3–1
“SignalTap II Embedded Logic Analyzer” on page 3–4
“Configuration” on page 3–4
“Temperature Sensing Diode” on page 3–10
“Automated Single Event Upset (SEU) Detection” on page 3–12
Arria GX devices support I/O element (IOE) standard setting
reconfiguration through the JTAG BST chain. The JTAG chain can update
the I/O standard for all input and output pins any time before or during
user-mode through the CONFIG_IO instruction. You can use this
capability for JTAG testing before configuration when some of the
Arria GX pins drive or receive from other devices on the board using
voltage-referenced standards. Because the Arria GX device may not be
configured before JTAG testing, the I/O pins may not be configured for
appropriate electrical standards for chip-to-chip communication.
Programming these I/O standards via JTAG allows you to fully test the
I/O connections to other devices.
A device operating in JTAG mode uses four required pins, TDI, TDO, TMS,
and TCK, and one optional pin, TRST. The TCK pin has an internal weak
pull-down resistor, while the TDI, TMS, and TRST pins have weak
internal pull-up resistors. The JTAG input pins are powered by the 3.3-V
VCCPD pins. The TDO output pin is powered by the VCCIO power supply in
I/O bank 4.
Arria GX devices also use the JTAG port to monitor the logic operation of
the device with the SignalTap® II embedded logic analyzer. Arria GX
devices support the JTAG instructions shown in Table 3–1.
Altera Corporation
May 2008
3–1
Configuration and Testing
1
Arria GX, Stratix®, Stratix II, Stratix GX, Stratix II GX,
Cyclone® II, and Cyclone devices must be within the first 17
devices in a JTAG chain. All of these devices have the same JTAG
controller. If any of the Stratix, Arria GX, Cyclone, and
Cyclone II devices are in the 18th or further position, they will
fail configuration. This does not affect the functionality of the
SignalTap II embedded logic analyzer.
Table 3–1. Arria GX JTAG Instructions (Part 1 of 2)
JTAG Instruction
Instruction Code
Description
SAMPLE/PRELOAD
00 0000 0101
Allows a snapshot of signals at the device pins to be captured
and examined during normal device operation and permits an
initial data pattern to be output at the device pins. Also used by
the SignalTap II embedded logic analyzer.
EXTEST (1)
00 0000 1111
Allows external circuitry and board-level interconnects to be
tested by forcing a test pattern at the output pins and capturing
test results at the input pins.
BYPASS
11 1111 1111
Places the 1-bit bypass register between the TDI and TDO
pins, which allows the BST data to pass synchronously
through selected devices to adjacent devices during normal
device operation.
USERCODE
00 0000 0111
Selects the 32-bit USERCODE register and places it between
the TDI and TDO pins, allowing the USERCODE to be serially
shifted out of TDO.
IDCODE
00 0000 0110
Selects the IDCODE register and places it between TDI and
TDO, allowing IDCODE to be serially shifted out of TDO.
HIGHZ (1)
00 0000 1011
Places the 1-bit bypass register between the TDI and TDO
pins, which allows the BST data to pass synchronously
through selected devices to adjacent devices during normal
device operation, while tri-stating all of the I/O pins.
CLAMP (1)
00 0000 1010
Places the 1-bit bypass register between the TDI and TDO
pins, which allows the BST data to pass synchronously
through selected devices to adjacent devices during normal
device operation while holding I/O pins to a state defined by
the data in the boundary-scan register.
ICR instructions
PULSE_NCONFIG
—
00 0000 0001
3–2
Arria GX Device Handbook, Volume 1
Used when configuring an Arria GX device via the JTAG port
with a USB-Blaster™, MasterBlaster™, ByteBlasterMV™, or
ByteBlaster II download cable, or when using a .jam or .jbc via
an embedded processor or JRunnerTM.
Emulates pulsing the nCONFIG pin low to trigger
reconfiguration even though the physical pin is unaffected.
Altera Corporation
May 2008
IEEE Std. 1149.1 JTAG Boundary-Scan Support
Table 3–1. Arria GX JTAG Instructions (Part 2 of 2)
JTAG Instruction
CONFIG_IO (2)
Instruction Code
Description
00 0000 1101
Allows configuration of I/O standards through the JTAG chain
for JTAG testing. Can be executed before, during, or after
configuration. Stops configuration if executed during
configuration. Once issued, the CONFIG_IO instruction holds
nSTATUS low to reset the configuration device. nSTATUS is
held low until the IOE configuration register is loaded and the
TAP controller state machine transitions to the UPDATE_DR
state.
Notes to Table 3–1:
(1)
(2)
Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and
EXTEST.
For more information about using the CONFIG_IO instruction, refer to the MorphIO: An I/O Reconfiguration
Solution for Altera Devices White Paper.
The Arria GX device instruction register length is 10 bits and the
USERCODE register length is 32 bits. Tables 3–2 and 3–3 show the
boundary-scan register length and device IDCODE information for
Arria GX devices.
Table 3–2. Arria GX Boundary-Scan Register Length
Device
Boundary-Scan Register Length
EP1AGX20
1320
EP1AGX35
1320
EP1AGX50
1668
EP1AGX60
1668
EP1AGX90
2016
Table 3–3. 2-Bit Arria GX Device IDCODE (Part 1 of 2)
IDCODE (32 Bits)
Device
Version (4 Bits)
Part Number (16 Bits)
Manufacturer
Identity (11 Bits)
LSB (1 Bit)
EP1AGX20
0000
0010 0001 0010 0001
000 0110 1110
1
EP1AGX35
0000
0010 0001 0010 0001
000 0110 1110
1
EP1AGX50
0000
0010 0001 0010 0010
000 0110 1110
1
Altera Corporation
May 2008
3–3
Arria GX Device Handbook, Volume 1
Configuration and Testing
Table 3–3. 2-Bit Arria GX Device IDCODE (Part 2 of 2)
IDCODE (32 Bits)
Device
Version (4 Bits)
Part Number (16 Bits)
Manufacturer
Identity (11 Bits)
LSB (1 Bit)
EP1AGX60
0000
0010 0001 0010 0010
000 0110 1110
1
EP1AGX90
0000
0010 0001 0010 0011
000 0110 1110
1
SignalTap II
Embedded Logic
Analyzer
Arria GX devices feature the SignalTap II embedded logic analyzer,
which monitors design operation over a period of time through the IEEE
Std. 1149.1 (JTAG) circuitry. You can analyze internal logic at speed
without bringing internal signals to the I/O pins. This feature is
particularly important for advanced packages, such as FineLine BGA
(FBGA) packages, because it can be difficult to add a connection to a pin
during the debugging process after a board is designed and
manufactured.
Configuration
The logic, circuitry, and interconnects in the Arria GX architecture are
configured with CMOS SRAM elements. Altera® FPGAs are
reconfigurable and every device is tested with a high coverage
production test program so you do not have to perform fault testing and
can instead focus on simulation and design verification.
Arria GX devices are configured at system power up with data stored in
an Altera configuration device or provided by an external controller (for
example, a MAX® II device or microprocessor). You can configure
Arria GX devices using the fast passive parallel (FPP), active serial (AS),
passive serial (PS), passive parallel asynchronous (PPA), and JTAG
configuration schemes. Each Arria GX device has an optimized interface
that allows microprocessors to configure it serially or in parallel, and
synchronously or asynchronously. The interface also enables
microprocessors to treat Arria GX devices as memory and configure them
by writing to a virtual memory location, making reconfiguration easy.
In addition to the number of configuration methods supported, Arria GX
devices also offer decompression and remote system upgrade features.
The decompression feature allows Arria GX FPGAs to receive a
compressed configuration bitstream and decompress this data in
real-time, reducing storage requirements and configuration time. The
remote system upgrade feature allows real-time system upgrades from
remote locations of Arria GX designs. For more information, refer to
“Configuration Schemes” on page 3–6.
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May 2008
Configuration
Operating Modes
The Arria GX architecture uses SRAM configuration elements that
require configuration data to be loaded each time the circuit powers up.
The process of physically loading the SRAM data into the device is called
configuration. During initialization, which occurs immediately after
configuration, the device resets registers, enables I/O pins, and begins to
operate as a logic device. The I/O pins are tri-stated during power up,
and before and during configuration. Together, the configuration and
initialization processes are called command mode. Normal device
operation is called user mode.
SRAM configuration elements allows you to reconfigure Arria GX
devices in-circuit by loading new configuration data into the device. With
real-time reconfiguration, the device is forced into command mode with
a device pin. The configuration process loads different configuration
data, re-initializes the device, and resumes user-mode operation. You can
perform in-field upgrades by distributing new configuration files either
within the system or remotely.
PORSEL is a dedicated input pin used to select power-on reset (POR)
delay times of 12 ms or 100 ms during power up. When the PORSEL pin
is connected to ground, the POR time is 100 ms. When the PORSEL pin is
connected to VCC, the POR time is 12 ms.
The nIO_PULLUP pin is a dedicated input that chooses whether the
internal pull-up resistors on the user I/O pins and dual-purpose
configuration I/O pins (nCSO, ASDO, DATA[7..0], nWS, nRS, RDYnBSY,
nCS, CS, RUnLU, PGM[2..0], CLKUSR, INIT_DONE, DEV_OE, DEV_CLR)
are on or off before and during configuration. A logic high (1.5, 1.8, 2.5,
3.3 V) turns off the weak internal pull-up resistors, while a logic low turns
them on.
Arria GX devices also offer a new power supply, VCCPD, which must be
connected to 3.3 V in order to power the 3.3-V/2.5-V buffer available on
the configuration input pins and JTAG pins. VCCPD applies to all the JTAG
input pins (TCK, TMS, TDI, and TRST) and the following configuration
pins: nCONFIG, DCLK (when used as an input), nIO_PULLUP,
DATA[7..0], RUnLU, nCE, nWS, nRS, CS, nCS, and CLKUSR. The VCCSEL
pin allows the VCCIO setting (of the banks where the configuration inputs
reside) to be independent of the voltage required by the configuration
inputs. Therefore, when selecting the VCCIO voltage, you do not have to
take the VIL and VIH levels driven to the configuration inputs into
consideration. The configuration input pins, nCONFIG, DCLK (when used
as an input), nIO_PULLUP, RUnLU, nCE, nWS, nRS, CS, nCS, and CLKUSR,
have a dual buffer design: a 3.3-V/2.5-V input buffer and a 1.8-V/1.5-V
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May 2008
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Configuration and Testing
input buffer. The VCCSEL input pin selects which input buffer is used. The
3.3-V/2.5-V input buffer is powered by VCCPD, while the 1.8-V/1.5-V
input buffer is powered by VCCIO.
VCCSEL is sampled during power up. Therefore, the VCCSEL setting cannot
change on-the-fly or during a reconfiguration. The VCCSEL input buffer is
powered by VCCINT and must be hard-wired to VCCPD or ground. A logic
high VCCSEL connection selects the 1.8-V/1.5-V input buffer, and a logic
low selects the 3.3-V/2.5-V input buffer. VCCSEL should be set to comply
with the logic levels driven out of the configuration device or MAX II
microprocessor.
If the design must support configuration input voltages of 3.3 V/2.5 V, set
VCCSEL to a logic low. You can set the VCCIO voltage of the I/O bank that
contains the configuration inputs to any supported voltage. If the design
must support configuration input voltages of 1.8 V/1.5 V, set VCCSEL to a
logic high and the VCCIO of the bank that contains the configuration
inputs to 1.8 V/1.5 V.
f
For more information about multi-volt support, including information
about using TDO and nCEO in multi-volt systems, refer to the Arria GX
Architecture chapter in volume 1 of the Arria GX Device Handbook.
Configuration Schemes
You can load the configuration data for an Arria GX device with one of
five configuration schemes (refer to Table 3–4), chosen on the basis of the
target application. You can use a configuration device, intelligent
controller, or the JTAG port to configure an Arria GX device. A
configuration device can automatically configure an Arria GX device at
system power up.
You can configure multiple Arria GX devices in any of the five
configuration schemes by connecting the configuration enable (nCE) and
configuration enable output (nCEO) pins on each device. Arria GX FPGAs
offer the following:
■
■
Configuration data decompression to reduce configuration file
storage
Remote system upgrades for remotely updating Arria GX designs
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Altera Corporation
May 2008
Configuration
Table 3–4 summarizes which configuration features can be used in each
configuration scheme.
f
For more information about configuration schemes in Arria GX devices,
refer to the Configuring Arria GX Devices chapter in volume 2 of the
Arria GX Device Handbook.
Table 3–4. Arria GX Configuration Features
Configuration
Scheme
FPP
Decompression
Remote System
Upgrade
MAX II device or microprocessor and
flash device
v(1)
v
Enhanced configuration device
v(2)
v
Configuration Method
AS
Serial configuration device
v
v(3)
PS
MAX II device or microprocessor and
flash device
v
v
Enhanced configuration device
v
v
Download cable (4)
v
—
PPA
MAX II device or microprocessor and
flash device
—
v
JTAG
Download cable (4)
—
—
MAX II device or microprocessor and
flash device
—
—
Notes for Table 3–4:
(1)
(2)
(3)
(4)
In these modes, the host system must send a DCLK that is 4× the data rate.
The enhanced configuration device decompression feature is available, while the Arria GX decompression feature
is not available.
Only remote update mode is supported when using the AS configuration scheme. Local update mode is not
supported.
The supported download cables include the Altera USB-Blaster universal serial bus (USB) port download cable,
MasterBlaster serial/USB communications cable, ByteBlaster II parallel port download cable, and the
ByteBlasterMV parallel port download cable.
Device Configuration Data Decompression
Arria GX FPGAs support decompression of configuration data, which
saves configuration memory space and time. This feature allows you to
store compressed configuration data in configuration devices or other
memory and transmit this compressed bitstream to Arria GX FPGAs.
During configuration, the Arria GX FPGA decompresses the bitstream in
real time and programs its SRAM cells. Arria GX FPGAs support
decompression in the FPP (when using a MAX II device or
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May 2008
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Configuration and Testing
microprocessor and flash memory), AS, and PS configuration schemes.
Decompression is not supported in the PPA configuration scheme nor in
JTAG-based configuration.
Remote System Upgrades
Shortened design cycles, evolving standards, and system deployments in
remote locations are difficult challenges faced by system designers.
Arria GX devices can help effectively deal with these challenges with
their inherent re programmability and dedicated circuitry to perform
remote system updates. Remote system updates help deliver feature
enhancements and bug fixes without costly recalls, reduce time to
market, and extend product life.
Arria GX FPGAs feature dedicated remote system upgrade circuitry to
facilitate remote system updates. Soft logic (Nios® processor or user logic)
implemented in the Arria GX device can download a new configuration
image from a remote location, store it in configuration memory, and direct
the dedicated remote system upgrade circuitry to initiate a
reconfiguration cycle. The dedicated circuitry performs error detection
during and after the configuration process, recovers from any error
condition by reverting back to a safe configuration image, and provides
error status information. This dedicated remote system upgrade circuitry
avoids system downtime and is the critical component for successful
remote system upgrades.
Remote system configuration is supported in the following Arria GX
configuration schemes: FPP, AS, PS, and PPA. You can also implement
remote system configuration in conjunction with Arria GX features such
as real-time decompression of configuration data for efficient field
upgrades.
f
For more information about remote configuration in Arria GX devices,
refer to the Remote System Upgrades with Arria GX Devices chapter in
volume 2 of the Arria GX Device Handbook.
Configuring Arria GX FPGAs with JRunner
The JRunner software driver configures Altera FPGAs, including
Arria GX FPGAs, through the ByteBlaster II or ByteBlasterMV cables in
JTAG mode. The programming input file supported is in Raw Binary File
(.rbf) format. JRunner also requires a Chain Description File (.cdf)
generated by the Quartus II software. JRunner is targeted for embedded
JTAG configuration. The source code is developed for the Windows NT
operating system (OS), but can be customized to run on other platforms.
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May 2008
Configuration
f
For more information about the JRunner software driver, refer to the
AN414: JRunner Software Driver: An Embedded Solution for PLD JTAG
Configuration and the source files on the Altera web site
(www.altera.com).
Programming Serial Configuration Devices with SRunner
You can program a serial configuration device in-system by an external
microprocessor using SRunnerTM. SRunner is a software driver
developed for embedded serial configuration device programming that
can be easily customized to fit into different embedded systems. SRunner
reads a raw programming data file (.rpd) and writes to serial
configuration devices. The serial configuration device programming time
using SRunner is comparable to the programming time when using the
Quartus II software.
f
For more information about SRunner, refer to the AN418: SRunner: An
Embedded Solution for Serial Configuration Device Programming and the
source code on the Altera web site.
f
For more information about programming serial configuration devices,
refer to the Serial Configuration Devices (EPCS1, EPCS4, EPCS64, and
EPCS128) Data Sheet in the Configuration Handbook.
Configuring Arria GX FPGAs with the MicroBlaster Driver
The MicroBlaster™ software driver supports a raw binary file (RBF)
programming input file and is ideal for embedded FPP or PS
configuration. The source code is developed for the Windows NT
operating system, although it can be customized to run on other
operating systems.
f
For more information about the MicroBlaster software driver, refer to the
Configuring the MicroBlaster Fast Passive Parallel Software Driver White
Paper or the AN423: Configuring the MicroBlaster Passive Serial Software
Driver on the Altera web site.
PLL Reconfiguration
The phase-locked loops (PLLs) in the Arria GX device family support
reconfiguration of their multiply, divide, VCO-phase selection, and
bandwidth selection settings without reconfiguring the entire device. You
can use either serial data from the logic array or regular I/O pins to
program the PLL’s counter settings in a serial chain. This option provides
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May 2008
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Configuration and Testing
considerable flexibility for frequency synthesis, allowing real-time
variation of the PLL frequency and delay. The rest of the device is
functional while reconfiguring the PLL.
f
Temperature
Sensing Diode
For more information about Arria GX PLLs, refer to the PLLs in Arria GX
Devices chapter in volume 2 of the Arria GX Device Handbook.
Arria GX devices include a diode-connected transistor for use as a
temperature sensor in power management. This diode is used with an
external digital thermometer device such as a MAX1617A or MAX1619
from MAXIM Integrated Products. These devices steer bias current
through the Arria GX diode, measuring forward voltage and converting
this reading to temperature in the form of an eight-bit signed number
(seven bits plus one sign bit). The external device’s output represents the
junction temperature of the Arria GX device and can be used for
intelligent power management.
The diode requires two pins (tempdiodep and tempdioden) on the
Arria GX device to connect to the external temperature-sensing device, as
shown in Figure 3–1. The temperature sensing diode is a passive element
and therefore can be used before the Arria GX device is powered.
Figure 3–1. External Temperature-Sensing Diode
Arria GX Device
Temperature-Sensing
Device
tempdiodep
tempdioden
3–10
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
Temperature Sensing Diode
Table 3–5 shows the specifications for bias voltage and current of the
Arria GX temperature sensing diode.
Table 3–5. Temperature-Sensing Diode Electrical Characteristics
Parameter
IBIAS high
Minimum
Typical
Maximum
Unit
80
100
120
μA
8
10
12
μA
VBP - VBN
0.3
—
0.9
V
VBN
—
0.7
—
V
Series resistance
—
—
3
Ω
IBIAS low
The temperature-sensing diode works for the entire operating range, as
shown in Figure 3–2.
Figure 3–2. Temperature vs. Temperature-Sensing Diode Voltage
0.95
0.90
100 μA Bias Current
10 μA Bias Current
0.85
0.80
0.75
Voltage
(Across Diode)
0.70
0.65
0.60
0.55
0.50
0.45
0.40
–55
–30
–5
20
45
70
95
120
Temperature (˚C)
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May 2008
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Configuration and Testing
Automated
Single Event
Upset (SEU)
Detection
Arria GX devices offer on-chip circuitry for automated checking of single
event upset (SEU) detection. Some applications that require the device to
operate error free at high elevations or in close proximity to Earth’s North
or South Pole will require periodic checks to ensure continued data
integrity. The error detection cyclic redundancy check (CRC) feature
controlled by the Device and Pin Options dialog box in the Quartus II
software uses a 32-bit CRC circuit to ensure data reliability and is one of
the best options for mitigating SEU.
You can implement the error detection CRC feature with existing circuitry
in Arria GX devices, eliminating the need for external logic. Arria GX
devices compute CRC during configuration. The Arria GX device checks
the computed-CRC against an automatically computed CRC during
normal operation. The CRC_ERROR pin reports a soft error when
configuration SRAM data is corrupted, triggering device reconfiguration.
Custom-Built Circuitry
Dedicated circuitry is built into Arria GX devices to automatically
perform error detection. This circuitry constantly checks for errors in the
configuration SRAM cells while the device is in user mode. You can
monitor one external pin for the error and use it to trigger a
reconfiguration cycle. You can select the desired time between checks by
adjusting a built-in clock divider.
Software Interface
Beginning with version 7.1 of the Quartus II software, you can turn on the
automated error detection CRC feature in the Device and Pin Options
dialog box. This dialog box allows you to enable the feature and set the
internal frequency of the CRC between 400 kHz to 50 MHz. This controls
the rate that the CRC circuitry verifies the internal configuration SRAM
bits in the Arria GX FPGA.
f
Referenced
Documents
For more information about CRC, refer to AN 357: Error Detection Using
CRC in Altera FPGAs.
This chapter references the following documents:
■
■
■
■
AN 357: Error Detection Using CRC in Altera FPGAs
AN414: JRunner Software Driver: An Embedded Solution for PLD JTAG
Configuration
AN418: SRunner: An Embedded Solution for Serial Configuration Device
Programming
AN423: Configuring the MicroBlaster Passive Serial Software Driver
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May 2008
Document Revision History
■
Arria GX Architecture chapter in volume 1 of the Arria GX Device
Handbook
Configuring Arria GX Devices chapter in volume 2 of the Arria GX
Device Handbook
Configuring the MicroBlaster Fast Passive Parallel Software Driver White
Paper
MorphIO: An I/O Reconfiguration Solution for Altera Devices White
Paper
PLLs in Arria GX Devices chapter in volume 2 of the Arria GX Device
Handbook
Remote System Upgrades with Arria GX Devices chapter in volume 2 of
the Arria GX Device Handbook
Serial Configuration Devices (EPCS1, EPCS4, EPCS64, and EPCS128)
Data Sheet in the Configuration Handbook
■
■
■
■
■
■
Document
Revision History
Table 3–6 shows the revision history for this chapter.
Table 3–6. Document Revision History
Date and
Document
Version
Changes Made
Summary of Changes
May 2008
v1.3
Updated note in “Introduction” section.
—
Minor text edits.
—
August 2007
v1.2
Added the “Referenced Documents”
section.
—
June 2007
v1.1
Deleted Signal Tap II information from
Table 3–1.
—
May 2007
v1.0
Initial Release
—
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May 2008
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Configuration and Testing
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Altera Corporation
May 2008
4. DC and Switching
Characteristics
AGX51004-1.3
Operating
Conditions
Arria™ GX devices are offered in both commercial and industrial grades.
Both commercial and industrial devices are offered in -6 speed grade only.
This chapter contains the following sections:
■
■
■
■
■
■
■
■
■
■
■
■
“Operating Conditions” on page 4–1
“Power Consumption” on page 4–34
“I/O Timing Model” on page 4–34
“Typical Design Performance” on page 4–43
“Block Performance” on page 4–110
“IOE Programmable Delay” on page 4–113
“Maximum Input and Output Clock Toggle Rate” on page 4–114
“Duty Cycle Distortion” on page 4–125
“High-Speed I/O Specifications” on page 4–131
“PLL Timing Specifications” on page 4–133
“External Memory Interface Specifications” on page 4–135
“JTAG Timing Specifications” on page 4–137
Tables 4–1 through 4–42 provide information on absolute maximum
ratings, recommended operating conditions, DC electrical characteristics,
and other specifications for Arria GX devices.
Absolute Maximum Ratings
Table 4–1 contains the absolute maximum ratings for the Arria GX device
family.
Table 4–1. Arria GX Device Absolute Maximum Ratings
Symbol
Parameter
Notes (1), (2), (3)
Conditions
Minimum
Maximum
Unit
VCCINT
Supply voltage
With respect to ground
–0.5
1.8
V
VCCIO
Supply voltage
With respect to ground
–0.5
4.6
V
VCCPD
Supply voltage
With respect to ground
–0.5
4.6
V
VI
DC input voltage (4)
–0.5
4.6
V
IOUT
DC output current, per pin
–25
40
mA
TSTG
Storage temperature
–65
150
C
Altera Corporation
May 2008
No bias
4–1
Operating Conditions
Table 4–1. Arria GX Device Absolute Maximum Ratings
Symbol
TJ
Parameter
Notes (1), (2), (3)
Conditions
Junction temperature
Minimum
Maximum
Unit
–55
125
C
BGA packages under bias
Notes to Table 4–1:
(1)
(2)
(3)
(4)
See the operating requirements for Altera® devices in the Arria GX Device Family Data Sheet in volume 1 of the
Arria GX Device Handbook for more information.
Conditions beyond those listed in Table 4–1 may cause permanent damage to a device. Additionally, device
operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device.
Supply voltage specifications apply to voltage readings taken at the device pins, not at the power supply.
During transitions, the inputs may overshoot to the voltage shown in Table 4–2 based upon the input duty cycle.
The DC case is equivalent to 100% duty cycle. During transitions, the inputs may undershoot to –2.0 V for input
currents less than 100 mA and periods shorter than 20 ns.
Table 4–2. Maximum Duty Cycles in Voltage Transitions
Symbol
VI
Parameter
Maximum duty cycles
in voltage transitions
Note (1)
Condition
Maximum Duty Cycles
(%)
VI = 4.0 V
100
VI = 4.1 V
90
VI = 4.2 V
50
VI = 4.3 V
30
VI = 4.4 V
17
VI = 4.5 V
10
Note to Table 4–2:
(1)
During transition, the inputs may overshoot to the voltages shown based on the
input duty cycle. The DC case is equivalent to 100% duty cycle.
Recommended Operating Conditions
Table 4–3 contains the Arria GX device family recommended operating
conditions.
Table 4–3. Arria GX Device Recommended Operating Conditions (Part 1 of 2)
Symbol
VCCINT
Parameter
Supply voltage for internal logic
and input buffers
4–2
Arria GX Device Handbook, Volume 1
Conditions
Rise time ≤100 ms (3)
Note (1)
Minimum
Maximum
Unit
1.15
1.25
V
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–3. Arria GX Device Recommended Operating Conditions (Part 2 of 2)
Symbol
VCCIO
Parameter
Conditions
Note (1)
Minimum
Maximum
Unit
Supply voltage for output
buffers, 3.3-V operation
Rise time ≤100 ms (3), (6)
3.135
(3.00)
3.465
(3.60)
V
Supply voltage for output
buffers, 2.5-V operation
Rise time ≤100 ms (3)
2.375
2.625
V
Supply voltage for output
buffers, 1.8-V operation
Rise time ≤100 ms (3)
1.71
1.89
V
Supply voltage for output
buffers, 1.5-V operation
Rise time ≤100 ms (3)
1.425
1.575
V
Supply voltage for output
buffers, 1.2-V operation
Rise time ≤100 ms (3)
1.15
1.25
V
3.135
3.465
V
–0.5
4.0
V
0
VCCIO
V
0
85
C
–40
100
C
VCCPD
Supply voltage for pre-drivers as 100 μs ≤rise time ≤100 ms (4)
well as configuration and JTAG
I/O buffers.
VI
Input voltage (see Table 4–2)
VO
Output voltage
TJ
Operating junction temperature
(2), (5)
For commercial use
For industrial use
Notes to Table 4–3:
(1)
(2)
(3)
(4)
(5)
(6)
Supply voltage specifications apply to voltage readings taken at the device pins, not at the power supply.
During transitions, the inputs may overshoot to the voltage shown in Table 4–2 based upon the input duty cycle.
The DC case is equivalent to 100% duty cycle. During transitions, the inputs may undershoot to –2.0 V for input
currents less than 100 mA and periods shorter than 20 ns.
Maximum VCC rise time is 100 ms, and VCC must rise monotonically from ground to VCC.
VCCPD must ramp-up from 0 V to 3.3 V within 100 μs to 100 ms. If VCCPD is not ramped up within this specified
time, the Arria GX device will not configure successfully. If the system does not allow for a VCCPD ramp-up time of
100 ms or less, hold nCONFIG low until all power supplies are reliable.
All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before VCCINT, VCCPD, and VCCIO
are powered.
VCCIO maximum and minimum conditions for PCI and PCI-X are shown in parentheses.
Transceiver Block Characteristics
Tables 4–4 through 4–6 contain transceiver block specifications.
Table 4–4. Arria GX Transceiver Block Absolute Maximum Ratings (Part 1 of 2)
Symbol
Parameter
Conditions
Note (1)
Minimum Maximum
Units
VCCA
Transceiver block supply
voltage
Commercial and
industrial
–0.5
4.6
V
VCCP
Transceiver block supply
voltage
Commercial and
industrial
–0.5
1.8
V
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May 2008
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Operating Conditions
Table 4–4. Arria GX Transceiver Block Absolute Maximum Ratings (Part 2 of 2)
Symbol
Parameter
Conditions
Note (1)
Minimum Maximum
Units
VCCR
Transceiver block supply
Voltage
Commercial and
industrial
–0.5
1.8
V
VCCT_B
Transceiver block supply
voltage
Commercial and
industrial
–0.5
1.8
V
VCCL_B
Transceiver block supply
voltage
Commercial and
industrial
–0.5
1.8
V
VCCH_B
Transceiver block supply
voltage
Commercial and
industrial
–0.5
2.4
V
Note to Tables 4–4:
(1)
The device can tolerate prolonged operation at this absolute maximum, as long as the maximum specification is
not violated.
Table 4–5. Arria GX Transceiver Block Operating Conditions
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Units
VCCA
Transceiver block supply
voltage
Commercial
and industrial
3.135
3.3
3.465
V
VCCP
Transceiver block supply
voltage
Commercial
and industrial
1.15
1.2
1.25
V
VCCR
Transceiver block supply
voltage
Commercial
and industrial
1.15
1.2
1.25
V
VCCT_B
Transceiver block supply
voltage
Commercial
and industrial
1.15
1.2
1.25
V
VCCL_B
Transceiver block supply
voltage
Commercial
and industrial
1.15
1.2
1.25
V
VCCH_B
Transceiver block supply
voltage
Commercial
and industrial
Reference resistor
Commercial
and industrial
RREFB (1)
1.15
1.2
1.25
V
1.425
1.5
1.575
V
2K –1%
2K
2K +1%
Ω
Notes to Table 4–5:
(1)
The DC signal on this pin must be as clean as possible. Ensure that no noise is coupled to this pin.
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May 2008
DC and Switching Characteristics
Table 4–6. Arria GX Transceiver Block AC Specification (Part 1 of 4)
Symbol / Description
Conditions
-6 Speed Grade Commercial and
Industrial
Unit
Min
Typ
Max
Input reference clock
frequency
50
—
622.08
MHz
Absolute VM A X for a
REFCLK Pin
—
—
3.3
V
Absolute VM I N for a
-0.3
—
—
V
Rise/Fall time
—
0.2
—
UI
Duty cycle
45
—
55
%
Peak to peak differential
input voltage Vid (diff
p-p)
200
—
2000
mV
30
—
33
kHz
Reference clock
REFCLK Pin
Spread spectrum
clocking (1)
0 to -0.5%
On-chip termination
resistors
115 ± 20%
Ω
VI C M (AC coupled)
1200 ± 5%
mV
VI C M (DC coupled) (2)
PCI Express (PIPE) mode
0.25
RREFB
—
0.55
V
Ω
2000 +/-1%
Transceiver Clocks
Calibration block clock
frequency
10
-
125
MHz
Calibration block
minimum power-down
pulse width
30
-
-
ns
125 ±10%
fixedclk clock
frequency (3)
reconfig clock
SDI mode
2.5
MHz
50
MHz
-
ns
frequency
Transceiver block
minimum power-down
pulse width
Altera Corporation
May 2008
100
-
4–5
Arria GX Device Handbook, Volume 1
Operating Conditions
Table 4–6. Arria GX Transceiver Block AC Specification (Part 2 of 4)
Symbol / Description
Conditions
-6 Speed Grade Commercial and
Industrial
Unit
Min
Typ
Max
600
-
3125
Mbps
Absolute VM A X for a
receiver pin (4)
-
-
2.0
V
Absolute VM I N for a
receiver pin
-0.4
-
-
V
Receiver
Data rate
Maximum peak-to-peak
differential input voltage
VI D (diff p-p)
Vicm = 0.85 V
-
-
3.3
V
Minimum peak-to-peak
differential input voltage
VI D (diff p-p)
DC Gain = 3 dB
160
-
-
mV
On-chip termination
resistors
VI C M (15)
Vicm = 0.85 V setting
850 ± 10%
850 ± 10%
850 ± 10%
Vicm = 1.2 V setting
1200 ± 10%
1200 ± 10%
1200 ± 10%
mV
30
-
MHz
-
MHz
BW = Low
Bandwidth at 3.125
Gbps
Bandwidth at 2.5 Gbps
Return loss differential
mode
Return loss common
mode
Ω
100±15%
BW = Med
40
BW = High
50
BW = Low
35
BW = Med
50
mV
BW = High
60
50 MHz to 1.25 GHz
(PCI Express)
-10
dB
-6
dB
± 62.5, 100, 125, 200, 250, 300, 500, 1000
PPM
100 MHz to 2.5 GHz (XAUI)
50 MHz to 1.25 GHz
(PCI Express)
100 MHz to 2.5 GHz (XAUI)
Programmable PPM
detector (5)
Run length (6)
80
Programmable
equalization
Signal detect/loss
threshold (7)
4–6
Arria GX Device Handbook, Volume 1
65
-
UI
5
dB
175
mV
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–6. Arria GX Transceiver Block AC Specification (Part 3 of 4)
Symbol / Description
Conditions
-6 Speed Grade Commercial and
Industrial
Min
Typ
Max
Unit
CDR LTR TIme (8), (9)
-
-
75
us
CDR Minimum T1b (9),
(10)
15
-
-
us
LTD lock time (9), (11)
0
100
4000
ns
Data lock time from
rx_freqlocked (9),
(12)
-
-
4
us
Programmable DC gain
0, 3, 6
dB
Vocm = 0.6 V setting
580 ± 10%
mV
Vocm = 0.7 V setting
680 ± 10%
mV
108±10%
Ω
-10
dB
-6
dB
Transmitter Buffer
Output Common Mode
voltage (Vocm)
On-chip termination
resistors
Return loss differential
mode
Return loss common
mode
50 MHz to 1.25 GHz (PCI
Express)
312 MHz to 625 MHz (XAUI)
50 MHz to 1.25 GHz (PCI
Express)
Rise time
35
-
65
ps
Fall time
35
-
65
ps
-
-
15
ps
-
-
100
ps
500
-
1562.5
MHz
BW = Low
3
-
MHz
BW = Med
5
-
MHz
100
us
Intra differential pair
skew
VOD = 800 mV
Intra-transceiver block
skew (×4) (13)
Transmitter PLL
VCO frequency range
Bandwidth at 3.125
Gbps
Bandwidth at 2.5 Gbps
TX PLL lock time from
BW = High
9
BW = Low
1
BW = Med
2
BW = High
4
-
-
gxb_powerdown
deassertion (9), (14)
Altera Corporation
May 2008
4–7
Arria GX Device Handbook, Volume 1
Operating Conditions
Table 4–6. Arria GX Transceiver Block AC Specification (Part 4 of 4)
Symbol / Description
Conditions
-6 Speed Grade Commercial and
Industrial
Min
Typ
Unit
Max
PCS
Interface speed per
mode
25
Digital Reset Pulse
Width
156.25
MHz
Minimum is 2 parallel clock cycles
Note to Table 4–6:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
Spread spectrum clocking is allowed only in PCI Express (PIPE) mode if the upstream transmitter and the receiver
share the same clock source.
The reference clock DC coupling option is only available in PCI Express (PIPE) mode for the HCSL I/O standard.
The fixedclk is used in PIPE mode receiver detect circuitry.
The device cannot tolerate prolonged operation at this absolute maximum.
The rate matcher supports only up to ± 300 PPM for PIPE mode and ± 100 PPM for GIGE mode.
This parameter is measured by embedding the run length data in a PRBS sequence.
Signal detect threshold detector circuitry is available only in PCI Express (PIPE mode).
Time taken for rx_pll_locked to go high from rx_analogreset deassertion. Refer to Figure 4–1.
Refer to protocol characterization documents for lock times specific to the protocols.
Time for which the CDR needs to stay in LTR mode after rx_pll_locked is asserted and before rx_locktodata is
asserted in manual mode. Refer to Figure 4–1.
Time taken to recover valid data from GXB after the rx_locktodata signal is asserted in manual mode. Measurement
results are based on PRBS31, for native data rates only. Refer to Figure 4–1.
Time taken to recover valid data from GXB after the rx_freqlocked signal goes high in automatic mode.
Measurement results are based on PRBS31, for native data rates only. Refer to Figure 4–2.
This is applicable only to PCI Express (PIPE) ×4 and XAUI ×4 mode.
Time taken to lock TX PLL from gxb_powerdown deassertion.
The 1.2 V RX VICM settings is intended for DC-coupled LVDS links.
Figure 4–1 shows the lock time parameters in manual mode. Figure 4–2
shows the lock time parameters in automatic mode.
1
4–8
Arria GX Device Handbook, Volume 1
LTD = Lock to data
LTR = Lock to reference clock
Altera Corporation
May 2008
DC and Switching Characteristics
Figure 4–1. Lock Time Parameters for Manual Mode
r x_analogreset
CDR status
LTR
LTD
r x_pll_locked
r x_locktodata
Invalid Data
Valid data
r x_dataout
CDR LTR Time
LTD lock time
CDR Minimum T1b
Figure 4–2. Lock Time Parameters for Automatic Mode
CDR status
LTR
LTD
r x_freqlocked
r x_dataout
Invalid
Valid
data
data
Data lock time from rx_freqlocked
Altera Corporation
May 2008
4–9
Arria GX Device Handbook, Volume 1
Operating Conditions
Figure 4–3 and Figure 4–4 show differential receiver input and
transmitter output waveforms, respectively.
Figure 4–3. Receiver Input Waveform
Single-Ended Waveform
Positive Channel (p)
VID
Negative Channel (n)
VCM
Ground
Differential Waveform
VID (diff peak-peak) = 2 x VID (single-ended)
VID
p−n=0V
VID
Figure 4–4. Transmitter Output Waveform
Single-Ended Waveform
Positive Channel (p)
VOD
Negative Channel (n)
VCM
Ground
Differential Waveform
VOD (diff peak-peak) = 2 x VOD (single-ended)
VOD
p−n=0V
VOD
4–10
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–7 shows the Arria GX transceiver block AC specification.
Table 4–7. Arria GX Transceiver Block AC Specification Notes (1), (2), (3) (Part 1 of 3)
-6 Speed Grade
Commercial & Industrial
Unit
0.3
UI
Total jitter at 3.125 Gbps
REFCLK = 156.25 MHz
Pattern = CJPAT
VOD = 1200 mV
No Pre-emphasis
0.17
UI
Deterministic jitter at 3.125 Gbps
REFCLK = 156.25 MHz
Pattern = CJPAT
VOD = 1200 mV
No Pre-emphasis
> 0.65
UI
Description
Condition
XAUI Transmit Jitter Generation (4)
XAUI Receiver Jitter Tolerance (4)
Total jitter
Deterministic jitter
> 0.37
UI
Peak-to-peak jitter
Jitter frequency = 22.1 KHz
> 8.5
UI
Peak-to-peak jitter
Jitter frequency = 1.875 MHz
> 0.1
UI
Peak-to-peak jitter
Jitter frequency = 20 MHz
> 0.1
UI
< 0.25
UI p-p
> 0.6
UI p-p
PCI Express (PIPE) Transmitter Jitter Generation (5)
Total Transmitter Jitter Generation
Compliance Pattern;
VOD = 800 mV;
Pre-emphasis = 49%
PCI Express (PIPE) Receiver Jitter Tolerance (5)
Total Receiver Jitter Tolerance
Compliance Pattern;
DC Gain = 3 db
Gigabit Ethernet (GIGE) Transmitter Jitter Generation (7)
Total Transmitter Jitter Generation
(TJ)
CRPAT: VOD = 800 mV;
Pre-emphasis = 0%
< 0.279
UI p-p
Deterministic Transmitter Jitter
Generation (DJ)
CRPAT; VOD = 800 mV;
Pre-emphasis = 0%
< 0.14
UI p-p
Gigabit Ethernet (GIGE) Receiver Jitter Tolerance
Total Jitter Tolerance
CJPAT Compliance Pattern;
DC Gain = 0 dB
> 0.66
UI p-p
Deterministic Jitter Tolerance
CJPAT Compliance Pattern;
DC Gain = 0 dB
> 0.4
UI p-p
Altera Corporation
May 2008
4–11
Arria GX Device Handbook, Volume 1
Operating Conditions
Table 4–7. Arria GX Transceiver Block AC Specification Notes (1), (2), (3) (Part 2 of 3)
Description
Condition
-6 Speed Grade
Commercial & Industrial
Unit
Serial RapidIO (1.25 Gbps, 2.5 Gbps, and 3.125 Gbps) Transmitter Jitter Generation (6)
Total Transmitter Jitter Generation
(TJ)
CJPAT Compliance Pattern;
VOD = 800 mV;
Pre-emphasis = 0%
< 0.35
UI p-p
Deterministic Transmitter Jitter
Generation (DJ)
CJPAT Compliance Pattern;
VOD = 800 mV;
Pre-emphasis = 0%
< 0.17
UI p-p
Serial RapidIO (1.25 Gbps, 2.5 Gbps, and 3.125 Gbps) Receiver Jitter Tolerance (6)
Total Jitter Tolerance
CJPAT Compliance Pattern;
DC Gain = 0 dB
> 0.65
UI p-p
Combined Deterministic and
Random Jitter Tolerance (JDR)
CJPAT Compliance Pattern;
DC Gain = 0 dB
> 0.55
UI p-p
Deterministic Jitter Tolerance (JD)
CJPAT Compliance Pattern;
DC Gain = 0 dB
> 0.37
UI p-p
Jitter Frequency = 22.1 KHz
> 8.5
UI p-p
Sinusoidal Jitter Tolerance
Jitter Frequency = 200 KHz
> 1.0
UI p-p
Jitter Frequency = 1.875 MHz
> 0.1
UI p-p
Jitter Frequency = 20 MHz
> 0.1
UI p-p
Data Rate = 1.485 Gbps (HD)
REFCLK = 74.25 MHz
Pattern = Color Bar
Vod = 800 mV
No Pre-emphasis
Low-Frequency Roll-Off =
100 KHz
0.2
UI
Data Rate = 2.97 Gbps (3G)
REFCLK = 148.5 MHz
Pattern = Color Bar
Vod = 800 mV
No Pre-emphasis
Low-Frequency Roll-Off =
100 KHz
0.3
UI
SDI Transmitter Jitter Generation (8)
Alignment Jitter (peak-to-peak)
4–12
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–7. Arria GX Transceiver Block AC Specification Notes (1), (2), (3) (Part 3 of 3)
Description
-6 Speed Grade
Commercial & Industrial
Unit
Jitter Frequency = 15 KHz
Data Rate = 2.97 Gbps (3G)
REFCLK = 148.5 MHz
Pattern = Single Line Scramble
Color Bar
No
Equalization
DC Gain = 0 dB
>2
UI
Jitter Frequency = 100 KHz
Data Rate = 2.97 Gbps (3G)
REFCLK = 148.5 MHz
Pattern = Single Line Scramble
Color Bar
No
Equalization
DC Gain = 0 dB
> 0.3
UI
Jitter Frequency = 148.5 MHz
Data Rate = 2.97 Gbps (3G)
REFCLK = 148.5 MHz
Pattern = Single Line Scramble
Color Bar
No
Equalization
DC Gain = 0 dB
> 0.3
UI
Jitter Frequency = 20 KHz
Data Rate = 1.485 Gbps (HD)
REFCLK = 74.25 MHz
Pattern = 75% Color Bar
No Equalization
DC Gain = 0 dB
>1
UI
Jitter Frequency = 100 KHz
Data Rate = 1.485 Gbps (HD)
REFCLK = 74.25 MHz
Pattern = 75% Color Bar
No Equalization
DC Gain = 0 dB
> 0.2
UI
Condition
SDI Receiver Jitter Tolerance (8)
Sinusoidal Jitter Tolerance
(peak-to-peak)
Sinusoidal Jitter Tolerance
(peak-to-peak)
Notes to Table 4–7:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Dedicated REFCLK pins were used to drive the input reference clocks.
Jitter numbers specified are valid for the stated conditions only.
Refer to the protocol characterization documents for detailed information.
The jitter numbers for XAUI are compliant to the IEEE802.3ae-2002 Specification.
The jitter numbers for PCI Express are compliant to the PCIe Base Specification 2.0.
The jitter numbers for Serial RapidIO are compliant to the RapidIO Specification 1.3.
The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification.
The HD-SDI and 3G-SDI jitter numbers are compliant to the SMPTE292M and SMPTE424M specifications.
Altera Corporation
May 2008
4–13
Arria GX Device Handbook, Volume 1
Operating Conditions
Tables 4–8 and 4–9 show the transmitter and receiver PCS latency for each
mode, respectively.
Table 4–8. PCS Latency Note (1)
Transmitter PCS Latency
Functional Mode
TX PIPE
TX
Phase
Comp
FIFO
Byte
Serializer
TX State
Machine
8B/10B
Encoder
Sum (2)
-
2-3
1
0.5
0.5
4-5
×1, ×4, ×8
8-bit channel
width
1
3-4
1
-
1
6-7
×1, ×4, ×8
16-bit channel
width
1
3-4
1
-
0.5
6-7
Configuration
XAUI
PIPE
GIGE
Serial RapidIO
SDI
BASIC Single Width
-
2-3
1
-
1
4-5
1.25 Gbps,
2.5 Gbps,
3.125 Gbps
-
2-3
1
-
0.5
4-5
HD
10-bit channel
width
-
2-3
1
-
1
4-5
HD, 3G
20-bit channel
width
-
2-3
1
-
0.5
4-5
8-bit/10-bit
channel width
-
2-3
1
-
1
4-5
16-bit/20-bit
channel width
-
2-3
1
-
0.5
4-5
Notes to Tables 4–8:
(1)
(2)
The latency numbers are with respect to the PLD-transceiver interface clock cycles.
The total latency number is rounded off in the Sum column.
4–14
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–9. PCS Latency (Part 1 of 2) Note (1)
Receiver PCS Latency
Functional
Mode
Word
Aligner
Deskew
FIFO
Rate
Matcher
(3)
8B/10B
Decoder
Receiver
State
Machine
Byte
Deserializer
Byte
Order
Receiver
Phase
Comp
FIFO
Receiver
PIPE
Sum
(2)
2-2.5
2-2.5
5.5-6.5
0.5
1
1
1
1-2
-
14-17
×1, ×4
8-bit
channel
width
4-5
-
11-13
1
-
1
1
2-3
1
21-25
×1, ×4
16-bit
channel
width
2-2.5
-
5.5-6.5
0.5
-
1
1
2-3
1
13-16
4-5
-
11-13
1
-
1
1
1-2
-
19-23
1.25 Gbps,
2.5 Gbps,
3.125 Gbps
2-2.5
-
-
0.5
-
1
1
1-2
-
6-7
HD
10-bit
channel
width
5
-
-
1
-
1
1
1-2
-
9-10
HD, 3G
20-bit
channel
width
2.5
-
-
0.5
-
1
1
1-2
-
6-7
Configuration
XAUI
PIPE
GIGE
Serial
RapidIO
SDI
Altera Corporation
May 2008
4–15
Arria GX Device Handbook, Volume 1
Operating Conditions
Table 4–9. PCS Latency (Part 2 of 2) Note (1)
Receiver PCS Latency
Functional
Mode
BASIC
Single
Width
Word
Aligner
Deskew
FIFO
Rate
Matcher
(3)
8B/10B
Decoder
Receiver
State
Machine
Byte
Deserializer
Byte
Order
Receiver
Phase
Comp
FIFO
Receiver
PIPE
Sum
(2)
8/10-bit
channel
width;
with Rate
Matcher
4-5
-
11-13
1
-
1
1
1-2
1
19-23
8/10-bit
channel
width;
without
Rate
Matcher
4-5
-
-
1
-
1
1
1-2
-
8-10
16/20-bit
channel
width;
with Rate
Matcher
2-2.5
-
5.5-6.5
0.5
-
1
1
1-2
-
11-14
16/20-bit
channel
width;
without
Rate
Matcher
2-2.5
-
-
0.5
-
1
1
1-2
-
6-7
Configuration
Notes to Tables 4–9:
(1)
(2)
(3)
The latency numbers are with respect to the PLD-transceiver interface clock cycles.
The total latency number is rounded off in the Sum column.
The rate matcher latency shown is the steady state latency. Actual latency may vary depending on the skip ordered set
gap allowed by the protocol, actual PPM difference between the reference clocks, and so forth.
4–16
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Tables 4–10 to Tables 4–13 show the typical VOD for data rates from
600 Mbps to 3.125 Gbps. The specification is for measurement at the
package ball.
Table 4–10. Typical VOD Setting, TX Term = 100 Ω
VOD Setting (mV)
VccHTX = 1.5 V
VOD Typical (mV)
400
600
800
1000
1200
430
625
830
1020
1200
Table 4–11. Typical VOD Setting, TX Term = 100 Ω
VOD Setting (mV)
VccHTX = 1.2 V
VOD Typical (mV)
320
480
640
800
960
344
500
664
816
960
Table 4–12. Typical Pre-Emphasis (First Post-Tap), Note (1)
VccHTX =
1.5 V
First Post Tap Pre-Emphasis Level
VOD Setting
(mV)
1
2
3
4
5
TX Term = 100 Ω
400
24%
62%
112%
184%
600
31%
56%
86%
122%
800
20%
35%
53%
73%
1000
23%
36%
49%
1200
17%
25%
35%
Note to Table 4–12:
(1)
Altera Corporation
May 2008
Applicable to data rates from 600 Mbps to 3.125 Gbps. Specification is for
measurement at the package ball.
4–17
Arria GX Device Handbook, Volume 1
Operating Conditions
Table 4–13. Typical Pre-Emphasis (First Post-Tap), Note (1)
VccHTX =
1.2 V
First Post Tap Pre-Emphasis Level
VOD Setting
(mV)
1
2
3
4
5
TX Term = 100 Ω
320
61%
114%
480
24%
31%
55%
86%
121%
640
20%
35%
54%
72%
800
23%
36%
49%
960
18%
25%
35%
Note to Table 4–13:
(1)
Applicable to data rates from 600 Mbps to 3.125 Gbps. Specification is for
measurement at the package ball.
DC Electrical Characteristics
Table 4–14 shows the Arria GX device family DC electrical characteristics.
Table 4–14. Arria GX Device DC Operating Conditions (Part 1 of 2)
Symbol
Parameter
Conditions
Device
Note (1)
Minimum Typical Maximum
Unit
II
Input pin leakage
current
VI = VCCIOmax to
0 V (2)
All
–10
10
μA
IOZ
Tri-stated I/O pin
leakage current
VO = VCCIOmax to
0 V (2)
All
–10
10
μA
VCCINT supply current
(standby)
VI = ground, no
load, no toggling
inputs
TJ = 25 °C
EP1AGX20/35
0.30
(3)
A
EP1AGX50/60
0.50
(3)
A
EP1AGX90
0.62
(3)
A
ICCINT0
VCCPD supply current
(standby)
ICCPD0
ICCI00
VCCIO supply current
(standby)
VI = ground, no
load, no toggling
inputs
TJ = 25 °C,
VCCPD = 3.3V
VI = ground, no
load, no toggling
inputs
TJ = 25 °C
4–18
Arria GX Device Handbook, Volume 1
EP1AGX20/35
2.7
(3)
mA
EP1AGX50/60
3.6
(3)
mA
EP1AGX90
4.3
(3)
mA
EP1AGX20/35
4.0
(3)
mA
EP1AGX50/60
4.0
(3)
mA
EP1AGX90
4.0
(3)
mA
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–14. Arria GX Device DC Operating Conditions (Part 2 of 2)
Symbol
Parameter
Conditions
Device
Note (1)
Minimum Typical Maximum
Unit
Value of I/O pin pull-up Vi = 0, VCCIO =
resistor before and
3.3 V
during configuration
Vi = 0, VCCIO =
2.5 V
10
25
50
kΩ
15
35
70
kΩ
Vi = 0, VCCIO =
1.8 V
30
50
100
kΩ
Vi = 0, VCCIO =
1.5 V
40
75
150
kΩ
Vi = 0, VCCIO =
1.2 V
50
90
170
kΩ
1
2
kΩ
RCONF
(4)
Recommended value
of I/O pin external
pull-down resistor
before and during
configuration
Notes to Table 4–14:
(1)
(2)
(3)
(4)
Typical values are for TA = 25 °C, VCCINT = 1.2 V, and VCCIO = 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V.
This value is specified for normal device operation. The value may vary during power-up. This applies for all VCCIO
settings (3.3, 2.5, 1.8, 1.5, and 1.2 V).
Maximum values depend on the actual TJ and design utilization. See the Excel-based PowerPlay Early Power
Estimator (available at www.altera.com) or the Quartus® II PowerPlay Power Analyzer feature for maximum values.
See the section “Power Consumption” on page 4–34 for more information.
Pin pull-up resistance values will be lower if an external source drives the pin higher than VCCIO.
I/O Standard Specifications
Tables 4–15 through 4–38 show the Arria GX device family I/O standard
specifications.
Table 4–15. LVTTL Specifications
Symbol
Parameter
VCCIO (1)
Output supply voltage
Conditions
Minimum
Maximum
Unit
3.135
3.465
V
VIH
High-level input voltage
1.7
4.0
V
VIL
Low-level input voltage
–0.3
0.8
V
VOH
High-level output voltage
Altera Corporation
May 2008
IOH = –4 mA (2)
2.4
V
4–19
Arria GX Device Handbook, Volume 1
Operating Conditions
Table 4–15. LVTTL Specifications
Symbol
VOL
Parameter
Low-level output voltage
Conditions
Minimum
IOL = 4 mA (2)
Maximum
Unit
0.45
V
Notes to Table 4–15:
(1)
(2)
Arria GX devices comply to the narrow range for the supply voltage as specified in the EIA/JEDEC Standard,
JESD8-B.
This specification is supported across all the programmable drive strength settings available for this I/O standard.
Table 4–16. LVCMOS Specifications
Symbol
Parameter
Conditions
Minimum
Maximum
Unit
3.135
3.465
V
VCCIO(1)
Output supply voltage
VIH
High-level input voltage
1.7
4.0
V
VIL
Low-level input voltage
–0.3
0.8
V
VOH
High-level output voltage
VCCIO = 3.0, IOH = –0.1 mA (2)
VOL
Low-level output voltage
VCCIO = 3.0, IOL = 0.1 mA (2)
VCCIO – 0.2
V
0.2
V
Notes to Table 4–16:
(1)
(2)
Arria GX devices comply to the narrow range for the supply voltage as specified in the EIA/JEDEC Standard,
JESD8-B.
This specification is supported across all the programmable drive strength available for this I/O standard.
4–20
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–17. 2.5-V I/O Specifications
Symbol
Parameter
Minimum
Maximum
Unit
2.375
2.625
V
High-level input voltage
1.7
4.0
V
VIL
Low-level input voltage
–0.3
0.7
V
VOH
High-level output voltage
IOH = –1 mA (2)
VOL
Low-level output voltage
IOL = 1 mA (2)
VCCIO (1)
Output supply voltage
VIH
Conditions
2.0
V
0.4
V
Notes to Table 4–17:
(1)
(2)
The Arria GX device VCCIO voltage level support of 2.5 to 5% is narrower than defined in the normal range of the
EIA/JEDEC standard.
This specification is supported across all the programmable drive settings available for this I/O standard.
Table 4–18. 1.8-V I/O Specifications
Symbol
Parameter
VCCIO (1)
Output supply voltage
VIH
High-level input voltage
Conditions
VIL
Low-level input voltage
VOH
High-level output voltage
IOH = –2 mA (2)
VOL
Low-level output voltage
IOL = 2 mA (2)
Minimum
Maximum
Unit
1.71
1.89
V
0.65 × VCCIO
2.25
V
–0.3
0.35 × VCCIO
VCCIO – 0.45
V
V
0.45
V
Notes to Table 4–18:
(1)
(2)
The Arria GX device VCCIO voltage level support of 1.8 to 5% is narrower than defined in the normal range of the
EIA/JEDEC standard.
This specification is supported across all the programmable drive settings available for this I/O standard as shown
in Arria GX Architecture chapter in volume 1 of the Arria GX Device Handbook.
Altera Corporation
May 2008
4–21
Arria GX Device Handbook, Volume 1
Operating Conditions
Table 4–19. 1.5-V I/O Specifications
Symbol
Parameter
VCCIO (1)
Output supply voltage
VIH
High-level input voltage
Conditions
VIL
Low-level input voltage
VOH
High-level output voltage
IOH = –2 mA (2)
VOL
Low-level output voltage
IOL = 2 mA (2)
Minimum
Maximum
Unit
1.425
1.575
V
0.65 VCCIO
VCCIO + 0.3
V
–0.3
0.35 VCCIO
V
0.75 VCCIO
V
0.25 VCCIO
V
Notes to Table 4–19:
(1)
(2)
The Arria GX device VCCIO voltage level support of 1.5 to 5% is narrower than defined in the normal range of the
EIA/JEDEC standard.
This specification is supported across all the programmable drive settings available for this I/O standard as shown
in Arria GX Architecture chapter in volume 1 of the Arria GX Device Handbook.
Figures 4–5 and 4–6 show receiver input and transmitter output
waveforms, respectively, for all differential I/O standards (LVDS and
LVPECL).
Figure 4–5. Receiver Input Waveforms for Differential I/O Standards
Single-Ended Waveform
Positive Channel (p) = VIH
VID
Negative Channel (n) = VIL
VCM
Ground
Differential Waveform
VID
p−n=0V
VID (Peak-to-Peak)
4–22
Arria GX Device Handbook, Volume 1
VID
Altera Corporation
May 2008
DC and Switching Characteristics
Figure 4–6. Transmitter Output Waveforms for Differential I/O Standards
Single-Ended Waveform
Positive Channel (p) = VOH
VOD
Negative Channel (n) = VOL
VCM
Ground
Differential Waveform
VOD
p−n=0V
VOD
Table 4–20. 2.5-V LVDS I/O Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
2.375
2.5
2.625
V
100
350
900
mV
200
1,250
VCCIO
I/O supply voltage for left and
right I/O banks (1, 2, 5, and
6)
VID
Input differential voltage
swing (single-ended)
VICM
Input common mode voltage
1,800
mV
VOD
Output differential voltage
(single-ended)
RL = 100 Ω
250
450
mV
VOCM
Output common mode
voltage
RL = 100 Ω
1.125
1.375
V
RL
Receiver differential input
discrete resistor (external to
Arria GX devices)
90
100
110
Ω
Minimum
Typical
Maximum
Unit
3.135
3.3
3.465
V
100
350
900
mV
Table 4–21. 3.3-V LVDS I/O Specifications (Part 1 of 2)
Symbol
Parameter
VCCIO (1)
I/O supply voltage for top and
bottom PLL banks (9, 10, 11,
and 12)
VID
Input differential voltage
swing (single-ended)
Altera Corporation
May 2008
Conditions
4–23
Arria GX Device Handbook, Volume 1
Operating Conditions
Table 4–21. 3.3-V LVDS I/O Specifications (Part 2 of 2)
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
200
1,250
1,800
mV
VICM
Input common mode voltage
VOD
Output differential voltage
(single-ended)
RL = 100 Ω
250
710
mV
VOCM
Output common mode
voltage
RL = 100 Ω
840
1,570
mV
RL
Receiver differential input
discrete resistor (external to
Arria GX devices)
110
Ω
90
100
Note to Table 4–21:
(1)
The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by VCCINT, not VCCIO.
The PLL clock output/feedback differential buffers are powered by VCC_PLL_OUT. For differential clock
output/feedback operation, connect VCC_PLL_OUT to 3.3 V.
Table 4–22. 3.3-V PCML Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
3.135
3.3
Units
VCCIO
I/O supply voltage
3.465
V
VID
Input differential voltage
swing (single-ended)
300
600
mV
VICM
Input common mode
voltage
1.5
3.465
V
VOD
Output differential voltage
(single-ended)
300
500
mV
ΔVOD
Change in VO D between
high and low
50
mV
VO C M
Output common mode
voltage
3.3
V
ΔVO C M
Change in VO C M between
high and low
50
mV
VT
Output termination voltage
R1
Output external pull-up
resistors
45
50
55
Ω
R2
Output external pull-up
resistors
45
50
55
Ω
4–24
Arria GX Device Handbook, Volume 1
2.5
370
2.85
VC C I O
V
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–23. LVPECL Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
3.135
3.3
3.465
V
600
1,000
mV
VCCIO (1)
I/O supply voltage
VID
Input differential voltage
swing (single-ended)
300
VICM
Input common mode voltage
1.0
2.5
V
VOD
Output differential voltage
(single-ended)
RL = 100 Ω
525
970
mV
VOCM
Output common mode
voltage
RL = 100 Ω
1,650
2,250
mV
RL
Receiver differential input
resistor
110
Ω
90
100
Note to Table 4–23:
(1)
The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by VCCINT, not VCCIO.
The PLL clock output/feedback differential buffers are powered by VCC_PLL_OUT. For differential clock
output/feedback operation, connect VCC_PLL_OUT to 3.3 V.
Table 4–24. 3.3-V PCI Specifications
Symbol
Parameter
VCCIO
Output supply voltage
Conditions
Minimum
Typical
Maximum
Unit
3.0
3.3
3.6
V
VIH
High-level input voltage
0.5 VCCIO
VCCIO + 0.5
V
VIL
Low-level input voltage
–0.3
0.3 VCCIO
V
VOH
High-level output voltage
IOUT = –500 μA
VOL
Low-level output voltage
IOUT = 1,500 μA
0.9 VCCIO
V
0.1 VCCIO
V
Maximum
Unit
3.0
3.6
V
Table 4–25. PCI-X Mode 1 Specifications
Symbol
Parameter
VCCIO
Output supply voltage
Conditions
Minimum
Typical
VIH
High-level input voltage
0.5 VCCIO
VCCIO + 0.5
V
VIL
Low-level input voltage
–0.3
0.35 VCCIO
V
VIPU
Input pull-up voltage
VOH
High-level output voltage
IOUT = –500 μA
VOL
Low-level output voltage
IOUT = 1,500 μA
Altera Corporation
May 2008
0.7 VCCIO
V
0.9 VCCIO
V
0.1 VCCIO
V
4–25
Arria GX Device Handbook, Volume 1
Operating Conditions
Table 4–26. SSTL-18 Class I Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
VCCIO
Output supply voltage
1.71
1.8
1.89
V
VREF
Reference voltage
0.855
0.9
0.945
V
VTT
Termination voltage
VREF – 0.04
VREF
VREF + 0.04
V
VIH (DC)
High-level DC input voltage
VREF + 0.125
VIL (DC)
Low-level DC input voltage
VIH (AC)
High-level AC input voltage
V
VREF – 0.125
VREF + 0.25
VIL (AC)
Low-level AC input voltage
VOH
High-level output voltage
IOH = –6.7 mA (1)
VOL
Low-level output voltage
IOL = 6.7 mA (1)
V
V
VREF – 0.25
VTT + 0.475
V
V
VTT – 0.475
V
Note to Table 4–26:
(1)
This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Arria GX Architecture chapter in volume 1 of the Arria GX Device Handbook.
Table 4–27. SSTL-18 Class II Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
VCCIO
Output supply voltage
1.71
1.8
1.89
V
VREF
Reference voltage
0.855
0.9
0.945
V
VTT
Termination voltage
VREF – 0.04
VREF
VREF + 0.04
V
VIH (DC) High-level DC input voltage
VREF + 0.125
VIL (DC) Low-level DC input voltage
VIH (AC) High-level AC input voltage
V
VREF – 0.125
V
VREF – 0.25
V
VREF + 0.25
VIL (AC) Low-level AC input voltage
VOH
High-level output voltage
IOH = –13.4 mA (1)
VOL
Low-level output voltage
IOL = 13.4 mA (1)
V
VCCIO – 0.28
V
0.28
V
Note to Table 4–27:
(1)
This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Arria GX Architecture chapter in volume 1 of the Arria GX Device Handbook.
4–26
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–28. SSTL-18 Class I & II Differential Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
1.8
1.89
V
VCCIO
Output supply voltage
1.71
VSWING
(DC)
DC differential input voltage
0.25
VX (AC)
AC differential input cross
point voltage
VSWING
(AC)
AC differential input voltage
VISO
Input clock signal offset
voltage
0.5 VCCIO
V
ΔVISO
Input clock signal offset
voltage variation
200
mV
VOX (AC)
AC differential cross point
voltage
V
(VCCIO/2) – 0.175
(VCCIO/2) + 0.175
0.5
V
V
(VCCIO/2) – 0.125
(VCCIO/2) + 0.125
V
Table 4–29. SSTL-2 Class I Specifications
Symbol
Parameter
VCCIO
Output supply voltage
VTT
Termination voltage
VREF
Reference voltage
VIH (DC)
High-level DC input voltage
Conditions
Minimum
Typical
Maximum
Unit
2.375
2.5
2.625
V
VREF – 0.04
VREF
VREF + 0.04
V
1.188
1.25
1.313
V
VREF + 0.18
3.0
V
VREF – 0.18
VIL (DC)
Low-level DC input voltage
–0.3
VIH (AC)
High-level AC input voltage
VREF + 0.35
VIL (AC)
Low-level AC input voltage
VOH
High-level output voltage
IOH = –8.1 mA (1)
VOL
Low-level output voltage
IOL = 8.1 mA (1)
V
V
VREF – 0.35
VTT + 0.57
V
V
VTT – 0.57
V
Note to Table 4–29:
(1)
This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Arria GX Architecture chapter in volume 1 of the Arria GX Device Handbook.
Table 4–30. SSTL-2 Class II Specifications (Part 1 of 2)
Symbol
Parameter
VCCIO
Output supply voltage
VTT
Termination voltage
VREF
Reference voltage
Altera Corporation
May 2008
Conditions
Minimum
Typical
Maximum
Unit
2.375
2.5
2.625
V
VREF – 0.04
VREF
VREF + 0.04
V
1.188
1.25
1.313
V
4–27
Arria GX Device Handbook, Volume 1
Operating Conditions
Table 4–30. SSTL-2 Class II Specifications (Part 2 of 2)
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
VIH (DC)
High-level DC input voltage
VREF + 0.18
VCCIO + 0.3
V
VIL (DC)
Low-level DC input voltage
–0.3
VREF – 0.18
V
VREF + 0.35
VREF – 0.35
V
VIH (AC)
High-level AC input voltage
VIL (AC)
Low-level AC input voltage
VOH
High-level output voltage
IOH = –16.4 mA (1)
VOL
Low-level output voltage
IOL = 16.4 mA (1)
V
VTT + 0.76
V
VTT – 0.76
V
Note to Table 4–30:
(1)
This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Arria GX Architecture chapter in volume 1 of the Arria GX Device Handbook.
Table 4–31. SSTL-2 Class I & II Differential Specifications
Symbol
VCCIO
Parameter
Conditions
Output supply voltage
VSWING (DC) DC differential input voltage
VX (AC)
AC differential input cross
point voltage
Note (1)
Minimum
Typical
Maximum
Unit
2.375
2.5
2.625
V
0.36
V
(VCCIO/2) – 0.2
VSWING (AC) AC differential input voltage
(VCCIO/2) + 0.2
0.7
V
V
VISO
Input clock signal offset
voltage
0.5 VCCIO
V
ΔVISO
Input clock signal offset
voltage variation
200
mV
VOX (AC)
AC differential output cross
point voltage
(VCCIO/2) – 0.2
(VCCIO/2) + 0.2
V
Note to Table 4–31:
(1)
This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Arria GX Architecture chapter in volume 1 of the Arria GX Device Handbook.
Table 4–32. 1.2-V HSTL Specifications (Part 1 of 2)
Symbol
Parameter
VCCIO
Output supply voltage
VREF
Conditions
Minimum
Typical
Maximum
Unit
1.14
1.2
1.26
V
0.5 VCCIO
Reference voltage
0.48 VCCIO
0.52 VCCIO
V
VIH (DC) High-level DC input voltage
VREF + 0.08
VCCIO + 0.15
V
VIL (DC) Low-level DC input voltage
–0.15
VREF – 0.08
V
VIH (AC) High-level AC input voltage
VREF + 0.15
VCCIO + 0.24
V
4–28
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–32. 1.2-V HSTL Specifications (Part 2 of 2)
Symbol
Parameter
Conditions
Minimum
VIL (AC) Low-level AC input voltage
Typical
Maximum
Unit
–0.24
VREF – 0.15
V
VOH
High-level output voltage
IOH = 8 mA
VREF + 0.15
VCCIO + 0.15
V
VOL
Low-level output voltage
IOH = –8 mA
–0.15
VREF – 0.15
V
Table 4–33. 1.5-V HSTL Class I Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
VCCIO
Output supply voltage
1.425
1.5
1.575
V
VREF
Input reference voltage
0.713
0.75
0.788
V
VTT
Termination voltage
0.713
0.75
0.788
V
VIH (DC)
DC high-level input voltage
VREF + 0.1
VIL (DC)
DC low-level input voltage
–0.3
VIH (AC)
AC high-level input voltage
VREF + 0.2
VIL (AC)
AC low-level input voltage
VOH
High-level output voltage
IOH = 8 mA (1)
VOL
Low-level output voltage
IOH = –8 mA (1)
V
VREF – 0.1
V
V
VREF – 0.2
VCCIO – 0.4
V
V
0.4
V
Note to Table 4–33:
(1)
This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Arria GX Architecture chapter in volume 1 of the Arria GX Device Handbook.
Table 4–34. 1.5-V HSTL Class II Specifications (Part 1 of 2)
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
VCCIO
Output supply voltage
1.425
1.50
1.575
V
VREF
Input reference voltage
0.713
0.75
0.788
V
VTT
Termination voltage
0.713
0.75
0.788
V
VIH (DC)
DC high-level input voltage
VREF + 0.1
VIL (DC)
DC low-level input voltage
–0.3
VIH (AC)
AC high-level input voltage
VREF + 0.2
VIL (AC)
AC low-level input voltage
VOH
High-level output voltage
Altera Corporation
May 2008
V
VREF – 0.1
V
VREF – 0.2
IOH = 16 mA (1)
VCCIO – 0.4
V
V
V
4–29
Arria GX Device Handbook, Volume 1
Operating Conditions
Table 4–34. 1.5-V HSTL Class II Specifications (Part 2 of 2)
Symbol
VOL
Parameter
Low-level output voltage
Conditions
Minimum
Typical
IOH = –16 mA (1)
Maximum
Unit
0.4
V
Note to Table 4–34:
(1)
This specification is supported across all the programmable drive settings available for this I/O standard, as
shown in the Arria GX Architecture chapter in volume 1 of the Arria GX Device Handbook.
Table 4–35. 1.5-V HSTL Class I & II Differential Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
1.425
1.5
1.575
V
VCCIO
I/O supply voltage
VDIF (DC)
DC input differential voltage
0.2
VCM (DC)
DC common mode input
voltage
0.68
VDIF (AC)
AC differential input voltage
0.4
VOX (AC)
AC differential cross point
voltage
0.68
V
0.9
V
V
0.9
V
Table 4–36. 1.8-V HSTL Class I Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
VCCIO
Output supply voltage
1.71
1.80
1.89
V
VREF
Input reference voltage
0.85
0.90
0.95
V
VTT
Termination voltage
0.85
0.90
0.95
VIH (DC)
DC high-level input voltage
VREF + 0.1
VIL (DC)
DC low-level input voltage
–0.3
VIH (AC)
AC high-level input voltage
VREF + 0.2
VIL (AC)
AC low-level input voltage
VOH
High-level output voltage
IOH = 8 mA (1)
VOL
Low-level output voltage
IOH = –8 mA (1)
V
V
VREF – 0.1
V
VREF – 0.2
V
V
VCCIO – 0.4
V
0.4
V
Note to Table 4–36:
(1)
This specification is supported across all the programmable drive settings available for this I/O standard, as
shown in the Arria GX Architecture chapter in volume 1 of the Arria GX Device Handbook.
4–30
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–37. 1.8-V HSTL Class II Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
VCCIO
Output supply voltage
1.71
1.80
1.89
V
VREF
Input reference voltage
0.85
0.90
0.95
V
VTT
Termination voltage
0.85
0.90
0.95
VIH (DC)
DC high-level input voltage
VREF + 0.1
VIL (DC)
DC low-level input voltage
–0.3
VIH (AC)
AC high-level input voltage
VREF + 0.2
VIL (AC)
AC low-level input voltage
VOH
High-level output voltage
IOH = 16 mA (1)
VOL
Low-level output voltage
IOH = –16 mA (1)
V
V
VREF – 0.1
V
V
VREF – 0.2
V
VCCIO – 0.4
V
0.4
V
Note to Table 4–37:
(1)
This specification is supported across all the programmable drive settings available for this I/O standard, as
shown in the Arria GX Architecture chapter in volume 1 of the Arria GX Device Handbook.
Table 4–38. 1.8-V HSTL Class I & II Differential Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
1.80
1.89
V
VCCIO
I/O supply voltage
1.71
VDIF (DC)
DC input differential voltage
0.2
VCM (DC)
DC common mode input
voltage
0.78
V
VDIF (AC)
AC differential input voltage
0.4
VOX (AC)
AC differential cross point
voltage
0.68
Altera Corporation
May 2008
1.12
V
V
0.9
V
4–31
Arria GX Device Handbook, Volume 1
Operating Conditions
Bus Hold Specifications
Table 4–39 shows the Arria GX device family bus hold specifications.
Table 4–39. Bus Hold Parameters
VCCIO Level
Parameter
Conditions
1.2 V
Min
Max
1.5 V
Min
Max
1.8 V
Min
2.5 V
Max
Min
Max
3.3 V
Min
Unit
Max
Low
sustaining
current
VIN > VIL
(maximum)
22.5
25
30
50
70
μA
High
sustaining
current
VIN < VIH
(minimum)
–22.5
–25
–30
–50
–70
μA
Low
overdrive
current
0 V < VIN <
VCCIO
120
160
200
300
500
μA
High
overdrive
current
0 V < VIN <
VCCIO
–120
–160
–200
–300
–500
μA
2.0
V
Bus-hold
trip point
0.45
0.95
0.5
1.0
0.68
1.07
0.7
1.7
0.8
On-Chip Termination Specifications
Tables 4–40 and 4–41 define the specification for internal termination
resistance tolerance when using series or differential on-chip termination.
Table 4–40. Series On-Chip Termination Specification for Top and Bottom I/O Banks (Part 1 of 2)
Resistance Tolerance
Symbol
Description
Conditions
Commercial
Max
Industrial
Max
Unit
25-Ω RS
3.3/2.5
Internal series termination without
calibration (25-Ω setting)
VCCIO = 3.3/2.5V
±30
±30
%
50-Ω RS
3.3/2.5
Internal series termination without
calibration (50-Ω setting)
VCCIO = 3.3/2.5V
±30
± 30
%
25-Ω RS
1.8
Internal series termination without
calibration (25-Ω setting)
VCCIO = 1.8V
±30
±30
%
50-Ω RS
1.8
Internal series termination without
calibration (50-Ω setting)
VCCIO = 1.8V
±30
±30
%
4–32
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–40. Series On-Chip Termination Specification for Top and Bottom I/O Banks (Part 2 of 2)
Resistance Tolerance
Symbol
Description
Conditions
Commercial
Max
Industrial
Max
Unit
50-Ω RS
1.5
Internal series termination without
calibration (50-Ω setting)
VCCIO = 1.5V
±36
±36
%
50-Ω RS
1.2
Internal series termination without
calibration (50-Ω setting)
VCCIO = 1.2V
±50
±50
%
Table 4–41. Series On-Chip Termination Specification for Left I/O Banks
Resistance Tolerance
Symbol
Description
Conditions
Commercial Industrial
Max
Max
Unit
25-Ω RS
3.3/2.5
Internal series termination without
calibration (25-Ω setting)
VCCIO = 3.3/2.5V
±30
±30
%
50-Ω RS
3.3/2.5/1.8
Internal series termination without
calibration (50-Ω setting)
VCCIO = 3.3/2.5/1.8V
±30
±30
%
50-Ω RS 1.5
Internal series termination without
calibration (50-Ω setting)
VCCIO = 1.5V
±36
±36
%
RD
Internal differential termination for
LVDS (100-Ω setting)
VCCIO = 3.3 V
±20
±25
%
Pin Capacitance
Table 4–42 shows the Arria GX device family pin capacitance.
Table 4–42. Arria GX Device Capacitance Note (1) (Part 1 of 2)
Symbol
Parameter
Typical
Unit
CIOTB
Input capacitance on I/O pins in I/O banks 3, 4, 7, and 8.
5.0
pF
CIOL
Input capacitance on I/O pins in I/O banks 1 and 2, including high-speed
differential receiver and transmitter pins.
6.1
pF
CCLKTB
Input capacitance on top/bottom clock input pins: CLK[4..7] and
CLK[12..15].
6.0
pF
CCLKL
Input capacitance on left clock inputs: CLK0 and CLK2.
6.1
pF
CCLKL+
Input capacitance on left clock inputs: CLK1 and CLK3.
3.3
pF
Altera Corporation
May 2008
4–33
Arria GX Device Handbook, Volume 1
Power Consumption
Table 4–42. Arria GX Device Capacitance Note (1) (Part 2 of 2)
Symbol
COUTFB
Parameter
Input capacitance on dual-purpose clock output/feedback pins in PLL
banks 11 and 12.
Typical
Unit
6.7
pF
Note to Table 4–42:
(1)
Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement
accuracy is within ±0.5 pF.
Power
Consumption
Altera offers two ways to calculate power for a design: the Excel-based
PowerPlay early power estimator power calculator and the Quartus II
PowerPlay power analyzer feature.
The interactive Excel-based PowerPlay Early Power Estimator is typically
used prior to designing the FPGA in order to get an estimate of device
power. The Quartus II PowerPlay Power Analyzer provides better quality
estimates based on the specifics of the design after place-and-route is
complete. The power analyzer can apply a combination of user-entered,
simulation-derived and estimated signal activities which, combined with
detailed circuit models, can yield very accurate power estimates.
In both cases, these calculations should only be used as an estimation of
power, not as a specification.
f
For more information on PowerPlay tools, refer to the PowerPlay Early
Power Estimator and PowerPlay Power Analyzer paper and the PowerPlay
Power Analysis chapter in volume 3 of the Quartus II Handbook.
The PowerPlay early power estimator is available on the Altera web site
at www.altera. com. See Table 4–14 on page 18 for typical ICC standby
specifications.
I/O Timing
Model
The DirectDrive technology and MultiTrack interconnect ensures
predictable performance, accurate simulation, and accurate timing
analysis across all Arria GX device densities and speed grades. This
section describes and specifies the performance of I/Os.
All specifications are representative of worst-case supply voltage and
junction temperature conditions.
1
4–34
Arria GX Device Handbook, Volume 1
The timing numbers listed in the tables of this section are
extracted from the Quartus II software, version 7.1.
Altera Corporation
May 2008
DC and Switching Characteristics
Preliminary, Correlated, and Final Timing
Timing models can have either preliminary, correlated, or final status. The
Quartus II software issues an informational message during design
compilation if the timing models are preliminary. Table 4–43 shows the
status of the Arria GX device timing models.
■
■
■
Preliminary status means the timing model is subject to change.
Initially, timing numbers are created using simulation results,
process data, and other known parameters. These tests are used to
make the preliminary numbers as close to the actual timing
parameters as possible.
Correlated numbers are based on actual device operation and
testing. These numbers reflect the actual performance of the device
under worst-case voltage and junction temperature conditions.
Final timing numbers are based on complete correlation to actual
devices and addressing any minor deviations from the correlated
timing model. When the timing models are final, all or most of the
Arria GX family devices have been completely characterized and no
further changes to the timing model are expected.
Table 4–43. Arria GX Device Timing Model Status
Device
Preliminary
Correlated
Final
EP1AGX20
v
EP1AGX35
v
EP1AGX50
v
EP1AGX60
v
EP1AGX90
v
I/O Timing Measurement Methodology
Different I/O standards require different baseline loading techniques for
reporting timing delays. Altera characterizes timing delays with the
required termination for each I/O standard and with 0 pF (except for PCI
and PCI-X which use 10 pF) loading and the timing is specified up to the
output pin of the FPGA device. The Quartus II software calculates the
I/O timing for each I/O standard with a default baseline loading as
specified by the I/O standards.
The following measurements are made during device characterization.
Altera measures clock-to-output delays (tCO) at worst-case process,
minimum voltage, and maximum temperature (PVT) for default loading
conditions shown in Table 4–44.
Altera Corporation
May 2008
4–35
Arria GX Device Handbook, Volume 1
I/O Timing Model
Use the following equations to calculate clock pin to output pin timing for
Arria GX devices:
tCO from clock pin to I/O pin = delay from clock pad to I/O output
register + IOE output register clock-to-output delay + delay
from output register to output pin + I/O output delay
txz/tzx from clock pin to I/O pin = delay from clock pad to I/O
output register + IOE output register clock-to-output delay +
delay from output register to output pin + I/O output delay +
output enable pin delay
Simulation using IBIS models is required to determine the delays on the
PCB traces in addition to the output pin delay timing reported by the
Quartus II software and the timing model in the device handbook.
1.
Simulate the output driver of choice into the generalized test setup,
using values from Table 4–44.
2.
Record the time to VMEAS.
3.
Simulate the output driver of choice into the actual PCB trace and
load, using the appropriate IBIS model or capacitance value to
represent the load.
4.
Record the time to VMEAS.
5.
Compare the results of steps 2 and 4. The increase or decrease in
delay should be added to or subtracted from the I/O Standard
Output Adder delays to yield the actual worst-case propagation
delay (clock-to-output) of the PCB trace.
The Quartus II software reports the timing with the conditions shown in
Table 4–44 using the above equation. Figure 4–7 shows the model of the
circuit that is represented by the output timing of the Quartus II software.
4–36
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Figure 4–7. Output Delay Timing Reporting Setup Modeled by Quartus II
VTT
VCCIO
Outputp
RT
Output
Buffer
RS
Output
VMEAS
GND
Outputn
CL
RD
GND
Notes to Figure 4–7:
(1)
(2)
(3)
Output pin timing is reported at the output pin of the FPGA device. Additional
delays for loading and board trace delay need to be accounted for with IBIS model
simulations.
VCCPD is 3.085 V unless otherwise specified.
VCCINT is 1.12 V unless otherwise specified.
Table 4–44. Output Timing Measurement Methodology for Output Pins Notes (1), (2), (3) (Part 1 of 2)
Measurement
Point
Loading and Termination
I/O Standard
RS (Ω)
RD (Ω)
RT (Ω)
VCCIO (V)
VTT (V)
CL (pF)
VMEAS (V)
LVTTL (4)
3.135
0
1.5675
LVCMOS (4)
3.135
0
1.5675
2.5 V (4)
2.375
0
1.1875
1.8 V (4)
1.710
0
0.855
1.5 V (4)
1.425
0
0.7125
PCI (5)
2.970
10
1.485
PCI-X (5)
SSTL-2 Class I
2.970
25
50
2.325
1.123
10
1.485
0
1.1625
SSTL-2 Class II
25
25
2.325
1.123
0
1.1625
SSTL-18 Class I
25
50
1.660
0.790
0
0.83
SSTL-18 Class II
25
25
1.660
0.790
0
0.83
1.8-V HSTL Class I
50
1.660
0.790
0
0.83
1.8-V HSTL Class II
25
1.660
0.790
0
0.83
1.5-V HSTL Class I
50
1.375
0.648
0
0.6875
1.5-V HSTL Class II
25
1.375
0.648
1.2-V HSTL with OCT
Differential SSTL-2 Class I
Altera Corporation
May 2008
1.140
25
50
2.325
1.123
0
0.6875
0
0.570
0
1.1625
4–37
Arria GX Device Handbook, Volume 1
I/O Timing Model
Table 4–44. Output Timing Measurement Methodology for Output Pins Notes (1), (2), (3) (Part 2 of 2)
Measurement
Point
Loading and Termination
I/O Standard
RS (Ω)
RD (Ω)
RT (Ω)
VCCIO (V)
VTT (V)
CL (pF)
VMEAS (V)
Differential SSTL-2 Class II
25
25
2.325
1.123
0
1.1625
Differential SSTL-18 Class I
50
50
1.660
0.790
0
0.83
Differential SSTL-18 Class II
25
25
1.660
0.790
0
0.83
1.5-V differential HSTL Class I
50
1.375
0.648
0
0.6875
1.5-V differential HSTL Class II
25
1.375
0.648
0
0.6875
1.8-V differential HSTL Class I
50
1.660
0.790
0
0.83
25
1.660
0.790
1.8-V differential HSTL Class II
0
0.83
LVDS
100
2.325
0
1.1625
LVPECL
100
3.135
0
1.5675
Notes to Table 4–44:
(1)
(2)
(3)
(4)
(5)
Input measurement point at internal node is 0.5 VCCINT.
Output measuring point for VMEAS at buffer output is 0.5 VCCIO.
Input stimulus edge rate is 0 to VCC in 0.2 ns (internal signal) from the driver preceding the I/O buffer.
Less than 50-mV ripple on VCCIO and VCCPD, VCCINT = 1.15 V with less than 30-mV ripple.
VCCPD = 2.97 V, less than 50-mV ripple on VCCIO and VCCPD, VCCINT = 1.15 V.
4–38
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Figures 4–8 and 4–9 show the measurement setup for output disable and
output enable timing.
Figure 4–8. Measurement Setup for txz Note (1)
tXZ, Driving High to Tristate
Enable
OE
OE
½ VCCINT
Dout
Din
100 Ω
Disable
“1”
Din
100 mv
Dout
thz
GND
tXZ, Driving Low to Tristate
Enable
OE
100 Ω
Disable
½ VCCINT
OE
Dout
Din
Din
Dout
“0”
tlz
VCCIO
100 mv
Note to Figure 4–8:
(1)
Altera Corporation
May 2008
VCCINT is 1.12 V for this measurement.
4–39
Arria GX Device Handbook, Volume 1
I/O Timing Model
Figure 4–9. Measurement Setup for tzx
tZX, Tristate to Driving High
Disable
OE
OE
Enable
½ VCCINT
Dout
Din
“1”
Din
1 MΩ
tzh
Dout
½ VCCIO
tZX, Tristate to Driving Low
Disable
Enable
½ VCCINT
OE
1 MΩ
OE
Dout
Din
“0”
Din
½ VCCIO
tzl
Dout
Table 4–45 specifies the input timing measurement setup.
Table 4–45. Timing Measurement Methodology for Input Pins Notes (1), (2), (3), (4) (Part 1 of 2)
Measurement Conditions
Measurement Point
I/O Standard
VCCIO (V)
LVTTL (5)
VREF (V)
3.135
Edge Rate (ns)
VMEAS (V)
3.135
1.5675
LVCMOS (5)
3.135
3.135
1.5675
2.5 V (5)
2.375
2.375
1.1875
1.8 V (5)
1.710
1.710
0.855
1.5 V (5)
1.425
1.425
0.7125
PCI (6)
2.970
2.970
1.485
PCI-X (6)
2.970
2.970
1.485
SSTL-2 Class I
2.325
1.163
2.325
1.1625
SSTL-2 Class II
2.325
1.163
2.325
1.1625
SSTL-18 Class I
1.660
0.830
1.660
0.83
SSTL-18 Class II
1.660
0.830
1.660
0.83
1.8-V HSTL Class I
1.660
0.830
1.660
0.83
4–40
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–45. Timing Measurement Methodology for Input Pins Notes (1), (2), (3), (4) (Part 2 of 2)
Measurement Conditions
Measurement Point
I/O Standard
VCCIO (V)
VREF (V)
Edge Rate (ns)
VMEAS (V)
1.8-V HSTL Class II
1.660
0.830
1.660
0.83
1.5-V HSTL Class I
1.375
0.688
1.375
0.6875
1.5-V HSTL Class II
1.375
0.688
1.375
0.6875
1.2-V HSTL with OCT
1.140
0.570
1.140
0.570
Differential SSTL-2 Class I
2.325
1.163
2.325
1.1625
Differential SSTL-2 Class II
2.325
1.163
2.325
1.1625
Differential SSTL-18 Class I
1.660
0.830
1.660
0.83
Differential SSTL-18 Class II
1.660
0.830
1.660
0.83
1.5-V differential HSTL Class I
1.375
0.688
1.375
0.6875
1.5-V differential HSTL Class II
1.375
0.688
1.375
0.6875
1.8-V differential HSTL Class I
1.660
0.830
1.660
0.83
1.8-V differential HSTL Class II
1.660
0.830
1.660
0.83
LVDS
2.325
0.100
1.1625
LVPECL
3.135
0.100
1.5675
Notes to Table 4–45:
(1)
(2)
(3)
(4)
(5)
(6)
Input buffer sees no load at buffer input.
Input measuring point at buffer input is 0.5 VCCIO.
Output measuring point is 0.5 VCC at internal node.
Input edge rate is 1 V/ns.
Less than 50-mV ripple on VCCIO and VCCPD, VCCINT = 1.15 V with less than 30-mV ripple.
VCCPD = 2.97 V, less than 50-mV ripple on VCCIO and VCCPD, VCCINT = 1.15 V.
Clock Network Skew Adders
The Quartus II software models skew within dedicated clock networks
such as global and regional clocks. Therefore, the intra-clock network
skew adder is not specified. Table 4–46 specifies the clock skew between
any two clock networks driving registers in the I/O element (IOE).
Table 4–46. Clock Network Specifications
Name
(Part 1 of 2)
Description
Min
Typ
Max
Unit
Clock skew adder
EP1AGX20/35 (1)
Inter-clock network, same side
± 50
ps
Inter-clock network, entire chip
± 100
ps
Clock skew adder
EP1AGX50/60 (1)
Inter-clock network, same side
± 50
ps
Inter-clock network, entire chip
± 100
ps
Altera Corporation
May 2008
4–41
Arria GX Device Handbook, Volume 1
I/O Timing Model
Table 4–46. Clock Network Specifications
Name
Clock skew adder
EP1AGX90 (1)
(Part 2 of 2)
Description
Min
Typ
Max
Unit
Inter-clock network, same side
± 55
ps
Inter-clock network, entire chip
± 110
ps
Notes to Table 4–46:
(1)
This is in addition to intra-clock network skew, which is modeled in the Quartus II software.
Default Capacitive Loading of Different I/O Standards
See Table 4–47 for default capacitive loading of different I/O standards.
Table 4–47. Default Loading of Different I/O Standards for Arria GX
Devices (Part 1 of 2)
I/O Standard
Capacitive Load
Unit
LVTTL
0
pF
LVCMOS
0
pF
2.5 V
0
pF
1.8 V
0
pF
1.5 V
0
pF
PCI
10
pF
PCI-X
10
pF
SSTL-2 Class I
0
pF
SSTL-2 Class II
0
pF
SSTL-18 Class I
0
pF
SSTL-18 Class II
0
pF
1.5-V HSTL Class I
0
pF
1.5-V HSTL Class II
0
pF
1.8-V HSTL Class I
0
pF
1.8-V HSTL Class II
0
pF
Differential SSTL-2 Class I
0
pF
Differential SSTL-2 Class II
0
pF
Differential SSTL-18 Class I
0
pF
Differential SSTL-18 Class II
0
pF
1.5-V differential HSTL Class I
0
pF
1.5-V differential HSTL Class II
0
pF
1.8-V differential HSTL Class I
0
pF
4–42
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–47. Default Loading of Different I/O Standards for Arria GX
Devices (Part 2 of 2)
I/O Standard
Typical Design
Performance
Capacitive Load
Unit
1.8-V differential HSTL Class II
0
pF
LVDS
0
pF
The following section describes the typical design performance for the
Arria GX device family.
User I/O Pin Timing
Tables 4–48 to 4–77 show user I/O pin timing for Arria GX devices. I/O
buffer tSU, tH, and tCO are reported for the cases when I/O clock is driven
by a non-PLL global clock (GCLK) and a PLL driven global clock
(GCLK-PLL). For tSU, tH, and tCO using regional clock, add the value from
the adder tables listed for each device to the GCLK/GCLK-PLL values for
the device.
EP1AGX20 I/O Timing Parameters
Tables 4–48 through 4–51 show the maximum I/O timing parameters for
EP1AGX20 devices for I/O standards which support general purpose
I/O pins.
Table 4–48 describes the row pin delay adders when using the regional
clock in Arria GX devices.
Table 4–48. EP1AGX20 Row Pin Delay Adders for Regional Clock
Fast Corner
Industrial
Commercial
-6 Speed
Grade
0.117
0.117
0.273
ns
0.011
0.011
0.019
ns
-0.117
-0.117
-0.273
ns
-0.011
-0.011
-0.019
ns
Parameter
RCLK input
Units
adder
RCLK PLL
input adder
RCLK output
adder
RCLK PLL
output adder
Altera Corporation
May 2008
4–43
Arria GX Device Handbook, Volume 1
Typical Design Performance
Table 4–49 describes I/O timing specifications.
Table 4–49. EP1AGX20 Column Pins Input Timing Parameters (Part 1 of 3)
Fast Corner
I/O Standard
Clock
tSU
1.251
1.251
2.915
tH
-1.146
-1.146
-2.638
ns
GCLK PLL
tSU
2.693
2.693
6.021
ns
tH
-2.588
-2.588
-5.744
ns
GCLK
tSU
1.251
1.251
2.915
ns
tH
-1.146
-1.146
-2.638
ns
GCLK PLL
tSU
2.693
2.693
6.021
ns
tH
-2.588
-2.588
-5.744
ns
tSU
1.261
1.261
2.897
ns
tH
-1.156
-1.156
-2.620
ns
GCLK PLL
tSU
2.703
2.703
6.003
ns
tH
-2.598
-2.598
-5.726
ns
GCLK
tSU
1.327
1.327
3.107
ns
tH
-1.222
-1.222
-2.830
ns
GCLK PLL
tSU
2.769
2.769
6.213
ns
tH
-2.664
-2.664
-5.936
ns
GCLK
tSU
1.330
1.330
3.200
ns
tH
-1.225
-1.225
-2.923
ns
GCLK
2.5 V
1.8 V
1.5 V
tSU
2.772
2.772
6.306
ns
tH
-2.667
-2.667
-6.029
ns
GCLK
tSU
1.075
1.075
2.372
ns
tH
-0.970
-0.970
-2.095
ns
GCLK PLL
tSU
2.517
2.517
5.480
ns
tH
-2.412
-2.412
-5.203
ns
GCLK
tSU
1.075
1.075
2.372
ns
tH
-0.970
-0.970
-2.095
ns
GCLK PLL
tSU
2.517
2.517
5.480
ns
tH
-2.412
-2.412
-5.203
ns
GCLK PLL
SSTL-2
CLASS I
SSTL-2
CLASS II
ns
GCLK
3.3-V LVTTL
3.3-V
LVCMOS
Commercial
-6 Speed
Grade
Units
Industrial
Parameter
4–44
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–49. EP1AGX20 Column Pins Input Timing Parameters (Part 2 of 3)
Fast Corner
I/O Standard
SSTL-18
CLASS I
Clock
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS II
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS II
Commercial
Units
ns
GCLK
tSU
1.113
1.113
2.479
tH
-1.008
-1.008
-2.202
ns
GCLK PLL
tSU
2.555
2.555
5.585
ns
tH
-2.450
-2.450
-5.308
ns
tSU
1.114
1.114
2.479
ns
tH
-1.009
-1.009
-2.202
ns
GCLK PLL
tSU
2.556
2.556
5.587
ns
tH
-2.451
-2.451
-5.310
ns
GCLK
tSU
1.113
1.113
2.479
ns
tH
-1.008
-1.008
-2.202
ns
GCLK PLL
tSU
2.555
2.555
5.585
ns
tH
-2.450
-2.450
-5.308
ns
GCLK
tSU
1.114
1.114
2.479
ns
tH
-1.009
-1.009
-2.202
ns
GCLK
SSTL-18
CLASS II
Industrial
-6 Speed
Grade
Parameter
tSU
2.556
2.556
5.587
ns
tH
-2.451
-2.451
-5.310
ns
GCLK
tSU
1.131
1.131
2.607
ns
tH
-1.026
-1.026
-2.330
ns
GCLK PLL
tSU
2.573
2.573
5.713
ns
tH
-2.468
-2.468
-5.436
ns
GCLK
tSU
1.132
1.132
2.607
ns
tH
-1.027
-1.027
-2.330
ns
GCLK PLL
tSU
2.574
2.574
5.715
ns
tH
-2.469
-2.469
-5.438
ns
GCLK PLL
GCLK
3.3-V PCI
GCLK PLL
Altera Corporation
May 2008
tSU
1.256
1.256
2.903
ns
tH
-1.151
-1.151
-2.626
ns
tSU
2.698
2.698
6.009
ns
tH
-2.593
-2.593
-5.732
ns
4–45
Arria GX Device Handbook, Volume 1
Typical Design Performance
Table 4–49. EP1AGX20 Column Pins Input Timing Parameters (Part 3 of 3)
Fast Corner
I/O Standard
Clock
Industrial
Commercial
-6 Speed
Grade
Parameter
Units
ns
GCLK
tSU
1.256
1.256
2.903
tH
-1.151
-1.151
-2.626
ns
GCLK PLL
tSU
2.698
2.698
6.009
ns
tH
-2.593
-2.593
-5.732
ns
3.3-V PCI-X
GCLK
LVDS
GCLK PLL
tSU
1.106
1.106
2.489
ns
tH
-1.001
-1.001
-2.212
ns
tSU
2.530
2.530
5.564
ns
tH
-2.425
-2.425
-5.287
ns
Table 4–50 describes I/O timing specifications.
Table 4–50. EP1AGX20 Row Pins output Timing Parameters (Part 1 of 3)
I/O
Standard
Fast Model
Drive
Strength
Clock
3.3-V
LVTTL
4 mA
GCLK
3.3-V
LVTTL
8 mA
3.3-V
LVTTL
12 mA
3.3-V
LVCMOS
4 mA
3.3-V
LVCMOS
8 mA
2.5 V
4 mA
2.5 V
8 mA
2.5 V
12 mA
Industrial
Commercial
-6 Speed
Grade
tCO
2.904
2.904
6.699
ns
GCLK PLL
tCO
1.485
1.485
3.627
ns
GCLK
tCO
2.776
2.776
6.059
ns
GCLK PLL
tCO
1.357
1.357
2.987
ns
GCLK
tCO
2.720
2.720
6.022
ns
GCLK PLL
tCO
1.301
1.301
2.950
ns
Parameter
Units
GCLK
tCO
2.776
2.776
6.059
ns
GCLK PLL
tCO
1.357
1.357
2.987
ns
GCLK
tCO
2.670
2.670
5.753
ns
GCLK PLL
tCO
1.251
1.251
2.681
ns
GCLK
tCO
2.759
2.759
6.033
ns
GCLK PLL
tCO
1.340
1.340
2.961
ns
GCLK
tCO
2.656
2.656
5.775
ns
GCLK PLL
tCO
1.237
1.237
2.703
ns
GCLK
tCO
2.637
2.637
5.661
ns
GCLK PLL
tCO
1.218
1.218
2.589
ns
4–46
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–50. EP1AGX20 Row Pins output Timing Parameters (Part 2 of 3)
I/O
Standard
Fast Model
Drive
Strength
Clock
1.8 V
2 mA
GCLK
1.8 V
4 mA
1.8 V
6 mA
1.8 V
8 mA
1.5 V
2 mA
1.5 V
4 mA
SSTL-2
CLASS I
8 mA
SSTL-2
CLASS I
12 mA
SSTL-2
CLASS II
16 mA
SSTL-18
CLASS I
4 mA
SSTL-18
CLASS I
6 mA
SSTL-18
CLASS I
8 mA
SSTL-18
CLASS I
10 mA
1.8-V HSTL
CLASS I
4 mA
1.8-V HSTL
CLASS I
6 mA
Altera Corporation
May 2008
Industrial
Commercial
-6 Speed
Grade
tCO
2.829
2.829
7.052
ns
GCLK PLL
tCO
1.410
1.410
3.980
ns
GCLK
tCO
2.818
2.818
6.273
ns
GCLK PLL
tCO
1.399
1.399
3.201
ns
Parameter
Units
GCLK
tCO
2.707
2.707
5.972
ns
GCLK PLL
tCO
1.288
1.288
2.900
ns
GCLK
tCO
2.676
2.676
5.858
ns
GCLK PLL
tCO
1.257
1.257
2.786
ns
GCLK
tCO
2.789
2.789
6.551
ns
GCLK PLL
tCO
1.370
1.370
3.479
ns
GCLK
tCO
2.682
2.682
5.950
ns
GCLK PLL
tCO
1.263
1.263
2.878
ns
GCLK
tCO
2.626
2.626
5.614
ns
GCLK PLL
tCO
1.207
1.207
2.542
ns
GCLK
tCO
2.602
2.602
5.538
ns
GCLK PLL
tCO
1.183
1.183
2.466
ns
GCLK
tCO
2.568
2.568
5.407
ns
GCLK PLL
tCO
1.149
1.149
2.335
ns
GCLK
tCO
2.614
2.614
5.556
ns
GCLK PLL
tCO
1.195
1.195
2.484
ns
GCLK
tCO
2.618
2.618
5.485
ns
GCLK PLL
tCO
1.199
1.199
2.413
ns
GCLK
tCO
2.594
2.594
5.468
ns
GCLK PLL
tCO
1.175
1.175
2.396
ns
GCLK
tCO
2.597
2.597
5.447
ns
GCLK PLL
tCO
1.178
1.178
2.375
ns
GCLK
tCO
2.595
2.595
5.466
ns
GCLK PLL
tCO
1.176
1.176
2.394
ns
GCLK
tCO
2.598
2.598
5.430
ns
GCLK PLL
tCO
1.179
1.179
2.358
ns
4–47
Arria GX Device Handbook, Volume 1
Typical Design Performance
Table 4–50. EP1AGX20 Row Pins output Timing Parameters (Part 3 of 3)
Fast Model
I/O
Standard
Drive
Strength
Clock
1.8-V HSTL
CLASS I
8 mA
GCLK
1.8-V HSTL
CLASS I
10 mA
1.8-V HSTL
CLASS I
12 mA
1.5-V HSTL
CLASS I
4 mA
1.5-V HSTL
CLASS I
6 mA
1.5-V HSTL
CLASS I
8 mA
LVDS
-
Industrial
Commercial
-6 Speed
Grade
tCO
2.580
2.580
5.426
ns
GCLK PLL
tCO
1.161
1.161
2.354
ns
GCLK
tCO
2.584
2.584
5.415
ns
GCLK PLL
tCO
1.165
1.165
2.343
ns
Parameter
Units
GCLK
tCO
2.575
2.575
5.414
ns
GCLK PLL
tCO
1.156
1.156
2.342
ns
GCLK
tCO
2.594
2.594
5.443
ns
GCLK PLL
tCO
1.175
1.175
2.371
ns
GCLK
tCO
2.597
2.597
5.429
ns
GCLK PLL
tCO
1.178
1.178
2.357
ns
GCLK
tCO
2.582
2.582
5.421
ns
GCLK PLL
tCO
1.163
1.163
2.349
ns
GCLK
tCO
2.654
2.654
5.613
ns
GCLK PLL
tCO
1.226
1.226
2.530
ns
Units
Table 4–51 describes I/O timing specifications.
Table 4–51. EP1AGX20 Column Pins Output Timing Parameters (Part 1 of 5)
I/O
Standard
Drive
Strength
3.3-V
LVTTL
4 mA
3.3-V
LVTTL
8 mA
3.3-V
LVTTL
12 mA
3.3-V
LVTTL
16 mA
3.3-V
LVTTL
20 mA
Fast Corner
Clock
Industrial
Commercial
-6 Speed
Grade
Parameter
GCLK
tCO
2.909
2.909
6.541
ns
GCLK PLL
tCO
1.467
1.467
3.435
ns
GCLK
tCO
2.764
2.764
6.169
ns
GCLK PLL
tCO
1.322
1.322
3.063
ns
GCLK
tCO
2.697
2.697
6.169
ns
GCLK PLL
tCO
1.255
1.255
3.063
ns
GCLK
tCO
2.671
2.671
6.000
ns
GCLK PLL
tCO
1.229
1.229
2.894
ns
GCLK
tCO
2.649
2.649
5.875
ns
GCLK PLL
tCO
1.207
1.207
2.769
ns
4–48
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–51. EP1AGX20 Column Pins Output Timing Parameters (Part 2 of 5)
I/O
Standard
Fast Corner
Drive
Strength
Clock
3.3-V
LVTTL
24 mA
GCLK
3.3-V
LVCMOS
4 mA
3.3-V
LVCMOS
8 mA
3.3-V
LVCMOS
12 mA
3.3-V
LVCMOS
16 mA
3.3-V
LVCMOS
20 mA
3.3-V
LVCMOS
24 mA
2.5 V
4 mA
2.5 V
8 mA
2.5 V
12 mA
2.5 V
16 mA
1.8 V
2 mA
1.8 V
4 mA
1.8 V
6 mA
1.8 V
8 mA
Altera Corporation
May 2008
Industrial
Commercial
-6 Speed
Grade
tCO
2.642
2.642
5.877
ns
GCLK PLL
tCO
1.200
1.200
2.771
ns
GCLK
tCO
2.764
2.764
6.169
ns
GCLK PLL
tCO
1.322
1.322
3.063
ns
Parameter
Units
GCLK
tCO
2.672
2.672
5.874
ns
GCLK PLL
tCO
1.230
1.230
2.768
ns
GCLK
tCO
2.644
2.644
5.796
ns
GCLK PLL
tCO
1.202
1.202
2.690
ns
GCLK
tCO
2.651
2.651
5.764
ns
GCLK PLL
tCO
1.209
1.209
2.658
ns
GCLK
tCO
2.638
2.638
5.746
ns
GCLK PLL
tCO
1.196
1.196
2.640
ns
GCLK
tCO
2.627
2.627
5.724
ns
GCLK PLL
tCO
1.185
1.185
2.618
ns
GCLK
tCO
2.726
2.726
6.201
ns
GCLK PLL
tCO
1.284
1.284
3.095
ns
GCLK
tCO
2.674
2.674
5.939
ns
GCLK PLL
tCO
1.232
1.232
2.833
ns
GCLK
tCO
2.653
2.653
5.822
ns
GCLK PLL
tCO
1.211
1.211
2.716
ns
GCLK
tCO
2.635
2.635
5.748
ns
GCLK PLL
tCO
1.193
1.193
2.642
ns
GCLK
tCO
2.766
2.766
7.193
ns
GCLK PLL
tCO
1.324
1.324
4.087
ns
GCLK
tCO
2.771
2.771
6.419
ns
GCLK PLL
tCO
1.329
1.329
3.313
ns
GCLK
tCO
2.695
2.695
6.155
ns
GCLK PLL
tCO
1.253
1.253
3.049
ns
GCLK
tCO
2.697
2.697
6.064
ns
GCLK PLL
tCO
1.255
1.255
2.958
ns
4–49
Arria GX Device Handbook, Volume 1
Typical Design Performance
Table 4–51. EP1AGX20 Column Pins Output Timing Parameters (Part 3 of 5)
I/O
Standard
Fast Corner
Drive
Strength
Clock
1.8 V
10 mA
GCLK
1.8 V
12 mA
1.5 V
2 mA
1.5 V
4 mA
1.5 V
6 mA
1.5 V
8 mA
SSTL-2
CLASS I
8 mA
SSTL-2
CLASS I
12 mA
SSTL-2
CLASS II
16 mA
SSTL-2
CLASS II
20 mA
SSTL-2
CLASS II
24 mA
SSTL-18
CLASS I
4 mA
SSTL-18
CLASS I
6 mA
SSTL-18
CLASS I
8 mA
SSTL-18
CLASS I
10 mA
Industrial
Commercial
-6 Speed
Grade
tCO
2.651
2.651
5.987
ns
GCLK PLL
tCO
1.209
1.209
2.881
ns
GCLK
tCO
2.652
2.652
5.930
ns
GCLK PLL
tCO
1.210
1.210
2.824
ns
Parameter
Units
GCLK
tCO
2.746
2.746
6.723
ns
GCLK PLL
tCO
1.304
1.304
3.617
ns
GCLK
tCO
2.682
2.682
6.154
ns
GCLK PLL
tCO
1.240
1.240
3.048
ns
GCLK
tCO
2.685
2.685
6.036
ns
GCLK PLL
tCO
1.243
1.243
2.930
ns
GCLK
tCO
2.644
2.644
5.983
ns
GCLK PLL
tCO
1.202
1.202
2.877
ns
GCLK
tCO
2.629
2.629
5.762
ns
GCLK PLL
tCO
1.184
1.184
2.650
ns
GCLK
tCO
2.612
2.612
5.712
ns
GCLK PLL
tCO
1.167
1.167
2.600
ns
GCLK
tCO
2.590
2.590
5.639
ns
GCLK PLL
tCO
1.145
1.145
2.527
ns
GCLK
tCO
2.591
2.591
5.626
ns
GCLK PLL
tCO
1.146
1.146
2.514
ns
GCLK
tCO
2.587
2.587
5.624
ns
GCLK PLL
tCO
1.142
1.142
2.512
ns
GCLK
tCO
2.626
2.626
5.733
ns
GCLK PLL
tCO
1.184
1.184
2.627
ns
GCLK
tCO
2.630
2.630
5.694
ns
GCLK PLL
tCO
1.185
1.185
2.582
ns
GCLK
tCO
2.609
2.609
5.675
ns
GCLK PLL
tCO
1.164
1.164
2.563
ns
GCLK
tCO
2.614
2.614
5.673
ns
GCLK PLL
tCO
1.169
1.169
2.561
ns
4–50
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–51. EP1AGX20 Column Pins Output Timing Parameters (Part 4 of 5)
I/O
Standard
Fast Corner
Drive
Strength
Clock
SSTL-18
CLASS I
12 mA
GCLK
SSTL-18
CLASS II
8 mA
SSTL-18
CLASS II
16 mA
SSTL-18
CLASS II
18 mA
SSTL-18
CLASS II
20 mA
1.8-V HSTL
CLASS I
4 mA
1.8-V HSTL
CLASS I
6 mA
1.8-V HSTL
CLASS I
8 mA
1.8-V HSTL
CLASS I
10 mA
1.8-V HSTL
CLASS I
12 mA
1.8-V HSTL
CLASS II
16 mA
1.8-V HSTL
CLASS II
18 mA
1.8-V HSTL
CLASS II
20 mA
1.5-V HSTL
CLASS I
4 mA
1.5-V HSTL
CLASS I
6 mA
Altera Corporation
May 2008
Industrial
Commercial
-6 Speed
Grade
tCO
2.608
2.608
5.659
ns
GCLK PLL
tCO
1.163
1.163
2.547
ns
GCLK
tCO
2.597
2.597
5.625
ns
GCLK PLL
tCO
1.152
1.152
2.513
ns
Parameter
Units
GCLK
tCO
2.609
2.609
5.603
ns
GCLK PLL
tCO
1.164
1.164
2.491
ns
GCLK
tCO
2.605
2.605
5.611
ns
GCLK PLL
tCO
1.160
1.160
2.499
ns
GCLK
tCO
2.605
2.605
5.609
ns
GCLK PLL
tCO
1.160
1.160
2.497
ns
GCLK
tCO
2.629
2.629
5.664
ns
GCLK PLL
tCO
1.187
1.187
2.558
ns
GCLK
tCO
2.634
2.634
5.649
ns
GCLK PLL
tCO
1.189
1.189
2.537
ns
GCLK
tCO
2.612
2.612
5.638
ns
GCLK PLL
tCO
1.167
1.167
2.526
ns
GCLK
tCO
2.616
2.616
5.644
ns
GCLK PLL
tCO
1.171
1.171
2.532
ns
GCLK
tCO
2.608
2.608
5.637
ns
GCLK PLL
tCO
1.163
1.163
2.525
ns
GCLK
tCO
2.591
2.591
5.401
ns
GCLK PLL
tCO
1.146
1.146
2.289
ns
GCLK
tCO
2.593
2.593
5.412
ns
GCLK PLL
tCO
1.148
1.148
2.300
ns
GCLK
tCO
2.593
2.593
5.421
ns
GCLK PLL
tCO
1.148
1.148
2.309
ns
GCLK
tCO
2.629
2.629
5.663
ns
GCLK PLL
tCO
1.187
1.187
2.557
ns
GCLK
tCO
2.633
2.633
5.641
ns
GCLK PLL
tCO
1.188
1.188
2.529
ns
4–51
Arria GX Device Handbook, Volume 1
Typical Design Performance
Table 4–51. EP1AGX20 Column Pins Output Timing Parameters (Part 5 of 5)
Fast Corner
I/O
Standard
Drive
Strength
Clock
1.5-V HSTL
CLASS I
8 mA
GCLK
1.5-V HSTL
CLASS I
10 mA
1.5-V HSTL
CLASS I
12 mA
1.5-V HSTL
CLASS II
16 mA
1.5-V HSTL
CLASS II
18 mA
1.5-V HSTL
CLASS II
20 mA
3.3-V PCI
3.3-V PCI-X
LVDS
-
-
-
Industrial
Commercial
-6 Speed
Grade
tCO
2.615
2.615
5.643
ns
GCLK PLL
tCO
1.170
1.170
2.531
ns
GCLK
tCO
2.615
2.615
5.645
ns
GCLK PLL
tCO
1.170
1.170
2.533
ns
Parameter
Units
GCLK
tCO
2.609
2.609
5.643
ns
GCLK PLL
tCO
1.164
1.164
2.531
ns
GCLK
tCO
2.596
2.596
5.455
ns
GCLK PLL
tCO
1.151
1.151
2.343
ns
GCLK
tCO
2.599
2.599
5.465
ns
GCLK PLL
tCO
1.154
1.154
2.353
ns
GCLK
tCO
2.601
2.601
5.478
ns
GCLK PLL
tCO
1.156
1.156
2.366
ns
GCLK
tCO
2.755
2.755
5.791
ns
GCLK PLL
tCO
1.313
1.313
2.685
ns
GCLK
tCO
2.755
2.755
5.791
ns
GCLK PLL
tCO
1.313
1.313
2.685
ns
GCLK
tCO
3.621
3.621
6.969
ns
GCLK PLL
tCO
2.190
2.190
3.880
ns
Tables 4–52 through 4–53 shows EP1AGX20 regional clock (RCLK) adder
values that should be added to GCLK values. These adder values are used
to determine I/O timing when the I/O pin is driven using the regional
clock. This applies for all I/O standards supported by Arria GX with
general purpose I/O pins.
4–52
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–52 describes row pin delay adders when using the regional clock
in Arria GX devices.
Table 4–52. EP1AGX20 Row Pin Delay Adders for Regional Clock
Fast Corner
Industrial
Commercial
-6 Speed
Grade
0.117
0.117
0.273
ns
0.011
0.011
0.019
ns
-0.117
-0.117
-0.273
ns
-0.011
-0.011
-0.019
ns
Parameter
RCLK input
Units
adder
RCLK PLL
input adder
RCLK output
adder
RCLK PLL
output adder
Table 4–53 describes column pin delay adders when using the regional
clock in Arria GX devices.
Table 4–53. EP1AGX20 Column Pin Delay Adders for Regional Clock
Fast Corner
Industrial
Commercial
-6 Speed
Grade
0.081
0.081
0.223
ns
-0.012
-0.012
-0.008
ns
-0.081
-0.081
-0.224
ns
1.11
1.11
2.658
ns
Parameter
RCLK input
Units
adder
RCLK PLL
input adder
RCLK output
adder
RCLK PLL
output adder
Altera Corporation
May 2008
4–53
Arria GX Device Handbook, Volume 1
Typical Design Performance
EP1AGX35 I/O Timing Parameters
Tables 4–54 through 4–57 show the maximum I/O timing parameters for
EP1AGX35 devices for I/O standards which support general purpose
I/O pins.
Table 4–54 describes I/O timing specifications.
Table 4–54. EP1AGX35 Row Pins Input Timing Parameters (Part 1 of 3)
Fast Model
I/O Standard
Clock
GCLK
3.3-V LVTTL
GCLK PLL
GCLK
3.3-V
LVCMOS
Commercial
tSU
1.561
1.561
3.556
ns
tH
-1.456
-1.456
-3.279
ns
Units
tSU
2.980
2.980
6.628
ns
tH
-2.875
-2.875
-6.351
ns
tSU
1.561
1.561
3.556
ns
tH
-1.456
-1.456
-3.279
ns
tSU
2.980
2.980
6.628
ns
tH
-2.875
-2.875
-6.351
ns
GCLK
tSU
1.573
1.573
3.537
ns
tH
-1.468
-1.468
-3.260
ns
GCLK PLL
tSU
2.992
2.992
6.609
ns
tH
-2.887
-2.887
-6.332
ns
GCLK PLL
2.5 V
GCLK
1.8 V
GCLK PLL
tSU
1.639
1.639
3.744
ns
tH
-1.534
-1.534
-3.467
ns
tSU
3.058
3.058
6.816
ns
tH
-2.953
-2.953
-6.539
ns
tSU
1.642
1.642
3.839
ns
tH
-1.537
-1.537
-3.562
ns
GCLK PLL
tSU
3.061
3.061
6.911
ns
tH
-2.956
-2.956
-6.634
ns
GCLK
tSU
1.385
1.385
3.009
ns
tH
-1.280
-1.280
-2.732
ns
GCLK
1.5 V
SSTL-2
CLASS I
Industrial
-6 Speed
Grade
Parameter
GCLK PLL
tSU
2.804
2.804
6.081
ns
tH
-2.699
-2.699
-5.804
ns
4–54
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–54. EP1AGX35 Row Pins Input Timing Parameters (Part 2 of 3)
Fast Model
I/O Standard
SSTL-2
CLASS II
Clock
SSTL-18
CLASS II
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS II
1.5-V HSTL
CLASS I
Units
tSU
1.385
1.385
3.009
ns
tH
-1.280
-1.280
-2.732
ns
GCLK PLL
tSU
2.804
2.804
6.081
ns
tH
-2.699
-2.699
-5.804
ns
tSU
1.417
1.417
3.118
ns
tH
-1.312
-1.312
-2.841
ns
GCLK PLL
tSU
2.836
2.836
6.190
ns
tH
-2.731
-2.731
-5.913
ns
GCLK
tSU
1.417
1.417
3.118
ns
tH
-1.312
-1.312
-2.841
ns
GCLK PLL
tSU
2.836
2.836
6.190
ns
tH
-2.731
-2.731
-5.913
ns
GCLK
tSU
1.417
1.417
3.118
ns
tH
-1.312
-1.312
-2.841
ns
tSU
2.836
2.836
6.190
ns
tH
-2.731
-2.731
-5.913
ns
GCLK
tSU
1.417
1.417
3.118
ns
tH
-1.312
-1.312
-2.841
ns
GCLK PLL
tSU
2.836
2.836
6.190
ns
tH
-2.731
-2.731
-5.913
ns
GCLK
tSU
1.443
1.443
3.246
ns
tH
-1.338
-1.338
-2.969
ns
GCLK PLL
tSU
2.862
2.862
6.318
ns
tH
-2.757
-2.757
-6.041
ns
GCLK PLL
GCLK
1.5-V HSTL
CLASS II
Commercial
GCLK
GCLK
SSTL-18
CLASS I
Industrial
-6 Speed
Grade
Parameter
GCLK PLL
Altera Corporation
May 2008
tSU
1.443
1.443
3.246
ns
tH
-1.338
-1.338
-2.969
ns
tSU
2.862
2.862
6.318
ns
tH
-2.757
-2.757
-6.041
ns
4–55
Arria GX Device Handbook, Volume 1
Typical Design Performance
Table 4–54. EP1AGX35 Row Pins Input Timing Parameters (Part 3 of 3)
Fast Model
I/O Standard
Clock
Industrial
Commercial
-6 Speed
Grade
Parameter
Units
GCLK
tSU
1.341
1.341
3.088
ns
tH
-1.236
-1.236
-2.811
ns
GCLK PLL
tSU
2.769
2.769
6.171
ns
tH
-2.664
-2.664
-5.894
ns
-6 Speed
Grade
Units
LVDS
Table 4–55 describes I/O timing specifications.
Table 4–55. EP1AGX35 Column Pins Input Timing Parameters (Part 1 of 3)
Fast Corner
I/O Standard
Clock
Parameter
Industrial
tSU
1.251
1.251
2.915
ns
tH
-1.146
-1.146
-2.638
ns
GCLK PLL
tSU
2.693
2.693
6.021
ns
tH
-2.588
-2.588
-5.744
ns
GCLK
tSU
1.251
1.251
2.915
ns
tH
-1.146
-1.146
-2.638
ns
GCLK PLL
tSU
2.693
2.693
6.021
ns
tH
-2.588
-2.588
-5.744
ns
GCLK
tSU
1.261
1.261
2.897
ns
tH
-1.156
-1.156
-2.620
ns
GCLK
3.3-V LVTTL
3.3-V
LVCMOS
Commercial
2.5 V
tSU
2.703
2.703
6.003
ns
tH
-2.598
-2.598
-5.726
ns
GCLK
tSU
1.327
1.327
3.107
ns
tH
-1.222
-1.222
-2.830
ns
GCLK PLL
tSU
2.769
2.769
6.213
ns
tH
-2.664
-2.664
-5.936
ns
GCLK
tSU
1.330
1.330
3.200
ns
tH
-1.225
-1.225
-2.923
ns
GCLK PLL
tSU
2.772
2.772
6.306
ns
tH
-2.667
-2.667
-6.029
ns
GCLK PLL
1.8 V
1.5 V
4–56
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–55. EP1AGX35 Column Pins Input Timing Parameters (Part 2 of 3)
Fast Corner
I/O Standard
SSTL-2
CLASS I
Clock
SSTL-18
CLASS I
SSTL-18
CLASS II
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS II
Units
tSU
1.075
1.075
2.372
ns
tH
-0.970
-0.970
-2.095
ns
GCLK PLL
tSU
2.517
2.517
5.480
ns
tH
-2.412
-2.412
-5.203
ns
tSU
1.075
1.075
2.372
ns
tH
-0.970
-0.970
-2.095
ns
GCLK PLL
tSU
2.517
2.517
5.480
ns
tH
-2.412
-2.412
-5.203
ns
GCLK
tSU
1.113
1.113
2.479
ns
tH
-1.008
-1.008
-2.202
ns
GCLK PLL
tSU
2.555
2.555
5.585
ns
tH
-2.450
-2.450
-5.308
ns
GCLK
tSU
1.114
1.114
2.479
ns
tH
-1.009
-1.009
-2.202
ns
tSU
2.556
2.556
5.587
ns
tH
-2.451
-2.451
-5.310
ns
GCLK
tSU
1.113
1.113
2.479
ns
tH
-1.008
-1.008
-2.202
ns
GCLK PLL
tSU
2.555
2.555
5.585
ns
tH
-2.450
-2.450
-5.308
ns
GCLK
tSU
1.114
1.114
2.479
ns
tH
-1.009
-1.009
-2.202
ns
GCLK PLL
tSU
2.556
2.556
5.587
ns
tH
-2.451
-2.451
-5.310
ns
GCLK PLL
GCLK
1.5-V HSTL
CLASS I
Commercial
GCLK
GCLK
SSTL-2
CLASS II
Industrial
-6 Speed
Grade
Parameter
GCLK PLL
Altera Corporation
May 2008
tSU
1.131
1.131
2.607
ns
tH
-1.026
-1.026
-2.330
ns
tSU
2.573
2.573
5.713
ns
tH
-2.468
-2.468
-5.436
ns
4–57
Arria GX Device Handbook, Volume 1
Typical Design Performance
Table 4–55. EP1AGX35 Column Pins Input Timing Parameters (Part 3 of 3)
Fast Corner
I/O Standard
1.5-V HSTL
CLASS II
Clock
Industrial
Commercial
-6 Speed
Grade
Parameter
Units
GCLK
tSU
1.132
1.132
2.607
ns
tH
-1.027
-1.027
-2.330
ns
GCLK PLL
tSU
2.574
2.574
5.715
ns
tH
-2.469
-2.469
-5.438
ns
tSU
1.256
1.256
2.903
ns
tH
-1.151
-1.151
-2.626
ns
GCLK PLL
tSU
2.698
2.698
6.009
ns
tH
-2.593
-2.593
-5.732
ns
GCLK
tSU
1.256
1.256
2.903
ns
tH
-1.151
-1.151
-2.626
ns
GCLK PLL
tSU
2.698
2.698
6.009
ns
tH
-2.593
-2.593
-5.732
ns
GCLK
tSU
1.106
1.106
2.489
ns
tH
-1.001
-1.001
-2.212
ns
GCLK
3.3-V PCI
3.3-V PCI-X
LVDS
GCLK PLL
tSU
2.530
2.530
5.564
ns
tH
-2.425
-2.425
-5.287
ns
Table 4–56 describes I/O timing specifications.
Table 4–56. EP1AGX35 Row Pins Output Timing Parameters (Part 1 of 3)
I/O
Standard
Fast Model
Drive
Strength
Clock
Commercial
-6 Speed
Grade
Units
Industrial
3.3-V
LVTTL
4 mA
GCLK
tCO
2.904
2.904
6.699
ns
3.3-V
LVTTL
8 mA
GCLK PLL
tCO
1.485
1.485
3.627
ns
GCLK
tCO
2.776
2.776
6.059
ns
GCLK PLL
tCO
1.357
1.357
2.987
ns
3.3-V
LVTTL
12 mA
GCLK
tCO
2.720
2.720
6.022
ns
3.3-V
LVCMOS
4 mA
GCLK PLL
tCO
1.301
1.301
2.950
ns
GCLK
tCO
2.776
2.776
6.059
ns
GCLK PLL
tCO
1.357
1.357
2.987
ns
4–58
Arria GX Device Handbook, Volume 1
Parameter
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–56. EP1AGX35 Row Pins Output Timing Parameters (Part 2 of 3)
I/O
Standard
Fast Model
Drive
Strength
Clock
3.3-V
LVCMOS
8 mA
GCLK
2.5 V
4 mA
2.5 V
8 mA
2.5 V
12 mA
1.8 V
2 mA
1.8 V
4 mA
1.8 V
6 mA
1.8 V
8 mA
1.5 V
2 mA
1.5 V
4 mA
SSTL-2
CLASS I
8 mA
SSTL-2
CLASS I
12 mA
SSTL-2
CLASS II
16 mA
SSTL-18
CLASS I
4 mA
SSTL-18
CLASS I
6 mA
Altera Corporation
May 2008
Industrial
Commercial
-6 Speed
Grade
tCO
2.670
2.670
5.753
ns
GCLK PLL
tCO
1.251
1.251
2.681
ns
GCLK
tCO
2.759
2.759
6.033
ns
GCLK PLL
tCO
1.340
1.340
2.961
ns
Parameter
Units
GCLK
tCO
2.656
2.656
5.775
ns
GCLK PLL
tCO
1.237
1.237
2.703
ns
GCLK
tCO
2.637
2.637
5.661
ns
GCLK PLL
tCO
1.218
1.218
2.589
ns
GCLK
tCO
2.829
2.829
7.052
ns
GCLK PLL
tCO
1.410
1.410
3.980
ns
GCLK
tCO
2.818
2.818
6.273
ns
GCLK PLL
tCO
1.399
1.399
3.201
ns
GCLK
tCO
2.707
2.707
5.972
ns
GCLK PLL
tCO
1.288
1.288
2.900
ns
GCLK
tCO
2.676
2.676
5.858
ns
GCLK PLL
tCO
1.257
1.257
2.786
ns
GCLK
tCO
2.789
2.789
6.551
ns
GCLK PLL
tCO
1.370
1.370
3.479
ns
GCLK
tCO
2.682
2.682
5.950
ns
GCLK PLL
tCO
1.263
1.263
2.878
ns
GCLK
tCO
2.626
2.626
5.614
ns
GCLK PLL
tCO
1.207
1.207
2.542
ns
GCLK
tCO
2.602
2.602
5.538
ns
GCLK PLL
tCO
1.183
1.183
2.466
ns
GCLK
tCO
2.568
2.568
5.407
ns
GCLK PLL
tCO
1.149
1.149
2.335
ns
GCLK
tCO
2.614
2.614
5.556
ns
GCLK PLL
tCO
1.195
1.195
2.484
ns
GCLK
tCO
2.618
2.618
5.485
ns
GCLK PLL
tCO
1.199
1.199
2.413
ns
4–59
Arria GX Device Handbook, Volume 1
Typical Design Performance
Table 4–56. EP1AGX35 Row Pins Output Timing Parameters (Part 3 of 3)
I/O
Standard
Fast Model
Drive
Strength
Clock
SSTL-18
CLASS I
8 mA
GCLK
SSTL-18
CLASS I
10 mA
1.8-V HSTL
CLASS I
4 mA
1.8-V HSTL
CLASS I
6 mA
1.8-V HSTL
CLASS I
8 mA
1.8-V HSTL
CLASS I
10 mA
1.8-V HSTL
CLASS I
12 mA
1.5-V HSTL
CLASS I
4 mA
1.5-V HSTL
CLASS I
6 mA
1.5-V HSTL
CLASS I
8 mA
LVDS
-
Industrial
Commercial
-6 Speed
Grade
tCO
2.594
2.594
5.468
ns
GCLK PLL
tCO
1.175
1.175
2.396
ns
GCLK
tCO
2.597
2.597
5.447
ns
GCLK PLL
tCO
1.178
1.178
2.375
ns
Parameter
Units
GCLK
tCO
2.595
2.595
5.466
ns
GCLK PLL
tCO
1.176
1.176
2.394
ns
GCLK
tCO
2.598
2.598
5.430
ns
GCLK PLL
tCO
1.179
1.179
2.358
ns
GCLK
tCO
2.580
2.580
5.426
ns
GCLK PLL
tCO
1.161
1.161
2.354
ns
GCLK
tCO
2.584
2.584
5.415
ns
GCLK PLL
tCO
1.165
1.165
2.343
ns
GCLK
tCO
2.575
2.575
5.414
ns
GCLK PLL
tCO
1.156
1.156
2.342
ns
GCLK
tCO
2.594
2.594
5.443
ns
GCLK PLL
tCO
1.175
1.175
2.371
ns
GCLK
tCO
2.597
2.597
5.429
ns
GCLK PLL
tCO
1.178
1.178
2.357
ns
GCLK
tCO
2.582
2.582
5.421
ns
GCLK PLL
tCO
1.163
1.163
2.349
ns
GCLK
tCO
2.654
2.654
5.613
ns
GCLK PLL
tCO
1.226
1.226
2.530
ns
Table 4–57 describes I/O timing specifications.
Table 4–57. EP1AGX35 Column Pins Output Timing Parameters (Part 1 of 5)
I/O
Standard
3.3-V
LVTTL
Fast Corner
Drive
Strength
Clock
4 mA
GCLK
GCLK PLL
4–60
Arria GX Device Handbook, Volume 1
Commercial
-6 Speed
Grade
Units
Industrial
tCO
2.909
2.909
6.541
ns
tCO
1.467
1.467
3.435
ns
Parameter
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–57. EP1AGX35 Column Pins Output Timing Parameters (Part 2 of 5)
I/O
Standard
Fast Corner
Drive
Strength
Clock
3.3-V
LVTTL
8 mA
GCLK
3.3-V
LVTTL
12 mA
3.3-V
LVTTL
16 mA
3.3-V
LVTTL
20 mA
3.3-V
LVTTL
24 mA
3.3-V
LVCMOS
4 mA
3.3-V
LVCMOS
8 mA
3.3-V
LVCMOS
12 mA
3.3-V
LVCMOS
16 mA
3.3-V
LVCMOS
20 mA
3.3-V
LVCMOS
24 mA
2.5 V
4 mA
2.5 V
8 mA
2.5 V
12 mA
2.5 V
16 mA
Altera Corporation
May 2008
Industrial
Commercial
-6 Speed
Grade
tCO
2.764
2.764
6.169
ns
GCLK PLL
tCO
1.322
1.322
3.063
ns
GCLK
tCO
2.697
2.697
6.169
ns
GCLK PLL
tCO
1.255
1.255
3.063
ns
Parameter
Units
GCLK
tCO
2.671
2.671
6.000
ns
GCLK PLL
tCO
1.229
1.229
2.894
ns
GCLK
tCO
2.649
2.649
5.875
ns
GCLK PLL
tCO
1.207
1.207
2.769
ns
GCLK
tCO
2.642
2.642
5.877
ns
GCLK PLL
tCO
1.200
1.200
2.771
ns
GCLK
tCO
2.764
2.764
6.169
ns
GCLK PLL
tCO
1.322
1.322
3.063
ns
GCLK
tCO
2.672
2.672
5.874
ns
GCLK PLL
tCO
1.230
1.230
2.768
ns
GCLK
tCO
2.644
2.644
5.796
ns
GCLK PLL
tCO
1.202
1.202
2.690
ns
GCLK
tCO
2.651
2.651
5.764
ns
GCLK PLL
tCO
1.209
1.209
2.658
ns
GCLK
tCO
2.638
2.638
5.746
ns
GCLK PLL
tCO
1.196
1.196
2.640
ns
GCLK
tCO
2.627
2.627
5.724
ns
GCLK PLL
tCO
1.185
1.185
2.618
ns
GCLK
tCO
2.726
2.726
6.201
ns
GCLK PLL
tCO
1.284
1.284
3.095
ns
GCLK
tCO
2.674
2.674
5.939
ns
GCLK PLL
tCO
1.232
1.232
2.833
ns
GCLK
tCO
2.653
2.653
5.822
ns
GCLK PLL
tCO
1.211
1.211
2.716
ns
GCLK
tCO
2.635
2.635
5.748
ns
GCLK PLL
tCO
1.193
1.193
2.642
ns
4–61
Arria GX Device Handbook, Volume 1
Typical Design Performance
Table 4–57. EP1AGX35 Column Pins Output Timing Parameters (Part 3 of 5)
I/O
Standard
Fast Corner
Drive
Strength
Clock
1.8 V
2 mA
GCLK
1.8 V
4 mA
1.8 V
6 mA
1.8 V
8 mA
1.8 V
10 mA
1.8 V
12 mA
1.5 V
2 mA
1.5 V
4 mA
1.5 V
6 mA
1.5 V
8 mA
SSTL-2
CLASS I
8 mA
SSTL-2
CLASS I
12 mA
SSTL-2
CLASS II
16 mA
SSTL-2
CLASS II
20 mA
SSTL-2
CLASS II
24 mA
Industrial
Commercial
-6 Speed
Grade
tCO
2.766
2.766
7.193
ns
GCLK PLL
tCO
1.324
1.324
4.087
ns
GCLK
tCO
2.771
2.771
6.419
ns
GCLK PLL
tCO
1.329
1.329
3.313
ns
Parameter
Units
GCLK
tCO
2.695
2.695
6.155
ns
GCLK PLL
tCO
1.253
1.253
3.049
ns
GCLK
tCO
2.697
2.697
6.064
ns
GCLK PLL
tCO
1.255
1.255
2.958
ns
GCLK
tCO
2.651
2.651
5.987
ns
GCLK PLL
tCO
1.209
1.209
2.881
ns
GCLK
tCO
2.652
2.652
5.930
ns
GCLK PLL
tCO
1.210
1.210
2.824
ns
GCLK
tCO
2.746
2.746
6.723
ns
GCLK PLL
tCO
1.304
1.304
3.617
ns
GCLK
tCO
2.682
2.682
6.154
ns
GCLK PLL
tCO
1.240
1.240
3.048
ns
GCLK
tCO
2.685
2.685
6.036
ns
GCLK PLL
tCO
1.243
1.243
2.930
ns
GCLK
tCO
2.644
2.644
5.983
ns
GCLK PLL
tCO
1.202
1.202
2.877
ns
GCLK
tCO
2.629
2.629
5.762
ns
GCLK PLL
tCO
1.184
1.184
2.650
ns
GCLK
tCO
2.612
2.612
5.712
ns
GCLK PLL
tCO
1.167
1.167
2.600
ns
GCLK
tCO
2.590
2.590
5.639
ns
GCLK PLL
tCO
1.145
1.145
2.527
ns
GCLK
tCO
2.591
2.591
5.626
ns
GCLK PLL
tCO
1.146
1.146
2.514
ns
GCLK
tCO
2.587
2.587
5.624
ns
GCLK PLL
tCO
1.142
1.142
2.512
ns
4–62
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–57. EP1AGX35 Column Pins Output Timing Parameters (Part 4 of 5)
I/O
Standard
Fast Corner
Drive
Strength
Clock
SSTL-18
CLASS I
4 mA
GCLK
SSTL-18
CLASS I
6 mA
SSTL-18
CLASS I
8 mA
SSTL-18
CLASS I
10 mA
SSTL-18
CLASS I
12 mA
SSTL-18
CLASS II
8 mA
SSTL-18
CLASS II
16 mA
SSTL-18
CLASS II
18 mA
SSTL-18
CLASS II
20 mA
1.8-V HSTL
CLASS I
4 mA
1.8-V HSTL
CLASS I
6 mA
1.8-V HSTL
CLASS I
8 mA
1.8-V HSTL
CLASS I
10 mA
1.8-V HSTL
CLASS I
12 mA
1.8-V HSTL
CLASS II
16 mA
Altera Corporation
May 2008
Industrial
Commercial
-6 Speed
Grade
tCO
2.626
2.626
5.733
ns
GCLK PLL
tCO
1.184
1.184
2.627
ns
GCLK
tCO
2.630
2.630
5.694
ns
GCLK PLL
tCO
1.185
1.185
2.582
ns
Parameter
Units
GCLK
tCO
2.609
2.609
5.675
ns
GCLK PLL
tCO
1.164
1.164
2.563
ns
GCLK
tCO
2.614
2.614
5.673
ns
GCLK PLL
tCO
1.169
1.169
2.561
ns
GCLK
tCO
2.608
2.608
5.659
ns
GCLK PLL
tCO
1.163
1.163
2.547
ns
GCLK
tCO
2.597
2.597
5.625
ns
GCLK PLL
tCO
1.152
1.152
2.513
ns
GCLK
tCO
2.609
2.609
5.603
ns
GCLK PLL
tCO
1.164
1.164
2.491
ns
GCLK
tCO
2.605
2.605
5.611
ns
GCLK PLL
tCO
1.160
1.160
2.499
ns
GCLK
tCO
2.605
2.605
5.609
ns
GCLK PLL
tCO
1.160
1.160
2.497
ns
GCLK
tCO
2.629
2.629
5.664
ns
GCLK PLL
tCO
1.187
1.187
2.558
ns
GCLK
tCO
2.634
2.634
5.649
ns
GCLK PLL
tCO
1.189
1.189
2.537
ns
GCLK
tCO
2.612
2.612
5.638
ns
GCLK PLL
tCO
1.167
1.167
2.526
ns
GCLK
tCO
2.616
2.616
5.644
ns
GCLK PLL
tCO
1.171
1.171
2.532
ns
GCLK
tCO
2.608
2.608
5.637
ns
GCLK PLL
tCO
1.163
1.163
2.525
ns
GCLK
tCO
2.591
2.591
5.401
ns
GCLK PLL
tCO
1.146
1.146
2.289
ns
4–63
Arria GX Device Handbook, Volume 1
Typical Design Performance
Table 4–57. EP1AGX35 Column Pins Output Timing Parameters (Part 5 of 5)
Fast Corner
I/O
Standard
Drive
Strength
Clock
1.8-V HSTL
CLASS II
18 mA
GCLK
1.8-V HSTL
CLASS II
20 mA
1.5-V HSTL
CLASS I
4 mA
1.5-V HSTL
CLASS I
6 mA
1.5-V HSTL
CLASS I
8 mA
1.5-V HSTL
CLASS I
10 mA
1.5-V HSTL
CLASS I
12 mA
1.5-V HSTL
CLASS II
16 mA
1.5-V HSTL
CLASS II
18 mA
1.5-V HSTL
CLASS II
20 mA
3.3-V PCI
-
3.3-V PCI-X
-
LVDS
-
Industrial
Commercial
-6 Speed
Grade
tCO
2.593
2.593
5.412
ns
GCLK PLL
tCO
1.148
1.148
2.300
ns
GCLK
tCO
2.593
2.593
5.421
ns
GCLK PLL
tCO
1.148
1.148
2.309
ns
Parameter
Units
GCLK
tCO
2.629
2.629
5.663
ns
GCLK PLL
tCO
1.187
1.187
2.557
ns
GCLK
tCO
2.633
2.633
5.641
ns
GCLK PLL
tCO
1.188
1.188
2.529
ns
GCLK
tCO
2.615
2.615
5.643
ns
GCLK PLL
tCO
1.170
1.170
2.531
ns
GCLK
tCO
2.615
2.615
5.645
ns
GCLK PLL
tCO
1.170
1.170
2.533
ns
GCLK
tCO
2.609
2.609
5.643
ns
GCLK PLL
tCO
1.164
1.164
2.531
ns
GCLK
tCO
2.596
2.596
5.455
ns
GCLK PLL
tCO
1.151
1.151
2.343
ns
GCLK
tCO
2.599
2.599
5.465
ns
GCLK PLL
tCO
1.154
1.154
2.353
ns
GCLK
tCO
2.601
2.601
5.478
ns
GCLK PLL
tCO
1.156
1.156
2.366
ns
GCLK
tCO
2.755
2.755
5.791
ns
GCLK PLL
tCO
1.313
1.313
2.685
ns
GCLK
tCO
2.755
2.755
5.791
ns
GCLK PLL
tCO
1.313
1.313
2.685
ns
GCLK
tCO
3.621
3.621
6.969
ns
GCLK PLL
tCO
2.190
2.190
3.880
ns
Tables 4–58 through 4–59 shows EP1AGX35 regional clock (RCLK) adder
values that should be added to GCLK values. These adder values are used
to determine I/O timing when the I/O pin is driven using the regional
clock. This applies for all I/O standards supported by Arria GX with
general purpose I/O pins.
4–64
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–58 describes row pin delay adders when using the regional clock
in Arria GX devices.
Table 4–58. EP1AGX35 Row Pin Delay Adders for Regional Clock
Fast Corner
Industrial
Commercial
-6 Speed
Grade
0.126
0.126
0.281
ns
0.011
0.011
0.018
ns
-0.126
-0.126
-0.281
ns
-0.011
-0.011
-0.018
ns
Parameter
RCLK input
Units
adder
RCLK PLL
input adder
RCLK output
adder
RCLK PLL
output adder
Table 4–59 describes column pin delay adders when using the regional
clock in Arria GX devices.
Table 4–59. EP1AGX35 Column Pin Delay Adders for Regional Clock
Fast Corner
Commercial
-6 Speed
Grade
Units
Industrial
0.099
0.099
0.254
ns
-0.012
-0.012
-0.01
ns
-0.086
-0.086
-0.244
ns
1.253
1.253
3.133
ns
Parameter
RCLK input
adder
RCLK PLL
input adder
RCLK output
adder
RCLK PLL
output adder
Altera Corporation
May 2008
4–65
Arria GX Device Handbook, Volume 1
Typical Design Performance
EP1AGX50 I/O Timing Parameters
Tables 4–60 through 4–63 show the maximum I/O timing parameters for
EP1AGX50 devices for I/O standards which support general purpose
I/O pins.
Table 4–60 describes I/O timing specifications.
Table 4–60. EP1AGX50 Row Pins Input Timing Parameters (Part 1 of 3)
Fast Model
I/O Standard
Clock
Parameter
Industrial
1.550
1.550
3.542
ns
tH
-1.445
-1.445
-3.265
ns
GCLK PLL
tSU
2.978
2.978
6.626
ns
tH
-2.873
-2.873
-6.349
ns
GCLK
tSU
1.550
1.550
3.542
ns
tH
-1.445
-1.445
-3.265
ns
3.3-V LVTTL
GCLK PLL
GCLK
2.5 V
tSU
2.978
2.978
6.626
ns
tH
-2.873
-2.873
-6.349
ns
tSU
1.562
1.562
3.523
ns
tH
-1.457
-1.457
-3.246
ns
tSU
2.990
2.990
6.607
ns
tH
-2.885
-2.885
-6.330
ns
GCLK
tSU
1.628
1.628
3.730
ns
tH
-1.523
-1.523
-3.453
ns
GCLK PLL
tSU
3.056
3.056
6.814
ns
tH
-2.951
-2.951
-6.537
ns
GCLK PLL
1.8 V
GCLK
1.5 V
GCLK PLL
GCLK
SSTL-2
CLASS I
Units
tSU
GCLK
3.3-V
LVCMOS
Commercial
-6 Speed
Grade
GCLK PLL
tSU
1.631
1.631
3.825
ns
tH
-1.526
-1.526
-3.548
ns
tSU
3.059
3.059
6.909
ns
tH
-2.954
-2.954
-6.632
ns
tSU
1.375
1.375
2.997
ns
tH
-1.270
-1.270
-2.720
ns
tSU
2.802
2.802
6.079
ns
tH
-2.697
-2.697
-5.802
ns
4–66
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–60. EP1AGX50 Row Pins Input Timing Parameters (Part 2 of 3)
Fast Model
I/O Standard
SSTL-2
CLASS II
Clock
SSTL-18
CLASS II
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS II
1.5-V HSTL
CLASS I
Units
tSU
1.375
1.375
2.997
ns
tH
-1.270
-1.270
-2.720
ns
GCLK PLL
tSU
2.802
2.802
6.079
ns
tH
-2.697
-2.697
-5.802
ns
tSU
1.406
1.406
3.104
ns
tH
-1.301
-1.301
-2.827
ns
GCLK PLL
tSU
2.834
2.834
6.188
ns
tH
-2.729
-2.729
-5.911
ns
GCLK
tSU
1.407
1.407
3.106
ns
tH
-1.302
-1.302
-2.829
ns
GCLK PLL
tSU
2.834
2.834
6.188
ns
tH
-2.729
-2.729
-5.911
ns
GCLK
tSU
1.406
1.406
3.104
ns
tH
-1.301
-1.301
-2.827
ns
tSU
2.834
2.834
6.188
ns
tH
-2.729
-2.729
-5.911
ns
GCLK
tSU
1.407
1.407
3.106
ns
tH
-1.302
-1.302
-2.829
ns
GCLK PLL
tSU
2.834
2.834
6.188
ns
tH
-2.729
-2.729
-5.911
ns
GCLK
tSU
1.432
1.432
3.232
ns
tH
-1.327
-1.327
-2.955
ns
GCLK PLL
tSU
2.860
2.860
6.316
ns
tH
-2.755
-2.755
-6.039
ns
GCLK PLL
GCLK
1.5-V HSTL
CLASS II
Commercial
GCLK
GCLK
SSTL-18
CLASS I
Industrial
-6 Speed
Grade
Parameter
GCLK PLL
Altera Corporation
May 2008
tSU
1.433
1.433
3.234
ns
tH
-1.328
-1.328
-2.957
ns
tSU
2.860
2.860
6.316
ns
tH
-2.755
-2.755
-6.039
ns
4–67
Arria GX Device Handbook, Volume 1
Typical Design Performance
Table 4–60. EP1AGX50 Row Pins Input Timing Parameters (Part 3 of 3)
Fast Model
I/O Standard
Clock
Industrial
Commercial
-6 Speed
Grade
Parameter
Units
GCLK
tSU
1.341
1.341
3.088
ns
tH
-1.236
-1.236
-2.811
ns
GCLK PLL
tSU
2.769
2.769
6.171
ns
tH
-2.664
-2.664
-5.894
ns
Units
LVDS
Table 4–61 describes I/O timing specifications.
Table 4–61. EP1AGX50 Column Pins Input Timing Parameters (Part 1 of 3)
Fast Corner
I/O Standard
Clock
Commercial
GCLK
tSU
1.242
1.242
2.902
ns
tH
-1.137
-1.137
-2.625
ns
GCLK PLL
tSU
2.684
2.684
6.009
ns
tH
-2.579
-2.579
-5.732
ns
3.3-V LVTTL
tSU
1.242
1.242
2.902
ns
tH
-1.137
-1.137
-2.625
ns
GCLK PLL
tSU
2.684
2.684
6.009
ns
tH
-2.579
-2.579
-5.732
ns
GCLK
tSU
1.252
1.252
2.884
ns
tH
-1.147
-1.147
-2.607
ns
GCLK PLL
tSU
2.694
2.694
5.991
ns
tH
-2.589
-2.589
-5.714
ns
GCLK
tSU
1.318
1.318
3.094
ns
tH
-1.213
-1.213
-2.817
ns
GCLK
3.3-V
LVCMOS
Industrial
-6 Speed
Grade
Parameter
2.5 V
1.8 V
tSU
2.760
2.760
6.201
ns
tH
-2.655
-2.655
-5.924
ns
GCLK
tSU
1.321
1.321
3.187
ns
tH
-1.216
-1.216
-2.910
ns
GCLK PLL
tSU
2.763
2.763
6.294
ns
tH
-2.658
-2.658
-6.017
ns
GCLK PLL
1.5 V
4–68
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–61. EP1AGX50 Column Pins Input Timing Parameters (Part 2 of 3)
Fast Corner
I/O Standard
SSTL-2
CLASS I
Clock
SSTL-18
CLASS I
SSTL-18
CLASS II
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS II
Units
tSU
1.034
1.034
2.314
ns
tH
-0.929
-0.929
-2.037
ns
GCLK PLL
tSU
2.500
2.500
5.457
ns
tH
-2.395
-2.395
-5.180
ns
tSU
1.034
1.034
2.314
ns
tH
-0.929
-0.929
-2.037
ns
GCLK PLL
tSU
2.500
2.500
5.457
ns
tH
-2.395
-2.395
-5.180
ns
GCLK
tSU
1.104
1.104
2.466
ns
tH
-0.999
-0.999
-2.189
ns
GCLK PLL
tSU
2.546
2.546
5.573
ns
tH
-2.441
-2.441
-5.296
ns
GCLK
tSU
1.074
1.074
2.424
ns
tH
-0.969
-0.969
-2.147
ns
tSU
2.539
2.539
5.564
ns
tH
-2.434
-2.434
-5.287
ns
GCLK
tSU
1.104
1.104
2.466
ns
tH
-0.999
-0.999
-2.189
ns
GCLK PLL
tSU
2.546
2.546
5.573
ns
tH
-2.441
-2.441
-5.296
ns
GCLK
tSU
1.074
1.074
2.424
ns
tH
-0.969
-0.969
-2.147
ns
GCLK PLL
tSU
2.539
2.539
5.564
ns
tH
-2.434
-2.434
-5.287
ns
GCLK PLL
GCLK
1.5-V HSTL
CLASS I
Commercial
GCLK
GCLK
SSTL-2
CLASS II
Industrial
-6 Speed
Grade
Parameter
GCLK PLL
Altera Corporation
May 2008
tSU
1.122
1.122
2.594
ns
tH
-1.017
-1.017
-2.317
ns
tSU
2.564
2.564
5.701
ns
tH
-2.459
-2.459
-5.424
ns
4–69
Arria GX Device Handbook, Volume 1
Typical Design Performance
Table 4–61. EP1AGX50 Column Pins Input Timing Parameters (Part 3 of 3)
Fast Corner
I/O Standard
1.5-V HSTL
CLASS II
Clock
Industrial
Commercial
-6 Speed
Grade
Parameter
Units
GCLK
tSU
1.094
1.094
2.557
ns
tH
-0.989
-0.989
-2.280
ns
GCLK PLL
tSU
2.557
2.557
5.692
ns
tH
-2.452
-2.452
-5.415
ns
tSU
1.247
1.247
2.890
ns
tH
-1.142
-1.142
-2.613
ns
GCLK PLL
tSU
2.689
2.689
5.997
ns
tH
-2.584
-2.584
-5.720
ns
GCLK
tSU
1.247
1.247
2.890
ns
tH
-1.142
-1.142
-2.613
ns
GCLK PLL
tSU
2.689
2.689
5.997
ns
tH
-2.584
-2.584
-5.720
ns
GCLK
tSU
1.106
1.106
2.489
ns
tH
-1.001
-1.001
-2.212
ns
GCLK
3.3-V PCI
3.3-V PCI-X
LVDS
GCLK PLL
tSU
2.530
2.530
5.564
ns
tH
-2.425
-2.425
-5.287
ns
Table 4–62 describes I/O timing specifications.
Table 4–62. EP1AGX50 Row Pins Output Timing Parameters (Part 1 of 3)
I/O
Standard
Fast Model
Drive
Strength
Clock
Commercial
-6 Speed
Grade
Units
Industrial
3.3-V
LVTTL
4 mA
GCLK
tCO
2.915
2.915
6.713
ns
GCLK PLL
tCO
1.487
1.487
3.629
ns
3.3-V
LVTTL
8 mA
3.3-V
LVTTL
12 mA
3.3-V
LVCMOS
4 mA
Parameter
GCLK
tCO
2.787
2.787
6.073
ns
GCLK PLL
tCO
1.359
1.359
2.989
ns
GCLK
tCO
2.731
2.731
6.036
ns
GCLK PLL
tCO
1.303
1.303
2.952
ns
GCLK
tCO
2.787
2.787
6.073
ns
GCLK PLL
tCO
1.359
1.359
2.989
ns
4–70
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–62. EP1AGX50 Row Pins Output Timing Parameters (Part 2 of 3)
I/O
Standard
Fast Model
Drive
Strength
Clock
3.3-V
LVCMOS
8 mA
GCLK
2.5 V
4 mA
2.5 V
8 mA
2.5 V
12 mA
1.8 V
2 mA
1.8 V
4 mA
1.8 V
6 mA
1.8 V
8 mA
1.5 V
2 mA
1.5 V
4 mA
SSTL-2
CLASS I
8 mA
SSTL-2
CLASS I
12 mA
SSTL-2
CLASS II
16 mA
SSTL-18
CLASS I
4 mA
SSTL-18
CLASS I
6 mA
Altera Corporation
May 2008
Industrial
Commercial
-6 Speed
Grade
tCO
2.681
2.681
5.767
ns
GCLK PLL
tCO
1.253
1.253
2.683
ns
GCLK
tCO
2.770
2.770
6.047
ns
GCLK PLL
tCO
1.342
1.342
2.963
ns
Parameter
Units
GCLK
tCO
2.667
2.667
5.789
ns
GCLK PLL
tCO
1.239
1.239
2.705
ns
GCLK
tCO
2.648
2.648
5.675
ns
GCLK PLL
tCO
1.220
1.220
2.591
ns
GCLK
tCO
2.840
2.840
7.066
ns
GCLK PLL
tCO
1.412
1.412
3.982
ns
GCLK
tCO
2.829
2.829
6.287
ns
GCLK PLL
tCO
1.401
1.401
3.203
ns
GCLK
tCO
2.718
2.718
5.986
ns
GCLK PLL
tCO
1.290
1.290
2.902
ns
GCLK
tCO
2.687
2.687
5.872
ns
GCLK PLL
tCO
1.259
1.259
2.788
ns
GCLK
tCO
2.800
2.800
6.565
ns
GCLK PLL
tCO
1.372
1.372
3.481
ns
GCLK
tCO
2.693
2.693
5.964
ns
GCLK PLL
tCO
1.265
1.265
2.880
ns
GCLK
tCO
2.636
2.636
5.626
ns
GCLK PLL
tCO
1.209
1.209
2.544
ns
GCLK
tCO
2.612
2.612
5.550
ns
GCLK PLL
tCO
1.185
1.185
2.468
ns
GCLK
tCO
2.578
2.578
5.419
ns
GCLK PLL
tCO
1.151
1.151
2.337
ns
GCLK
tCO
2.625
2.625
5.570
ns
GCLK PLL
tCO
1.197
1.197
2.486
ns
GCLK
tCO
2.628
2.628
5.497
ns
GCLK PLL
tCO
1.201
1.201
2.415
ns
4–71
Arria GX Device Handbook, Volume 1
Typical Design Performance
Table 4–62. EP1AGX50 Row Pins Output Timing Parameters (Part 3 of 3)
I/O
Standard
Fast Model
Drive
Strength
Clock
SSTL-18
CLASS I
8 mA
GCLK
SSTL-18
CLASS I
10 mA
1.8-V HSTL
CLASS I
4 mA
1.8-V HSTL
CLASS I
6 mA
1.8-V HSTL
CLASS I
8 mA
1.8-V HSTL
CLASS I
10 mA
1.8-V HSTL
CLASS I
12 mA
1.5-V HSTL
CLASS I
4 mA
1.5-V HSTL
CLASS I
6 mA
1.5-V HSTL
CLASS I
8 mA
LVDS
-
Industrial
Commercial
-6 Speed
Grade
tCO
2.604
2.604
5.480
ns
GCLK PLL
tCO
1.177
1.177
2.398
ns
GCLK
tCO
2.607
2.607
5.459
ns
GCLK PLL
tCO
1.180
1.180
2.377
ns
Parameter
Units
GCLK
tCO
2.606
2.606
5.480
ns
GCLK PLL
tCO
1.178
1.178
2.396
ns
GCLK
tCO
2.608
2.608
5.442
ns
GCLK PLL
tCO
1.181
1.181
2.360
ns
GCLK
tCO
2.590
2.590
5.438
ns
GCLK PLL
tCO
1.163
1.163
2.356
ns
GCLK
tCO
2.594
2.594
5.427
ns
GCLK PLL
tCO
1.167
1.167
2.345
ns
GCLK
tCO
2.585
2.585
5.426
ns
GCLK PLL
tCO
1.158
1.158
2.344
ns
GCLK
tCO
2.605
2.605
5.457
ns
GCLK PLL
tCO
1.177
1.177
2.373
ns
GCLK
tCO
2.607
2.607
5.441
ns
GCLK PLL
tCO
1.180
1.180
2.359
ns
GCLK
tCO
2.592
2.592
5.433
ns
GCLK PLL
tCO
1.165
1.165
2.351
ns
GCLK
tCO
2.654
2.654
5.613
ns
GCLK PLL
tCO
1.226
1.226
2.530
ns
Units
Table 4–63 describes I/O timing specifications.
Table 4–63. EP1AGX50 Column Pins Output Timing Parameters (Part 1 of 5)
I/O
Standard
3.3-V
LVTTL
Fast Corner
Drive
Strength
Clock
4 mA
GCLK
GCLK PLL
4–72
Arria GX Device Handbook, Volume 1
Industrial
Commercial
-6 Speed
Grade
tCO
2.948
2.948
6.608
ns
tCO
1.476
1.476
3.447
ns
Parameter
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–63. EP1AGX50 Column Pins Output Timing Parameters (Part 2 of 5)
I/O
Standard
Fast Corner
Drive
Strength
Clock
3.3-V
LVTTL
8 mA
GCLK
3.3-V
LVTTL
12 mA
3.3-V
LVTTL
16 mA
3.3-V
LVTTL
20 mA
3.3-V
LVTTL
24 mA
3.3-V
LVCMOS
4 mA
3.3-V
LVCMOS
8 mA
3.3-V
LVCMOS
12 mA
3.3-V
LVCMOS
16 mA
3.3-V
LVCMOS
20 mA
3.3-V
LVCMOS
24 mA
2.5 V
4 mA
2.5 V
8 mA
2.5 V
12 mA
2.5 V
16 mA
Altera Corporation
May 2008
Industrial
Commercial
-6 Speed
Grade
tCO
2.797
2.797
6.203
ns
GCLK PLL
tCO
1.331
1.331
3.075
ns
GCLK
tCO
2.722
2.722
6.204
ns
GCLK PLL
tCO
1.264
1.264
3.075
ns
Parameter
Units
GCLK
tCO
2.694
2.694
6.024
ns
GCLK PLL
tCO
1.238
1.238
2.906
ns
GCLK
tCO
2.670
2.670
5.896
ns
GCLK PLL
tCO
1.216
1.216
2.781
ns
GCLK
tCO
2.660
2.660
5.895
ns
GCLK PLL
tCO
1.209
1.209
2.783
ns
GCLK
tCO
2.797
2.797
6.203
ns
GCLK PLL
tCO
1.331
1.331
3.075
ns
GCLK
tCO
2.695
2.695
5.893
ns
GCLK PLL
tCO
1.239
1.239
2.780
ns
GCLK
tCO
2.663
2.663
5.809
ns
GCLK PLL
tCO
1.211
1.211
2.702
ns
GCLK
tCO
2.666
2.666
5.776
ns
GCLK PLL
tCO
1.218
1.218
2.670
ns
GCLK
tCO
2.651
2.651
5.758
ns
GCLK PLL
tCO
1.205
1.205
2.652
ns
GCLK
tCO
2.638
2.638
5.736
ns
GCLK PLL
tCO
1.194
1.194
2.630
ns
GCLK
tCO
2.754
2.754
6.240
ns
GCLK PLL
tCO
1.293
1.293
3.107
ns
GCLK
tCO
2.697
2.697
5.963
ns
GCLK PLL
tCO
1.241
1.241
2.845
ns
GCLK
tCO
2.672
2.672
5.837
ns
GCLK PLL
tCO
1.220
1.220
2.728
ns
GCLK
tCO
2.654
2.654
5.760
ns
GCLK PLL
tCO
1.202
1.202
2.654
ns
4–73
Arria GX Device Handbook, Volume 1
Typical Design Performance
Table 4–63. EP1AGX50 Column Pins Output Timing Parameters (Part 3 of 5)
I/O
Standard
Fast Corner
Drive
Strength
Clock
1.8 V
2 mA
GCLK
1.8 V
4 mA
1.8 V
6 mA
1.8 V
8 mA
1.8 V
10 mA
1.8 V
12 mA
1.5 V
2 mA
1.5 V
4 mA
1.5 V
6 mA
1.5 V
8 mA
SSTL-2
CLASS I
8 mA
SSTL-2
CLASS I
12 mA
SSTL-2
CLASS II
16 mA
SSTL-2
CLASS II
20 mA
SSTL-2
CLASS II
24 mA
Industrial
Commercial
-6 Speed
Grade
tCO
2.804
2.804
7.295
ns
GCLK PLL
tCO
1.333
1.333
4.099
ns
GCLK
tCO
2.808
2.808
6.479
ns
GCLK PLL
tCO
1.338
1.338
3.325
ns
Parameter
Units
GCLK
tCO
2.717
2.717
6.195
ns
GCLK PLL
tCO
1.262
1.262
3.061
ns
GCLK
tCO
2.719
2.719
6.098
ns
GCLK PLL
tCO
1.264
1.264
2.970
ns
GCLK
tCO
2.671
2.671
6.012
ns
GCLK PLL
tCO
1.218
1.218
2.893
ns
GCLK
tCO
2.671
2.671
5.953
ns
GCLK PLL
tCO
1.219
1.219
2.836
ns
GCLK
tCO
2.779
2.779
6.815
ns
GCLK PLL
tCO
1.313
1.313
3.629
ns
GCLK
tCO
2.703
2.703
6.210
ns
GCLK PLL
tCO
1.249
1.249
3.060
ns
GCLK
tCO
2.705
2.705
6.118
ns
GCLK PLL
tCO
1.252
1.252
2.942
ns
GCLK
tCO
2.660
2.660
6.014
ns
GCLK PLL
tCO
1.211
1.211
2.889
ns
GCLK
tCO
2.648
2.648
5.777
ns
GCLK PLL
tCO
1.202
1.202
2.675
ns
GCLK
tCO
2.628
2.628
5.722
ns
GCLK PLL
tCO
1.185
1.185
2.625
ns
GCLK
tCO
2.606
2.606
5.649
ns
GCLK PLL
tCO
1.163
1.163
2.552
ns
GCLK
tCO
2.606
2.606
5.636
ns
GCLK PLL
tCO
1.164
1.164
2.539
ns
GCLK
tCO
2.601
2.601
5.634
ns
GCLK PLL
tCO
1.160
1.160
2.537
ns
4–74
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–63. EP1AGX50 Column Pins Output Timing Parameters (Part 4 of 5)
I/O
Standard
Fast Corner
Drive
Strength
Clock
SSTL-18
CLASS I
4 mA
GCLK
SSTL-18
CLASS I
6 mA
SSTL-18
CLASS I
8 mA
SSTL-18
CLASS I
10 mA
SSTL-18
CLASS I
12 mA
SSTL-18
CLASS II
8 mA
SSTL-18
CLASS II
16 mA
SSTL-18
CLASS II
18 mA
SSTL-18
CLASS II
20 mA
1.8-V HSTL
CLASS I
4 mA
1.8-V HSTL
CLASS I
6 mA
1.8-V HSTL
CLASS I
8 mA
1.8-V HSTL
CLASS I
10 mA
1.8-V HSTL
CLASS I
12 mA
1.8-V HSTL
CLASS II
16 mA
Altera Corporation
May 2008
Industrial
Commercial
-6 Speed
Grade
tCO
2.643
2.643
5.749
ns
GCLK PLL
tCO
1.193
1.193
2.639
ns
GCLK
tCO
2.649
2.649
5.708
ns
GCLK PLL
tCO
1.203
1.203
2.607
ns
Parameter
Units
GCLK
tCO
2.626
2.626
5.686
ns
GCLK PLL
tCO
1.182
1.182
2.588
ns
GCLK
tCO
2.630
2.630
5.685
ns
GCLK PLL
tCO
1.187
1.187
2.586
ns
GCLK
tCO
2.625
2.625
5.669
ns
GCLK PLL
tCO
1.181
1.181
2.572
ns
GCLK
tCO
2.614
2.614
5.635
ns
GCLK PLL
tCO
1.170
1.170
2.538
ns
GCLK
tCO
2.623
2.623
5.613
ns
GCLK PLL
tCO
1.182
1.182
2.516
ns
GCLK
tCO
2.616
2.616
5.621
ns
GCLK PLL
tCO
1.178
1.178
2.524
ns
GCLK
tCO
2.616
2.616
5.619
ns
GCLK PLL
tCO
1.178
1.178
2.522
ns
GCLK
tCO
2.637
2.637
5.676
ns
GCLK PLL
tCO
1.196
1.196
2.570
ns
GCLK
tCO
2.645
2.645
5.659
ns
GCLK PLL
tCO
1.207
1.207
2.562
ns
GCLK
tCO
2.623
2.623
5.648
ns
GCLK PLL
tCO
1.185
1.185
2.551
ns
GCLK
tCO
2.627
2.627
5.654
ns
GCLK PLL
tCO
1.189
1.189
2.557
ns
GCLK
tCO
2.619
2.619
5.647
ns
GCLK PLL
tCO
1.181
1.181
2.550
ns
GCLK
tCO
2.602
2.602
5.574
ns
GCLK PLL
tCO
1.164
1.164
2.314
ns
4–75
Arria GX Device Handbook, Volume 1
Typical Design Performance
Table 4–63. EP1AGX50 Column Pins Output Timing Parameters (Part 5 of 5)
Fast Corner
I/O
Standard
Drive
Strength
Clock
1.8-V HSTL
CLASS II
18 mA
GCLK
1.8-V HSTL
CLASS II
20 mA
1.5-V HSTL
CLASS I
4 mA
1.5-V HSTL
CLASS I
6 mA
1.5-V HSTL
CLASS I
8 mA
1.5-V HSTL
CLASS I
10 mA
1.5-V HSTL
CLASS I
12 mA
1.5-V HSTL
CLASS II
16 mA
1.5-V HSTL
CLASS II
18 mA
1.5-V HSTL
CLASS II
20 mA
3.3-V PCI
-
3.3-V PCI-X
-
LVDS
-
Industrial
Commercial
-6 Speed
Grade
tCO
2.604
2.604
5.578
ns
GCLK PLL
tCO
1.166
1.166
2.325
ns
GCLK
tCO
2.604
2.604
5.577
ns
GCLK PLL
tCO
1.166
1.166
2.334
ns
Parameter
Units
GCLK
tCO
2.637
2.637
5.675
ns
GCLK PLL
tCO
1.196
1.196
2.569
ns
GCLK
tCO
2.644
2.644
5.651
ns
GCLK PLL
tCO
1.206
1.206
2.554
ns
GCLK
tCO
2.626
2.626
5.653
ns
GCLK PLL
tCO
1.188
1.188
2.556
ns
GCLK
tCO
2.626
2.626
5.655
ns
GCLK PLL
tCO
1.188
1.188
2.558
ns
GCLK
tCO
2.620
2.620
5.653
ns
GCLK PLL
tCO
1.182
1.182
2.556
ns
GCLK
tCO
2.607
2.607
5.573
ns
GCLK PLL
tCO
1.169
1.169
2.368
ns
GCLK
tCO
2.610
2.610
5.571
ns
GCLK PLL
tCO
1.172
1.172
2.378
ns
GCLK
tCO
2.612
2.612
5.581
ns
GCLK PLL
tCO
1.174
1.174
2.391
ns
GCLK
tCO
2.786
2.786
5.803
ns
GCLK PLL
tCO
1.322
1.322
2.697
ns
GCLK
tCO
2.786
2.786
5.803
ns
GCLK PLL
tCO
1.322
1.322
2.697
ns
GCLK
tCO
3.621
3.621
6.969
ns
GCLK PLL
tCO
2.190
2.190
3.880
ns
Tables 4–64 through 4–65 shows EP1AGX50 regional clock (RCLK) adder
values that should be added to the GCLK values. These adder values are
used to determine I/O timing when the I/O pin is driven using the
regional clock. This applies for all I/O standards supported by Arria GX
with general purpose I/O pins.
4–76
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–64 describes row pin delay adders when using the regional clock
in Arria GX devices.
Table 4–64. EP1AGX50 Row Pin Delay Adders for Regional Clock
Fast Corner
Industrial
Commercial
-6 Speed
Grade
0.151
0.151
0.329
ns
0.011
0.011
0.016
ns
-0.151
-0.151
-0.329
ns
-0.011
-0.011
-0.016
ns
Parameter
RCLK input
Units
adder
RCLK PLL
input adder
RCLK output
adder
RCLK PLL
output adder
Table 4–65 describes column pin delay adders when using the regional
clock in Arria GX devices.
Table 4–65. EP1AGX50 Column Pin Delay Adders for Regional Clock
Fast Corner
Industrial
Commercial
-6 Speed
Grade
0.146
0.146
0.334
ns
-1.713
-1.713
-3.645
ns
-0.146
-0.146
-0.336
ns
1.716
1.716
4.488
ns
Parameter
RCLK input
Units
adder
RCLK PLL
input adder
RCLK output
adder
RCLK PLL
output adder
Altera Corporation
May 2008
4–77
Arria GX Device Handbook, Volume 1
Typical Design Performance
EP1AGX60 I/O Timing Parameters
Tables 4–66 through 4–69 show the maximum I/O timing parameters for
EP1AGX60 devices for I/O standards which support general purpose
I/O pins.
Table 4–66 describes I/O timing specifications.
Table 4–66. EP1AGX60 Row Pins Input Timing Parameters (Part 1 of 3)
Fast Model
I/O Standard
Clock
Parameter
Industrial
1.413
1.413
3.113
ns
tH
-1.308
-1.308
-2.836
ns
GCLK PLL
tSU
2.975
2.975
6.536
ns
tH
-2.870
-2.870
-6.259
ns
GCLK
tSU
1.413
1.413
3.113
ns
tH
-1.308
-1.308
-2.836
ns
3.3-V LVTTL
GCLK PLL
GCLK
2.5 V
tSU
2.975
2.975
6.536
ns
tH
-2.870
-2.870
-6.259
ns
tSU
1.425
1.425
3.094
ns
tH
-1.320
-1.320
-2.817
ns
tSU
2.987
2.987
6.517
ns
tH
-2.882
-2.882
-6.240
ns
GCLK
tSU
1.477
1.477
3.275
ns
tH
-1.372
-1.372
-2.998
ns
GCLK PLL
tSU
3.049
3.049
6.718
ns
tH
-2.944
-2.944
-6.441
ns
GCLK PLL
1.8 V
GCLK
1.5 V
GCLK PLL
GCLK
SSTL-2
CLASS I
Units
tSU
GCLK
3.3-V
LVCMOS
Commercial
-6 Speed
Grade
GCLK PLL
tSU
1.480
1.480
3.370
ns
tH
-1.375
-1.375
-3.093
ns
tSU
3.052
3.052
6.813
ns
tH
-2.947
-2.947
-6.536
ns
tSU
1.237
1.237
2.566
ns
tH
-1.132
-1.132
-2.289
ns
tsu
2.800
2.800
5.990
ns
tH
-2.695
-2.695
-5.713
ns
4–78
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–66. EP1AGX60 Row Pins Input Timing Parameters (Part 2 of 3)
Fast Model
I/O Standard
SSTL-2
CLASS II
Clock
SSTL-18
CLASS II
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS II
1.5-V HSTL
CLASS I
Units
tSU
1.237
1.237
2.566
ns
tH
-1.132
-1.132
-2.289
ns
GCLK PLL
tSU
2.800
2.800
5.990
ns
tH
-2.695
-2.695
-5.713
ns
tSU
1.255
1.255
2.649
ns
tH
-1.150
-1.150
-2.372
ns
GCLK PLL
tSU
2.827
2.827
6.092
ns
tH
-2.722
-2.722
-5.815
ns
GCLK
tSU
1.255
1.255
2.649
ns
tH
-1.150
-1.150
-2.372
ns
GCLK PLL
tSU
2.827
2.827
6.092
ns
tH
-2.722
-2.722
-5.815
ns
GCLK
tSU
1.255
1.255
2.649
ns
tH
-1.150
-1.150
-2.372
ns
tSU
2.827
2.827
6.092
ns
tH
-2.722
-2.722
-5.815
ns
GCLK
tSU
1.255
1.255
2.649
ns
tH
-1.150
-1.150
-2.372
ns
GCLK PLL
tSU
2.827
2.827
6.092
ns
tH
-2.722
-2.722
-5.815
ns
GCLK
tSU
1.281
1.281
2.777
ns
tH
-1.176
-1.176
-2.500
ns
GCLK PLL
tSU
2.853
2.853
6.220
ns
tH
-2.748
-2.748
-5.943
ns
GCLK PLL
GCLK
1.5-V HSTL
CLASS II
Commercial
GCLK
GCLK
SSTL-18
CLASS I
Industrial
-6 Speed
Grade
Parameter
GCLK PLL
Altera Corporation
May 2008
tSU
1.281
1.281
2.777
ns
tH
-1.176
-1.176
-2.500
ns
tSU
2.853
2.853
6.220
ns
tH
-2.748
-2.748
-5.943
ns
4–79
Arria GX Device Handbook, Volume 1
Typical Design Performance
Table 4–66. EP1AGX60 Row Pins Input Timing Parameters (Part 3 of 3)
Fast Model
I/O Standard
Clock
Industrial
Commercial
-6 Speed
Grade
Parameter
Units
GCLK
tSU
1.208
1.208
2.664
ns
tH
-1.103
-1.103
-2.387
ns
GCLK PLL
tSU
2.767
2.767
6.083
ns
tH
-2.662
-2.662
-5.806
ns
Units
LVDS
Table 4–67 describes I/O timing specifications.
Table 4–67. EP1AGX60 Column Pins Input Timing Parameters (Part 1 of 3)
Fast Corner
I/O Standard
Clock
Commercial
GCLK
tSU
1.124
1.124
2.493
ns
tH
-1.019
-1.019
-2.216
ns
GCLK PLL
tSU
2.694
2.694
5.928
ns
tH
-2.589
-2.589
-5.651
ns
3.3-V LVTTL
tSU
1.124
1.124
2.493
ns
tH
-1.019
-1.019
-2.216
ns
GCLK PLL
tSU
2.694
2.694
5.928
ns
tH
-2.589
-2.589
-5.651
ns
GCLK
tSU
1.134
1.134
2.475
ns
tH
-1.029
-1.029
-2.198
ns
GCLK PLL
tSU
2.704
2.704
5.910
ns
tH
-2.599
-2.599
-5.633
ns
GCLK
tSU
1.200
1.200
2.685
ns
tH
-1.095
-1.095
-2.408
ns
GCLK
3.3-V
LVCMOS
Industrial
-6 Speed
Grade
Parameter
2.5 V
1.8 V
tSU
2.770
2.770
6.120
ns
tH
-2.665
-2.665
-5.843
ns
GCLK
tSU
1.203
1.203
2.778
ns
tH
-1.098
-1.098
-2.501
ns
GCLK PLL
tSU
2.773
2.773
6.213
ns
tH
-2.668
-2.668
-5.936
ns
GCLK PLL
1.5 V
4–80
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–67. EP1AGX60 Column Pins Input Timing Parameters (Part 2 of 3)
Fast Corner
I/O Standard
SSTL-2
CLASS I
Clock
SSTL-18
CLASS I
SSTL-18
CLASS II
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS II
Units
tSU
0.948
0.948
1.951
ns
tH
-0.843
-0.843
-1.674
ns
GCLK PLL
tSU
2.519
2.519
5.388
ns
tH
-2.414
-2.414
-5.111
ns
tSU
0.948
0.948
1.951
ns
tH
-0.843
-0.843
-1.674
ns
GCLK PLL
tSU
2.519
2.519
5.388
ns
tH
-2.414
-2.414
-5.111
ns
GCLK
tSU
0.986
0.986
2.057
ns
tH
-0.881
-0.881
-1.780
ns
GCLK PLL
tSU
2.556
2.556
5.492
ns
tH
-2.451
-2.451
-5.215
ns
GCLK
tSU
0.987
0.987
2.058
ns
tH
-0.882
-0.882
-1.781
ns
tSU
2.558
2.558
5.495
ns
tH
-2.453
-2.453
-5.218
ns
GCLK
tSU
0.986
0.986
2.057
ns
tH
-0.881
-0.881
-1.780
ns
GCLK PLL
tSU
2.556
2.556
5.492
ns
tH
-2.451
-2.451
-5.215
ns
GCLK
tSU
0.987
0.987
2.058
ns
tH
-0.882
-0.882
-1.781
ns
GCLK PLL
tSU
2.558
2.558
5.495
ns
tH
-2.453
-2.453
-5.218
ns
GCLK PLL
GCLK
1.5-V HSTL
CLASS I
Commercial
GCLK
GCLK
SSTL-2
CLASS II
Industrial
-6 Speed
Grade
Parameter
GCLK PLL
Altera Corporation
May 2008
tSU
1.004
1.004
2.185
ns
tH
-0.899
-0.899
-1.908
ns
tSU
2.574
2.574
5.620
ns
tH
-2.469
-2.469
-5.343
ns
4–81
Arria GX Device Handbook, Volume 1
Typical Design Performance
Table 4–67. EP1AGX60 Column Pins Input Timing Parameters (Part 3 of 3)
Fast Corner
I/O Standard
1.5-V HSTL
CLASS II
Clock
Industrial
Commercial
-6 Speed
Grade
Parameter
Units
GCLK
tSU
1.005
1.005
2.186
ns
tH
-0.900
-0.900
-1.909
ns
GCLK PLL
tSU
2.576
2.576
5.623
ns
tH
-2.471
-2.471
-5.346
ns
tSU
1.129
1.129
2.481
ns
tH
-1.024
-1.024
-2.204
ns
GCLK PLL
tSU
2.699
2.699
5.916
ns
tH
-2.594
-2.594
-5.639
ns
GCLK
tSU
1.129
1.129
2.481
ns
tH
-1.024
-1.024
-2.204
ns
GCLK PLL
tSU
2.699
2.699
5.916
ns
tH
-2.594
-2.594
-5.639
ns
GCLK
tSU
0.980
0.980
2.062
ns
tH
-0.875
-0.875
-1.785
ns
GCLK
3.3-V PCI
3.3-V PCI-X
LVDS
GCLK PLL
tSU
2.557
2.557
5.512
ns
tH
-2.452
-2.452
-5.235
ns
Table 4–68 describes I/O timing specifications.
Table 4–68. EP1AGX60 Row Pins Output Timing Parameters (Part 1 of 3)
I/O
Standard
Fast Model
Drive
Strength
Clock
Commercial
-6 Speed
Grade
Units
Industrial
3.3-V
LVTTL
4 mA
GCLK
tCO
3.052
3.052
7.142
ns
GCLK PLL
tCO
1.490
1.490
3.719
ns
3.3-V
LVTTL
8 mA
3.3-V
LVTTL
12 mA
3.3-V
LVCMOS
4 mA
Parameter
GCLK
tCO
2.924
2.924
6.502
ns
GCLK PLL
tCO
1.362
1.362
3.079
ns
GCLK
tCO
2.868
2.868
6.465
ns
GCLK PLL
tCO
1.306
1.306
3.042
ns
GCLK
tCO
2.924
2.924
6.502
ns
GCLK PLL
tCO
1.362
1.362
3.079
ns
4–82
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–68. EP1AGX60 Row Pins Output Timing Parameters (Part 2 of 3)
I/O
Standard
Fast Model
Drive
Strength
Clock
3.3-V
LVCMOS
8 mA
GCLK
2.5 V
4 mA
2.5 V
8 mA
2.5 V
12 mA
1.8 V
2 mA
1.8 V
4 mA
1.8 V
6 mA
1.8 V
8 mA
1.5 V
2 mA
1.5 V
4 mA
SSTL-2
CLASS I
8 mA
SSTL-2
CLASS I
12 mA
SSTL-2
CLASS II
16 mA
SSTL-18
CLASS I
4 mA
SSTL-18
CLASS I
6 mA
Altera Corporation
May 2008
Industrial
Commercial
-6 Speed
Grade
tCO
2.818
2.818
6.196
ns
GCLK PLL
tCO
1.256
1.256
2.773
ns
GCLK
tCO
2.907
2.907
6.476
ns
GCLK PLL
tCO
1.345
1.345
3.053
ns
Parameter
Units
GCLK
tCO
2.804
2.804
6.218
ns
GCLK PLL
tCO
1.242
1.242
2.795
ns
GCLK
tCO
2.785
2.785
6.104
ns
GCLK PLL
tCO
1.223
1.223
2.681
ns
GCLK
tCO
2.991
2.991
7.521
ns
GCLK PLL
tCO
1.419
1.419
4.078
ns
GCLK
tCO
2.980
2.980
6.742
ns
GCLK PLL
tCO
1.408
1.408
3.299
ns
GCLK
tCO
2.869
2.869
6.441
ns
GCLK PLL
tCO
1.297
1.297
2.998
ns
GCLK
tCO
2.838
2.838
6.327
ns
GCLK PLL
tCO
1.266
1.266
2.884
ns
GCLK
tCO
2.951
2.951
7.020
ns
GCLK PLL
tCO
1.379
1.379
3.577
ns
GCLK
tCO
2.844
2.844
6.419
ns
GCLK PLL
tCO
1.272
1.272
2.976
ns
GCLK
tCO
2.774
2.774
6.057
ns
GCLK PLL
tCO
1.211
1.211
2.633
ns
GCLK
tCO
2.750
2.750
5.981
ns
GCLK PLL
tCO
1.187
1.187
2.557
ns
GCLK
tCO
2.716
2.716
5.850
ns
GCLK PLL
tCO
1.153
1.153
2.426
ns
GCLK
tCO
2.776
2.776
6.025
ns
GCLK PLL
tCO
1.204
1.204
2.582
ns
GCLK
tCO
2.780
2.780
5.954
ns
GCLK PLL
tCO
1.208
1.208
2.511
ns
4–83
Arria GX Device Handbook, Volume 1
Typical Design Performance
Table 4–68. EP1AGX60 Row Pins Output Timing Parameters (Part 3 of 3)
I/O
Standard
Fast Model
Drive
Strength
Clock
SSTL-18
CLASS I
8 mA
GCLK
SSTL-18
CLASS I
10 mA
1.8-V HSTL
CLASS I
4 mA
1.8-V HSTL
CLASS I
6 mA
1.8-V HSTL
CLASS I
8 mA
1.8-V HSTL
CLASS I
10 mA
1.8-V HSTL
CLASS I
12 mA
1.5-V HSTL
CLASS I
4 mA
1.5-V HSTL
CLASS I
6 mA
1.5-V HSTL
CLASS I
8 mA
LVDS
-
Industrial
Commercial
-6 Speed
Grade
tCO
2.756
2.756
5.937
ns
GCLK PLL
tCO
1.184
1.184
2.494
ns
GCLK
tCO
2.759
2.759
5.916
ns
GCLK PLL
tCO
1.187
1.187
2.473
ns
Parameter
Units
GCLK
tCO
2.757
2.757
5.935
ns
GCLK PLL
tCO
1.185
1.185
2.492
ns
GCLK
tCO
2.760
2.760
5.899
ns
GCLK PLL
tCO
1.188
1.188
2.456
ns
GCLK
tCO
2.742
2.742
5.895
ns
GCLK PLL
tCO
1.170
1.170
2.452
ns
GCLK
tCO
2.746
2.746
5.884
ns
GCLK PLL
tCO
1.174
1.174
2.441
ns
GCLK
tCO
2.737
2.737
5.883
ns
GCLK PLL
tCO
1.165
1.165
2.440
ns
GCLK
tCO
2.756
2.756
5.912
ns
GCLK PLL
tCO
1.184
1.184
2.469
ns
GCLK
tCO
2.759
2.759
5.898
ns
GCLK PLL
tCO
1.187
1.187
2.455
ns
GCLK
tCO
2.744
2.744
5.890
ns
GCLK PLL
tCO
1.172
1.172
2.447
ns
GCLK
tCO
2.787
2.787
6.037
ns
GCLK PLL
tCO
1.228
1.228
2.618
ns
Units
Table 4–69 describes I/O timing specifications.
Table 4–69. EP1AGX60 Column Pins Output Timing Parameters (Part 1 of 5)
IO Standard
3.3-V
LVTTL
Fast Corner
Drive
Strength
Clock
4 mA
GCLK
GCLK PLL
4–84
Arria GX Device Handbook, Volume 1
Industrial
Commercial
-6 Speed
Grade
tCO
3.036
3.036
6.963
ns
tCO
1.466
1.466
3.528
ns
Parameter
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–69. EP1AGX60 Column Pins Output Timing Parameters (Part 2 of 5)
Fast Corner
Drive
Strength
Clock
3.3-V
LVTTL
8 mA
GCLK
3.3-V
LVTTL
12 mA
3.3-V
LVTTL
16 mA
3.3-V
LVTTL
20 mA
3.3-V
LVTTL
24 mA
3.3-V
LVCMOS
4 mA
3.3-V
LVCMOS
8 mA
3.3-V
LVCMOS
12 mA
3.3-V
LVCMOS
16 mA
3.3-V
LVCMOS
20 mA
3.3-V
LVCMOS
24 mA
2.5 V
4 mA
IO Standard
2.5 V
8 mA
2.5 V
12 mA
2.5 V
16 mA
Altera Corporation
May 2008
Industrial
Commercial
-6 Speed
Grade
tCO
2.891
2.891
6.591
ns
GCLK PLL
tCO
1.321
1.321
3.156
ns
GCLK
tCO
2.824
2.824
6.591
ns
GCLK PLL
tCO
1.254
1.254
3.156
ns
Parameter
Units
GCLK
tCO
2.798
2.798
6.422
ns
GCLK PLL
tCO
1.228
1.228
2.987
ns
GCLK
tCO
2.776
2.776
6.297
ns
GCLK PLL
tCO
1.206
1.206
2.862
ns
GCLK
tCO
2.769
2.769
6.299
ns
GCLK PLL
tCO
1.199
1.199
2.864
ns
GCLK
tCO
2.891
2.891
6.591
ns
GCLK PLL
tCO
1.321
1.321
3.156
ns
GCLK
tCO
2.799
2.799
6.296
ns
GCLK PLL
tCO
1.229
1.229
2.861
ns
GCLK
tCO
2.771
2.771
6.218
ns
GCLK PLL
tCO
1.201
1.201
2.783
ns
GCLK
tCO
2.778
2.778
6.186
ns
GCLK PLL
tCO
1.208
1.208
2.751
ns
GCLK
tCO
2.765
2.765
6.168
ns
GCLK PLL
tCO
1.195
1.195
2.733
ns
GCLK
tCO
2.754
2.754
6.146
ns
GCLK PLL
tCO
1.184
1.184
2.711
ns
GCLK
tCO
2.853
2.853
6.623
ns
GCLK PLL
tCO
1.283
1.283
3.188
ns
GCLK
tCO
2.801
2.801
6.361
ns
GCLK PLL
tCO
1.231
1.231
2.926
ns
GCLK
tCO
2.780
2.780
6.244
ns
GCLK PLL
tCO
1.210
1.210
2.809
ns
GCLK
tCO
2.762
2.762
6.170
ns
GCLK PLL
tCO
1.192
1.192
2.735
ns
4–85
Arria GX Device Handbook, Volume 1
Typical Design Performance
Table 4–69. EP1AGX60 Column Pins Output Timing Parameters (Part 3 of 5)
Fast Corner
Drive
Strength
Clock
1.8 V
2 mA
GCLK
1.8 V
4 mA
IO Standard
1.8 V
6 mA
1.8 V
8 mA
1.8 V
10 mA
1.8 V
12 mA
1.5 V
2 mA
1.5 V
4 mA
1.5 V
6 mA
1.5 V
8 mA
SSTL-2
CLASS I
8 mA
SSTL-2
CLASS I
12 mA
SSTL-2
CLASS II
16 mA
SSTL-2
CLASS II
20 mA
SSTL-2
CLASS II
24 mA
Industrial
Commercial
-6 Speed
Grade
tCO
2.893
2.893
7.615
ns
GCLK PLL
tCO
1.323
1.323
4.180
ns
GCLK
tCO
2.898
2.898
6.841
ns
GCLK PLL
tCO
1.328
1.328
3.406
ns
Parameter
Units
GCLK
tCO
2.822
2.822
6.577
ns
GCLK PLL
tCO
1.252
1.252
3.142
ns
GCLK
tCO
2.824
2.824
6.486
ns
GCLK PLL
tCO
1.254
1.254
3.051
ns
GCLK
tCO
2.778
2.778
6.409
ns
GCLK PLL
tCO
1.208
1.208
2.974
ns
GCLK
tCO
2.779
2.779
6.352
ns
GCLK PLL
tCO
1.209
1.209
2.917
ns
GCLK
tCO
2.873
2.873
7.145
ns
GCLK PLL
tCO
1.303
1.303
3.710
ns
GCLK
tCO
2.809
2.809
6.576
ns
GCLK PLL
tCO
1.239
1.239
3.141
ns
GCLK
tCO
2.812
2.812
6.458
ns
GCLK PLL
tCO
1.242
1.242
3.023
ns
GCLK
tCO
2.771
2.771
6.405
ns
GCLK PLL
tCO
1.201
1.201
2.970
ns
GCLK
tCO
2.757
2.757
6.184
ns
GCLK PLL
tCO
1.184
1.184
2.744
ns
GCLK
tCO
2.740
2.740
6.134
ns
GCLK PLL
tCO
1.167
1.167
2.694
ns
GCLK
tCO
2.718
2.718
6.061
ns
GCLK PLL
tCO
1.145
1.145
2.621
ns
GCLK
tCO
2.719
2.719
6.048
ns
GCLK PLL
tCO
1.146
1.146
2.608
ns
GCLK
tCO
2.715
2.715
6.046
ns
GCLK PLL
tCO
1.142
1.142
2.606
ns
4–86
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–69. EP1AGX60 Column Pins Output Timing Parameters (Part 4 of 5)
Fast Corner
Drive
Strength
Clock
SSTL-18
CLASS I
4 mA
GCLK
SSTL-18
CLASS I
6 mA
SSTL-18
CLASS I
8 mA
SSTL-18
CLASS I
10 mA
SSTL-18
CLASS I
12 mA
SSTL-18
CLASS II
8 mA
SSTL-18
CLASS II
16 mA
SSTL-18
CLASS II
18 mA
SSTL-18
CLASS II
20 mA
1.8-V HSTL
CLASS I
4 mA
1.8-V HSTL
CLASS I
6 mA
1.8-V HSTL
CLASS I
8 mA
1.8-V HSTL
CLASS I
10 mA
1.8-V HSTL
CLASS I
12 mA
1.8-V HSTL
CLASS II
16 mA
IO Standard
Altera Corporation
May 2008
Industrial
Commercial
-6 Speed
Grade
tCO
2.753
2.753
6.155
ns
GCLK PLL
tCO
1.183
1.183
2.720
ns
GCLK
tCO
2.758
2.758
6.116
ns
GCLK PLL
tCO
1.185
1.185
2.676
ns
Parameter
Units
GCLK
tCO
2.737
2.737
6.097
ns
GCLK PLL
tCO
1.164
1.164
2.657
ns
GCLK
tCO
2.742
2.742
6.095
ns
GCLK PLL
tCO
1.169
1.169
2.655
ns
GCLK
tCO
2.736
2.736
6.081
ns
GCLK PLL
tCO
1.163
1.163
2.641
ns
GCLK
tCO
2.725
2.725
6.047
ns
GCLK PLL
tCO
1.152
1.152
2.607
ns
GCLK
tCO
2.737
2.737
6.025
ns
GCLK PLL
tCO
1.164
1.164
2.585
ns
GCLK
tCO
2.733
2.733
6.033
ns
GCLK PLL
tCO
1.160
1.160
2.593
ns
GCLK
tCO
2.733
2.733
6.031
ns
GCLK PLL
tCO
1.160
1.160
2.591
ns
GCLK
tCO
2.756
2.756
6.086
ns
GCLK PLL
tCO
1.186
1.186
2.651
ns
GCLK
tCO
2.762
2.762
6.071
ns
GCLK PLL
tCO
1.189
1.189
2.631
ns
GCLK
tCO
2.740
2.740
6.060
ns
GCLK PLL
tCO
1.167
1.167
2.620
ns
GCLK
tCO
2.744
2.744
6.066
ns
GCLK PLL
tCO
1.171
1.171
2.626
ns
GCLK
tCO
2.736
2.736
6.059
ns
GCLK PLL
tCO
1.163
1.163
2.619
ns
GCLK
tCO
2.719
2.719
5.823
ns
GCLK PLL
tCO
1.146
1.146
2.383
ns
4–87
Arria GX Device Handbook, Volume 1
Typical Design Performance
Table 4–69. EP1AGX60 Column Pins Output Timing Parameters (Part 5 of 5)
Fast Corner
Drive
Strength
Clock
1.8-V HSTL
CLASS II
18 mA
GCLK
1.8-V HSTL
CLASS II
20 mA
1.5-V HSTL
CLASS I
4 mA
1.5-V HSTL
CLASS I
6 mA
1.5-V HSTL
CLASS I
8 mA
1.5-V HSTL
CLASS I
10 mA
1.5-V HSTL
CLASS I
12 mA
1.5-V HSTL
CLASS II
16 mA
1.5-V HSTL
CLASS II
18 mA
1.5-V HSTL
CLASS II
20 mA
IO Standard
3.3-V PCI
-
3.3-V PCI-X
-
LVDS
-
Industrial
Commercial
-6 Speed
Grade
tCO
2.721
2.721
5.834
ns
GCLK PLL
tCO
1.148
1.148
2.394
ns
GCLK
tCO
2.721
2.721
5.843
ns
GCLK PLL
tCO
1.148
1.148
2.403
ns
Parameter
Units
GCLK
tCO
2.756
2.756
6.085
ns
GCLK PLL
tCO
1.186
1.186
2.650
ns
GCLK
tCO
2.761
2.761
6.063
ns
GCLK PLL
tCO
1.188
1.188
2.623
ns
GCLK
tCO
2.743
2.743
6.065
ns
GCLK PLL
tCO
1.170
1.170
2.625
ns
GCLK
tCO
2.743
2.743
6.067
ns
GCLK PLL
tCO
1.170
1.170
2.627
ns
GCLK
tCO
2.737
2.737
6.065
ns
GCLK PLL
tCO
1.164
1.164
2.625
ns
GCLK
tCO
2.724
2.724
5.877
ns
GCLK PLL
tCO
1.151
1.151
2.437
ns
GCLK
tCO
2.727
2.727
5.887
ns
GCLK PLL
tCO
1.154
1.154
2.447
ns
GCLK
tCO
2.729
2.729
5.900
ns
GCLK PLL
tCO
1.156
1.156
2.460
ns
GCLK
tCO
2.882
2.882
6.213
ns
GCLK PLL
tCO
1.312
1.312
2.778
ns
GCLK
tCO
2.882
2.882
6.213
ns
GCLK PLL
tCO
1.312
1.312
2.778
ns
GCLK
tCO
3.746
3.746
7.396
ns
GCLK PLL
tCO
2.185
2.185
3.973
ns
Tables 4–70 through 4–71 show EP1AGX60 regional clock (RCLK) adder
values that should be added to the GCLK values. These adder values are
used to determine I/O timing when the I/O pin is driven using the
regional clock. This applies for all I/O standards supported by Arria GX
with general purpose I/O pins.
4–88
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–70 describes row pin delay adders when using the regional clock
in Arria GX devices.
Table 4–70. EP1AGX60 Row Pin Delay Adders for Regional Clock
Fast Corner
Industrial
Commercial
-6 Speed
Grade
0.138
0.138
0.311
ns
-0.003
-0.003
-0.006
ns
-0.138
-0.138
-0.311
ns
0.003
0.003
0.006
ns
Parameter
RCLK input
Units
adder
RCLK PLL
input adder
RCLK output
adder
RCLK PLL
output adder
Table 4–71 describes column pin delay adders when using the regional
clock in Arria GX devices.
Table 4–71. EP1AGX60 Column Pin Delay Adders for Regional Clock
Fast Corner
Industrial
Commercial
-6 Speed
Grade
0.153
0.153
0.344
ns
-1.066
-1.066
-2.338
ns
-0.153
-0.153
-0.343
ns
1.721
1.721
4.486
ns
Parameter
RCLK input
Units
adder
RCLK PLL
input adder
RCLK output
adder
RCLK PLL
output adder
Altera Corporation
May 2008
4–89
Arria GX Device Handbook, Volume 1
Typical Design Performance
EP1AGX90 I/O Timing Parameters
Tables 4–72 through 4–75 show the maximum I/O timing parameters for
EP1AGX90 devices for I/O standards which support general purpose
I/O pins.
Table 4–72 describes I/O timing specifications.
Table 4–72. EP1AGX90 Row Pins Input Timing Parameters (Part 1 of 3)
Fast Model
I/O Standard
Clock
Parameter
Industrial
1.295
1.295
2.873
ns
tH
-1.190
-1.190
-2.596
ns
GCLK PLL
tSU
3.366
3.366
7.017
ns
tH
-3.261
-3.261
-6.740
ns
GCLK
tSU
1.295
1.295
2.873
ns
tH
-1.190
-1.190
-2.596
ns
3.3-V LVTTL
GCLK PLL
GCLK
2.5 V
tSU
3.366
3.366
7.017
ns
tH
-3.261
-3.261
-6.740
ns
tSU
1.307
1.307
2.854
ns
tH
-1.202
-1.202
-2.577
ns
tSU
3.378
3.378
6.998
ns
tH
-3.273
-3.273
-6.721
ns
GCLK
tSU
1.381
1.381
3.073
ns
tH
-1.276
-1.276
-2.796
ns
GCLK PLL
tSU
3.434
3.434
7.191
ns
tH
-3.329
-3.329
-6.914
ns
GCLK PLL
1.8 V
GCLK
1.5 V
GCLK PLL
GCLK
SSTL-2
CLASS I
Units
tSU
GCLK
3.3-V
LVCMOS
Commercial
-6 Speed
Grade
GCLK PLL
tSU
1.384
1.384
3.168
ns
tH
-1.279
-1.279
-2.891
ns
tSU
3.437
3.437
7.286
ns
tH
-3.332
-3.332
-7.009
ns
tSU
1.121
1.121
2.329
ns
tH
-1.016
-1.016
-2.052
ns
tSU
3.187
3.187
6.466
ns
tH
-3.082
-3.082
-6.189
ns
4–90
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–72. EP1AGX90 Row Pins Input Timing Parameters (Part 2 of 3)
Fast Model
I/O Standard
SSTL-2
CLASS II
Clock
SSTL-18
CLASS II
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS II
1.5-V HSTL
CLASS I
Units
tSU
1.121
1.121
2.329
ns
tH
-1.016
-1.016
-2.052
ns
GCLK PLL
tSU
3.187
3.187
6.466
ns
tH
-3.082
-3.082
-6.189
ns
tSU
1.159
1.159
2.447
ns
tH
-1.054
-1.054
-2.170
ns
GCLK PLL
tSU
3.212
3.212
6.565
ns
tH
-3.107
-3.107
-6.288
ns
GCLK
tSU
1.157
1.157
2.441
ns
tH
-1.052
-1.052
-2.164
ns
GCLK PLL
tSU
3.235
3.235
6.597
ns
tH
-3.130
-3.130
-6.320
ns
GCLK
tSU
1.159
1.159
2.447
ns
tH
-1.054
-1.054
-2.170
ns
tSU
3.212
3.212
6.565
ns
tH
-3.107
-3.107
-6.288
ns
GCLK
tSU
1.157
1.157
2.441
ns
tH
-1.052
-1.052
-2.164
ns
GCLK PLL
tSU
3.235
3.235
6.597
ns
tH
-3.130
-3.130
-6.320
ns
GCLK
tSU
1.185
1.185
2.575
ns
tH
-1.080
-1.080
-2.298
ns
GCLK PLL
tSU
3.238
3.238
6.693
ns
tH
-3.133
-3.133
-6.416
ns
GCLK PLL
GCLK
1.5-V HSTL
CLASS II
Commercial
GCLK
GCLK
SSTL-18
CLASS I
Industrial
-6 Speed
Grade
Parameter
GCLK PLL
Altera Corporation
May 2008
tSU
1.183
1.183
2.569
ns
tH
-1.078
-1.078
-2.292
ns
tSU
3.261
3.261
6.725
ns
tH
-3.156
-3.156
-6.448
ns
4–91
Arria GX Device Handbook, Volume 1
Typical Design Performance
Table 4–72. EP1AGX90 Row Pins Input Timing Parameters (Part 3 of 3)
Fast Model
I/O Standard
Clock
Industrial
Commercial
-6 Speed
Grade
Parameter
Units
GCLK
tSU
1.098
1.098
2.439
ns
tH
-0.993
-0.993
-2.162
ns
GCLK PLL
tSU
3.160
3.160
6.566
ns
tH
-3.055
-3.055
-6.289
ns
LVDS
Table 4–73 describes I/O timing specifications.
Table 4–73. EP1AGX90 Column Pins Input Timing Parameters (Part 1 of 3)
Fast Corner
I/O Standard
Clock
Commercial
Units
GCLK
tSU
1.018
1.018
2.290
ns
tH
-0.913
-0.913
-2.013
ns
GCLK PLL
tSU
3.082
3.082
6.425
ns
tH
-2.977
-2.977
-6.148
ns
3.3-V LVTTL
tSU
1.018
1.018
2.290
ns
tH
-0.913
-0.913
-2.013
ns
GCLK PLL
tSU
3.082
3.082
6.425
ns
tH
-2.977
-2.977
-6.148
ns
GCLK
tSU
1.028
1.028
2.272
ns
tH
-0.923
-0.923
-1.995
ns
GCLK PLL
tSU
3.092
3.092
6.407
ns
tH
-2.987
-2.987
-6.130
ns
GCLK
tSU
1.094
1.094
2.482
ns
tH
-0.989
-0.989
-2.205
ns
GCLK
3.3-V
LVCMOS
Industrial
-6 Speed
Grade
Parameter
2.5 V
1.8 V
tSU
3.158
3.158
6.617
ns
tH
-3.053
-3.053
-6.340
ns
GCLK
tSU
1.097
1.097
2.575
ns
tH
-0.992
-0.992
-2.298
ns
GCLK PLL
tSU
3.161
3.161
6.710
ns
tH
-3.056
-3.056
-6.433
ns
GCLK PLL
1.5 V
4–92
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–73. EP1AGX90 Column Pins Input Timing Parameters (Part 2 of 3)
Fast Corner
I/O Standard
SSTL-2
CLASS I
Clock
SSTL-18
CLASS I
SSTL-18
CLASS II
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS II
Units
tSU
0.844
0.844
1.751
ns
tH
-0.739
-0.739
-1.474
ns
GCLK PLL
tSU
2.908
2.908
5.886
ns
tH
-2.803
-2.803
-5.609
ns
tSU
0.844
0.844
1.751
ns
tH
-0.739
-0.739
-1.474
ns
GCLK PLL
tSU
2.908
2.908
5.886
ns
tH
-2.803
-2.803
-5.609
ns
GCLK
tSU
0.880
0.880
1.854
ns
tH
-0.775
-0.775
-1.577
ns
GCLK PLL
tSU
2.944
2.944
5.989
ns
tH
-2.839
-2.839
-5.712
ns
GCLK
tSU
0.883
0.883
1.858
ns
tH
-0.778
-0.778
-1.581
ns
tSU
2.947
2.947
5.993
ns
tH
-2.842
-2.842
-5.716
ns
GCLK
tSU
0.880
0.880
1.854
ns
tH
-0.775
-0.775
-1.577
ns
GCLK PLL
tSU
2.944
2.944
5.989
ns
tH
-2.839
-2.839
-5.712
ns
GCLK
tSU
0.883
0.883
1.858
ns
tH
-0.778
-0.778
-1.581
ns
GCLK PLL
tSU
2.947
2.947
5.993
ns
tH
-2.842
-2.842
-5.716
ns
GCLK PLL
GCLK
1.5-V HSTL
CLASS I
Commercial
GCLK
GCLK
SSTL-2
CLASS II
Industrial
-6 Speed
Grade
Parameter
GCLK PLL
Altera Corporation
May 2008
tSU
0.898
0.898
1.982
ns
tH
-0.793
-0.793
-1.705
ns
tSU
2.962
2.962
6.117
ns
tH
-2.857
-2.857
-5.840
ns
4–93
Arria GX Device Handbook, Volume 1
Typical Design Performance
Table 4–73. EP1AGX90 Column Pins Input Timing Parameters (Part 3 of 3)
Fast Corner
I/O Standard
1.5-V HSTL
CLASS II
Clock
Industrial
Commercial
-6 Speed
Grade
Parameter
Units
GCLK
tSU
0.901
0.901
1.986
ns
tH
-0.796
-0.796
-1.709
ns
GCLK PLL
tSU
2.965
2.965
6.121
ns
tH
-2.860
-2.860
-5.844
ns
tSU
1.023
1.023
2.278
ns
tH
-0.918
-0.918
-2.001
ns
GCLK PLL
tSU
3.087
3.087
6.413
ns
tH
-2.982
-2.982
-6.136
ns
GCLK
tSU
1.023
1.023
2.278
ns
tH
-0.918
-0.918
-2.001
ns
GCLK PLL
tSU
3.087
3.087
6.413
ns
tH
-2.982
-2.982
-6.136
ns
GCLK
tSU
0.891
0.891
1.920
ns
tH
-0.786
-0.786
-1.643
ns
GCLK
3.3-V PCI
3.3-V PCI-X
LVDS
GCLK PLL
tSU
2.963
2.963
6.066
ns
tH
-2.858
-2.858
-5.789
ns
Table 4–74 describes I/O timing specifications.
Table 4–74. EP1AGX90 Row Pins Output Timing Parameters (Part 1 of 3)
I/O
Standard
Fast Model
Drive
Strength
Clock
Commercial
-6 Speed
Grade
Units
Industrial
3.3-V
LVTTL
4 mA
GCLK
tCO
3.170
3.170
7.382
ns
GCLK PLL
tCO
1.099
1.099
3.238
ns
3.3-V
LVTTL
8 mA
3.3-V
LVTTL
12 mA
3.3-V
LVCMOS
4 mA
Parameter
GCLK
tCO
3.042
3.042
6.742
ns
GCLK PLL
tCO
0.971
0.971
2.598
ns
GCLK
tCO
2.986
2.986
6.705
ns
GCLK PLL
tCO
0.915
0.915
2.561
ns
GCLK
tCO
3.042
3.042
6.742
ns
GCLK PLL
tCO
0.971
0.971
2.598
ns
4–94
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–74. EP1AGX90 Row Pins Output Timing Parameters (Part 2 of 3)
I/O
Standard
Fast Model
Drive
Strength
Clock
3.3-V
LVCMOS
8 mA
GCLK
2.5 V
4 mA
2.5 V
8 mA
2.5 V
12 mA
1.8 V
2 mA
1.8 V
4 mA
1.8 V
6 mA
1.8 V
8 mA
1.5 V
2 mA
1.5 V
4 mA
SSTL-2
CLASS I
8 mA
SSTL-2
CLASS I
12 mA
SSTL-2
CLASS II
16 mA
SSTL-18
CLASS I
4 mA
SSTL-18
CLASS I
6 mA
Altera Corporation
May 2008
Industrial
Commercial
-6 Speed
Grade
tCO
2.936
2.936
6.436
ns
GCLK PLL
tCO
0.865
0.865
2.292
ns
GCLK
tCO
3.025
3.025
6.716
ns
GCLK PLL
tCO
0.954
0.954
2.572
ns
Parameter
Units
GCLK
tCO
2.922
2.922
6.458
ns
GCLK PLL
tCO
0.851
0.851
2.314
ns
GCLK
tCO
2.903
2.903
6.344
ns
GCLK PLL
tCO
0.832
0.832
2.200
ns
GCLK
tCO
3.087
3.087
7.723
ns
GCLK PLL
tCO
1.034
1.034
3.605
ns
GCLK
tCO
3.076
3.076
6.944
ns
GCLK PLL
tCO
1.023
1.023
2.826
ns
GCLK
tCO
2.965
2.965
6.643
ns
GCLK PLL
tCO
0.912
0.912
2.525
ns
GCLK
tCO
2.934
2.934
6.529
ns
GCLK PLL
tCO
0.881
0.881
2.411
ns
GCLK
tCO
3.047
3.047
7.222
ns
GCLK PLL
tCO
0.994
0.994
3.104
ns
GCLK
tCO
2.940
2.940
6.621
ns
GCLK PLL
tCO
0.887
0.887
2.503
ns
GCLK
tCO
2.890
2.890
6.294
ns
GCLK PLL
tCO
0.824
0.824
2.157
ns
GCLK
tCO
2.866
2.866
6.218
ns
GCLK PLL
tCO
0.800
0.800
2.081
ns
GCLK
tCO
2.832
2.832
6.087
ns
GCLK PLL
tCO
0.766
0.766
1.950
ns
GCLK
tCO
2.872
2.872
6.227
ns
GCLK PLL
tCO
0.819
0.819
2.109
ns
GCLK
tCO
2.878
2.878
6.162
ns
GCLK PLL
tCO
0.800
0.800
2.006
ns
4–95
Arria GX Device Handbook, Volume 1
Typical Design Performance
Table 4–74. EP1AGX90 Row Pins Output Timing Parameters (Part 3 of 3)
I/O
Standard
Fast Model
Drive
Strength
Clock
SSTL-18
CLASS I
8 mA
GCLK
SSTL-18
CLASS I
10 mA
1.8-V HSTL
CLASS I
4 mA
1.8-V HSTL
CLASS I
6 mA
1.8-V HSTL
CLASS I
8 mA
1.8-V HSTL
CLASS I
10 mA
1.8-V HSTL
CLASS I
12 mA
1.5-V HSTL
CLASS I
4 mA
1.5-V HSTL
CLASS I
6 mA
1.5-V HSTL
CLASS I
8 mA
LVDS
-
Industrial
Commercial
-6 Speed
Grade
tCO
2.854
2.854
6.145
ns
GCLK PLL
tCO
0.776
0.776
1.989
ns
GCLK
tCO
2.857
2.857
6.124
ns
GCLK PLL
tCO
0.779
0.779
1.968
ns
Parameter
Units
GCLK
tCO
2.853
2.853
6.137
ns
GCLK PLL
tCO
0.800
0.800
2.019
ns
GCLK
tCO
2.858
2.858
6.107
ns
GCLK PLL
tCO
0.780
0.780
1.951
ns
GCLK
tCO
2.840
2.840
6.103
ns
GCLK PLL
tCO
0.762
0.762
1.947
ns
GCLK
tCO
2.844
2.844
6.092
ns
GCLK PLL
tCO
0.766
0.766
1.936
ns
GCLK
tCO
2.835
2.835
6.091
ns
GCLK PLL
tCO
0.757
0.757
1.935
ns
GCLK
tCO
2.852
2.852
6.114
ns
GCLK PLL
tCO
0.799
0.799
1.996
ns
GCLK
tCO
2.857
2.857
6.106
ns
GCLK PLL
tCO
0.779
0.779
1.950
ns
GCLK
tCO
2.842
2.842
6.098
ns
GCLK PLL
tCO
0.764
0.764
1.942
ns
GCLK
tCO
2.898
2.898
6.265
ns
GCLK PLL
tCO
0.831
0.831
2.129
ns
Units
Table 4–75 describes I/O timing specifications.
Table 4–75. EP1AGX90 Column Pins Output Timing Parameters (Part 1 of 5)
I/O
Standard
3.3-V
LVTTL
Fast Corner
Drive
Strength
Clock
4 mA
GCLK
GCLK PLL
4–96
Arria GX Device Handbook, Volume 1
Industrial
Commercial
-6 Speed
Grade
tCO
3.141
3.141
7.164
ns
tCO
1.077
1.077
3.029
ns
Parameter
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–75. EP1AGX90 Column Pins Output Timing Parameters (Part 2 of 5)
I/O
Standard
Fast Corner
Drive
Strength
Clock
3.3-V
LVTTL
8 mA
GCLK
3.3-V
LVTTL
12 mA
3.3-V
LVTTL
16 mA
3.3-V
LVTTL
20 mA
3.3-V
LVTTL
24 mA
3.3-V
LVCMOS
4 mA
3.3-V
LVCMOS
8 mA
3.3-V
LVCMOS
12 mA
3.3-V
LVCMOS
16 mA
3.3-V
LVCMOS
20 mA
3.3-V
LVCMOS
24 mA
2.5 V
4 mA
2.5 V
8 mA
2.5 V
12 mA
2.5 V
16 mA
Altera Corporation
May 2008
Industrial
Commercial
-6 Speed
Grade
tCO
2.996
2.996
6.792
ns
GCLK PLL
tCO
0.932
0.932
2.657
ns
GCLK
tCO
2.929
2.929
6.792
ns
GCLK PLL
tCO
0.865
0.865
2.657
ns
Parameter
Units
GCLK
tCO
2.903
2.903
6.623
ns
GCLK PLL
tCO
0.839
0.839
2.488
ns
GCLK
tCO
2.881
2.881
6.498
ns
GCLK PLL
tCO
0.817
0.817
2.363
ns
GCLK
tCO
2.874
2.874
6.500
ns
GCLK PLL
tCO
0.810
0.810
2.365
ns
GCLK
tCO
2.996
2.996
6.792
ns
GCLK PLL
tCO
0.932
0.932
2.657
ns
GCLK
tCO
2.904
2.904
6.497
ns
GCLK PLL
tCO
0.840
0.840
2.362
ns
GCLK
tCO
2.876
2.876
6.419
ns
GCLK PLL
tCO
0.812
0.812
2.284
ns
GCLK
tCO
2.883
2.883
6.387
ns
GCLK PLL
tCO
0.819
0.819
2.252
ns
GCLK
tCO
2.870
2.870
6.369
ns
GCLK PLL
tCO
0.806
0.806
2.234
ns
GCLK
tCO
2.859
2.859
6.347
ns
GCLK PLL
tCO
0.795
0.795
2.212
ns
GCLK
tCO
2.958
2.958
6.824
ns
GCLK PLL
tCO
0.894
0.894
2.689
ns
GCLK
tCO
2.906
2.906
6.562
ns
GCLK PLL
tCO
0.842
0.842
2.427
ns
GCLK
tCO
2.885
2.885
6.445
ns
GCLK PLL
tCO
0.821
0.821
2.310
ns
GCLK
tCO
2.867
2.867
6.371
ns
GCLK PLL
tCO
0.803
0.803
2.236
ns
4–97
Arria GX Device Handbook, Volume 1
Typical Design Performance
Table 4–75. EP1AGX90 Column Pins Output Timing Parameters (Part 3 of 5)
I/O
Standard
Fast Corner
Drive
Strength
Clock
1.8 V
2 mA
GCLK
1.8 V
4 mA
1.8 V
6 mA
1.8 V
8 mA
1.8 V
10 mA
1.8 V
12 mA
1.5 V
2 mA
1.5 V
4 mA
1.5 V
6 mA
1.5 V
8 mA
SSTL-2
CLASS I
8 mA
SSTL-2
CLASS I
12 mA
SSTL-2
CLASS II
16 mA
SSTL-2
CLASS II
20 mA
SSTL-2
CLASS II
24 mA
Industrial
Commercial
-6 Speed
Grade
tCO
2.998
2.998
7.816
ns
GCLK PLL
tCO
0.934
0.934
3.681
ns
GCLK
tCO
3.003
3.003
7.042
ns
GCLK PLL
tCO
0.939
0.939
2.907
ns
Parameter
Units
GCLK
tCO
2.927
2.927
6.778
ns
GCLK PLL
tCO
0.863
0.863
2.643
ns
GCLK
tCO
2.929
2.929
6.687
ns
GCLK PLL
tCO
0.865
0.865
2.552
ns
GCLK
tCO
2.883
2.883
6.610
ns
GCLK PLL
tCO
0.819
0.819
2.475
ns
GCLK
tCO
2.884
2.884
6.553
ns
GCLK PLL
tCO
0.820
0.820
2.418
ns
GCLK
tCO
2.978
2.978
7.346
ns
GCLK PLL
tCO
0.914
0.914
3.211
ns
GCLK
tCO
2.914
2.914
6.777
ns
GCLK PLL
tCO
0.850
0.850
2.642
ns
GCLK
tCO
2.917
2.917
6.659
ns
GCLK PLL
tCO
0.853
0.853
2.524
ns
GCLK
tCO
2.876
2.876
6.606
ns
GCLK PLL
tCO
0.812
0.812
2.471
ns
GCLK
tCO
2.859
2.859
6.381
ns
GCLK PLL
tCO
0.797
0.797
2.250
ns
GCLK
tCO
2.842
2.842
6.331
ns
GCLK PLL
tCO
0.780
0.780
2.200
ns
GCLK
tCO
2.820
2.820
6.258
ns
GCLK PLL
tCO
0.758
0.758
2.127
ns
GCLK
tCO
2.821
2.821
6.245
ns
GCLK PLL
tCO
0.759
0.759
2.114
ns
GCLK
tCO
2.817
2.817
6.243
ns
GCLK PLL
tCO
0.755
0.755
2.112
ns
4–98
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–75. EP1AGX90 Column Pins Output Timing Parameters (Part 4 of 5)
I/O
Standard
Fast Corner
Drive
Strength
Clock
SSTL-18
CLASS I
4 mA
GCLK
SSTL-18
CLASS I
6 mA
SSTL-18
CLASS I
8 mA
SSTL-18
CLASS I
10 mA
SSTL-18
CLASS I
12 mA
SSTL-18
CLASS II
8 mA
SSTL-18
CLASS II
16 mA
SSTL-18
CLASS II
18 mA
SSTL-18
CLASS II
20 mA
1.8-V HSTL
CLASS I
4 mA
1.8-V HSTL
CLASS I
6 mA
1.8-V HSTL
CLASS I
8 mA
1.8-V HSTL
CLASS I
10 mA
1.8-V HSTL
CLASS I
12 mA
1.8-V HSTL
CLASS II
16 mA
Altera Corporation
May 2008
Industrial
Commercial
-6 Speed
Grade
tCO
2.858
2.858
6.356
ns
GCLK PLL
tCO
0.794
0.794
2.221
ns
GCLK
tCO
2.860
2.860
6.313
ns
GCLK PLL
tCO
0.798
0.798
2.182
ns
Parameter
Units
GCLK
tCO
2.839
2.839
6.294
ns
GCLK PLL
tCO
0.777
0.777
2.163
ns
GCLK
tCO
2.844
2.844
6.292
ns
GCLK PLL
tCO
0.782
0.782
2.161
ns
GCLK
tCO
2.838
2.838
6.278
ns
GCLK PLL
tCO
0.776
0.776
2.147
ns
GCLK
tCO
2.827
2.827
6.244
ns
GCLK PLL
tCO
0.765
0.765
2.113
ns
GCLK
tCO
2.839
2.839
6.222
ns
GCLK PLL
tCO
0.777
0.777
2.091
ns
GCLK
tCO
2.835
2.835
6.230
ns
GCLK PLL
tCO
0.773
0.773
2.099
ns
GCLK
tCO
2.835
2.835
6.228
ns
GCLK PLL
tCO
0.773
0.773
2.097
ns
GCLK
tCO
2.861
2.861
6.287
ns
GCLK PLL
tCO
0.797
0.797
2.152
ns
GCLK
tCO
2.864
2.864
6.268
ns
GCLK PLL
tCO
0.802
0.802
2.137
ns
GCLK
tCO
2.842
2.842
6.257
ns
GCLK PLL
tCO
0.780
0.780
2.126
ns
GCLK
tCO
2.846
2.846
6.263
ns
GCLK PLL
tCO
0.784
0.784
2.132
ns
GCLK
tCO
2.838
2.838
6.256
ns
GCLK PLL
tCO
0.776
0.776
2.125
ns
GCLK
tCO
2.821
2.821
6.020
ns
GCLK PLL
tCO
0.759
0.759
1.889
ns
4–99
Arria GX Device Handbook, Volume 1
Typical Design Performance
Table 4–75. EP1AGX90 Column Pins Output Timing Parameters (Part 5 of 5)
Fast Corner
I/O
Standard
Drive
Strength
Clock
1.8-V HSTL
CLASS II
18 mA
GCLK
1.8-V HSTL
CLASS II
20 mA
1.5-V HSTL
CLASS I
4 mA
1.5-V HSTL
CLASS I
6 mA
1.5-V HSTL
CLASS I
8 mA
1.5-V HSTL
CLASS I
10 mA
1.5-V HSTL
CLASS I
12 mA
1.5-V HSTL
CLASS II
16 mA
1.5-V HSTL
CLASS II
18 mA
1.5-V HSTL
CLASS II
20 mA
3.3-V PCI
-
3.3-V PCI-X
-
LVDS
-
Industrial
Commercial
-6 Speed
Grade
tCO
2.823
2.823
6.031
ns
GCLK PLL
tCO
0.761
0.761
1.900
ns
GCLK
tCO
2.823
2.823
6.040
ns
GCLK PLL
tCO
0.761
0.761
1.909
ns
Parameter
Units
GCLK
tCO
2.861
2.861
6.286
ns
GCLK PLL
tCO
0.797
0.797
2.151
ns
GCLK
tCO
2.863
2.863
6.260
ns
GCLK PLL
tCO
0.801
0.801
2.129
ns
GCLK
tCO
2.845
2.845
6.262
ns
GCLK PLL
tCO
0.783
0.783
2.131
ns
GCLK
tCO
2.845
2.845
6.264
ns
GCLK PLL
tCO
0.783
0.783
2.133
ns
GCLK
tCO
2.839
2.839
6.262
ns
GCLK PLL
tCO
0.777
0.777
2.131
ns
GCLK
tCO
2.826
2.826
6.074
ns
GCLK PLL
tCO
0.764
0.764
1.943
ns
GCLK
tCO
2.829
2.829
6.084
ns
GCLK PLL
tCO
0.767
0.767
1.953
ns
GCLK
tCO
2.831
2.831
6.097
ns
GCLK PLL
tCO
0.769
0.769
1.966
ns
GCLK
tCO
2.987
2.987
6.414
ns
GCLK PLL
tCO
0.923
0.923
2.279
ns
GCLK
tCO
2.987
2.987
6.414
ns
GCLK PLL
tCO
0.923
0.923
2.279
ns
GCLK
tCO
3.835
3.835
7.541
ns
GCLK PLL
tCO
1.769
1.769
3.404
ns
Tables 4–76 through 4–77 show the EP1AGX90 regional clock (RCLK)
adder values that should be added to the GCLK values. These adder
values are used to determine I/O timing when the I/O pin is driven using
the regional clock. This applies for all I/O standards supported by
Arria GX with general purpose I/O pins.
4–100
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–76 describes row pin delay adders when using the regional clock
in Arria GX devices.
Table 4–76. EP1AGX90 Row Pin Delay Adders for Regional Clock
Fast Corner
Industrial
Commercial
-6 Speed
Grade
0.175
0.175
0.418
ns
0.007
0.007
0.015
ns
-0.175
-0.175
-0.418
ns
-0.007
-0.007
-0.015
ns
Parameter
RCLK input
Units
adder
RCLK PLL
input adder
RCLK output
adder
RCLK PLL
output adder
Table 4–77 describes column pin delay adders when using the regional
clock in Arria GX devices.
Table 4–77. EP1AGX90 Column Pin Delay Adders for Regional Clock
Fast Corner
Industrial
Commercial
-6 Speed
Grade
0.138
0.138
0.354
ns
-1.697
-1.697
-3.607
ns
-0.138
-0.138
-0.353
ns
1.966
1.966
5.188
ns
Parameter
RCLK input
Units
adder
RCLK PLL
input adder
RCLK output
adder
RCLK PLL
output adder
Altera Corporation
May 2008
4–101
Arria GX Device Handbook, Volume 1
Typical Design Performance
Dedicated Clock Pin Timing
Tables 4–79 to 4–98 show clock pin timing for Arria GX devices when the
clock is driven by the global clock, regional clock, periphery clock, and a
PLL.
Tables 4–78 describes Arria GX clock timing parameters.
Table 4–78. Arria GX Clock Timing Parameters
Symbol
Parameter
tCIN
Delay from clock pad to I/O input register
tCOUT
Delay from clock pad to I/O output register
tPLLCIN
Delay from PLL inclk pad to I/O input register
tPLLCOUT
Delay from PLL inclk pad to I/O output register
EP1AGX20 Clock Timing Parameters
Tables 4–79 through 4–80 show the GCLK clock timing parameters for
EP1AGX20 devices.
Table 4–79 describes clock timing specifications.
Table 4–79. EP1AGX20 Row Pins Global Clock Timing Parameters
Fast Model
Industrial
Commercial
-6 Speed
Grade
tcin
1.394
1.394
3.161
ns
tcout
1.399
1.399
3.155
ns
tpllcin
-0.027
-0.027
0.091
ns
tpllcout
-0.022
-0.022
0.085
ns
Parameter
Units
Table 4–80 describes clock timing specifications.
Table 4–80. EP1AGX20 Row Pins Global Clock Timing Parameters (Part 1
Fast Model
Industrial
Commercial
-6 Speed
Grade
tCIN
1.655
1.655
3.726
ns
tCOUT
1.655
1.655
3.726
ns
Parameter
4–102
Arria GX Device Handbook, Volume 1
Units
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–80. EP1AGX20 Row Pins Global Clock Timing Parameters (Part 2
Fast Model
Industrial
Commercial
-6 Speed
Grade
tPLLCIN
0.236
0.236
0.655
ns
tPLLCOUT
0.236
0.236
0.655
ns
Parameter
Units
Tables 4–81 through 4–82 show the RCLK clock timing parameters for
EP1AGX20 devices.
Table 4–81 describes clock timing specifications.
Table 4–81. EP1AGX20 Row Pins Regional Clock Timing Parameters
Fast Model
Commercial
-6 Speed
Grade
Units
Industrial
tCIN
1.283
1.283
2.901
ns
tCOUT
1.288
1.288
2.895
ns
tPLLCIN
-0.034
-0.034
0.077
ns
tPLLCOUT
-0.029
-0.029
0.071
ns
Parameter
Table 4–82 describes clock timing specifications.
Table 4–82. EP1AGX20 Row Pins Regional Clock Timing Parameters
Fast Model
Commercial
-6 Speed
Grade
Units
Industrial
tCIN
1.569
1.569
3.487
ns
tCOUT
1.569
1.569
3.487
ns
tPLLCIN
0.278
0.278
0.706
ns
tPLLCOUT
0.278
0.278
0.706
ns
Parameter
Altera Corporation
May 2008
4–103
Arria GX Device Handbook, Volume 1
Typical Design Performance
EP1AGX35 Clock Timing Parameters
Tables 4–83 through 4–84 show the GCLK clock timing parameters for
EP1AGX35 devices.
Table 4–83 describes clock timing specifications.
Table 4–83. EP1AGX35 Row Pins Global Clock Timing Parameters
Fast Model
Industrial
Commercial
-6 Speed
Grade
tCIN
1.394
1.394
3.161
ns
tCOUT
1.399
1.399
3.155
ns
tPLLCIN
-0.027
-0.027
0.091
ns
tPLLCOUT
-0.022
-0.022
0.085
ns
Parameter
Units
Table 4–84 describes clock timing specifications.
Table 4–84. EP1AGX35 Row Pins Global Clock Timing Parameters
Fast Model
Industrial
Commercial
-6 Speed
Grade
tCIN
1.655
1.655
3.726
ns
tCOUT
1.655
1.655
3.726
ns
tPLLCIN
0.236
0.236
0.655
ns
tPLLCOUT
0.236
0.236
0.655
ns
Parameter
Units
Tables 4–85 through 4–86 show the RCLK clock timing parameters for
EP1AGX35 devices.
Table 4–85 describes clock timing specifications.
Table 4–85. EP1AGX35 Row Pins Regional Clock Timing Parameters (Part
Fast Model
Commercial
-6 Speed
Grade
Units
Industrial
tCIN
1.283
1.283
2.901
ns
tCOUT
1.288
1.288
2.895
ns
Parameter
4–104
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–85. EP1AGX35 Row Pins Regional Clock Timing Parameters (Part
Fast Model
Industrial
Commercial
-6 Speed
Grade
tPLLCIN
-0.034
-0.034
0.077
ns
tPLLCOUT
-0.029
-0.029
0.071
ns
Parameter
Units
Table 4–86 describes clock timing specifications.
Table 4–86. EP1AGX35 Row Pins Regional Clock Timing Parameters
Fast Model
Industrial
Commercial
-6 Speed
Grade
tCIN
1.569
1.569
3.487
ns
tCOUT
1.569
1.569
3.487
ns
tPLLCIN
0.278
0.278
0.706
ns
tPLLCOUT
0.278
0.278
0.706
ns
Parameter
Units
EP1AGX50 Clock Timing Parameters
Tables 4–87 through 4–88 show the GCLK clock timing parameters for
EP1AGX50 devices.
Table 4–87 describes clock timing specifications.
Table 4–87. EP1AGX50 Row Pins Global Clock Timing Parameters
Fast Model
Industrial
Commercial
-6 Speed
Grade
tCIN
1.529
1.529
3.587
ns
tCOUT
1.534
1.534
3.581
ns
tPLLCIN
-0.024
-0.024
0.181
ns
tPLLCOUT
-0.019
-0.019
0.175
ns
Parameter
Altera Corporation
May 2008
Units
4–105
Arria GX Device Handbook, Volume 1
Typical Design Performance
Table 4–88 describes clock timing specifications.
Table 4–88. EP1AGX50 Row Pins Global Clock Timing Parameters
Fast Model
Commercial
-6 Speed
Grade
Units
Industrial
tCIN
1.793
1.793
4.165
ns
tCOUT
1.793
1.793
4.165
ns
tPLLCIN
0.238
0.238
0.758
ns
tPLLCOUT
0.238
0.238
0.758
ns
Parameter
Tables 4–89 through 4–90 show the RCLK clock timing parameters for
EP1AGX50 devices.
Table 4–89 describes clock timing specifications.
Table 4–89. EP1AGX50 Row Pins Regional Clock Timing Parameters
Fast Model
Commercial
-6 Speed
Grade
Units
Industrial
tCIN
1.396
1.396
3.287
ns
tCOUT
1.401
1.401
3.281
ns
tPLLCIN
-0.017
-0.017
0.195
ns
tPLLCOUT
-0.012
-0.012
0.189
ns
Parameter
Table 4–90 describes clock timing specifications.
Table 4–90. EP1AGX50 Row Pins Regional Clock Timing Parameters
Fast Model
Commercial
-6 Speed
Grade
Units
Industrial
tCIN
1.653
1.653
3.841
ns
tCOUT
1.651
1.651
3.839
ns
tPLLCIN
0.245
0.245
0.755
ns
tPLLCOUT
0.245
0.245
0.755
ns
Parameter
4–106
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
EP1AGX60 Clock Timing Parameters
Tables 4–91 through 4–92 show the GCLK clock timing parameters for
EP1AGX60 devices.
Table 4–91 describes clock timing specifications.
Table 4–91. EP1AGX60 Row Pins Global Clock Timing Parameters
Fast Model
Industrial
Commercial
-6 Speed
Grade
tCIN
1.531
1.531
3.593
ns
tCOUT
1.536
1.536
3.587
ns
tPLLCIN
-0.023
-0.023
0.188
ns
tPLLCOUT
-0.018
-0.018
0.182
ns
Parameter
Units
Table 4–92 describes clock timing specifications.
Table 4–92. EP1AGX60 Row Pins Global Clock Timing Parameters
Fast Model
Industrial
Commercial
-6 Speed
Grade
tCIN
1.792
1.792
4.165
ns
tCOUT
1.792
1.792
4.165
ns
tPLLCIN
0.238
0.238
0.758
ns
tPLLCOUT
0.238
0.238
0.758
ns
Parameter
Units
Tables 4–93 through 4–94 show the RCLK clock timing parameters for
EP1AGX60 devices.
Table 4–93 describes clock timing specifications.
Table 4–93. EP1AGX60 Row Pins Regional Clock Timing Parameters (Part
Fast Model
Commercial
-6 Speed
Grade
Units
Industrial
tCIN
1.382
1.382
3.268
ns
tCOUT
1.387
1.387
3.262
ns
Parameter
Altera Corporation
May 2008
4–107
Arria GX Device Handbook, Volume 1
Typical Design Performance
Table 4–93. EP1AGX60 Row Pins Regional Clock Timing Parameters (Part
Fast Model
Industrial
Commercial
-6 Speed
Grade
tPLLCIN
-0.031
-0.031
0.174
ns
tPLLCOUT
-0.026
-0.026
0.168
ns
Parameter
Units
Table 4–94 describes clock timing specifications.
Table 4–94. EP1AGX60 Row Pins Regional Clock Timing Parameters
Fast Model
Industrial
Commercial
-6 Speed
Grade
tCIN
1.649
1.649
3.835
ns
tCOUT
1.651
1.651
3.839
ns
tPLLCIN
0.245
0.245
0.755
ns
tPLLCOUT
0.245
0.245
0.755
ns
Parameter
Units
EP1AGX90 Clock Timing Parameters
Tables 4–95 through 4–96 show the GCLK clock timing parameters for
EP1AGX90 devices.
Table 4–95 describes clock timing specifications.
Table 4–95. EP1AGX90 Row Pins Global Clock Timing Parameters
Fast Model
Industrial
Commercial
-6 Speed
Grade
tCIN
1.630
1.630
3.799
ns
tCOUT
1.635
1.635
3.793
ns
tPLLCIN
-0.422
-0.422
-0.310
ns
tPLLCOUT
-0.417
-0.417
-0.316
ns
Parameter
4–108
Arria GX Device Handbook, Volume 1
Units
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–96 describes clock timing specifications.
Table 4–96. EP1AGX90 Row Pins Global Clock Timing Parameters
Fast Model
Commercial
-6 Speed
Grade
Units
Industrial
tCIN
1.904
1.904
4.376
ns
tCOUT
1.904
1.904
4.376
ns
tPLLCIN
-0.153
-0.153
0.254
ns
tPLLCOUT
-0.153
-0.153
0.254
ns
Parameter
Tables 4–97 through 4–98 show the RCLK clock timing parameters for
EP1AGX90 devices.
Table 4–97 describes clock timing specifications.
Table 4–97. EP1AGX90 Row Pins Regional Clock Timing Parameters
Fast Model
Commercial
-6 Speed
Grade
Units
Industrial
tCIN
1.462
1.462
3.407
ns
tCOUT
1.467
1.467
3.401
ns
tPLLCIN
-0.430
-0.430
-0.322
ns
tPLLCOUT
-0.425
-0.425
-0.328
ns
Parameter
Table 4–98 describes clock timing specifications.
Table 4–98. EP1AGX90 Row Pins Regional Clock Timing Parameters
Fast Model
Commercial
-6 Speed
Grade
Units
Industrial
tCIN
1.760
1.760
4.011
ns
tCOUT
1.760
1.760
4.011
ns
tPLLCIN
-0.118
-0.118
0.303
ns
tPLLCOUT
-0.118
-0.118
0.303
ns
Parameter
Altera Corporation
May 2008
4–109
Arria GX Device Handbook, Volume 1
Block Performance
Block
Performance
Table 4–99 shows the Arria GX performance for some common designs.
All performance values were obtained with the Quartus II software
compilation of library of parameterized modules (LPM) or MegaCore
functions for finite impulse response (FIR) and fast Fourier transform
(FFT) designs.
Table 4–99 describes performance notes.
Table 4–99. Arria GX Performance Notes (Part 1 of 3)
Resources Used
Applications
LE
Performance
ALUTs
TriMatrix
Memory Blocks
DSP Blocks
-6 Speed Grade
16-to-1
multiplexer
5
0
0
168.41
32-to-1
multiplexer
11
0
0
334.11
16-bit counter
16
0
0
374.0
64-bit counter
64
0
0
168.41
TriMatrix
Memory M512
block
Simple dual-port
RAM 32 x 18 bit
0
1
0
348.0
FIFO 32 x 18 bit
0
1
0
333.22
TriMatrix
Memory M4K
block
Simple dual-port
RAM 128 x 36 bit
0
1
0
344.71
True dual-port
RAM 128 x 18 bit
0
1
0
348.0
4–110
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–99. Arria GX Performance Notes (Part 2 of 3)
Resources Used
Applications
Performance
ALUTs
TriMatrix
Memory Blocks
DSP Blocks
-6 Speed Grade
Single port RAM
4K x 144 bit
0
2
0
244.0
Simple dual-port
RAM 4K x 144
bit
0
1
0
292.0
True dual-port
RAM 4K x 144
bit
0
2
0
244.0
Single port RAM
8K x 72 bit
0
1
0
247.0
0
1
0
292.0
0
1
0
254.0
Simple dual-port
RAM 16K x 36
bit
0
1
0
292.0
True dual-port
RAM 16K x 36
bit
0
1
0
251.0
Single port RAM
32K x 18 bit
0
1
0
317.36
Simple dual-port
RAM 32K x 18
bit
0
1
0
292.0
True dual-port
RAM 32K x 18
bit
0
1
0
251.0
Single port RAM
64K x 9 bit
0
1
0
254.0
Simple dual-port
RAM 64K x 9 bit
0
1
0
292.0
True dual-port
RAM 64K x 9 bit
0
1
0
251.0
TriMatrix
Simple dual-port
Memory
RAM 8K x 72 bit
MegaRAM block
Single port RAM
16K x 36 bit
Altera Corporation
May 2008
4–111
Arria GX Device Handbook, Volume 1
IOE Programmable Delay
Table 4–99. Arria GX Performance Notes (Part 3 of 3)
Resources Used
Applications
DSP block
Larger Designs
Performance
ALUTs
TriMatrix
Memory Blocks
DSP Blocks
-6 Speed Grade
9 x 9-bit
multiplier
0
0
1
335.35
18 x 18-bit
multiplier
0
0
2
285.0
18 x 18-bit
multiplier
0
0
4
335.35
36 x 36-bit
multiplier
0
0
8
174.4
36 x 36-bit
multiplier
0
0
8
285.0
18-bit 4-tap FIR
filter
0
0
8
163.0
8-bit 16-tap
parallel FIR filter
0
0
4
163.0
IOE
Programmable
Delay
Refer to Tables 4–100 to 4–101 for IOE programmable delay.
Table 4–100 describes IOE programmable delays.
Table 4–100. Arria GX IOE Programmable Delay on Row Pins (Part 1 of 2)
Fast Model
-6 Speed Grade
Paths
Affected
Available
Settings
Input delay from
pin to internal
cells
Pad to I/O
dataout to
core
Input delay from
pin to input
register
Pad to I/O
input register
Parameter
Industrial
Commercial
Units
Min
Offset
Max
Offset
Min
Offset
Max
Offset
Min
Offset
Max
Offset
8
0
1.782
0
1.782
0
4.124
ns
64
0
2.054
0
2.054
0
4.689
ns
4–112
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–100. Arria GX IOE Programmable Delay on Row Pins (Part 2 of 2)
Fast Model
-6 Speed Grade
Paths
Affected
Available
Settings
Delay from
output register
to output pin
I/O output
register to
pad
Output enable
pin delay
txz/tzx
Parameter
Industrial
Commercial
Units
Min
Offset
Max
Offset
Min
Offset
Max
Offset
Min
Offset
Max
Offset
2
0
0.332
0
0.332
0
0.717
ns
2
0
0.32
0
0.32
0
0.693
ns
Table 4–101 describes IOE programmable delays.
Table 4–101. Arria GX IOE Programmable Delay on Column Pins
Fast Model
-6 Speed Grade
Paths
Affected
Available
Settings
Input delay
from pin to
internal cells
Pad to I/O
dataout to
core
Input delay
from pin to
input register
Parameter
Industrial
Commercial
Units
Min
Offset
Max
Offset
Min
Offset
Max
Offset
Min
Offset
Max
Offset
8
0
1.781
0
1.781
0
4.132
ns
Pad to I/O
input
register
64
0
2.053
0
2.053
0
4.697
ns
Delay from
output register
to output pin
I/O output
register to
pad
2
0
0.332
0
0.332
0
0.717
ns
Output enable
pin delay
txz/tzx
2
0
0.32
0
0.32
0
0.693
ns
Maximum Input
and Output Clock
Toggle Rate
Altera Corporation
May 2008
Maximum clock toggle rate is defined as the maximum frequency
achievable for a clock type signal at an I/O pin. The I/O pin can be a
regular I/O pin or a dedicated clock I/O pin.
The maximum clock toggle rate is different from the maximum data bit
rate. If the maximum clock toggle rate on a regular I/O pin is 300 MHz,
the maximum data bit rate for dual data rate (DDR) could be potentially
as high as 600 Mbps on the same I/O pin.
4–113
Arria GX Device Handbook, Volume 1
Maximum Input and Output Clock Toggle Rate
To calculate the output toggle rate for a non 0 pF load, use this formula:
The toggle rate for a non 0 pF load
= 1,000 / (1,000/ toggle rate at 0 pF load + derating factor × load
value in pF /1,000)
For example, the output toggle rate at 0 pF load for SSTL-18 Class II
20 mA I/O standard is 550 MHz on a -3 device clock output pin. The
derating factor is 94 ps/pF. For a 10 pF load the toggle rate is calculated
as:
1,000 / (1,000/550 + 94 × 10 /1,000) = 363 (MHz)
Table 4–102 shows the maximum input clock toggle rates for Arria GX
device column I/O pins.
Table 4–102. Arria GX Maximum Input Toggle Rate for Column I/O Pins
I/O Standards
-6 Speed Grade
Units
3.3-V LVTTL
420
MHz
3.3-V LVCMOS
420
MHz
2.5 V
420
MHz
1.8 V
420
MHz
1.5 V
420
MHz
SSTL-2 CLASS I
467
MHz
SSTL-2 CLASS II
467
MHz
SSTL-18 CLASS I
467
MHz
SSTL-18 CLASS II
467
MHz
1.8-V HSTL CLASS I
467
MHz
1.8-V HSTL CLASS II
467
MHz
1.5-V HSTL CLASS I
467
MHz
1.5-V HSTL CLASS II
467
MHz
3.3-V PCI
420
MHz
3.3-V PCI-X
420
MHz
4–114
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–103 shows the maximum input clock toggle rates for Arria GX
device row I/O pins.
Table 4–103. Arria GX Maximum Input Toggle Rate for Row I/O Pins
I/O Standards
3.3-V LVTTL
-6 Speed Grade
Units
420
MHz
3.3-V LVCMOS
420
MHz
2.5 V
420
MHz
1.8 V
420
MHz
1.5 V
420
MHz
SSTL-2 CLASS I
467
MHz
SSTL-2 CLASS II
467
MHz
SSTL-18 CLASS I
467
MHz
SSTL-18 CLASS II
467
MHz
1.8-V HSTL CLASS I
467
MHz
1.8-V HSTL CLASS II
467
MHz
1.5-V HSTL CLASS I
467
MHz
1.5-V HSTL CLASS II
467
MHz
LVDS
392
MHz
Table 4–104 shows the maximum input clock toggle rates for Arria GX
device dedicated clock pins.
Table 4–104. Arria GX Maximum Input Clock Rate for Dedicated Clock Pins
(Part 1 of 2)
I/O Standards
Altera Corporation
May 2008
-6 Speed Grade
Units
3.3-V LVTTL
373
MHz
3.3-V LVCMOS
373
MHz
2.5 V
373
MHz
1.8 V
373
MHz
1.5 V
373
MHz
SSTL-2 CLASS I
467
MHz
SSTL-2 CLASS II
467
MHz
3.3-V PCI
373
MHz
3.3-V PCI-X
373
MHz
SSTL-18 CLASS I
467
MHz
4–115
Arria GX Device Handbook, Volume 1
Maximum Input and Output Clock Toggle Rate
Table 4–104. Arria GX Maximum Input Clock Rate for Dedicated Clock Pins
(Part 2 of 2)
I/O Standards
-6 Speed Grade
Units
SSTL-18 CLASS II
467
MHz
1.8-V HSTL CLASS I
467
MHz
1.8-V HSTL CLASS II
467
MHz
1.5-V HSTL CLASS I
467
MHz
1.5-V HSTL CLASS II
467
MHz
1.2-V HSTL
233
MHz
DIFFERENTAL SSTL-2
467
MHz
DIFFERENTIAL 2.5-V
SSTL CLASS II
467
MHz
DIFFERENTIAL 1.8-V
SSTL CLASS I
467
MHz
DIFFERENTIAL 1.8-V
SSTL CLASS II
467
MHz
DIFFERENTIAL 1.8-V
HSTL CLASS I
467
MHz
DIFFERENTIAL 1.8-V
HSTL CLASS II
467
MHz
DIFFERENTIAL 1.5-V
HSTL CLASS I
467
MHz
DIFFERENTIAL 1.5-V
HSTL CLASS II
467
MHz
DIFFERENTIAL 1.2-V
HSTL
233
MHz
LVDS
598
MHz
LVDS (1)
373
MHz
Note to Table 4–104:
(1)
This set of numbers refers to the VIO dedicated input clock pins.
4–116
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–105 shows the maximum output clock toggle rates for Arria GX
device column I/O pins.
Table 4–105. Arria GX Maximum Output Toggle Rate for Column I/O Pins
(Part 1 of 2)
I/O Standards
Drive Strength -6 Speed Grade
4 mA
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
1.8 V
1.5 V
SSTL-2 CLASS I
SSTL-2 CLASS II
Altera Corporation
May 2008
196
Units
MHz
8 mA
303
MHz
12 mA
393
MHz
16 mA
486
MHz
20 mA
570
MHz
24 mA
626
MHz
4 mA
215
MHz
8 mA
411
MHz
12 mA
626
MHz
16 mA
819
MHz
20 mA
874
MHz
24 mA
934
MHz
4 mA
168
MHz
8 mA
355
MHz
12 mA
514
MHz
16 mA
766
MHz
2 mA
97
MHz
4 mA
215
MHz
6 mA
336
MHz
8 mA
486
MHz
10 mA
706
MHz
12 mA
925
MHz
2 mA
168
MHz
4 mA
303
MHz
6 mA
350
MHz
8 mA
392
MHz
8 mA
280
MHz
12 mA
327
MHz
16 mA
280
MHz
20 mA
327
MHz
24 mA
327
MHz
4–117
Arria GX Device Handbook, Volume 1
Maximum Input and Output Clock Toggle Rate
Table 4–105. Arria GX Maximum Output Toggle Rate for Column I/O Pins
(Part 2 of 2)
I/O Standards
SSTL-18 CLASS I
SSTL-18 CLASS II
1.8-V HSTL CLASS I
1.8-V HSTL CLASS II
Drive Strength -6 Speed Grade
Units
4 mA
140
MHz
6 mA
186
MHz
8 mA
280
MHz
10 mA
373
MHz
12 mA
373
MHz
8 mA
140
MHz
16 mA
327
MHz
18 mA
373
MHz
20 mA
420
MHz
4 mA
280
MHz
6 mA
420
MHz
8 mA
561
MHz
10 mA
561
MHz
12 mA
607
MHz
16 mA
420
MHz
18 mA
467
MHz
20 mA
514
MHz
4 mA
280
MHz
6 mA
420
MHz
8 mA
561
MHz
10 mA
607
MHz
12 mA
654
MHz
16 mA
514
MHz
18 mA
561
MHz
20 mA
561
MHz
3.3-V PCI
mA
626
MHz
3.3-V PCI-X
mA
626
MHz
1.5-V HSTL CLASS I
1.5-V HSTL CLASS II
4–118
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–106 shows the maximum output clock toggle rates for Arria GX
device row I/O pins.
Table 4–106. Arria GX Maximum Output Toggle Rate for Row I/O Pins
I/O Standards
Drive Strength -6 Speed Grade
4 mA
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
1.8 V
1.5 V
SSTL-2 CLASS I
SSTL-2 CLASS II
SSTL-18 CLASS I
1.8-V HSTL CLASS I
1.5-V HSTL CLASS I
LVDS
Altera Corporation
May 2008
Units
196
MHz
8 mA
303
MHz
12 mA
393
MHz
4 mA
215
MHz
8 mA
411
MHz
4 mA
168
MHz
8 mA
355
MHz
12 mA
514
MHz
2 mA
97
MHz
4 mA
215
MHz
6 mA
336
MHz
8 mA
486
MHz
2 mA
168
MHz
4 mA
303
MHz
8 mA
280
MHz
12 mA
327
MHz
16 mA
280
MHz
4 mA
140
MHz
6 mA
186
MHz
8 mA
280
MHz
10 mA
373
MHz
4 mA
280
MHz
6 mA
420
MHz
8 mA
561
MHz
10 mA
561
MHz
12 mA
607
MHz
4 mA
280
MHz
6 mA
420
MHz
8 mA
561
MHz
mA
598
MHz
4–119
Arria GX Device Handbook, Volume 1
Maximum Input and Output Clock Toggle Rate
Table 4–107 describes maximum output clock rate for dedicated clock
pins.
Table 4–107. Arria GX Maximum Output Clock Rate for Dedicated Clock Pins
(Part 1 of 4)
I/O Standards
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
1.8 V
1.5 V
SSTL-2 CLASS I
4–120
Arria GX Device Handbook, Volume 1
Drive Strength
-6 Speed
Grade
Units
4 mA
196
MHz
8 mA
303
MHz
12 mA
393
MHz
16 mA
486
MHz
20 mA
570
MHz
24 mA
626
MHz
4 mA
215
MHz
8 mA
411
MHz
12 mA
626
MHz
16 mA
819
MHz
20 mA
874
MHz
24 mA
934
MHz
4 mA
168
MHz
8 mA
355
MHz
12 mA
514
MHz
16 mA
766
MHz
2 mA
97
MHz
4 mA
215
MHz
6 mA
336
MHz
8 mA
486
MHz
10 mA
706
MHz
12 mA
925
MHz
2 mA
168
MHz
4 mA
303
MHz
6 mA
350
MHz
8 mA
392
MHz
8 mA
280
MHz
12 mA
327
MHz
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–107. Arria GX Maximum Output Clock Rate for Dedicated Clock Pins
(Part 2 of 4)
I/O Standards
SSTL-2 CLASS II
SSTL-18 CLASS I
SSTL-18 CLASS II
1.8-V HSTL CLASS I
1.8-V HSTL CLASS II
1.5-V HSTL CLASS I
1.5-V HSTL CLASS II
DIFFERENTIAL SSTL-2
Altera Corporation
May 2008
Drive Strength
-6 Speed
Grade
Units
16 mA
280
MHz
20 mA
327
MHz
24 mA
327
MHz
4 mA
140
MHz
6 mA
186
MHz
8 mA
280
MHz
10 mA
373
MHz
12 mA
373
MHz
8 mA
140
MHz
16 mA
327
MHz
18 mA
373
MHz
20 mA
420
MHz
4 mA
280
MHz
6 mA
420
MHz
8 mA
561
MHz
10 mA
561
MHz
12 mA
607
MHz
16 mA
420
MHz
18 mA
467
MHz
20 mA
514
MHz
4 mA
280
MHz
6 mA
420
MHz
8 mA
561
MHz
10mA
607
MHz
12 mA
654
MHz
16 mA
514
MHz
18 mA
561
MHz
20 mA
561
MHz
24 mA
278
MHz
8 mA
280
MHz
12 mA
327
MHz
4–121
Arria GX Device Handbook, Volume 1
Maximum Input and Output Clock Toggle Rate
Table 4–107. Arria GX Maximum Output Clock Rate for Dedicated Clock Pins
(Part 3 of 4)
I/O Standards
DIFFERENTIAL 2.5-V
SSTL CLASS II
DIFFERENTIAL 1.8-V
SSTL CLASS I
DIFFERENTIAL 1.8-V
SSTL CLASS II
DIFFERENTIAL 1.8-V
HSTL CLASS I
DIFFERENTIAL 1.8-V
HSTL CLASS II
DIFFERENTIAL 1.5-V
HSTL CLASS I
DIFFERENTIAL 1.5-V
HSTL CLASS II
3.3-V PCI
Drive Strength
-6 Speed
Grade
Units
16 mA
280
MHz
20 mA
327
MHz
24 mA
327
MHz
4 mA
140
MHz
6 mA
186
MHz
8 mA
280
MHz
10 mA
373
MHz
12 mA
373
MHz
8 mA
140
MHz
16 mA
327
MHz
18 mA
373
MHz
20 mA
420
MHz
4 mA
280
MHz
6 mA
420
MHz
8 mA
561
MHz
10 mA
561
MHz
12 mA
607
MHz
16 mA
420
MHz
18 mA
467
MHz
20 mA
514
MHz
4 mA
280
MHz
6 mA
420
MHz
8 mA
561
MHz
10 mA
607
MHz
12 mA
654
MHz
16 mA
514
MHz
18 mA
561
MHz
20 mA
561
MHz
24 mA
278
MHz
-
626
MHz
3.3-V PCI-X
-
626
MHz
LVDS
-
280
MHz
HYPERTRANSPORT
-
116
MHz
4–122
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–107. Arria GX Maximum Output Clock Rate for Dedicated Clock Pins
(Part 4 of 4)
I/O Standards
LVPECL
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
1.8 V
Altera Corporation
May 2008
Drive Strength
-6 Speed
Grade
Units
-
280
MHz
SERIES_25_OHMS
327
MHz
SERIES_50_OHMS
327
MHz
SERIES_25_OHMS
280
MHz
SERIES_50_OHMS
280
MHz
SERIES_25_OHMS
280
MHz
SERIES_50_OHMS
280
MHz
SERIES_25_OHMS
420
MHz
SERIES_50_OHMS
420
MHz
1.5 V
SERIES_50_OHMS
373
MHz
SSTL-2 CLASS I
SERIES_50_OHMS
467
MHz
SSTL-2 CLASS II
SERIES_25_OHMS
467
MHz
SSTL-18 CLASS I
SERIES_50_OHMS
327
MHz
SSTL-18 CLASS II
SERIES_25_OHMS
420
MHz
1.8-V HSTL CLASS I
SERIES_50_OHMS
561
MHz
1.8-V HSTL CLASS II
SERIES_25_OHMS
420
MHz
1.5-V HSTL CLASS I
SERIES_50_OHMS
467
MHz
1.2-V HSTL
SERIES_50_OHMS
233
MHz
DIFFERENTIAL SSTL-2
SERIES_50_OHMS
467
MHz
DIFFERENTIAL 2.5-V
SSTL CLASS II
SERIES_25_OHMS
467
MHz
DIFFERENTIAL 1.8-V
SSTL CLASS I
SERIES_50_OHMS
327
MHz
DIFFERENTIAL 1.8-V
SSTL CLASS II
SERIES_25_OHMS
420
MHz
DIFFERENTIAL 1.8-V
HSTL CLASS I
SERIES_50_OHMS
561
MHz
DIFFERENTIAL 1.8-V
HSTL CLASS II
SERIES_25_OHMS
420
MHz
DIFFERENTIAL 1.5-V
HSTL CLASS I
SERIES_50_OHMS
467
MHz
DIFFERENTIAL 1.2-V
HSTL
SERIES_50_OHMS
233
MHz
4–123
Arria GX Device Handbook, Volume 1
Duty Cycle Distortion
Duty Cycle
Distortion
Duty cycle distortion (DCD) describes how much the falling edge of a
clock is off from its ideal position. The ideal position is when both the
clock high time (CLKH) and the clock low time (CLKL) equal half of the
clock period (T), as shown in Figure 4–10. DCD is the deviation of the
non-ideal falling edge from the ideal falling edge, such as D1 for the
falling edge A and D2 for the falling edge B (see Figure 4–10). The
maximum DCD for a clock is the larger value of D1 and D2.
Figure 4–10. Duty Cycle Distortion
Ideal Falling Edge
CLKH = T/2
CLKL = T/2
D1
Falling Edge A
D2
Falling Edge B
Clock Period (T)
DCD expressed in absolution derivation, for example, D1 or D2 in
Figure 4–10, is clock-period independent. DCD can also be expressed as a
percentage, and the percentage number is clock-period dependent. DCD
as a percentage is defined as:
(T/2 – D1) / T (the low percentage boundary)
(T/2 + D2) / T (the high percentage boundary)
DCD Measurement Techniques
DCD is measured at an FPGA output pin driven by registers inside the
corresponding I/O element (IOE) block. When the output is a single data
rate signal (non-DDIO), only one edge of the register input clock (positive
or negative) triggers output transitions (Figure 4–11). Therefore, any
DCD present on the input clock signal or caused by the clock input buffer
or different input I/O standard does not transfer to the output signal.
4–124
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Figure 4–11. DCD Measurement Technique for Non-DDIO (Single-Data Rate) Outputs
However, when the output is a double data rate input/output (DDIO)
signal, both edges of the input clock signal (positive and negative) trigger
output transitions (Figure 4–12). Therefore, any distortion on the input
clock and the input clock buffer affect the output DCD.
Figure 4–12. DCD Measurement Technique for DDIO (Double-Data Rate) Outputs
When an FPGA PLL generates the internal clock, the PLL output clocks
the IOE block. As the PLL only monitors the positive edge of the reference
clock input and internally re-creates the output clock signal, any DCD
present on the reference clock is filtered out. Therefore, the DCD for a
DDIO output with PLL in the clock path is better than the DCD for a
DDIO output without PLL in the clock path.
Altera Corporation
May 2008
4–125
Arria GX Device Handbook, Volume 1
Duty Cycle Distortion
Tables 4–108 through 4–113 show the maximum DCD in absolution
derivation for different I/O standards on Arria GX devices. Examples are
also provided that show how to calculate DCD as a percentage.
Table 4–108. Maximum DCD for Non-DDIO Output on Row I/O Pins
Maximum DCD (ps) for Non-DDIO Output
Row I/O Output Standard
-6 Speed Grade
Unit
275
ps
3.3-V LVCMOS
155
ps
2.5 V
135
ps
1.8 V
180
ps
1.5-V LVCMOS
195
ps
3.3-V LVTTTL
SSTL-2 Class I
145
ps
SSTL-2 Class II
125
ps
SSTL-18 Class I
85
ps
1.8-V HSTL Class I
100
ps
1.5-V HSTL Class I
115
ps
LVDS
80
ps
Here is an example for calculating the DCD as a percentage for a
non-DDIO output on a row I/O:
If the non-DDIO output I/O standard is SSTL-2 Class II, the maximum
DCD is 125 ps (see Table 4–109). If the clock frequency is 267 MHz, the
clock period T is:
T = 1/ f = 1 / 267 MHz = 3.745 ns = 3,745 ps
To calculate the DCD as a percentage:
(T/2 – DCD) / T = (3,745 ps/2 – 125 ps) / 3,745 ps = 46.66% (for low
boundary)
(T/2 + DCD) / T = (3,745 ps/2 + 125 ps) / 3,745 ps = 53.33% (for high
boundary)
Therefore, the DCD percentage for the output clock at 267 MHz is from
46.66% to 53.33%.
4–126
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–109. Maximum DCD for Non-DDIO Output on Column I/O Pins
Column I/O Output
Standard I/O Standard
Maximum DCD (ps) for Non-DDIO
Output
Unit
-6 Speed Grade
3.3-V LVTTL
220
ps
3.3-V LVCMOS
175
ps
2.5 V
155
ps
1.8 V
110
ps
1.5-V LVCMOS
215
ps
SSTL-2 Class I
135
ps
SSTL-2 Class II
130
ps
SSTL-18 Class I
115
ps
SSTL-18 Class II
100
ps
1.8-V HSTL Class I
110
ps
1.8-V HSTL Class II
110
ps
1.5-V HSTL Class I
115
ps
1.5-V HSTL Class II
80
ps
1.2-V HSTL-12
200
ps
LVPECL
80
ps
Table 4–110. Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path (Part 1 of 2)
Note (1)
Maximum DCD (ps) for
Row DDIO Output I/O
Standard
3.3-V LVTTL
Input I/O Standard (No PLL in the Clock Path)
TTL/CMOS
SSTL-2
SSTL/HSTL
LVDS
Unit
3.3/2.5V
1.8/1.5V
2.5V
1.8/1.5V
3.3V
440
495
170
160
105
ps
3.3-V LVCMOS
390
450
120
110
75
ps
2.5 V
375
430
105
95
90
ps
1.8 V
325
385
90
100
135
ps
1.5-V LVCMOS
430
490
160
155
100
ps
SSTL-2 Class I
355
410
85
75
85
ps
Altera Corporation
May 2008
4–127
Arria GX Device Handbook, Volume 1
Duty Cycle Distortion
Table 4–110. Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path (Part 2 of 2)
Note (1)
Maximum DCD (ps) for
Row DDIO Output I/O
Standard
SSTL-2 Class II
Input I/O Standard (No PLL in the Clock Path)
TTL/CMOS
SSTL-2
SSTL/HSTL
LVDS
3.3/2.5V
1.8/1.5V
2.5V
1.8/1.5V
3.3V
350
405
80
70
90
Unit
ps
SSTL-18 Class I
335
390
65
65
105
ps
1.8-V HSTL Class I
330
385
60
70
110
ps
1.5-V HSTL Class I
330
390
60
70
105
ps
LVDS
180
180
180
180
180
ps
Note to Table 4–110:
(1)
Table 4–110 assumes the input clock has zero DCD.
Table 4–111. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path
Maximum DCD (ps) for
DDIO Column Output I/O
Standard
Note (1)
Input IO Standard (No PLL in the Clock Path)
TTL/CMOS
SSTL-2
SSTL/HSTL
Unit
3.3/2.5V
1.8/1.5V
2.5V
1.8/1.5V
3.3-V LVTTL
440
495
170
160
ps
3.3-V LVCMOS
390
450
120
110
ps
2.5 V
375
430
105
95
ps
1.8 V
325
385
90
100
ps
1.5-V LVCMOS
430
490
160
155
ps
SSTL-2 Class I
355
410
85
75
ps
SSTL-2 Class II
350
405
80
70
ps
SSTL-18 Class I
335
390
65
65
ps
SSTL-18 Class II
320
375
70
80
ps
1.8-V HSTL Class I
330
385
60
70
ps
1.8-V HSTL Class II
330
385
60
70
ps
1.5-V HSTL Class I
330
390
60
70
ps
1.5-V HSTL Class II
330
360
90
100
ps
LVPECL
180
180
180
180
ps
Note to Table 4–111:
(1)
Table 4–111 assumes the input clock has zero DCD.
4–128
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–112. Maximum DCD for DDIO Output on Row I/O Pins With PLL in
the Clock Path
Maximum DCD (ps) for Row DDIO
Output I/O Standard
Arria GX Devices (PLL Output
Feeding DDIO)
Unit
-6 Speed Grade
3.3-V LVTTL
105
ps
3.3-V LVCMOS
75
ps
2.5V
90
ps
1.8V
100
ps
1.5-V LVCMOS
100
ps
SSTL-2 Class I
75
ps
SSTL-2 Class II
70
ps
SSTL-18 Class I
65
ps
1.8-V HSTL Class I
70
ps
1.5-V HSTL Class I
70
ps
LVDS
180
ps
Table 4–113. Maximum DCD for DDIO Output on Column I/O Pins With PLL
in the Clock Path (Part 1 of 2)
Maximum DCD (ps) for Column
DDIO Output I/O Standard
Arria GX Devices (PLL Output
Feeding DDIO)
Unit
-6 Speed Grade
Altera Corporation
May 2008
3.3-V LVTTL
160
ps
3.3-V LVCMOS
110
ps
2.5V
95
ps
1.8V
100
ps
1.5-V LVCMOS
155
ps
SSTL-2 Class I
75
ps
SSTL-2 Class II
70
ps
SSTL-18 Class I
65
ps
SSTL-18 Class II
80
ps
1.8-V HSTL Class I
70
ps
1.8-V HSTL Class II
70
ps
1.5-V HSTL Class I
70
ps
1.5-V HSTL Class II
100
ps
4–129
Arria GX Device Handbook, Volume 1
High-Speed I/O Specifications
Table 4–113. Maximum DCD for DDIO Output on Column I/O Pins With PLL
in the Clock Path (Part 2 of 2)
Maximum DCD (ps) for Column
DDIO Output I/O Standard
Arria GX Devices (PLL Output
Feeding DDIO)
Unit
-6 Speed Grade
High-Speed I/O
Specifications
1.2-V HSTL
155
ps
LVPECL
180
ps
Table 4–114 provides high-speed timing specifications definitions.
Table 4–114. High-Speed Timing Specifications and Definitions
High-Speed Timing Specifications
Definitions
tC
High-speed receiver/transmitter input and output clock period.
fH S C L K
High-speed receiver/transmitter input and output clock frequency.
J
Deserialization factor (width of parallel data bus).
W
PLL multiplication factor.
tR I S E
Low-to-high transmission time.
tF A L L
High-to-low transmission time.
Timing unit interval (TUI)
The timing budget allowed for skew, propagation delays, and data
sampling window. (TUI = 1/(Receiver Input Clock Frequency ×
Multiplication Factor) = tC /w).
fH S D R
Maximum/minimum LVDS data transfer rate (fH S D R = 1/TUI), non-DPA.
fH S D R D P A
Maximum/minimum LVDS data transfer rate (fH S D R D PA = 1/TUI), DPA.
Channel-to-channel skew (TCCS)
The timing difference between the fastest and slowest output edges,
including tC O variation and clock skew. The clock is included in the TCCS
measurement.
Sampling window (SW)
The period of time during which the data must be valid in order to capture
it correctly. The setup and hold times determine the ideal strobe position
within the sampling window.
Input jitter
Peak-to-peak input jitter on high-speed PLLs.
Output jitter
Peak-to-peak output jitter on high-speed PLLs.
tDUTY
Duty cycle on high-speed transmitter output clock.
tL O C K
Lock time for high-speed transmitter and receiver PLLs.
4–130
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–115 shows the high-speed I/O timing specifications.
Table 4–115. High-Speed I/O Specifications
Notes (1), (2)
-6 Speed Grade
Symbol
Conditions
Unit
Min
fH S C L K (clock frequency)
fH S C L K = f H S D R / W
fH S D R (data rate)
Typ
Max
W = 2 to 32 (LVDS, HyperTransport technology)
(3)
16
420
MHz
W = 1 (SERDES bypass, LVDS only)
16
500
MHz
W = 1 (SERDES used, LVDS only)
150
640
MHz
J = 4 to 10 (LVDS, HyperTransport technology)
150
840
Mbps
J = 2 (LVDS, HyperTransport technology)
(4)
700
Mbps
J = 1 (LVDS only)
(4)
500
Mbps
fH S D R D PA (DPA data rate) J = 4 to 10 (LVDS, HyperTransport technology)
150
840
Mbps
TCCS
All differential I/O standards
-
200
ps
SW
All differential I/O standards
440
Output jitter
-
ps
190
ps
Output tR I S E
All differential I/O standards
290
ps
Output tFA L L
All differential I/O standards
290
ps
55
%
6,400
UI
tDUTY
45
DPA run length
DPA jitter tolerance
Data channel peak-to-peak jitter
Standard
SPI-4
DPA lock time
Parallel Rapid I/O
Miscellaneous
0.44
Training
Pattern
Transition
Density
0000000000
1111111111
10%
256
00001111
25%
256
10010000
50%
256
10101010
100%
256
01010101
50
UI
Number of
repetitions
256
Notes to Table 4–115:
(1)
(2)
(3)
(4)
When J = 4 to 10, the SERDES block is used.
When J = 1 or 2, the SERDES block is bypassed.
The input clock frequency and the W factor must satisfy the following fast PLL VCO specification: 150 ≤input clock
frequency × W ≤1,040.
The minimum specification is dependent on the clock source (fast PLL, enhanced PLL, clock pin, and so on) and
the clock routing resource (global, regional, or local) utilized. The I/O differential buffer and input register do not
have a minimum toggle rate.
Altera Corporation
May 2008
4–131
Arria GX Device Handbook, Volume 1
PLL Timing Specifications
PLL Timing
Specifications
Tables 4–116 and 4–117 describe the Arria GX PLL specifications when
operating in both the commercial junction temperature range (0 to 85 C)
and the industrial junction temperature range (–40 to 100 C), except for
the clock switchover and phase-shift stepping features. These two
features are only supported from the 0 to 100 C junction temperature
range.
Table 4–116. Enhanced PLL Specifications (Part 1 of 2)
Name
Description
Min
Typ
Max
Unit
fIN
Input clock frequency
2
500
MHz
fINPFD
Input frequency to the PFD
2
420
MHz
fINDUTY
Input clock duty cycle
40
60
%
fENDUTY
External feedback input clock duty cycle
40
60
%
tINJITTER
Input or external feedback clock input jitter
tolerance in terms of period jitter.
Bandwidth ≤0.85 MHz
0.5
ns (peakto-peak)
Input or external feedback clock input jitter
tolerance in terms of period jitter.
Bandwidth > 0.85 MHz
1.0
ns (peakto-peak)
tOUTJITTER
Dedicated clock output period jitter
(3)
ps or mUI
(p-p)
tFCOMP
External feedback compensation time
10
ns
fOUT
Output frequency for internal global or
regional clock
550
MHz
fSCANCLK
Scanclk frequency
100
MHz
tCONFIGEPLL
Time required to reconfigure scan chains
for EPLLs
1.5 (2)
174/fSCANCLK
fOUT_EXT
PLL external clock output frequency
1.5 (2)
fOUTDUTY
Duty cycle for external clock output
45
tLOCK
Time required for the PLL to lock from the
time it is enabled or the end of device
configuration
tDLOCK
Time required for the PLL to lock
dynamically after automatic clock
switchover between two identical clock
frequencies
fSWITCHOVER
Frequency range where the clock
switchover performs properly
1.5
fCLBW
PLL closed-loop bandwidth
0.13
fVCO
PLL VCO operating range
fSS
Spread-spectrum modulation frequency
4–132
Arria GX Device Handbook, Volume 1
ns
(1)
MHz
50
55
%
0.03
1
ms
1
ms
1
500
MHz
1.2
16.9
MHz
300
840
MHz
100
500
kHz
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–116. Enhanced PLL Specifications (Part 2 of 2)
Name
Description
Min
Typ
Max
Unit
0.4
0.5
0.6
%
±30
ps
% spread
Percent down spread for a given clock
frequency
tP L L _ P S E R R
Accuracy of PLL phase shift
tARESET
Minimum pulse width on areset signal.
10
ns
tARESET_RECONFIG
Minimum pulse width on the areset
signal when using PLL reconfiguration.
Reset the PLL after scandone goes high.
500
ns
tRECONFIGWAIT
The time required for the wait after the
reconfiguration is done and the areset is
applied.
2
us
Notes to Table 4–116:
(1)
(2)
(3)
This is limited by the I/O fMAX.
If the counter cascading feature of the PLL is utilized, there is no minimum output clock frequency.
250 ps for ≥ 100 MHz outclk. 25 mUI for <100 MHz outclk.
Table 4–117. Fast PLL Specifications (Part 1 of 2)
Name
Description
Min
Typ
Max
Unit
fIN
Input clock frequency
16.08
640
MHz
fINPFD
Input frequency to the PFD
16.08
500
MHz
fINDUTY
Input clock duty cycle
tINJITTER
Input clock jitter tolerance in terms of period
jitter. Bandwidth ≤2 MHz
0.5
ns (p-p)
Input clock jitter tolerance in terms of period
jitter. Bandwidth > 0.2 MHz
1.0
ns (p-p)
fVCO
Upper VCO frequency range
Lower VCO frequency range
fOUT
PLL output frequency to GCLK or RCLK
PLL output frequency to LVDS or DPA clock
fOUT_EXT
PLL clock output frequency to regular I/O
tCONFIGPLL
Time required to reconfigure scan chains for
fast PLLs
fCLBW
PLL closed-loop bandwidth
tLOCK
Time required for the PLL to lock from the
time it is enabled or the end of the device
configuration
tPLL_PSERR
Accuracy of PLL phase shift
Altera Corporation
May 2008
40
60
%
300
840
MHz
150
420
MHz
4.6875
550
MHz
150
840
MHz
4.6875
(1)
MHz
75/fSCANCLK
1.16
ns
5
28
MHz
0.03
1
ms
±30
ps
4–133
Arria GX Device Handbook, Volume 1
External Memory Interface Specifications
Table 4–117. Fast PLL Specifications (Part 2 of 2)
Name
Description
Min
Typ
Max
Unit
tARESET
Minimum pulse width on areset signal.
10
ns
tARESET_RECONFIG
Minimum pulse width on the areset signal
when using PLL reconfiguration. Reset the
PLL after scandone goes high.
500
ns
Note to Table 4–117:
(1)
This is limited by the I/O fMAX.
External
Memory
Interface
Specifications
Tables 4–118 through 4–122 contain Arria GX device specifications for the
dedicated circuitry used for interfacing with external memory devices.
Table 4–118. DLL Frequency Range Specifications
Frequency Mode
Frequency Range (MHz)
0
100 to 175
1
150 to 230
2
200 to 310
Table 4–119. DQS Jitter Specifications for DLL-Delayed Clock (tDQS_JITTER) ,
Note (1)
Number of DQS Delay Buffer Stages
(2)
Commercial (ps)
Industrial (ps)
1
80
110
2
110
130
3
130
180
4
160
210
Notes to Table 4–119:
(1)
(2)
Peak-to-peak period jitter on the phase-shifted DQS clock. For example, jitter on
two delay stages under commercial conditions is 200 ps peak-to-peak or 100 ps.
Delay stages used for requested DQS phase shift are reported in a project’s
Compilation Report in the Quartus II software.
4–134
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–120. DQS Phase-Shift Error Specifications for DLL-Delayed Clock
(tDQS_PSERR)
Number of DQS Delay Buffer Stages
–6 Speed Grade (ps)
1
35
2
70
3
105
4
140
Table 4–121. DQS Bus Clock Skew Adder Specifications
(tDQS_CLOCK_SKEW_ADDER)
Mode
DQS Clock Skew Adder (ps)
4 DQ per DQS
40
9 DQ per DQS
70
18 DQ per DQS
75
36 DQ per DQS
95
Table 4–122. DQS Phase Offset Delay Per Stage (ps)
Positive Offset
Notes (1), (2), (3)
Negative Offset
Speed Grade
-6
Min
Max
Min
Max
10
16
8
12
Notes to Table 4–122:
(1)
(2)
(3)
Altera Corporation
May 2008
The delay settings are linear.
The valid settings for phase offset are -32 to +31.
The typical value equals the average of the minimum and maximum values.
4–135
Arria GX Device Handbook, Volume 1
JTAG Timing Specifications
JTAG Timing
Specifications
Figure 4–13 shows the timing requirements for the JTAG signals
Figure 4–13. Arria GX JTAG Waveforms.
TMS
TDI
t JCP
t JCH
t JCL
t JPSU
t JPH
TCK
tJPZX
t JPXZ
t JPCO
TDO
tJSSU
Signal
to be
Captured
Signal
to be
Driven
tJSZX
4–136
Arria GX Device Handbook, Volume 1
tJSH
tJSCO
tJSXZ
Altera Corporation
May 2008
DC and Switching Characteristics
Table 4–123 shows the JTAG timing parameters and values for Arria GX
devices.
Table 4–123. Arria GX JTAG Timing Parameters and Values
Symbol
Referenced
Documents
Min Max Unit
TCK clock period
30
ns
tJCH
TCK clock high time
12
ns
tJCL
TCK clock low time
12
ns
tJPSU
JTAG port setup time
4
ns
tJPH
JTAG port hold time
5
ns
tJPCO
JTAG port clock to output
tJPZX
JTAG port high impedance to valid output
9
ns
tJPXZ
JTAG port valid output to high impedance
9
ns
tJSSU
Capture register setup time
4
tJSH
Capture register hold time
5
tJSCO
Update register clock to output
12
ns
tJSZX
Update register high impedance to valid output
12
ns
tJSXZ
Update register valid output to high impedance
12
ns
9
ns
ns
ns
This chapter references the following documents:
■
■
■
■
Altera Corporation
May 2008
Parameter
tJCP
Arria GX Architecture chapter in volume 1 of the Arria GX Device
Handbook
Arria GX Device Family Data Sheet in volume 1 of the Arria GX Device
Handbook
PowerPlay Early Power Estimator and PowerPlay Power Analyzer
PowerPlay Power Analysis chapter in volume 3 of the Quartus II
Handbook
4–137
Arria GX Device Handbook, Volume 1
Document Revision History
Document
Revision History
Table 4–124 shows the revision history for this chapter.
Table 4–124. Document Revision History
Date and
Document
Version
May 2008
v1.3
August 2007
v1.2
Changes Made
Summary of Changes
Updated:
Table 4–5
● Table 4–7
● Table 4–8
● Table 4–9
● Table 4–10
● Table 4–11
● Table 4–12
● Table 4–13
● Table 4–14
● Table 4–15
● Table 4–16
● Table 4–17
● Table 4–43
● Table 4–116
● Table 4–117
—
Updated:
● Figure 4–4
—
Minor text edits.
—
Removed “Preliminary” from each page.
—
Removed “Preliminary” note from Tables 4–44,
4–45, and 4–47.
—
●
Added “Referenced Documents” section.
—
June 2007
v1.1
Updated Table 4–99.
—
Added GIGE information.
—
May 2007
v1.0
Initial release.
—
4–138
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
5. Reference and Ordering
Information
AGX51005-1.1
Software
ArriaTM GX devices are supported by the Altera® Quartus® II design
software, which provides a comprehensive environment for
system-on-a-programmable-chip (SOPC) design. The Quartus II software
includes HDL and schematic design entry, compilation and logic
synthesis, full simulation and advanced timing analysis, SignalTap® II
logic analyzer, and device configuration.
f
Refer to the Quartus II Development Software Handbook for more
information on the Quartus II software features.
The Quartus II software supports the Windows XP/2000/NT,
Sun Solaris 8/9, Linux Red Hat v7.3, Linux Red Hat Enterprise 3, and
HP-UX operating systems. It also supports seamless integration with
industry-leading EDA tools through the NativeLink interface.
Device Pin-Outs
f
Altera Corporation
August 2007
Arria GX device pin-outs are available on the Altera web site at
www.altera.com.
5–1
Reference and Ordering Information
Ordering
Information
f
Figure 5–1 describes the ordering codes for Arria GX devices.
For more information on a specific package, refer to the Package
Information for Arria GX Devices chapter in volume 2 of the Arria GX
Device Handbook.
Figure 5–1. Arria GX Device Packaging Ordering Information
EP1AGX
20
C
F
484
C
6
N
Family Signature
Optional Suffix
EP1AGX : Arria GX
Indicates specific device options or
shipment method.
N:
Lead-free devices
Device Type
20
35
50
60
90
Speed Grade
6
Operating Temperature
Number of
Transceiver
Channels
C: Commercial temperature (TJ = 0˚ C to 85˚ C)
I: Industrial temperature (TJ = -40˚ C to 100˚ C)
Pin Count
C: 4
D: 8
E: 12
Package Type
484
780
1152
F: FineLine BGA (FBGA)
Referenced
Documents
This chapter references the following documents:
■
■
Package Information for Arria GX Devices chapter in volume 2 of the
Arria GX Device Handbook
Quartus II Development Software Handbook
5–2
Arria GX Device Handbook, Volume 1
Altera Corporation
August 2007
Document Revision History
Document
Revision History
Table 5–1 shows the revision history for this chapter.
Table 5–1. Document Revision History
Date and
Document
Version
Changes Made
Summary of Changes
August 2007, v1.1 Added the “Referenced Documents”
section.
—
May 2007, v1.0
—
Altera Corporation
August 2007
Initial Release.
5–3
Arria GX Device Handbook, Volume 1
Reference and Ordering Information
5–4
Arria GX Device Handbook, Volume 1
Altera Corporation
August 2007