AD ADUM5401 Quad-channel, 2.5 kv isolators with integrated dc-to-dc converter Datasheet

FUNCTIONAL BLOCK DIAGRAMS
isoPower integrated, isolated dc-to-dc converter
Regulated 3.3 V or 5.0 V output
Up to 500 mW output power
Quad dc-to-25 Mbps (NRZ) signal isolation channels
16-lead SOIC package with 7.6 mm creepage
High temperature operation: 105°C maximum
High common-mode transient immunity: >25 kV/μs
Safety and regulatory approvals
UL recognition
2500 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A)
VDE certificate of conformity (pending)
IEC 60747-5-2 (VDE 0884, Part 2)
VIORM = 560 V peak
VDD1 1
VIA/VOA 3
VIB/VOB 4
VIC/VOC 5
RECT
REG
16 VISO
15 GNDISO
14 VOA/VIA
4 CHANNEL iCOUPLER CORE
13 VOB/VIB
ADuM5401/ADuM5402/
ADuM5403/ADuM5404
12 VOC/VIC
VOD 6
11 VID
RCOUT 7
10 VSEL
GND1 8
9
GNDISO
Figure 1.
VIB
VIC
RS-232/RS-422/RS-485 transceivers
Industrial field bus isolation
Power supply startup bias and gate drives
Isolated sensor interfaces
Industrial PLCs
VOD
3
ADuM5401
14
4
13
5
12
6
11
VOA
VOB
VOC
VID
06577-100
VIA
APPLICATIONS
Figure 2. ADuM5401
VIB
VOC
VOD
1
The ADuM5401/ADuM5402/ADuM5403/ADuM5404 are
quad-channel digital isolators with isoPower®, an integrated,
isolated dc-to-dc converter. Based on the Analog Devices, Inc.,
iCoupler® technology, the dc-to-dc converter provides up to
500 mW of regulated, isolated power at either 5.0 V or 3.3 V from
a 5.0 V input supply, or at 3.3 V from a 3.3 V supply at the power
levels shown in Table 1. These devices eliminate the need for a
separate, isolated dc-to-dc converter in low power, isolated designs.
The iCoupler chip scale transformer technology is used to isolate
the logic signals and for the power and feedback paths in the dc-todc converter. The result is a small form factor, total isolation solution.
ADuM5402
14
4
13
5
12
6
11
VOA
VOB
VIC
VID
Figure 3. ADuM5402
VOB
VOC
VOD
3
ADuM5403
14
4
13
5
12
6
11
VOA
VIB
VIC
VID
06577-102
VIA
Figure 4. ADuM5403
VOA
VOB
VOC
The ADuM5401/ADuM5402/ADuM5403/ADuM5404 isolators
provide four independent isolation channels in a variety of
channel configurations and data rates (see the Ordering Guide
for more information).
isoPower uses high frequency switching elements to transfer
power through its transformer. Special care must be taken
during printed circuit board (PCB) layout to meet emissions
standards. See the AN-0971 Application Note for board layout
recommendations.
3
06577-101
VIA
GENERAL DESCRIPTION
1
OSC
GND1 2
06577-001
FEATURES
3
ADuM5404
14
4
13
5
12
6
11
VOD
VIA
VIB
VIC
VID
06577-103
Data Sheet
Quad-Channel, 2.5 kV Isolators with
Integrated DC-to-DC Converter
ADuM5401/ADuM5402/ADuM5403/ADuM5404
Figure 5. ADuM5404
Table 1. Power Levels
Input Voltage (V)
5.0
5.0
3.3
Output Voltage (V)
5.0
3.3
3.3
Output Power (mW)
500
330
200
Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2008–2011 Analog Devices, Inc. All rights reserved.
ADuM5401/ADuM5402/ADuM5403/ADuM5404
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution................................................................................ 11
Applications....................................................................................... 1
Pin Configurations and Function Descriptions ......................... 12
General Description ......................................................................... 1
Truth Table .................................................................................. 15
Functional Block Diagrams............................................................. 1
Typical Performance Characteristics ........................................... 16
Revision History ............................................................................... 2
Terminology .................................................................................... 19
Specifications..................................................................................... 3
Applications Information .............................................................. 20
Electrical Characteristics—5 V Primary Input Supply/5 V
Secondary Isolated Supply .......................................................... 3
PCB Layout ................................................................................. 20
Electrical Characteristics—3.3 V Primary Input Supply/3.3 V
Secondary Isolated Supply .......................................................... 5
Propagation Delay-Related Parameters................................... 21
Electrical Characteristics—5 V Primary Input Supply/3.3 V
Secondary Isolated Supply .......................................................... 7
EMI Considerations................................................................... 21
Thermal Analysis ....................................................................... 20
Start-Up Behavior....................................................................... 21
Package Characteristics ............................................................... 9
DC Correctness and Magnetic Field Immunity........................... 21
Regulatory Information............................................................... 9
Power Consumption .................................................................. 22
Insulation and Safety-Related Specifications............................ 9
Power Considerations................................................................ 23
IEC 60747-5-2 (VDE 0884, Part 2):2003-01 Insulation
Characteristics ............................................................................ 10
Increasing Available Power ....................................................... 23
Recommended Operating Conditions .................................... 10
Outline Dimensions ....................................................................... 25
Absolute Maximum Ratings.......................................................... 11
Ordering Guide .......................................................................... 25
Insulation Lifetime ..................................................................... 24
REVISION HISTORY
9/11—Rev. A to Rev. B
Changes to Product Title, Features Section, and General
Description Section .......................................................................... 1
Added Table 1; Renumbered Sequentially .................................... 1
Changes to Specifications Section.................................................. 3
Changes to Table 19 and Table 20 ................................................ 11
Changes to Table 21........................................................................ 12
Changes to Table 22........................................................................ 13
Changes to Table 23........................................................................ 14
Changes to Table 24 and Table 25 ................................................ 15
Changes to Figure 11 to Figure 13................................................ 16
Changes to Figure 11, Figure 12 Caption, Figure 14 Caption,
and Figure 16 Caption.................................................................... 16
Added Figure 19 and Figure 20; Renumbered Sequentially ..... 17
Changes to Figure 21 and Figure 22............................................. 17
Changes to Terminology Section.................................................. 19
Changes to Applications Information Section............................ 20
Deleted Increasing Available Power, Figure 15, and Figure 16;
Renumbered Sequentially.............................................................. 20
Changes to PCB Layout Section ................................................... 20
Added Start-Up Behavior Section ................................................ 21
Moved and Changes to EMI Considerations Section................ 21
Changes to DC Correctness and Magnetic Field Immunity
Section.............................................................................................. 21
Changes to Power Consumption Section and Figure 29........... 22
Changes to Power Considerations................................................ 23
Added Increasing Available Power Section and Table 26 ......... 23
Added Table 27 ............................................................................... 24
Changes to Insulation Lifetime Section ...................................... 24
11/08—Rev. 0 to Rev. A
Changes to Figure 1 and General Description Section ................1
Changes to Table 1.............................................................................3
Changes to Table 2.............................................................................5
Changes to Table 4.............................................................................7
Changes to Table 6 and Table 7 .......................................................8
Changes to Table 8 and Table 9 .......................................................9
Changes to Figure 7 and Table 10................................................. 10
Changes to Figure 8 and Table 11................................................. 11
Changes to Figure 9 and Table 12................................................. 12
Changes to Figure 10 and Table 13 .............................................. 13
Moved Truth Table Section ........................................................... 13
Changes to Applications Information Section and PCB Layout
Section.............................................................................................. 17
Changes to DC Correctness and Magnetic Field Immunity
Section.............................................................................................. 18
Changes to Power Considerations Section ................................. 20
Added Increasing Available Power Section, Table 15, and
Table 16 ............................................................................................ 20
5/08—Revision 0: Initial Version
Rev. B | Page 2 of 28
Data Sheet
ADuM5401/ADuM5402/ADuM5403/ADuM5404
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY
Typical specifications are at TA = 25°C, VDD1 = VSEL = VISO = 5 V. Minimum/maximum specifications apply over the entire recommended
operation range which is 4.5 V ≤ VDD1, VSEL, VISO ≤ 5.5 V; and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching specifications are
tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 2. DC-to-DC Converter Static Specifications
Parameter
DC-TO-DC CONVERTER SUPPLY
Setpoint
Line Regulation
Load Regulation
Output Ripple
Output Noise
Switching Frequency
PWM Frequency
Output Supply Current
Efficiency at IISO (MAX)
IDD1, No VISO Load
IDD1, Full VISO Load
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
VISO
VISO (LINE)
VISO (LOAD)
VISO (RIP)
VISO (NOISE)
fOSC
fPWM
IISO (MAX)
4.7
5.0
1
1
75
200
180
625
5.4
V
mV/V
%
mV p-p
mV p-p
MHz
kHz
mA
%
mA
mA
IISO = 0 mA
IISO = 50 mA, VDD1 = 4.5 V to 5.5 V
IISO = 10 mA to 90 mA
20 MHz bandwidth, CBO = 0.1 μF||10 μF, IISO = 90 mA
CBO = 0.1 μF||10 μF, IISO = 90 mA
5
100
34
19
290
IDD1 (Q)
IDD1 (MAX)
30
VISO > 4.5 V
IISO = 100 mA
Table 3. DC-to-DC Converter Dynamic Specifications
Parameter
SUPPLY CURRENT
Input
ADuM5401
ADuM5402
ADuM5403
ADuM5404
Available to Load
ADuM5401
ADuM5402
ADuM5403
ADuM5404
Symbol
1 Mbps—A Grade, C Grade
Min
Typ
Max
25 Mbps—C Grade
Min
Typ
Max
Unit
Test Conditions/Comments
No VISO load
No VISO load
No VISO load
No VISO load
IDD1
19
19
19
19
68
71
75
78
mA
mA
mA
mA
100
100
100
100
87
85
83
81
mA
mA
mA
mA
IISO (LOAD)
Table 4. Switching Specifications
Parameter
SWITCHING SPECIFICATIONS
Data Rate
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Pulse Width
Propagation Delay Skew
Channel Matching
Codirectional 1
Opposing Directional 2
Symbol
Min
tPHL, tPLH
PWD
A Grade
Typ
Max
55
Min
1
100
40
C Grade
Typ
Max
tPSKCD
tPSKOD
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
50
15
50
50
6
15
ns
ns
5
PW
tPSK
Test Conditions/Comments
Mbps
ns
ns
ps/°C
ns
ns
45
25
60
6
Unit
1000
40
1
Within PWD limit
Between any two units
Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the
isolation barrier.
2
Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the
isolation barrier.
7
Rev. B | Page 3 of 28
ADuM5401/ADuM5402/ADuM5403/ADuM5404
Data Sheet
Table 5. Input and Output Characteristics
Parameter
DC SPECIFICATIONS
Logic High Input Threshold
Logic Low Input Threshold
Symbol
Min
VIH
VIL
0.7 × VISO or 0.7 × VDD1
Logic High Output Voltages
VOH
VDD1 − 0.3 or VISO − 0.3
VDD1 − 0.5 or VISO − 0.5
Logic Low Output Voltages
VOL
Undervoltage Lockout
Positive Going Threshold
Negative Going Threshold
Hysteresis
Input Currents per Channel
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient
Immunity 1
Refresh Rate
1
Typ
Max
0.3 × VISO or 0.3 ×
VDD1
5.0
4.8
0.0
0.2
Unit
V
V
0.1
0.4
V
V
V
V
+20
V
V
V
μA
UVLO
VUV+
VUV−
VUVH
II
−20
2.7
2.4
0.3
+0.01
tR/tF
|CM|
25
2.5
35
ns
kV/μs
1.0
Mbps
fr
Test Conditions/Comments
IOx = −20 μA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 μA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
VDD1, VDDL, VISO supplies
0 V ≤ VIx ≤ VDDx
10% to 90%
VIx= VDD1 or VISO, VCM = 1000 V,
transient magnitude = 800 V
|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.7 × VDD1 or 0.7 × VISO for a high output or VO < 0.3 × VDD1 or 0.3 × VISO for a
low output. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
Rev. B | Page 4 of 28
Data Sheet
ADuM5401/ADuM5402/ADuM5403/ADuM5404
ELECTRICAL CHARACTERISTICS—3.3 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY
Typical specifications are at TA = 25°C, VDD1 = VISO = 3.3 V, VSEL = GNDISO. Minimum/maximum specifications apply over the entire
recommended operation range which is 3.0 V ≤ VDD1, VSEL, VISO ≤ 3.6 V; and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching
specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 6. DC-to-DC Converter Static Specifications
Parameter
DC-TO-DC CONVERTER SUPPLY
Setpoint
Line Regulation
Load Regulation
Output Ripple
Output Noise
Switching Frequency
PWM Frequency
Output Supply Current
Efficiency at IISO (MAX)
IDD1, No VISO Load
IDD1, Full VISO Load
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
VISO
VISO (LINE)
VISO (LOAD)
VISO (RIP)
VISO (NOISE)
fOSC
fPWM
IISO (MAX)
3.0
3.3
1
1
50
130
180
625
3.6
V
mV/V
%
mV p-p
mV p-p
MHz
kHz
mA
%
mA
mA
IISO = 0 mA
IISO = 30 mA, VDD1 = 3.0 V to 3.6 V
IISO = 6 mA to 54 mA
20 MHz bandwidth, CBO = 0.1 μF||10 μF, IISO = 54 mA
CBO = 0.1 μF||10 μF, IISO = 54 mA
5
60
33
14
175
IDD1 (Q)
IDD1 (MAX)
20
VISO > 3 V
IISO = 60 mA
Table 7. DC-to-DC Converter Dynamic Specifications
Parameter
SUPPLY CURRENT
Input
ADuM5401
ADuM5402
ADuM5403
ADuM5404
Available to Load
ADuM5401
ADuM5402
ADuM5403
ADuM5404
Symbol
Min
1 Mbps—A or C Grade
Typ
Max
25 Mbps—C Grade
Min Typ Max
Unit
Test
Conditions/Comments
No VISO load
No VISO load
No VISO load
No VISO load
IDD1
14
14
14
14
44
46
47
51
mA
mA
mA
mA
60
60
60
60
52
51
49
48
mA
mA
mA
mA
IISO (LOAD)
Table 8. Switching Specifications
Parameter
SWITCHING SPECIFICATIONS
Data Rate
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Pulse Width
Propagation Delay Skew
Channel Matching
Codirectional 1
Opposing Directional 2
Symbol
Min
tPHL, tPLH
PWD
A Grade
Typ
Max
60
Min
1
100
40
C Grade
Typ
Max
tPSKCD
tPSKOD
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
50
45
50
50
6
15
ns
ns
5
PW
tPSK
Test Conditions/Comments
Mbps
ns
ns
ps/°C
ns
ns
45
25
60
6
Unit
1000
40
1
Within PWD limit
Between any two units
Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the
isolation barrier.
2
Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the
isolation barrier.
7
Rev. B | Page 5 of 28
ADuM5401/ADuM5402/ADuM5403/ADuM5404
Data Sheet
Table 9. Input and Output Characteristics
Parameter
DC SPECIFICATIONS
Logic High Input Threshold
Logic Low Input Threshold
Symbol
Min
VIH
VIL
0.7 × VISO or 0.7 × VDD1
Logic High Output Voltages
VOH
VDD1 − 0.3 or VISO − 0.3
VDD1 − 0.5 or VISO − 0.5
Logic Low Output Voltages
VOL
Undervoltage Lockout
Positive Going Threshold
Negative Going Threshold
Hysteresis
Input Currents per Channel
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient
Immunity 1
Refresh Rate
1
Typ
Max
0.3 × VISO or 0.3 ×
VDD1
3.3
3.1
0.0
0.0
Unit
V
V
0.1
0.4
V
V
V
V
+10
V
V
V
μA
UVLO
VUV+
VUV−
VUVH
II
−10
2.7
2.4
0.3
+0.01
tR/tF
|CM|
25
2.5
35
ns
kV/μs
1.0
Mbps
fr
Test Conditions/Comments
IOx = −20 μA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 μA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
VDD1, VDDL, VISO supplies
0 V ≤ VIx ≤ VDDx
10% to 90%
VIx = VDD1 or VISO, VCM = 1000 V,
transient magnitude = 800 V
|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.7 × VDD1 or 0.7 × VISO for a high output or VO < 0.3 × VDD1 or 0.3 × VISO for a
low output. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
Rev. B | Page 6 of 28
Data Sheet
ADuM5401/ADuM5402/ADuM5403/ADuM5404
ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY
Typical specifications are at TA = 25°C, VDD1 = 5.0 V, VISO = 3.3 V, VSEL = GNDISO. Minimum/maximum specifications apply over the
entire recommended operation range which is 4.5 V ≤ VDD1 ≤ 5.5 V, 3.0 V ≤ VISO ≤ 3.6 V; and −40°C ≤ TA ≤ +105°C, unless otherwise noted.
Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 10. DC-to-DC Converter Static Specifications
Parameter
DC-TO-DC CONVERTER SUPPLY
Setpoint
Line Regulation
Load Regulation
Output Ripple
Output Noise
Switching Frequency
PWM Frequency
Output Supply Current
Efficiency at IISO (MAX)
IDD1, No VISO Load
IDD1, Full VISO Load
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
VISO
VISO (LINE)
VISO (LOAD)
VISO (RIP)
VISO (NOISE)
fOSC
fPWM
IISO (MAX)
3.0
3.3
1
1
50
130
180
625
3.6
V
mV/V
%
mV p-p
mV p-p
MHz
kHz
mA
%
mA
mA
IISO = 0 mA
IISO = 50 mA, VDD1 = 3.0 V to 3.6 V
IISO = 6 mA to 54 mA
20 MHz bandwidth, CBO = 0.1 μF||10 μF, IISO = 90 mA
CBO = 0.1 μF||10 μF, IISO = 90 mA
5
100
30
14
230
IDD1 (Q)
IDD1 (MAX)
20
VISO > 3 V
IISO = 90 mA
Table 11. DC-to-DC Converter Dynamic Specifications
Parameter
SUPPLY CURRENT
Input
ADuM5401
ADuM5402
ADuM5403
ADuM5404
Available to Load
ADuM5401
ADuM5402
ADuM5403
ADuM5404
Symbol
1 Mbps—A or C Grade
Min
Typ
Max
25 Mbps—C Grade
Min
Typ
Max
Unit
Test Conditions/Comments
No VISO load
No VISO load
No VISO load
No VISO load
IDD1
9
9
9
9
44
45
46
47
mA
mA
mA
mA
100
100
100
100
92
91
89
88
mA
mA
mA
mA
IISO (LOAD)
Table 12. Switching Specifications
Parameter
SWITCHING SPECIFICATIONS
Data Rate
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Pulse Width
Propagation Delay Skew
Channel Matching
Codirectional 1
Opposing Directional 2
1
Symbol
Min
tPHL, tPLH
PWD
A Grade
Typ
Max
60
Min
1
100
40
25
60
6
tPSKCD
tPSKOD
Test Conditions/Comments
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
50
15
50
50
6
15
ns
ns
5
PW
tPSK
Unit
Mbps
ns
ns
ps/°C
ns
ns
45
1000
40
Within PWD limit
Between any two units
Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.
Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.
7
2
C Grade
Typ
Max
Rev. B | Page 7 of 28
ADuM5401/ADuM5402/ADuM5403/ADuM5404
Data Sheet
Table 13. Input and Output Characteristics
Parameter
DC SPECIFICATIONS
Logic High Input Threshold
Symbol
Min
VIH
0.7 × VISO or 0.7 ×
VDD1
Logic Low Input Threshold
VIL
Logic High Output Voltages
VOH
Logic Low Output Voltages
VOL
Undervoltage Lockout
Positive Going Threshold
Negative Going Threshold
Hysteresis
Input Currents per Channel
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient
Immunity 1
Refresh Rate
1
Typ
Max
Unit
V
0.3 × VISO or 0.3 ×
VDD1
VDD1 − 0.2, VISO − 0.2
VDD1 − 0.5 or
VISO − 0.5
VDD1 or VISO
VDD1 − 0.2 or
VISO − 0.2
0.0
0.0
V
V
V
IOx = −20 μA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
0.1
0.4
V
V
IOx = 20 μA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
VDD1, VDDL, VISO supplies
+10
V
V
V
μA
UVLO
VUV+
VUV−
VUVH
II
−10
2.7
2.4
0.3
+0.01
tR/tF
|CM|
25
2.5
35
ns
kV/μs
1.0
Mbps
fr
Test Conditions/Comments
0 V ≤ VIx ≤ VDDx
10% to 90%
VIx = VDD1 or VISO, VCM = 1000 V,
transient magnitude = 800 V
|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.7 × VDD1 or 0.7 × VISO for a high output or VO < 0.3 × VDD1 or 0.3 × VISO for a
low output. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
Rev. B | Page 8 of 28
Data Sheet
ADuM5401/ADuM5402/ADuM5403/ADuM5404
PACKAGE CHARACTERISTICS
Table 14.
Parameter
RESISTANCE AND CAPACITANCE
Resistance (Input-to-Output) 1
Capacitance (Input-to-Output)1
Input Capacitance 2
IC Junction-to-Ambient Thermal
Resistance
Symbol
Min
Typ
Max
1012
2.2
4.0
45
RI-O
CI-O
CI
θJA
Unit
Ω
pF
pF
°C/W
Test Conditions/Comments
f = 1 MHz
Thermocouple located at center of package underside,
test conducted on 4-layer board with thin traces 3
1
This device is considered a 2-terminal device; Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.
Input capacitance is from any input data pin to ground.
3
See the Thermal Analysis section for thermal model definitions.
2
REGULATORY INFORMATION
The ADuM5401/ADuM5402/ADuM5403/ADuM5404 are approved by the organizations listed in Table 15. Refer to Table 20 and the
Insulation Lifetime section for more information about the recommended maximum working voltages for specific cross-insulation
waveforms and insulation levels.
Table 15.
UL 1
Recognized under 1577 component
recognition program1
Single protection, 2500 V rms
isolation voltage
File E214100
CSA
Approved under CSA Component
Acceptance Notice #5A
Testing was conducted per CSA 60950-1-07
and IEC 60950-1 2nd Ed. at 2.5 kV rated voltage.
Basic insulation at 600 V rms (848 V peak)
working voltage.
Reinforced insulation at 250 V rms (353 V peak)
working voltage.
File 205078
VDE (Pending)2
Certified according to IEC 60747-5-2
(VDE 0884 Part 2):2003-01 2
Basic insulation, 560 V peak
File 2471900-4880-0001
1
In accordance with UL 1577, each ADuM5401/ADuM5402/ADuM5403/ADuM5404 is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second
(current leakage detection limit = 10 μA).
2
In accordance with IEC 60747-5-2 (VDE 0884 Part 2):2003-01, each ADuM540x is proof tested by applying an insulation test voltage ≥1590 V peak for 1 second (partial
discharge detection limit = 5 pC). The * marking branded on the component designates IEC 60747-5-2 (VDE 0884 Part 2):2003-01 approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 16. Critical Safety-Related Dimensions and Material Properties
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Distance
Symbol Value
2500
L(I01)
8.0
Unit Test Conditions/Comments
V rms 1-minute duration
mm
Measured from input terminals to output terminals,
shortest distance through air
7.6
mm
Measured from input terminals to output terminals,
shortest distance path along body
0.017 min mm
Distance through insulation
>175
V
DIN IEC 112/VDE 0303, Part 1
IIIa
Material Group (DIN VDE 0110, 1/89, Table 1)
Minimum External Tracking (Creepage)
L(I02)
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Material Group
CTI
Rev. B | Page 9 of 28
ADuM5401/ADuM5402/ADuM5403/ADuM5404
Data Sheet
IEC 60747-5-2 (VDE 0884, PART 2):2003-01 INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
the protective circuits. The asterisk (*) marking on packages denotes IEC 60747-5-2 (VDE 0884, Part 2) approval.
Table 17. VDE Characteristics
Description
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 400 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input-to-Output Test Voltage, Method b1
Conditions
VIORM × 1.875 = VPR, 100% production test, tm = 1 sec,
partial discharge < 5 pC
Input-to-Output Test Voltage, Method a
After Environmental Tests Subgroup 1
After Input and/or Safety Test Subgroup 2
and Subgroup 3
Highest Allowable Overvoltage
Safety Limiting Values
Symbol
Characteristic
Unit
VIORM
VPR
I to IV
I to III
I to II
40/105/21
2
560
1050
V peak
V peak
896
672
V peak
V peak
VTR
4000
V peak
TS
IS1
RS
150
555
>109
°C
mA
Ω
VPR
VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC
VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC
Transient overvoltage, tTR = 10 sec
Maximum value allowed in the event of a failure
(see Figure 6)
Case Temperature
Side 1 IDD1 Current
Insulation Resistance at TS
VIO = 500 V
500
400
300
200
100
0
0
50
100
150
AMBIENT TEMPERATURE (°C)
200
06577-002
SAFE OPERATING VDD1 CURRENT (mA)
600
Figure 6. Thermal Derating Curve, Dependence of Safety Limiting Values on Case Temperature, per DIN EN 60747-5-2
RECOMMENDED OPERATING CONDITIONS
Table 18.
Parameter
Operating Temperature 1
Supply Voltages 2
VDD1 @ VSEL = 0 V
VDD1 @ VSEL = VISO
1
2
Symbol
TA
Min
−40
Max
+105
Unit
°C
VDD
VDD
3.0
4.5
5.5
5.5
V
V
Operation at 105°C requires reduction of the maximum load current as specified in Table 19.
Each voltage is relative to its respective ground.
Rev. B | Page 10 of 28
Data Sheet
ADuM5401/ADuM5402/ADuM5403/ADuM5404
ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25°C, unless otherwise noted.
Table 19.
Parameter
Storage Temperature Range (TST)
Ambient Operating Temperature
Range (TA)
Supply Voltages (VDD1, VISO) 1
Input Voltage (VIA, VIB, VIC, VID, VSEL)1, 2
Output Voltage (VOA, VOB, VOC, VOD)1, 2
Average Output Current per Pin 3
Common-Mode Transients 4
Rating
−55°C to +150°C
−40°C to +105°C
−0.5 V to +7.0 V
−0.5 V to VDDI + 0.5 V
−0.5 V to VDDO + 0.5 V
−10 mA to +10 mA
−100 kV/μs to +100 kV/μs
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
1
Each voltage is relative to its respective ground.
VDDI and VDDO refer to the supply voltages on the input and output sides of a
given channel, respectively. See the PCB Layout section.
3
See Figure 6 for maximum rated current values for various temperatures.
4
. Common-mode transients exceeding the absolute maximum slew rate may
cause latch-up or permanent damage.
2
Table 20. Maximum Continuous Working Voltage Supporting 50-Year Minimum Lifetime 1
Parameter
AC Voltage, Bipolar Waveform
AC Voltage, Unipolar Waveform
Basic Insulation
Reinforced Insulation
DC Voltage
Basic Insulation
Reinforced Insulation
1
Max
424
Unit
V peak
Applicable Certification
All certifications, 50-year operation
600
353
V peak
V peak
Working voltage per IEC 60950-1
Working voltage per IEC 60950-1
600
353
V peak
V peak
Working voltage per IEC 60950-1
Working voltage per IEC 60950-1
Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more information.
Rev. B | Page 11 of 28
ADuM5401/ADuM5402/ADuM5403/ADuM5404
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VDD1 1
16
VISO
GND1 2
15
GNDISO
VIA 3
14
VOA
VIC 5
ADuM5401
13 VOB
TOP VIEW
(Not to Scale) 12 VOC
VOD 6
11
VID
RCOUT 7
10
VSEL
GND1 8
9
GNDISO
06577-004
VIB 4
Figure 7. ADuM5401 Pin Configuration
Table 21. ADuM5401 Pin Function Descriptions
Pin No. Mnemonic Description
1
VDD1
Primary Supply Voltage, 3.0 V to 5.5 V.
2, 8
GND1
Ground 1. Ground reference for isolator primary. Pin 2 and Pin 8 are internally connected, and it is recommended that both
pins be connected to a common ground.
3
VIA
Logic Input A.
4
VIB
Logic Input B.
5
VIC
Logic Input C.
6
VOD
Logic Output D.
7
RCOUT
Regulation Control Output. This pin is connected to the RCIN of a slave isoPower device to allow the ADuM5401 to
control the regulation of the slave device.
9, 15
GNDISO
Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and it is recommended that both pins be
connected to a common ground.
10
VSEL
Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V.
11
VID
Logic Input D.
12
VOC
Logic Output C.
13
VOB
Logic Output B.
14
VOA
Logic Output A.
16
VISO
Secondary Supply Voltage Output for External Loads, 3.3 V (VSEL Low) or 5.0 V (VSEL High).
Rev. B | Page 12 of 28
ADuM5401/ADuM5402/ADuM5403/ADuM5404
VDD1 1
16
VISO
GND1 2
15
GNDISO
VIA 3
14
VOA
VIB 4
VOC 5
ADuM5402
13 VOB
TOP VIEW
(Not to Scale) 12 VIC
VOD 6
11
VID
RCOUT 7
10
VSEL
GND1 8
9
GNDISO
06577-005
Data Sheet
Figure 8. ADuM5402 Pin Configuration
Table 22. ADuM5402 Pin Function Descriptions
Pin No. Mnemonic Description
1
VDD1
Primary Supply Voltage, 3.0 V to 5.5 V.
2, 8
GND1
Ground 1. Ground reference for isolator primary. Pin 2 and Pin 8 are internally connected, and it is recommended that both
pins be connected to a common ground.
3
VIA
Logic Input A.
4
VIB
Logic Input B.
5
VOC
Logic Output C.
6
VOD
Logic Output D.
7
RCOUT
Regulation Control Output. This pin is connected to the RCIN of a slave isoPower device to allow the ADuM5402 to
control the regulation of the slave device.
9, 15
GNDISO
Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and it is recommended that both pins be
connected to a common ground.
10
VSEL
Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V.
11
VID
Logic Input D.
12
VIC
Logic Input C.
13
VOB
Logic Output B.
14
VOA
Logic Output A.
16
VISO
Secondary Supply Voltage Output for External Loads, 3.3 V (VSEL Low) or 5.0 V (VSEL High).
Rev. B | Page 13 of 28
ADuM5401/ADuM5402/ADuM5403/ADuM5404
Data Sheet
VDD1 1
16
VISO
GND1 2
15
GNDISO
VIA 3
14
VOA
VOC 5
ADuM5403
13 VIB
TOP VIEW
(Not to Scale) 12 VIC
VOD 6
11
VID
RCOUT 7
10
VSEL
GND1 8
9
GNDISO
06577-006
VOB 4
Figure 9. ADuM5403 Pin Configuration
Table 23. ADuM5403 Pin Function Descriptions
Pin No. Mnemonic Description
1
VDD1
Primary Supply Voltage, 3.0 V to 5.5 V.
2, 8
GND1
Ground 1. Ground reference for isolator primary. Pin 2 and Pin 8 are internally connected, and it is recommended that both
pins be connected to a common ground.
3
VIA
Logic Input A.
4
VOB
Logic Output B.
5
VOC
Logic Output C.
6
VOD
Logic Output D.
7
RCOUT
Regulation Control Output. This pin is connected to the RCIN of a slave isoPower device to allow the ADuM5403 to
control the regulation of the slave device.
9, 15
GNDISO
Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and it is recommended that both pins be
connected to a common ground.
10
VSEL
Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V.
11
VID
Logic Input D.
12
VIC
Logic Input C.
13
VIB
Logic Input B.
14
VOA
Logic Output A.
16
VISO
Secondary Supply Voltage Output for External Loads, 3.3 V (VSEL Low) or 5.0 V (VSEL High).
Rev. B | Page 14 of 28
ADuM5401/ADuM5402/ADuM5403/ADuM5404
VDD1 1
16
VISO
GND1 2
15
GNDISO
VOA 3
14
VIA
VOB 4
VOC 5
ADuM5404
13 VIB
TOP VIEW
(Not to Scale) 12 VIC
VOD 6
11
VID
RCOUT 7
10
VSEL
GND1 8
9
GNDISO
06577-007
Data Sheet
Figure 10. ADuM5404 Pin Configuration
Table 24. ADuM5404 Pin Function Descriptions
Pin No. Mnemonic Description
1
VDD1
Primary Supply Voltage, 3.0 V to 5.5 V.
2, 8
GND1
Ground 1. Ground reference for isolator primary. Pin 2 and Pin 8 are internally connected, and it is recommended that both
pins be connected to a common ground.
3
VOA
Logic Output A.
4
VOB
Logic Output B.
5
VOC
Logic Output C.
6
VOD
Logic Output D.
7
RCOUT
Regulation Control Output. This pin is connected to the RCIN of a slave isoPower device to allow the ADuM5404 to
control the regulation of the slave device.
9, 15
GNDISO
Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and it is recommended that both pins be
connected to a common ground.
10
VSEL
Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V.
11
VID
Logic Input D.
12
VIC
Logic Input C.
13
VIB
Logic Input B.
14
VIA
Logic Input A.
16
VISO
Secondary Supply Voltage Output for External Loads, 3.3 V (VSEL Low) or 5.0 V (VSEL High).
TRUTH TABLE
Table 25. Truth Table (Positive Logic)
VSEL 1
H
L
L
H
1
2
RCOUT 2
PWM
PWM
PWM
PWM
VDD1 (V)
5
5
3.3
3.3
VISO (V)
5
3.3
3.3
5
Notes
Master mode, normal operation.
Master mode, normal operation.
Master mode, normal operation.
This supply configuration is not recommended due to extremely poor efficiency.
H refers to a high logic, and L refers to a low logic.
PWM refers to the regulation control signal. This signal is derived from the secondary side regulator and can be used to control other isoPower devices.
Rev. B | Page 15 of 28
ADuM5401/ADuM5402/ADuM5403/ADuM5404
Data Sheet
0.40
4.0
0.35
3.5
0.30
3.0
3.0
2.5
2.5
2.0
2.0
1.5
1.5
0.25
0.20
0.15
4.0
3.5
POWER
1.0
1.0
0.10
POWER (W)
INPUT CURRENT (A)
EFFICIENCY
TYPICAL PERFORMANCE CHARACTERISTICS
IDD
0
0.02
0.04
0.06
0.08
OUTPUT CURRENT (A)
0.10
0.12
06577-033
0
0.5
0.5
0
3.0
3.5
4.0
4.5
5.0
5.5
6.0
0
6.5
06577-011
3.3V INPUT/3.3V OUTPUT
5V INPUT/3.3V OUTPUT
5V INPUT/5V OUTPUT
0.05
INPUT SUPPLY VOLTAGE (V)
Figure 14. Typical Short-Circuit Input Current and Power vs.
VDD1 Supply Voltage
Figure 11. Typical Power Supply Efficiency at
5 V Input/5 V Output and 3.3 V Input/3.3 V Output
OUTPUT VOLTAGE
(500mV/DIV)
1.0
0.9
0.7
0.6
0.5
10% LOAD
0.3
0.2
0
0
0.02
0.04
0.06
0.08
0.10
0.12
IISO (A)
(100µs/DIV)
06577-026
VDD1 = 5V, VISO = 5V
VDD1 = 5V, VISO = 3V
VDD1 = 3.3V, VISO = 3.3V
06577-012
0.4
0.1
90% LOAD
DYNAMIC LOAD
POWER DISSIPATION (W)
0.8
Figure 12. Typical Total Power Dissipation vs. Isolated Output Supply
Current in All Supported Power Configurations
Figure 15. Typical VISO Transient Load Response, 5 V Output,
10% to 90% Load Step
OUTPUT VOLTAGE
(500mV/DIV)
0.12
0.08
0.04
0.02
0
3.3V INPUT/3.3V OUTPUT
5V INPUT/3.3V OUTPUT
5V INPUT/5V OUTPUT
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
INPUT CURRENT (A)
Figure 13. Typical Isolated Output Supply Current vs. Input Current
in All Supported Power Configurations
10% LOAD
90% LOAD
06577-013
DYNAMIC LOAD
0.06
06577-027
OUTPUT CURRENT (A)
0.10
(100µs/DIV)
Figure 16. Typical VISO Transient Load Response, 3.3 V Output,
10% to 90% Load Step
Rev. B | Page 16 of 28
Data Sheet
ADuM5401/ADuM5402/ADuM5403/ADuM5404
5V OUTPUT RIPPLE (10mV/DIV)
5
VISO (V)
4
10% LOAD
3
90% LOAD
2
0
–1.0
BW = 20MHz (400ns/DIV)
Figure 17. Typical VISO = 5 V Output Voltage Ripple at 90% Load
06577-031
06577-014
1
–0.5
0
0.5
1.0
1.5
TIME (ms)
2.0
2.5
3.0
Figure 20. Typical Output Voltage Start-Up Transient at
10% and 90% Load, VISO = 3.3 V
20
5V INPUT/5V OUTPUT
3.3V INPUT/3.3V OUTPUT
5V INPUT/3.3V OUTPUT
SUPPLY CURRENT (mA)
3.3V OUTPUT RIPPLE (10mV/DIV)
16
12
8
0
BW = 20MHz (400ns/DIV)
0
5
10
15
DATA RATE (Mbps)
20
25
06577-028
06577-015
4
Figure 21. Typical ICH Supply Current per Forward Data Channel
(15 pF Output Load)
Figure 18. Typical VISO = 3.3 V Output Voltage Ripple at 90% Load
20
7
5V INPUT/5V OUTPUT
3.3V INPUT/3.3V OUTPUT
5V INPUT/3.3V OUTPUT
10% LOAD
6
SUPPLY CURRENT (mA)
16
4
90% LOAD
3
2
12
8
0
–1
0
1
TIME (ms)
2
0
3
0
5
10
15
DATA RATE (Mbps)
20
25
Figure 22. Typical ICH Supply Current per Reverse Data Channel
(15 pF Output Load)
Figure 19. Typical Output Voltage Start-Up Transient at
10% and 90% Load, VISO = 5 V
Rev. B | Page 17 of 28
06577-029
4
1
06577-030
VISO (V)
5
ADuM5401/ADuM5402/ADuM5403/ADuM5404
Data Sheet
5
3.0
2.5
SUPPLY CURRENT (mA)
3
5V
2
3.3V
1.5
5V
1.0
0.5
0
5
10
15
DATA RATE (Mbps)
20
25
0
Figure 23. Typical IISO(D) Dynamic Supply Current per Input
0
5
10
15
DATA RATE (Mbps)
20
25
Figure 24. Typical IISO(D) Dynamic Supply Current per Output
(15 pF Output Load)
Rev. B | Page 18 of 28
06577-118
0
2.0
3.3V
1
06577-119
SUPPLY CURRENT (mA)
4
Data Sheet
ADuM5401/ADuM5402/ADuM5403/ADuM5404
TERMINOLOGY
IDD1 (Q)
IDD1(Q) is the minimum operating current drawn at the VDD1 pin
when there is no external load at VISO and the I/O pins are
operating below 2 Mbps, requiring no additional dynamic supply
current. IDD1(Q) reflects the minimum current operating condition.
IDD1 (D)
IDD1 (D) is the typical input supply current with all channels
simultaneously driven at a maximum data rate of 25 Mbps
with full capacitive load representing the maximum dynamic
load conditions. Resistive loads on the outputs should be
treated separately from the dynamic load.
IDD1 (MAX)
IDD1 (MAX) is the input current under full dynamic and VISO load
conditions.
ISO (LOAD)
ISO (LOAD) is the current available to the load.
tPHL Propagation Delay
The tPHL propagation delay is measured from the 50% level of
the falling edge of the VIx signal to the 50% level of the falling
edge of the VOx signal.
tPLH Propagation Delay
tPLH propagation delay is measured from the 50% level of the rising
edge of the VIx signal to the 50% level of the rising edge of the
VOx signal.
Propagation Delay Skew, tPSK
tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH
that is measured between units at the same operating temperature,
supply voltages, and output load within the recommended
operating conditions.
Channel-to-Channel Matching, (tPSKCD/tPSKOD)
Channel-to-channel matching is the absolute value of the
difference in propagation delays between two channels when
operated with identical loads.
Minimum Pulse Width
The minimum pulse width is the shortest pulse width at which
the specified pulse width distortion is guaranteed.
Maximum Data Rate
The maximum data rate is the fastest data rate at which the
specified pulse width distortion is guaranteed.
Rev. B | Page 19 of 28
ADuM5401/ADuM5402/ADuM5403/ADuM5404
Data Sheet
APPLICATIONS INFORMATION
The ADuM5401/ADuM5402/ADuM5403/ADuM5404 implement
undervoltage lockout (UVLO) with hysteresis on the VDD1 power
input. This feature ensures that the converter does not enter
oscillation due to noisy input power or slow power-on ramp rates.
PCB LAYOUT
The ADuM5401/ADuM5402/ADuM5403/ADuM5404 digital
isolators with 0.5 W isoPower integrated dc-to-dc converter
require no external interface circuitry for the logic interfaces.
Power supply bypassing is required at the input and output
supply pins (see Figure 25). Note that low ESR bypass capacitors
are required between Pin 1 and Pin 2 and between Pin 15 and
Pin 16, as close to the chip pads as possible.
The power supply section of the ADuM5401/ADuM5402/
ADuM5403/ADuM5404 uses a 180 MHz oscillator frequency
to pass power efficiently through its chip scale transformers. In
addition, the normal operation of the data section of the iCoupler
introduces switching transients on the power supply pins. Bypass
capacitors are required for several operating frequencies. Noise
suppression requires a low inductance, high frequency capacitor;
ripple suppression and proper regulation require a large value
capacitor. These are most conveniently connected between Pin 1
and Pin 2 for VDD1 and between Pin 15 and Pin 16 for VISO.
To suppress noise and reduce ripple, a parallel combination of
at least two capacitors is required. The recommended capacitor
values are 0.1 μF and 10 μF for VDD1 and VISO. The smaller
capacitor must have a low ESR; for example, use of a ceramic
capacitor is advised.
The total lead length between the ends of the low ESR capacitor
and the input power supply pin must not exceed 2 mm. Installing
the bypass capacitor with traces more than 2 mm in length may
result in data corruption. Consider bypassing between Pin 1 and
Pin 8 and between Pin 9 and Pin 16 unless both common
ground pins are connected together close to the package.
BYPASS < 2mm
VDD1
VISO
GND1
GNDISO
VIA/VOA
VOA/VIA
VIB/VOB
VOB/VIB
VIC/VOC
VOC/VIC
VID/VOD
VOD/VID
RCOUT
VSEL
GND1
GNDISO
06577-120
The dc-to-dc converter section of the ADuM5401/ADuM5402/
ADuM5403/ADuM5404 works on principles that are common to
most switching power supplies. It has a secondary side controller
architecture with isolated pulse-width modulation (PWM)
feedback. VDD1 power is supplied to an oscillating circuit that
switches current into a chip-scale air core transformer. Power
transferred to the secondary side is rectified and regulated to
either 3.3 V or 5 V. The secondary (VISO) side controller regulates
the output by creating a PWM control signal that is sent to the
primary (VDD1) side by a dedicated iCoupler data channel. The
PWM modulates the oscillator circuit to control the power being
sent to the secondary side. Feedback allows for significantly higher
power and efficiency.
Figure 25. Recommended PCB Layout
In applications involving high common-mode transients, ensure
that board coupling across the isolation barrier is minimized.
Furthermore, design the board layout such that any coupling that
does occur affects all pins equally on a given component side.
Failure to ensure this can cause voltage differentials between
pins exceeding the absolute maximum ratings for the device
as specified in Table 19, thereby leading to latch-up and/or
permanent damage.
The ADuM5401/ADuM5402/ADuM5403/ADuM5404 are power
devices that dissipates approximately 1 W of power when fully
loaded and running at maximum speed. Because it is not possible
to apply a heat sink to an isolation device, the devices primarily
depend on heat dissipation into the PCB through the GND
pins. If the devices are used at high ambient temperatures, provide
a thermal path from the GND pins to the PCB ground plane.
The board layout in Figure 25 shows enlarged pads for Pin 8 and
Pin 9. Large diameter vias should be implemented from the pad to
the ground, and power planes should be used to reduce inductance.
Multiple vias should be implemented from the pad to the ground
plane to significantly reduce the temperature inside the chip.
The dimensions of the expanded pads are at the discretion of
the designer and depend on the available board space.
THERMAL ANALYSIS
The ADuM5401/ADuM5402/ADuM5403/ADuM5404 parts
consist of four internal die attached to a split lead frame with two
die attach paddles. For the purposes of thermal analysis, the die
is treated as a thermal unit, with the highest junction temperature
reflected in the θJA from Table 14. The value of θJA is based on
measurements taken with the parts mounted on a JEDEC standard,
4-layer board with fine width traces and still air. Under normal
operating conditions, the ADuM5401/ADuM5402/ADuM5403/
ADuM5404 devices operate at full load across the full temperature
range without derating the output current. However, following the
recommendations in the PCB Layout section decreases thermal
resistance to the PCB, allowing increased thermal margins in high
ambient temperatures.
Rev. B | Page 20 of 28
Data Sheet
ADuM5401/ADuM5402/ADuM5403/ADuM5404
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component (see Figure 26).
The propagation delay to a logic low output may differ from the
propagation delay to a logic high.
INPUT (VIx)
50%
OUTPUT (VOx)
tPHL
06577-018
tPLH
50%
Figure 26. Propagation Delay Parameters
Pulse width distortion is the maximum difference between these
two propagation delay values and is an indication of how
accurately the input signal timing is preserved.
Channel-to-channel matching refers to the maximum amount
the propagation delay differs between channels within a single
ADuM5401/ADuM5402/ADuM5403/ADuM5404 component.
Propagation delay skew refers to the maximum amount the
propagation delay differs between multiple ADuM5401/
ADuM5402/ADuM5403/ADuM5404 components operating
under the same conditions.
START-UP BEHAVIOR
The ADuM5401/ADuM5402/ADuM5403/ADuM5404 do not
contain a soft start circuit. Therefore, the start-up current and
voltage behavior must be taken into account when designing
with this device.
When power is applied to VDD1, the input switching circuit begins
to operate and draw current when the UVLO minimum voltage
is reached. The switching circuit drives the maximum available
power to the output until it reaches the regulation voltage where
PWM control begins. The amount of current and the time
required to reach regulation voltage depends on the load and
the VDD1 slew rate.
With a fast VDD1 slew rate (200 μs or less), the peak current draws
up to 100 mA/V of VDD1. The input voltage goes high faster than
the output can turn on, so the peak current is proportional to
the maximum input voltage.
With a slow VDD1 slew rate (in the millisecond range), the input
voltage is not changing quickly when VDD1 reaches the UVLO
minimum voltage. The current surge is approximately 300 mA
because VDD1 is nearly constant at the 2.7 V UVLO voltage. The
behavior during startup is similar to when the device load is a
short circuit; these values are consistent with the short-circuit
current shown in Figure 14.
When starting the device for VISO = 5 V operation, do not limit
the current available to the VDD1 power pin to less than 300 mA.
The ADuM5401/ADuM5402/ADuM5403/ADuM5404 devices
may not be able to drive the output to the regulation point if a
current-limiting device clamps the VDD1 voltage during startup.
As a result, the ADuM5401/ADuM5402/ADuM5403/ADuM5404
devices can draw large amounts of current at low voltage for
extended periods of time.
The output voltage of the ADuM5401/ADuM5402/ADuM5403/
ADuM5404 devices exhibits VISO overshoot during startup. If
this overshoot could potentially damage components attached to
VISO, a voltage-limiting device such as a Zener diode can be used to
clamp the voltage. Typical behavior is shown in Figure 19 and
Figure 20.
EMI CONSIDERATIONS
The dc-to-dc converter section of the ADuM5401/ADuM5402/
ADuM5403/ADuM5404 devices must operate at 180 MHz to
allow efficient power transfer through the small transformers.
This creates high frequency currents that can propagate in circuit
board ground and power planes, causing edge emissions and
dipole radiation between the primary and secondary ground
planes. Grounded enclosures are recommended for applications
that use these devices. If grounded enclosures are not possible,
follow good RF design practices in the layout of the PCB. See the
AN-0971 Application Note for board layout recommendations
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent to the decoder via the transformer.
The decoder is bistable and is, therefore, either set or reset by the
pulses, indicating input logic transitions. In the absence of logic
transitions at the input for more than 1 μs, a periodic set of refresh
pulses indicative of the correct input state is sent to ensure dc
correctness at the output. If the decoder receives no internal pulses
for more than approximately 5 μs, the input side is assumed to be
unpowered or nonfunctional, and the isolator output is forced to a
default low state by the watchdog timer circuit. This situation should
occur in the ADuM5401/ADuM5402/ADuM5403/ADuM5404
during power-up and power-down operations.
The limitation on the magnetic field immunity of the ADuM5401/
ADuM5402/ADuM5403/ADuM5404 is set by the condition in
which induced voltage in the receiving coil of the transformer is
sufficiently large to either falsely set or reset the decoder. The
following analysis defines the conditions under which this may
occur. The 3.3 V operating condition of the ADuM5401/
ADuM5402/ADuM5403/ADuM5404 is examined because it
represents the most susceptible mode of operation.
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at approximately
0.5 V, thus establishing a 0.5 V margin in which induced voltages
can be tolerated. The voltage induced across the receiving coil is
given by
V = (−dβ/dt)∑πrn2; n = 1, 2, … , N
where:
β is the magnetic flux density (gauss).
rn is the radius of the nth turn in the receiving coil (cm).
N is the total number of turns in the receiving coil.
Rev. B | Page 21 of 28
ADuM5401/ADuM5402/ADuM5403/ADuM5404
Given the geometry of the receiving coil in the ADuM5401/
ADuM5402/ADuM5403/ADuM5404, and an imposed
requirement that the induced voltage be, at most, 50% of the
0.5 V margin at the decoder, a maximum allowable magnetic
field is calculated as shown in Figure 27.
MAXIMUM ALLOWABLE MAGNETIC FLUX
DENSITY (kGauss)
100
Data Sheet
Note that, at combinations of strong magnetic field and high
frequency, any loops formed by PCB traces can induce error
voltages sufficiently large to trigger the thresholds of succeeding
circuitry. Exercise care in the layout of such traces to avoid this
possibility.
POWER CONSUMPTION
The VDD1 power supply input provides power to the iCoupler data
channels, as well as to the power converter. For this reason, the
quiescent currents drawn by the data converter and the primary
and secondary input/output channels cannot be determined
separately. All of these quiescent power demands have been
combined into the IDD1 (Q) current, as shown in Figure 29. The
total IDD1 supply current is the sum of the quiescent operating
current; the dynamic current, IDD1 (D), demanded by the I/O
channels; and any external IISO load.
10
1
0.1
0.01
10k
1M
10M
100k
MAGNETIC FIELD FREQUENCY (Hz)
100M
06577-019
IDD1(Q)
0.001
1k
IDD1(D)
Figure 27. Maximum Allowable External Magnetic Flux Density
IISO
CONVERTER
PRIMARY
IDDP(D)
For example, at a magnetic field frequency of 1 MHz, the maximum
allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at
the receiving coil. This voltage is approximately 50% of the sensing
threshold and does not cause a faulty output transition. Similarly, if
such an event occurs during a transmitted pulse (and is of the
worst-case polarity), it reduces the received pulse from >1.0 V to
0.75 V, still well above the 0.5 V sensing threshold of the decoder.
The preceding magnetic flux density values correspond to specific
current magnitudes at given distances from the ADuM5401/
ADuM5402/ADuM5403/ADuM5404 transformers. Figure 28
expresses these allowable current magnitudes as a function of
frequency for selected distances. As shown in Figure 28, the
ADuM5401/ADuM5402/ADuM5403/ADuM5404 are extremely
immune and can be affected only by extremely large currents
operated at high frequency very close to the component. For the
1 MHz example, a 0.5 kA current placed 5 mm away from the
ADuM5401/ADuM5402/ADuM5403/ADuM5404 is required to
affect the operation of the device.
IISO(D)
SECONDARY
DATA
INPUT/OUTPUT
4-CHANNEL
06577-024
PRIMARY
DATA
INPUT/OUTPUT
4-CHANNEL
CONVERTER
SECONDARY
Figure 29. Power Consumption Within the
ADuM5401/ADuM5402/ADuM5403/ADuM5404
Both dynamic input and output current is consumed only
when operating at channel speeds higher than the refresh rate,
fr. Each channel has a dynamic current determined by its data
rate. Figure 21 shows the current for a channel in the forward
direction, which means that the input is on the primary side of
the part. Figure 22 shows the current for a channel in the reverse
direction, which means that the input is on the secondary side of
the part. Both figures assume a typical 15 pF load. The following
relationship allows the total IDD1 current to be calculated:
IDD1 = (IISO × VISO)/(E × VDD1) + Σ ICHn; n = 1 to 4
(1)
where:
IDD1 is the total supply input current.
ICHn is the current drawn by a single channel determined from
Figure 21 or Figure 22, depending on channel direction.
IISO is the current drawn by the secondary side external load.
E is the power supply efficiency at 100 mA load from Figure 11
at the VISO and VDD1 condition of interest.
DISTANCE = 1m
100
10
DISTANCE = 100mm
1
DISTANCE = 5mm
0.1
0.01
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
06577-020
MAXIMUM ALLOWABLE CURRENT (kA)
1k
Figure 28. Maximum Allowable Current for Various Current-toADuM5401/ADuM5402/ADuM5403/ADuM5404 Spacings
Rev. B | Page 22 of 28
Data Sheet
ADuM5401/ADuM5402/ADuM5403/ADuM5404
The maximum external load can be calculated by subtracting
the dynamic output load from the maximum allowable load.
IISO (LOAD) = IISO (MAX) − Σ IISO (D)n; n = 1 to 4
(2)
where:
IISO (LOAD) is the current available to supply an external secondary
side load.
IISO (MAX) is the maximum external secondary side load current
available at VISO.
IISO (D)n is the dynamic load current drawn from VISO by an input
or output channel, as shown in Figure 23 and Figure 24.
The preceding analysis assumes a 15 pF capacitive load on each
data output. If the capacitive load is larger than 15 pF, the additional
current must be included in the analysis of IDD1 and IISO (LOAD).
POWER CONSIDERATIONS
The ADuM5401/ADuM5402/ADuM5403/ADuM5404 power
input, data input channels on the primary side, and data channels
on the secondary side are all protected from premature operation
by under voltage lockout (UVLO) circuitry. Below the minimum
operating voltage, the power converter holds its oscillator inactive
and all input channel drivers and refresh circuits are idle. Outputs
remain in a high impedance state to prevent transmission of
undefined states during power-up and power-down operations.
During application of power to VDD1, the primary side circuitry
is held idle until the UVLO preset voltage is reached. At that
time, the data channels initialize to their default low output
state until they receive data pulses from the secondary side.
When the primary side is above the UVLO threshold, the data
input channels sample their inputs and begin sending encoded
pulses to the inactive secondary output channels. The outputs
on the primary side remain in their default low state because no
data comes from the secondary side inputs until secondary side
power is established. The primary side oscillator also begins to
operate, transferring power to the secondary power circuits.
The secondary VISO voltage is below its UVLO limit at this point;
the regulation control signal from the secondary side is not being
generated. The primary side power oscillator is allowed to free
run under these conditions, supplying the maximum amount of
power to the secondary side.
As the secondary side voltage rises to its regulation setpoint,
a large inrush current transient is present at VDD1. When the
regulation point is reached, the regulation control circuit produces
the regulation control signal that modulates the oscillator on
the primary side. The VDD1 current is then reduced and is
proportional to the load current. The inrush current is less than
the short-circuit current shown in Figure 14. The duration of
the inrush current depends on the VISO loading conditions and
on the current and voltage available at the VDD1 pin.
As the secondary side converter begins to accept power from
the primary, the VISO voltage starts to rise. When the secondary
side UVLO is reached, the secondary side outputs are initialized
to their default low state until data is received from the corresponding primary side input. It can take up to 1 μs after the
secondary side is initialized for the state of the output to
correlate to the primary side input.
Secondary side inputs sample their state and transmit it to the
primary side. Outputs are valid about 1 μs after the secondary
side becomes active.
Because the rate of charge of the secondary side power supply is
dependent on loading conditions, the input voltage, and the output
voltage level selected, take care that the design allows the converter
sufficient time to stabilize before valid data is required.
When power is removed from VDD1, the primary side converter
and coupler shut down when the UVLO level is reached. The
secondary side stops receiving power and starts to discharge.
The outputs on the secondary side hold the last state that they
received from the primary side. Either the UVLO level is
reached and the outputs are placed in their high impedance
state, or the outputs detect a lack of activity from the primary
side inputs and the outputs are set to their default low value
before the secondary power reaches UVLO.
INCREASING AVAILABLE POWER
The ADuM5401/ADuM5402/ADuM5403/ADuM5404 are
designed with the capability of running in combination with
other compatible isoPower devices. The RCOUT pin allows the
ADuM5401/ADuM5402/ADuM5403/ADuM5404 to provide its
PWM signal to another device acting as a master to regulate its
self and slave devices. Power outputs are combined in parallel
while sharing output power equally.
The ADuM5401/ADuM5402/ADuM5403/ADuM5404 can only
be a master/standalone, and the ADuM5200 can only be a slave/
standalone device. The ADuM5000 can operate as either a master
or slave. This means that the ADuM5000, ADuM520x, and
ADuM540x can only be used in the master/slave combinations
listed in Table 26.
Table 26. Allowed Combinations of isoPower Parts
Master
ADuM5000
ADuM520x
ADuM540x
ADuM5000
Yes
No
Yes
Slave
ADuM520x
Yes
No
Yes
ADuM540x
No
No
No
The allowed combinations of master and slave configured parts
listed in Table 26 is sufficient to make any combination of power
and channel count.
Rev. B | Page 23 of 28
ADuM5401/ADuM5402/ADuM5403/ADuM5404
Data Sheet
Table 27 illustrates how isoPower devices can provide many combinations of data channel count and multiples of the single unit power.
Table 27. Configurations for Power and Data Channels
Power Unit
1-Unit Power
0
ADuM5000 master
2
ADuM520x master
Number of Data Channels
4
ADuM5401 to ADuM5404 master
2-Unit Power
ADuM5000 master
ADuM5000 slave
ADuM5000 master
ADuM5000 slave
ADuM5000 slave
ADuM5000 master
ADuM520x slave
ADuM5000 master
ADuM5000 slave
ADuM520x slave
ADuM5401 to ADuM5404 master
ADuM520x slave
ADuM5401 to ADuM5404 master
ADuM5000 slave
ADuM5000 slave
Analog Devices performs accelerated life testing using voltage levels
higher than the rated continuous working voltage. Acceleration
factors for several operating conditions are determined. These
factors allow calculation of the time to failure at the actual working
voltage. The values shown in Table 20 summarize the peak voltage
for 50 years of service life for a bipolar ac operating condition
and the maximum CSA/VDE approved working voltages. In
many cases, the approved working voltage is higher than the
50-year service life voltage. Operation at these high working
voltages can lead to shortened insulation life in some cases.
Any cross-insulation voltage waveform that does not conform
to Figure 31 or Figure 32 should be treated as a bipolar ac waveform and its peak voltage limited to the 50-year lifetime voltage
value listed in Table 20. The voltage presented in Figure 32 is
shown as sinusoidal for illustration purposes only. It is meant to
represent any voltage waveform varying between 0 V and some
limiting value. The limiting value can be positive or negative,
but the voltage cannot cross 0 V.
The insulation lifetime of the ADuM5401/ADuM5402/
ADuM5403/ADuM5404 devices depends on the voltage
waveform type imposed across the isolation barrier. The iCoupler
insulation structure degrades at different rates depending on
whether the waveform is bipolar ac, unipolar ac, or dc. Figure 30,
Figure 31, and Figure 32 illustrate these different isolation voltage
waveforms.
Bipolar ac voltage is the most stringent environment. The goal
of a 50-year operating lifetime under the bipolar ac condition
determines the maximum working voltage recommended by
Analog Devices.
RATED PEAK VOLTAGE
0V
Figure 30. Bipolar AC Waveform
RATED PEAK VOLTAGE
0V
Figure 31. DC Waveform
RATED PEAK VOLTAGE
0V
NOTES:
1. THE VOLTAGE IS SHOWN AS SINUSOIDAL FOR ILLUSTRATION
PURPOSES ONLY. IT IS MEANT TO REPRESENT ANY VOLTAGE
WAVEFORM VARYING BETWEEN 0V AND SOME LIMITING VALUE.
THE LIMITING VALUE CAN BE POSITIVE OR NEGATIVE, BUT THE
VOLTAGE CANNOT CROSS 0V.
Figure 32. Unipolar AC Waveform
Rev. B | Page 24 of 28
06577-022
All insulation structures eventually break down when subjected to
voltage stress over a sufficiently long period. The rate of insulation
degradation is dependent on the characteristics of the voltage
waveform applied across the insulation. In addition to the testing
performed by the regulatory agencies, Analog Devices carries
out an extensive set of evaluations to determine the life-time
of the insulation structure within the ADuM5401/ADuM5402/
ADuM5403/ADuM5404 devices.
In the case of unipolar ac or dc voltage, the stress on the insulation
is significantly lower. This allows operation at higher working
voltages while still achieving a 50-year service life. The working
voltages listed in Table 20 can be applied while maintaining the
50-year minimum lifetime, provided that the voltage conforms
to either the unipolar ac or dc voltage cases.
06577-021
INSULATION LIFETIME
06577-023
3-Unit Power
6
ADuM5401 to ADuM5404 master
ADuM121x
ADuM5401 to ADuM5404 master
ADuM520x slave
ADuM5401 to ADuM5404 master
ADuM520x slave
ADuM5000 slave
Data Sheet
ADuM5401/ADuM5402/ADuM5403/ADuM5404
OUTLINE DIMENSIONS
10.50 (0.4134)
10.10 (0.3976)
9
16
7.60 (0.2992)
7.40 (0.2913)
8
1.27 (0.0500)
BSC
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
0.51 (0.0201)
0.31 (0.0122)
10.65 (0.4193)
10.00 (0.3937)
0.75 (0.0295)
0.25 (0.0098)
2.65 (0.1043)
2.35 (0.0925)
SEATING
PLANE
45°
8°
0°
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013- AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
032707-B
1
Figure 33. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body (RW-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model 1, 2
ADuM5401ARWZ
ADuM5401CRWZ
ADuM5402ARWZ
ADuM5402CRWZ
ADuM5403ARWZ
ADuM5403CRWZ
ADuM5404ARWZ
ADuM5404CRWZ
1
2
Number
of Inputs,
VDD1 Side
3
3
2
2
1
1
0
0
Number
of Inputs,
VISO Side
1
1
2
2
3
3
4
4
Maximum
Data Rate
(Mbps)
1
25
1
25
1
25
1
25
Maximum
Propagation
Delay, 5 V (ns)
100
60
100
60
100
60
100
60
Maximum
Pulse Width
Distortion (ns)
40
6
40
6
40
6
40
6
Tape and reel are available. The addition of an RL suffix designates a 13” (1,000 units) tape and reel option.
Z = RoHS Compliant Part.
Rev. B | Page 25 of 28
Temperature
Range (°C)
−40 to +105
−40 to +105
−40 to +105
−40 to +105
−40 to +105
−40 to +105
−40 to +105
−40 to +105
Package
Description
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
Package
Option
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
ADuM5401/ADuM5402/ADuM5403/ADuM5404
NOTES
Rev. B | Page 26 of 28
Data Sheet
Data Sheet
ADuM5401/ADuM5402/ADuM5403/ADuM5404
NOTES
Rev. B | Page 27 of 28
ADuM5401/ADuM5402/ADuM5403/ADuM5404
NOTES
©2008–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06577-0-9/11(B)
Rev. B | Page 28 of 28
Data Sheet