NEC D780232 8-bit single-chip microcontroller Datasheet

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD780232
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The µPD780232 is a member of the µPD780232 Subseries in the 78K/0 Series.
The µPD780232 Subseries consists of products that incorporate a VFD controller/driver for panel control.
A flash memory version, the µPD78F0233, that can operate within the same power supply voltage range as the
mask ROM version, and various development tools are also under development.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
µPD780232 Subseries User’s Manual:
U13364E
78K/0 Series User’s Manual Instructions: U12326E
FEATURES
• I/O ports: 40
• VFD controller/driver: 53 display outputs
• Internal ROM and RAM
(Universal grid supported)
• Internal ROM:
16 KB
• 8-bit resolution A/D converter: 4 channels
• Internal high-speed RAM:
768 bytes
• Serial interface: 2 channels
• Internal buffer RAM:
32 bytes
• Timer: 4 channels
• VFD display RAM:
112 bytes
• Power supply voltage: VDD = 4.5 to 5.5 V
• Minimum instruction execution time can be changed
from high speed (0.4 µs) to low speed (6.4 µs)
APPLICATIONS
Monolithic mini components, separated mini components, tuners, cassette tape decks, CD/MD players, audio
amplifiers, etc.
ORDERING INFORMATION
Part Number
Package
µPD780232GC-×××-8BT
80-pin plastic QFP (14 × 14)
Remark ××× indicates ROM code suffix.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U13415EJ2V0DS00 (2nd edition)
Date Published May 2001 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
2000
1998
µPD780232
78K/0 SERIES LINEUP
The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries names.
Products in mass production
Products under development
Y subseries products are compatible with I2C bus.
Control
100-pin
100-pin
100-pin
100-pin
80-pin
80-pin
µ PD780058
µ PD78058F
80-pin
µPD78054
µPD780065
64-pin
µ PD780078
64-pin
64-pin
64-pin
µ PD780034A
µ PD780024A
µPD78014H
64-pin
µPD78018F
µ PD78083
80-pin
42-/44-pin
EMI-noise reduced version of the µPD78078
µ PD78075B
µ PD78078
µ PD78070A
µPD78078Y
µPD78054 with added timer and enhanced external interface
µ PD78070AY
ROMless version of the µ PD78078
µPD78078Y with enhanced serial I/O and limited function
µ PD780018AY
µ PD780058Y
µ PD78058FY
µPD78054 with enhanced serial I/O
EMI-noise reduced version of the µ PD78054
µPD78018F with added UART and D/A converter and enhanced I/O
µPD780024A with expanded RAM capacity
µPD780034A with added timer and enhanced serial I/O
µ PD780078Y
µ PD780034AY µPD780024A with enhanced A/D converter
µ PD780024AY µPD78018F with enhanced serial I/O
EMI-noise reduced version of the µPD78018F
µ PD78054Y
µ PD78018FY
Basic subseries for control
On-chip UART, capable of operating at low voltage (1.8 V)
Inverter control
64-pin
µPD780988
On-chip inverter controller and UART. EMI-noise reduced.
VFD drive
78K/0
Series
100-pin
µ PD780208
µPD78044F with enhanced I/O and VFD C/D. Display output total: 53
80-pin
µ PD780232
µPD78044H
For panel control. On-chip VFD C/D. Display output total: 53
80-pin
80-pin
µPD78044F
Basic subseries for VFD drive. Display output total: 34
µPD78044F with added N-ch open-drain I/O. Display output total: 34
LCD drive
120-pin
µ PD780338
120-pin
µ PD780328
µPD780318
µ PD780308
µPD78064B
µPD78064
120-pin
100-pin
100-pin
100-pin
µ PD780308 with enhanced display capacity and timer. Segment signal output: 40 pins max.
µ PD780308 with enhanced display capacity and timer. Segment signal output: 32 pins max.
µ PD780308 with enhanced display capacity and timer. Segment signal output: 24 pins max.
µPD780308Y
µ PD78064 with enhanced SIO, and expanded ROM, RAM capacity
EMI-noise reduced version of the µ PD78064
µ PD78064Y
Basic subseries for LCD drive, on-chip UART
Bus interface supported
100-pin
80-pin
µ PD780948
µ PD78098B
On-chip DCAN controller
µPD78054 with added IEBusTM controller. EMI-noise reduced.
80-pin
µ PD780701Y
On-chip DCAN/IEBus controller
80-pin
µ PD780833Y
On-chip controller compliant with J1850 (Class 2)
Meter control
100-pin
µPD780958
For industrial meter control
80-pin
µPD780852
µPD780824
On-chip automobile meter controller/driver
For automobile meter driver. On-chip DCAN controller
80-pin
Remark VFD (Vacuum Fluorescent Display) is referred to as FIP™ (Fluorescent Indicator Panel) in some
documents, but the functions of the two are the same.
2
Data Sheet U13415EJ2V0DS
µPD780232
The major functional differences among the subseries are shown below.
Function
ROM
Capacity
Subseries Name
Timer
8-Bit 16-Bit Watch WDT A/D
µPD78075B 32 K to 40 K 4 ch
Control
µPD78078
µPD78070A
8-Bit 10-Bit 8-Bit
1 ch
1 ch
1 ch
8 ch
A/D
–
Serial Interface
I/O
VDD External
MIN.
Expansion
Value
88
1.8 V
61
2.7 V
D/A
2 ch 3 ch (UART: 1 ch)
48 K to 60 K
–
µPD780058 24 K to 60 K 2 ch
3 ch (time-division UART: 1 ch)
68
1.8 V
µPD78058F 48 K to 60 K
3 ch (UART: 1 ch)
69
2.7 V
µPD78054
√
16 K to 60 K
2.0 V
µPD780065 40 K to 48 K
–
µPD780078 48 K to 60 K
2 ch
µPD780034A 8 K to 32 K
1 ch
–
µPD780024A
8 ch
8 ch
4 ch (UART: 1 ch)
60
2.7 V
3 ch (UART: 2 ch)
52
1.8 V
3 ch (UART: 1 ch)
51
2 ch
53
1 ch (UART: 1 ch)
33
–
µPD78014H
µPD78018F 8 K to 60 K
µPD78083
8 K to 16 K
–
Inverter
control
µPD780988 16 K to 60 K 3 ch Note
VFD
drive
µPD780208 32 K to 60 K 2 ch
–
–
1 ch
–
8 ch
–
3 ch (UART: 2 ch)
47
4.0 V
√
1 ch
1 ch
1 ch
8 ch
–
–
2 ch
74
2.7 V
–
µPD780232 16 K to 24 K 3 ch
–
–
4 ch
40
4.5 V
µPD78044H 32 K to 48 K 2 ch
1 ch
1 ch
8 ch
68
2.7 V
54
1.8 V
1 ch
µPD78044F 16 K to 40 K
LCD
drive
–
µPD780338 48 K to 60 K 3 ch
2 ch
2 ch
1 ch
1 ch
–
10 ch 1 ch 2 ch (UART: 1 ch)
µPD780328
62
µPD780318
70
µPD780308 48 K to 60 K 2 ch
1 ch
8 ch
–
–
µPD78064B 32 K
µPD78064
3 ch (time-division UART: 1 ch)
–
57
2.0 V
79
4.0 V
√
69
2.7 V
–
2 ch (UART: 1 ch)
16 K to 32 K
Bus
µPD780948 60 K
2 ch
interface
supported µPD78098B 40 K to 60 K
1 ch
Meter
control
µPD780958 48 K to 60 K 4 ch
2 ch
–
1 ch
–
–
–
2 ch (UART: 1 ch)
69
2.2 V
–
Dashboard
control
µPD780852 32 K to 40 K 3 ch
1 ch
1 ch
1 ch
5 ch
–
–
3 ch (UART: 1 ch)
56
4.0 V
–
2 ch (UART: 1 ch)
59
Note
2 ch
1 ch
1 ch
8 ch
–
–
3 ch (UART: 1 ch)
2 ch
µPD780824 32 K to 60 K
16-bit timer: 2 channels
10-bit timer: 1 channel
Data Sheet U13415EJ2V0DS
3
µPD780232
FUNCTION OVERVIEW
Item
Internal memory
Function
ROM
16 KB
High-speed RAM
768 bytes
Buffer RAM
32 bytes
VFD display RAM
112 bytes
General-purpose register
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution time
• On-chip minimum instruction execution time variable function
• 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs (@ 5.0 MHz operation with system clock)
Instruction set
• Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)
• Bit manipulation (set, reset, test, Boolean operation)
I/O ports
Total:
40
(including alternate-function pins for VFD) • CMOS I/Os:
11
• P-ch open-drain I/Os:
13
• P-ch open-drain outputs: 16
VFD controller/driver
Total of display outputs: 53
• 15 mA display current: 20
• 5 mA display current: 33
A/D converter
• 8-bit resolution × 4 channels
• Power supply voltage: AVDD = 4.5 to 5.5 V
Serial interface
• 3-wire serial mode (automatic transmit/receive function): 1 channel
• 2-wire serial mode (transmit only):
1 channel
Timer
• 8-bit remote control timer: 1 channel
• 8-bit timer:
2 channels
• Watchdog timer:
Vectored interrupt
sources
4
Maskable
Internal: 10, external: 2
Non-maskable
Internal: 1
Software
1
Power supply voltage
VDD = 4.5 to 5.5 V
Package
80-pin plastic QFP (14 × 14)
1 channel
Data Sheet U13415EJ2V0DS
µPD780232
CONTENTS
1.
PIN CONFIGURATION (TOP VIEW) ................................................................................................. 6
2.
BLOCK DIAGRAM ............................................................................................................................. 8
3.
PIN FUNCTIONS ................................................................................................................................ 9
4.
5.
3.1
Port Pins ..................................................................................................................................................... 9
3.2
Non-Port Pins .......................................................................................................................................... 10
3.3
Pin I/O Circuits and Recommended Connection of Unused Pins ................................................... 11
MEMORY SPACE ............................................................................................................................. 13
PERIPHERAL HARDWARE FUNCTION FEATURES ................................................................... 14
5.1
Port ............................................................................................................................................................ 14
5.2
Clock Generator ...................................................................................................................................... 15
5.3
Timer/Event Counter ............................................................................................................................... 15
5.4
A/D Converter .......................................................................................................................................... 18
5.5
Serial Interface ........................................................................................................................................ 18
5.6
VFD Controller/Driver ............................................................................................................................. 19
6.
INTERRUPT FUNCTIONS ............................................................................................................... 21
7.
STANDBY FUNCTION ..................................................................................................................... 24
8.
RESET FUNCTION ........................................................................................................................... 24
9.
MASK OPTION ................................................................................................................................. 24
10. INSTRUCTION SET .......................................................................................................................... 25
11. ELECTRICAL SPECIFICATIONS .................................................................................................... 28
12. PACKAGE DRAWING ...................................................................................................................... 42
13. RECOMMENDED SOLDERING CONDITIONS .............................................................................. 43
APPENDIX A. DEVELOPMENT TOOLS ............................................................................................... 44
APPENDIX B. RELATED DOCUMENTS .............................................................................................. 47
Data Sheet U13415EJ2V0DS
5
µPD780232
1. PIN CONFIGURATION (TOP VIEW)
• 80-pin plastic QFP (14 × 14)
FIP0
FIP1
FIP2
FIP3
FIP4
FIP5
FIP6
FIP7
FIP8
FIP9
FIP10
FIP11
FIP12
FIP13
FIP14
FIP15
FIP16
FIP17
FIP18
FIP19
µPD780232GC-×××-8BT
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
VDD1
VSS1
X1
X2
IC
RESET
P27/SCK1
P26/SI1
P25/SO1
P24/BUSY
P23
P22
P21/SO3
P20/SCK3
P00/INTP0
P01/INTP1
P02/TI
AVSS
ANI3
ANI2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
VLOAD
VDD2
FIP20
FIP21
FIP22
FIP23
FIP24/P30
FIP25/P31
FIP26/P32
FIP27/P33
FIP28/P34
FIP29/P35
FIP30/P36
FIP31/P37
FIP32/P40
FIP33/P41
FIP34/P42
FIP35/P43
FIP36/P44
FIP37/P45
ANI1
ANI0
VSS0
AVDD
VDD0
P64/FIP52
P63/FIP51
P62/FIP50
P61/FIP49
P60/FIP48
P57/FIP47
P56/FIP46
P55/FIP45
P54/FIP44
P53/FIP43
P52/FIP42
P51/FIP41
P50/FIP40
P47/FIP39
P46/FIP38
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Cautions 1. Connect directly the IC (Internally Connected) pin to VSS1.
2. Connect the AVDD pin to VDD1.
3. Connect the AVSS pin to VSS1.
Remark When the µPD780232 is used in application fields that require reduction of the noise from inside the
microcontroller, the implementation of noise reduction measures, such as supplying voltage to VDD0 and
VDD1 individually and connecting VSS0 and VSS1 to different ground lines, is recommended.
6
Data Sheet U13415EJ2V0DS
µPD780232
ANI0 to ANI3:
Analog input
P50 to P57:
AVDD:
Analog power supply
P60 to P64:
Port 6
AVSS:
Analog ground
RESET:
Reset
BUSY:
Busy
SCK1, SCK3: Serial clock
FIP0 to FIP52:
Fluorescent indicator panel
SI1:
Serial input
IC:
Internally connected
SO1, SO3:
Serial output
INTP0, INTP1
External interrupt input
TI:
Timer input
P00 to P02:
Port 0
VDD0 to VDD2:
Power supply
P20 to P27:
Port 2
VLOAD:
Negative power supply
P30 to P37:
Port 3
VSS0, VSS1:
Ground
P40 to P47:
Port 4
X1, X2:
Crystal
Data Sheet U13415EJ2V0DS
Port 5
7
µPD780232
2. BLOCK DIAGRAM
TI/P02
8-bit remote
controller
timer 9
Port 0
P00 to P02
Port 2
P20 to P27
Port 3
P30 to P37
Port 4
P40 to P47
Port 5
P50 to P57
Port 6
P60 to P64
8-bit timer 80
78K/0
CPU core
ROM
16 KB
8-bit timer 81
Watchdog timer
SCK3/P20
SO3/P21
Serial
interface
(2-wire mode)
FIP0 to FIP23
RAM
768 bytes
FIP24/P30 to
FIP31/P37
BUSY/P24
SO1/P25
SI1/P26
Serial
interface
(3-wire mode)
VFD
controller/
driver
SCK1/P27
ANI0 to ANI3
AVDD
INTP1/P01
8
FIP40/P50 to
FIP47/P57
FIP48/P60 to
FIP52/P64
A/D converter
(A/D1)
AVSS
INTP0/P00
FIP32/P40 to
FIP39/P47
VLOAD
VDD2
Interrupt
control
(INT)
VDD0,
VDD1
VSS0,
VSS1
VPP
Data Sheet U13415EJ2V0DS
System
control
RESET
X1
X2
µPD780232
3. PIN FUNCTIONS
3.1 Port Pins
Pin Name
P00
Function
I/O
Port 0.
3-bit I/O port.
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be specified
by software.
Input
Port 2.
Input
P01
P02
P20
After
I/O
I/O
P22, P23
P24
Function
INTP0
INTP1
TI
8-bit I/O port.
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be specified
by software.
P21
Alternate
Reset
SCK3
SO3
—
BUSY
P25
SO1
P26
SI1
P27
SCK1
P30 to P37
Output
Port 3.
P-ch open-drain 8-bit high-tolerance output port.
A pull-down resistor can be incorporated in 1-bit units to VLOAD by mask
option.
Output
FIP24 to FIP31
P40 to P47
Output
Port 4.
P-ch open-drain 8-bit high-tolerance output port.
A pull-down resistor can be incorporated in 1-bit units to VLOAD by mask
option.
Output
FIP32 to FIP39
P50 to P57
I/O
Port 5.
P-ch open-drain 8-bit high-tolerance I/O port.
Input/output can be specified in 1-bit units.
A pull-down resistor can be incorporated in 1-bit units by mask option
(Connection to VLOAD or VSS0 can be specified in 1-bit units).
Input
FIP40 to FIP47
P60 to P64
I/O
Port 6.
P-ch open-drain 5-bit high-tolerance I/O port.
Input/output can be specified in 1-bit units.
A pull-down resistor can be incorporated in 1-bit units by mask option
(Connection to VLOAD or VSS0 can be specified in 1-bit units).
Input
FIP48 to FIP52
Data Sheet U13415EJ2V0DS
9
µPD780232
3.2 Non-Port Pins
Pin Name
INTP0
I/O
Input
INTP1
Function
After
Reset
External interrupt request input for which the valid edge (rising edge,
falling edge, or both rising and falling edges) can be specified.
Input
Alternate
Function
P00
P01
TI
Input
8-bit remote control timer 9 (TM9) timer input
Input
P02
SCK3
I/O
Serial interface serial clock input/output
Input
P20
SO3
Output
Serial interface serial data output
Input
P21
BUSY
Input
Serial interface automatic transmit/receive busy signal input
Input
P24
SO1
Output
Serial interface serial data output
Input
P25
SI1
Input
Serial interface serial data input
Input
P26
SCK1
I/O
Serial interface serial clock input/output
Input
P27
FIP0 to FIP23
Output
VFD controller/driver high-tolerance large current output.
A pull-down resistor can be incorporated to VLOAD in 1-bit units by a mask
Output
FIP24 to FIP31
P30 to P37
option.
FIP32 to FIP39
—
P40 to P47
FIP40 to FIP47
VFD controller/driver high-tolerance large current output.
FIP48 to FIP52
A pull-down resistor can be incorporated in 1-bit units by a mask option
Input
P50 to P57
P60 to P64
(Connection to VLOAD or VSS0 can be specified in 1-bit units).
VLOAD
—
Connecting pull-down resistor for VFD controller/driver
—
—
RESET
Input
System reset input
—
—
X1
Input
Connecting crystal resonator for system clock oscillation
—
—
X2
ANI0 to ANI3
—
Input
A/D converter analog input
—
—
Input
—
AVDD
—
A/D converter analog power supply/reference voltage input.
Make the same potential as VDD1.
—
—
AVSS
—
A/D converter ground potential. Make the same potential as VSS1.
—
—
VDD0
—
Positive power supply for ports
—
—
VDD1
—
Positive power supply except for ports, analog block, and VFD controller/driver
—
—
VDD2
—
Positive power supply for VFD controller/driver
—
—
VSS0
—
Ground potential for ports
—
—
VSS1
—
Ground potential except for ports and analog block
—
—
IC
—
Internally connected. Connect directly to VSS1.
—
—
10
Data Sheet U13415EJ2V0DS
µPD780232
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The I/O circuit type of each pin and the recommended connection of unused pins are shown in Table 3-1.
For the I/O circuit configuration of each type, see Figure 3-1.
Table 3-1. Types of Pin I/O Circuits
Pin Name
P00/INTP0
I/O Circuit Type
8-C
I/O
I/O
Recommended Connection of Unused Pins
Input: Independently connect to VSS0 via a resistor.
P01/INTP1
Output: Leave open.
P02/TI
P20/SCK3
Input: Independently connect to VDD0 or VSS0 via a resistor.
P21/SO3
Output: Leave open.
P22, P23
P24/BUSY
P25/SO1
P26/SI1
P27/SCK1
P30/FIP24 to P37/FIP31
14-F
Output
Leave open.
15-D
I/O
Input: Independently connect to VDD0 or VSS0 via a resistor.
FIP0 to FIP23
14-F
Output
RESET
2
Input
ANI0 to ANI3
7
P40/FIP32 to P47/FIP39
P50/FIP40 to P57/FIP47
P60/FIP48 to P64/FIP52
AVDD
AVSS
Output: Leave open.
Leave open.
—
Connect to VDD0 or VSS0.
—
—
Connect to VDD1.
Connect to VSS1.
VLOAD
IC
Connect directly to VSS1.
Data Sheet U13415EJ2V0DS
11
µPD780232
Figure 3-1. Pin I/O Circuits
Type 14-F
Type 2
VDD0
VDD0
P-ch
IN
P-ch
OUT
Data
 Mask 
 option 
N-ch
Schmitt-triggered input with hysteresis characteristics
VLOAD
VSS0
Type 15-D
Type 7
VDD0
VDD0
P-ch
P-ch
IN/OUT
Data
IN
Comparator
P-ch
N-ch
N-ch
+
–
VSS0
VREF
(threshold voltage)
N-ch
RD
VSS0
Type 8-C
VDD0
Pullup
enable
P-ch
VDD0
Data
P-ch
IN/OUT
Output
disable
N-ch
VSS0
12
Data Sheet U13415EJ2V0DS
VSS0
 Mask 
 option 
VLOAD
µPD780232
4. MEMORY SPACE
The memory map of the µPD780232 is shown in Figure 4-1.
Figure 4-1. Memory Map
F F F FH
Special function registers (SFR)
256 × 8 bits
F F 0 0H
F E F F H General-purpose registers
FEE 0H
F ED F H
32 × 8 bits
Internal high-speed RAM
768 × 8 bits
FC 0 0 H
FB F FH
3 F F FH
Reserved
Program area
FA 7 0H
FA 6 FH
VFD display RAM
Data memory
space
112 × 8 bits
1 0 0 0H
0 F F FH
FA 0 0H
F 9 F FH
CALLF entry area
Reserved
0 8 0 0H
0 7 F FH
F 9E 0H
F 9D F H
Internal buffer RAM
Program area
32 × 8 bits
F 9C 0 H
F 9B FH
0 0 8 0H
0 0 7 FH
Reserved
4 0 0 0H
3 F F FH
Program memory
space
CALLT table area
Internal ROM
0 0 4 0H
0 0 3 FH
Vector table area
0 0 0 0H
0 0 0 0H
Data Sheet U13415EJ2V0DS
13
µPD780232
5. PERIPHERAL HARDWARE FUNCTION FEATURES
5.1 Port
There are three kinds of I/O ports.
• CMOS I/O (ports 0, 2):
11
• P-ch open-drain output (ports 3, 4): 16
• P-ch open-drain I/O (ports 5, 6):
Total:
13
40
Table 5-1. Port Functions
Name
Pin Name
Port 0
P00 to P02
Port 2
P20 to P27
Function
I/O port. Input/output can be specified in 1-bit units.
When used as an input port, an on-chip resistor can be specified by software.
I/O port. Input/output can be specified in 1-bit units.
When used as an input port, an on-chip resistor can be specified by software.
Port 3
P30 to P37
P-ch open-drain high-tolerance output port.
A pull-down resistor can be incorporated in 1-bit units to VLOAD by a mask option.
Port 4
P40 to P47
P-ch open-drain high-tolerance output port.
A pull-down resistor can be incorporated in 1-bit units to VLOAD by a mask option.
Port 5
P50 to P57
Port 6
P60 to P64
P-ch open-drain high-tolerance I/O port. Input/output can be specified in 1-bit units.
A pull-down resistor can be incorporated in 1-bit units by a mask option (Connection to VLOAD or
VSS0 can be specified in 1-bit units ).
P-ch open-drain high-tolerance I/O port. Input/output can be specified in 1-bit units.
A pull-down resistor can be incorporated in 1-bit units by a mask option (Connection to VLOAD or
VSS0 can be specified in 1-bit units).
14
Data Sheet U13415EJ2V0DS
µPD780232
5.2 Clock Generator
The minimum instruction execution time can be changed.
• 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs (@ 5.0 MHz operation with main system clock)
Figure 5-1. Clock Generator Block Diagram
Prescaler
X1
X2
Main system
clock oscillator
Clock to
peripheral hardware
Prescaler
fX
fX
2
fX
22
fX
23
fX
24
Selector
STOP
Standby
controller
CPU clock (fCPU)
5.3 Timer/Event Counter
Four timer/event counter channels are incorporated.
• 8-bit remote control timer: 1 channel
• 8-bit timer:
2 channels
• Watchdog timer:
1 channel
Table 5-2. Timer/Event Counter Operations
Operation Interval timer
mode
Function
Pulse width measurement
Interrupt source
8-Bit Remote Control Timer
8-Bit Timer
Watchdog Timer
—
2 channels
1 channel
1 input
—
—
3
2
1
Data Sheet U13415EJ2V0DS
15
µPD780232
Figure 5-2. Block Diagram of 8-Bit Remote Control Timer (TM9)
Internal bus
INTTM90
Noise
elimination
rising edge
detector
fX/26
fX/27
fX/28
Selector
TI/P02
8-bit capture register 90
(CP90)
1/2
8-bit timer counter 9
(TM9)
fX/29
INTTM92
INTTM91
Noise
elimination
falling edge
detector
8-bit capture register 91
(CP91)
Internal bus
fX
fX/22
fX/24
fX/26
Selector/controller
Figure 5-3. Block Diagram of 8-Bit Timer (TM80)
8-bit timer counter 80
(TM80)
Match
INTTM80
8-bit compare register 80
(CR80)
Internal bus
16
Data Sheet U13415EJ2V0DS
µPD780232
Selector/controller
Figure 5-4. Block Diagram of 8-Bit Timer (TM81)
fX/2
fX/23
fX/25
fX/27
8-bit timer counter 81
(TM81)
Match
INTTM81
8-bit compare register 81
(CR81)
Internal bus
Figure 5-5. Watchdog Timer Block Diagram
fX
fX/28
Clock
input
controller
Divided
clock
selector
Divider
Output
controller
INTWDT
RESET
RUN
Division mode
selector
3
WDT mode signal
OSTS2 OSTS1 OSTS0
Oscillation
stabilization time
selection register
(OSTS)
WDCS2 WDCS1 WDCS0
Watchdog timer
clock selection
register (WDCS)
RUN WDTM4 WDTM3
Watchdog timer
mode register
(WDTM)
Internal bus
Data Sheet U13415EJ2V0DS
17
µPD780232
5.4 A/D Converter
An 8-bit resolution 4-channel A/D converter is incorporated.
A/D conversion can be started by software only.
Figure 5-6. A/D Converter Block Diagram
ANI0
ANI1
ANI2
Selector
INTAD
Sample &
hold circuit
A/D conversion
result register
(ADCR0)
A/D converter
(8 bits)
ANI3
Internal bus
5.5 Serial Interface
Two clocked serial interface channels are incorporated.
Serial interface SIO1 operates in the 3-wire serial mode (with automatic transmit/receive function), in which MSB
first/LSB first switching is possible.
Serial interface SIO3 operates in the 2-wire serial mode (transmit only) in which the first bit is fixed to MSB.
Figure 5-7. Serial Interface SIO1 Block Diagram
Internal bus
Automatic data transmit/receive
address pointer (ADTP)
SI1/P26
Buffer RAM
Serial shift register 1 (SIO1)
Automatic data transmit/receive
transfer interval specification register
(ADTI)
Match
SO1/P25
5-bit counter
Handshake
controller
BUSY/P24
Serial clock counter
Serial clock controller
18
Data Sheet U13415EJ2V0DS
Interrupt request
signal generator
Selector
SCK1/P27
fX/22 to fX/24
INTCSI1
µPD780232
Figure 5-8. Serial Interface SIO3 Block Diagram
Internal bus
Serial shift register 3 (SIO3)
SO3/P21
Interrupt request
signal generator
Serial clock
controller
Selector
Serial
clock counter
SCK3/P20
INTCSI3
fX/22 to fX/24
5.6 VFD Controller/Driver
A VFD controller/driver with the following functions is incorporated.
(a) Total number of display outputs: 53. Output of 16 patterns is enabled.
(b) 112-byte display RAM is provided to enable display signal output by reading display data automatically (direct
memory access (DMA)).
(c) A port pin that is not used for VFD display can be used as an output port or an I/O port (except for FIP0 to
FIP23, which are VFD output-only pins).
(d) The luminance can be adjusted in 8 levels using display mode register 1 (DSPM1).
(e) Hardware taking into consideration the key scan application is incorporated.
(f)
Whether the key scan timing is inserted or not is selectable.
(g) A high-tolerance output buffer (VFD driver) that can drive the VFD directly is incorporated.
(h) VFD output pins can incorporate a pull-down resistor, set by a mask option.
Data Sheet U13415EJ2V0DS
19
µPD780232
Figure 5-9. VFD Controller/Driver Block Diagram
Internal bus
Display data memory
Display data selector
Display data latch
Port output latch
High-tolerance buffer
FIP0
20
FIP24/P30
Data Sheet U13415EJ2V0DS
FIP52/P64
µPD780232
6. INTERRUPT FUNCTIONS
There are 3 types of interrupt functions.
• Non-maskable: 1
• Maskable:
12
• Software:
1
Table 6-1. Interrupt Source List
Interrupt Source
Default
Type
PriorityNote 1
Name
Trigger
External
Nonmaskable
—
INTWDT
Watchdog timer overflow (when watchdog timer
mode 1 is selected)
Internal
Maskable
0
INTWDT
Watchdog timer overflow (when interval timer
mode is selected)
1
INTP0
Pin input edge detection
2
INTP1
3
INTTM90
Remote control timer input rising edge detection
4
INTTM91
Remote control timer input falling edge detection
000CH
5
INTTM92
Remote control timer overflow
000EH
6
INTKS
Key scan timing from VFD controller/driver
0010H
7
INTCSI1
Serial interface SIO1 transfer end
0012H
8
INTCSI3
Serial interface SIO3 transfer end
0014H
9
INTTM80
TM80 and CR80 match
0016H
10
INTTM81
TM81 and CR81 match
0018H
11
INTAD
A/D conversion end
—
BRK
BRK instruction execution
Software
Internal/
Vector
Table
Interrupt
Basic
Address
Configuration
TypeNote 2
0004H
(A)
(B)
External
0006H
(C)
0008H
Internal
000AH
(B)
001AH
—
003EH
(D)
Notes 1. Default Priority is the priority order when more than one maskable interrupt request is generated
simultaneously. 0 is the highest priority and 11 is the lowest.
2. Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 6-1.
Remark
Two watchdog timer interrupt sources (INTWDT) are available: a non-maskable interrupt and a
maskable interrupt (internal), either of which can be selected.
Data Sheet U13415EJ2V0DS
21
µPD780232
Figure 6-1. Basic Interrupt Function Configuration (1/2)
(A) Internal non-maskable interrupt
Internal bus
Priority
controller
Interrupt
request
Vector table
address generator
Standby release
signal
(B) Internal maskable interrupt
Internal bus
MK
Interrupt
request
IE
PR
ISP
Priority
controller
IF
Vector table
address generator
Standby release
signal
(C) External maskable interrupt (INTP0, INTP1)
Internal bus
External interrupt
rising/falling edge
enable register (EGP, EGN)
Internal
request
Edge
detector
MK
IE
IF
PR
Priority
controller
ISP
Vector table
address generator
Standby
release signal
22
Data Sheet U13415EJ2V0DS
µPD780232
Figure 6-1. Basic Interrupt Function Configuration (2/2)
(D) Software interrupt
Internal bus
Interrupt
request
Priority
controller
Data Sheet U13415EJ2V0DS
Vector table
address generator
23
µPD780232
7. STANDBY FUNCTION
The standby function is a function to reduce the current consumption. The following two types of standby functions
are available.
• HALT mode:
Halts the CPU operating clock and enables a reduction in the average current consumption by
intermittent operation with normal operation.
• STOP mode:
Halts the system clock oscillation. Halts all operations with the system clock and sets an ultralow power consumption state.
Figure 7-1. Standby Function
System clock
operation
Interrupt
request
HALT instruction
Interrupt
request
STOP instruction
STOP mode
(System clock
oscillation is stopped)
HALT mode
(Clock supply to CPU is stopped,
and oscillation is maintained)
8. RESET FUNCTION
The following two types of resetting methods are available.
• External reset by the RESET input
• Internal reset by watchdog timer loop detection
9. MASK OPTION
The mask options for the µPD780232 are shown in Table 9-1.
Table 9-1. Pin Mask Option Selection
Pin Name
24
Mask Option
FIP 0 to FIP23,
P30/FIP24 to P37/FIP31,
P40/FIP32 to P47/FIP39
An on-chip pull-down resistor can be specified for VLOAD in 1-bit units.
P50/FIP40 to P57/FIP47,
P60/FIP48 to P64/FIP52
An on-chip pull-down resistor can be specified for VLOAD or VSS0 in 1-bit units.
Data Sheet U13415EJ2V0DS
µPD780232
10. INSTRUCTION SET
(1) 8-bit instructions
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC,
ROLC, ROR4, ROL4, PUSH, POP, DBNZ
2nd Operand
#byte
A
rNote
sfr
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
XCH
saddr !addr16
PSW
[DE]
[HL]
1st Operand
A
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
r
MOV
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
1
None
ROR
ROL
RORC
ROLC
MOV
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
INC
DEC
B, C
DBNZ
sfr
MOV
MOV
saddr
MOV
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
!addr16
PSW
MOV
XCH
[HL+byte]
[HL+B] $addr16
[HL+C]
DBNZ
INC
DEC
MOV
MOV
MOV
[DE]
MOV
[HL]
MOV
[HL+byte]
[HL+B]
[HL+C]
MOV
PUSH
POP
ROR4
ROL4
X
MULU
C
DIVUW
Note Except r = A
Data Sheet U13415EJ2V0DS
25
µPD780232
(2) 16-bit instructions
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
2nd Operand
#word
AX
rpNote
sfrp
saddrp
!addr16
SP
None
1st Operand
AX
ADDW
SUBW
CMPW
rp
MOVW
MOVWNote
sfrp
MOVW
MOVW
saddrp
MOVW
MOVW
!addr16
SP
MOVW
XCHW
MOVW
MOVW
MOVW
MOVW
INCW
DECW
PUSH
POP
MOVW
MOVW
MOVW
Note Only when rp = BC, DE, HL
(3) Bit manipulation instructions
MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
2nd Operand
A.bit
sfr.bit
saddr.bit
PSW.bit
[HL].bit
CY
$addr16
None
1st Operand
A.bit
MOV1
BT
BF
BTCLR
SET1
CLR1
sfr.bit
MOV1
BT
BF
BTCLR
SET1
CLR1
saddr.bit
MOV1
BT
BF
BTCLR
SET1
CLR1
PSW.bit
MOV1
BT
BF
BTCLR
SET1
CLR1
[HL].bit
MOV1
BT
BF
BTCLR
SET1
CLR1
CY
26
MOV1
AND1
OR1
XOR1
MOV1
AND1
OR1
XOR1
MOV1
AND1
OR1
XOR1
MOV1
AND1
OR1
XOR1
MOV1
AND1
OR1
XOR1
Data Sheet U13415EJ2V0DS
SET1
CLR1
NOT1
µPD780232
(4) Call instruction/branch instructions
CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
2nd Operand
AX
!addr16
!addr11
[addr5]
$addr16
1st Operand
Basic instruction
BR
CALL
BR
CALLF
CALLT
Compound instruction
BR
BC
BNC
BZ
BNZ
BT
BF
BTCLR
DBNZ
(5) Other instructions
ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
Data Sheet U13415EJ2V0DS
27
µPD780232
11. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C)
Parameter
Supply voltage
Symbol
Conditions
Rating
Unit
–0.3 to +6.5
V
VLOAD
VDD – 45 to VDD + 0.3
V
AVDD
–0.3 to VDD + 0.3
V
VDD
AVSS
Input voltage
Output voltage
VI1
P00 to P02, P20 to P27, X1, X2, RESET
VI2
P50 to P57, P60 to P64
P-ch open drain
V
VDD – 45 to VDD + 0.3
V
VO1
–0.3 to VDD + 0.3
V
VDD – 45 to VDD + 0.3
V
AVSS to AVDD
V
–10
mA
VAN
ANI0 to ANI3
Output current, high
IOH
Per pin for P00 to P02 and P20 to P27
IOLNote 1
Analog input pins
Total for P00 to P02 and P20 to P27
–30
mA
Per pin for FIP0 to FIP23, P30 to P37, P40 to P47,
P50 to P57, and P60 to P64
–30
mA
Total for FIP0 to FIP23, P30 to P37, P40 to P47,
Peak value
–300
mA
P50 to P57, and P60 to P64
Per pin for P00 to P02 and P20 to P27
rms value
Peak value
–120
10
mA
mA
rms value
5
mA
Peak value
20
mA
Total for P00 to P02 and P20 to P27
rms value
PTNote 2
Total power
V
VO2
Analog input voltage
Output current, low
–0.3 to +0.3
–0.3 to VDD + 0.3
dissipation
10
mA
TA = –40 to +60°C
700
mW
TA = +60 to +85°C
500
mW
Operating ambient
temperature
TA
–40 to +85
°C
Storage temperature
Tstg
–40 to +150
°C
Caution
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product is
on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
Notes 1. The rms value should be calculated as follows: [rms value] = [Peak value] × √Duty
28
Data Sheet U13415EJ2V0DS
µPD780232
Total power dissipation PT [mW]
Notes 2. The allowable total power dissipation differs depending on the temperature (see the following figure).
800
600
500
400
200
–40
0
+40
+80
Temperature [˚C]
+85
How to calculate total power dissipation
The power consumption of the µPD780232 can be divided to the following three types. The sum of the three power
consumption types should be less than the total power dissipation PT (80% or less of ratings is recommended).
<1>
CPU power consumption: Calculate VDD (MAX.) × IDD (MAX.).
<2>
Output pin power consumption: Power consumption when maximum current flows to VFD output pins.
<3>
Pull-down resistor power consumption: Power consumption by the pull-down resistors incorporated in the VFD
output pins by a mask option.
The following shows how to calculate total power consumption for the example in Figure 11-1.
Example Assume the following conditions:
VDD = 5.5 V, 5.0 MHz oscillation
Supply current (IDD) = 21.0 mA
VFD output:
11 grids × 10 segments (blanking width = 1/16)
The maximum current at the grid pin is 15 mA.
The maximum current at the segment pin is 5 mA.
At the key scan timing, the VFD output pin is OFF.
VFD output voltage: Grids
VOD = VDD – 2 V (voltage drop of 2 V)
Segments VOD = VDD – 0.5 V (voltage drop of 0.5 V)
Fluorescent display control voltage (VLOAD) = –35 V
Mask option pull-down resistor = 35 kΩ
Data Sheet U13415EJ2V0DS
29
µPD780232
By placing the above conditions in calculations <1> to <3>, the total dissipation can be calculated.
<1> CPU power consumption: 5.5 V × 21.0 mA = 115.5 mW
<2> Output pin power consumption:
(VDD – VOD) ×
Grid
= 2V×
Number of grids + 1
15 mA × 11 grids
11 grids + 1
(VDD – VOD) ×
Segment
Total current value of each grid
= 0.5 V ×
× (1 –
1
16
× (1 – Blanking width)
) = 25.8 mW
Total segment current value of illuminated dots
Number of grids +1
5 mA × 31 dots
11 grids + 1
× (1 –
1
16
× (1 – Blanking width)
) = 6.1 mW
<3> Pull-down resistor power consumption:
(VOD – VLOAD)2
Grid
Pull-down resistor value
=
(5.5 V – 2 V – (–35 V))2
35 kΩ
(VOD – VLOAD)2
Segment
Pull-down resistor value
=
×
×
35 kΩ
× (1 – Blanking width)
Number of grids + 1
11 grids
11 grids + 1
× (1 –
1
16
) = 36.4 mW
Number of illuminated dots
×
(5.5 V – 0.5 V – (–35 V))2
Number of grids
Number of grids + 1
×
31 dots
11 grids + 1
× (1 –
1
16
× (1 – Blanking width)
) = 110.7 mW
Total power consumption = <1> + <2> + <3> = 115.5 + 25.8 + 6.1 + 36.4 + 110.7 = 294.5 mW
In this example, the total power consumption does not exceed the rating of the allowable total power dissipation,
so there is no problem in the power consumption.
However, when the total power consumption exceeds the rating of the total power dissipation, it is necessary to
lower the power consumption. To reduce the power consumption, reduce the number of pull-down resistors.
30
Data Sheet U13415EJ2V0DS
µPD780232
Figure 11-1. Display Example of 10 Segments-11 Digits
Display data memory
FA02H, FA01H, FA00H
0
0
0
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
T0
FA09H, FA08H, FA07H
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
T1
FA10H, FA0FH, FA0EH
0
0
0
1
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
T2
FA17H, FA16H, FA15H
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
T3
FA1EH, FA1DH, FA1CH
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
T4
FA25H, FA24H, FA23H
0
0
0
1
1
0
1
1
0
1
0
0
0
0
0
1
0
0
0
0
0
T5
FA2CH, FA2BH, FA2AH
0
0
0
1
1
0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
0
T6
FA33H, FA32H, FA31H
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
T7
FA3AH, FA39H, FA38H
0
1
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
T8
FA41H, FA40H, FA3FH
0
0
0
0
0
0
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
T9
FA48H, FA47H, FA46H
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
T10
(VFD output pin: 20 19 18 17 16 15 14 13 12 11 10
FIP0 to FIP20)
j
i h g f e d c b a
9
8
7
6
5
4
3
2
1
0
SUN
MON
TUE
WED
THU
FRI
SAT
a
i
AM
i
PM
j
0
j
j
1
2
3
4
5
6
Data Sheet U13415EJ2V0DS
7
8
9
f
g
b
e
d
c
h
10
31
µPD780232
System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 4.5 to 5.5 V)
Resonator
Recommended Circuit
Ceramic resonator
VSS1 X1 X2
C1
Crystal resonator
C2
VSS1 X1 X2
C1
C2
External clock
X1
Parameter
Oscillation frequency
(fX)Note 1
X2
µ PD74HCU04
Conditions
MIN. TYP. MAX. Unit
VDD = Oscillation
voltage range
1
Oscillation stabilization After VDD reaches
timeNote 2
the minimum value of
oscillation voltage range
Oscillation frequency
(fX)Note 1
1
Oscillation stabilization
timeNote 2
5
MHz
4
ms
5
MHz
10
ms
X1 input frequency
(fX)Note 1
1
5
MHz
X1 input high-/low-level
width (tXH/tXL)
85
450
ns
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP release.
Caution
When using the system clock oscillator, wire as follows in the area enclosed by the broken lines
in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS1.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
32
Data Sheet U13415EJ2V0DS
µPD780232
Recommended Oscillator Constant
System Clock: Ceramic Resonator (TA = –40 to +85°C)
Manufacturer
Murata Mfg.
Co., Ltd.
Part Number
Frequency
(MHz)
Recommended Circuit Constant
C1 (pF)
C2 (pF)
CSB 1000J
1.00
150
150
CSA2.00MG040
2.00
100
100
On-chip
On-chip
CST2.00MG040
CSA3.58MG
3.58
CST3.58MGW
30
30
On-chip
On-chip
30
30
On-chip
On-chip
30
30
On-chip
On-chip
Oscillation Voltage Range
MIN. (V)
4.5
MAX. (V)
5.5
CSTS0358MG06
CSA4.19MG
4.19
CST4.19MGW
CSTS0419MG06
CSA5.00MG
CST5.00MGW
5.00
CSTS0500MG03
Caution
The oscillator constant and oscillation voltage range indicate conditions of stable oscillation.
Oscillation frequency precision is not guaranteed. For applications requiring oscillation frequency precision, the oscillation must be adjusted on the implementation circuit. For details,
please contact directly the manufacturer of the resonator you will use.
Data Sheet U13415EJ2V0DS
33
µPD780232
Capacitance (TA = 25°C, VDD = VSS = 0 V)
Parameter
Input capacitance
Output capacitance
Symbol
CIN
COUT
Conditions
MIN.
TYP.
MAX.
Unit
f = 1 MHz
P00 to P02, P20 to P27
Unmeasured pins returned to 0 V P50 to P57, P60 to P64
15
pF
35
pF
f = 1 MHz
P00 to P02, P20 to P27
Unmeasured pins returned to 0 V P30 to P37, P40 to P47,
P50 to P57, P60 to P64,
15
pF
35
pF
15
pF
35
pF
MAX.
Unit
0.7VDD
VDD
V
FIP0 to FIP23
I/O
capacitance
CIO
f = 1 MHz
P00 to P02, P20 to P27
Unmeasured pins returned to 0 V P50 to P57, P60 to P64
DC Characteristics (TA = –40 to +85°C, VDD = 4.5 to 5.5 V)
Parameter
Input voltage, high
Input voltage, low
Output voltage, high
Symbol
Conditions
MIN.
VIH1
P00 to P02, P20 to P27, RESET
VIH2
P50 to P57, P60 to P64
0.7VDD
VDD
V
VIH3
X1, X2
VDD – 0.5
VDD
V
VIL1
P00 to P02, P20 to P27, RESET
0
0.2VDD
V
VIL2
X1, X2
0
0.4
V
VOH
IOH = –1 mA
VDD – 1.0
VDD
V
IOH = –100 µA
VDD – 0.5
VDD
V
Output voltage, low
VOL
P00 to P02, P20 to P27
IOL = 400 µA
Input leakage
current, high
ILIH1
P00 to P02, P20 to P27, P50 to P57, P60 to P64, RESET
VIN = VDD
ILIH2
X1, X2
ILIL1
P00 to P02, P20 to P27, RESET
ILIL2
X1, X2
ILIH3
P50 to P57, P60 to P64
VIN = VLOAD = VDD – 40 V
ILOH
P00 to P02, P20 to P27, P30 to P37,
P40 to P47, P50 to P57, P60 to P64
VOUT = VDD
VOUT = 0 V
Input leakage
current, low
Output leakage
current, high
TYP.
VIN = 0 V
0.5
V
3
µA
20
µA
–3
µA
–20
µA
–10
µA
3
µA
Output leakage
current, low
ILOL1
P00 to P02, P20 to P27
–3
µA
ILOL2
P30 to P37, P40 to P47, P50 to P57, P60 to P64 VOUT = VLOAD = VDD – 40 V
–10
µA
VFD output current
IOD
FIP0 to FIP19
–15
mA
–5
mA
VOD = VDD – 2 V
FIP20 to FIP52
Software pull-up
resistance
R1
P00 to P02, P20 to P27
On-chip mask option
pull-down resistance
(VSS0 connection)
R2
P50 to P57, P60 to P64
On-chip mask option
pull-down resistance
(VLOAD connection)
R3
FIP0 to FIP52
VOD – VLOAD
= 40 V
PCC = 00H
Power supply
currentNote
IDD1
5 MHz crystal oscillation operation mode
IDD2
5 MHz crystal oscillation HALT mode
IDD3
STOP mode
VIN = 0 V
10
30
100
kΩ
15
35
90
kΩ
30
60
135
kΩ
7
14
mA
1.5
4.5
mA
1
30
µA
Note Refers to the current flowing to the VDD pin. The current flowing to the on-chip pull-up and pull-down resistors is not included.
Remarks 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
2. PCC: Processor clock control register
34
Data Sheet U13415EJ2V0DS
µPD780232
AC Characteristics
(1) Basic operation (TA = –40 to +85°C, VDD = 4.5 to 5.5 V)
Parameter
Cycle time
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
32
µs
TCY
Operated with main system clock
0.4
Interrupt request
input high-/low-level
width
tINTH
tINTL
INTP0, INTP1
10
µs
RESET low-level
width
tRSL
10
µs
(minimum instruction
execution time)
TCY vs. VDD
60
Guaranteed operating range
30
Cycle time TCY (µs)
µ
10
2.0
1.0
0.5
0.4
0
1
2
3
4
5
6
Supply voltage VDD (V)
(2) Timer/counter (TA = –40 to +85°C, VDD = 4.5 to 5.5 V)
Parameter
TI input high-/
low-level width
Symbol
Conditions
MIN.
2/Fcount + 0.2Note
tTIH
tTIL
TYP.
MAX.
Unit
µs
Note FCOUNT is the frequency of the count clock selected by TM9 (the frequency can be selected from fX/26,
fX/27, fX/28, and fX/29).
Data Sheet U13415EJ2V0DS
35
µPD780232
(3) Serial interface (TA = –40 to +85°C, VDD = 4.5 to 5.5 V)
(a) Serial interface (3-wire serial mode)
(i)
3-wire serial mode (SCK1: Internal clock output)
Parameter
SCK1 cycle time
Symbol
Conditions
tKCY1
SCK1 high-/low-level tKH1
width
tKL1
MIN.
TYP.
MAX.
Unit
800
ns
tKCY1/2 – 50
ns
SI1 setup time
(to SCK1↑)
tSIK1
100
ns
SI1 hold time
(from SCK1↑)
tKSI1
400
ns
Delay time from SCK1↓ tKSO1
to SO1 output
C = 100 pFNote
300
ns
MAX.
Unit
Note C is the load capacitance of the SCK1 and SO1 output lines.
(ii) 3-wire serial mode (SCK1: External clock input)
Parameter
Symbol
Conditions
MIN.
TYP.
SCK1 cycle time
tKCY2
800
ns
SCK1 high-/low-
tKH2
400
ns
level width
tKL2
SI1 setup time
(to SCK1↑)
tSIK2
100
ns
SI1 hold time
tKSI2
400
ns
(from SCK1↑)
Delay time from SCK1↓ tKSO2
to SO1 output
SCK1 rise/fall time
C = 100 pFNote
tR2
tF2
Note C is the load capacitance of the SO1 output line.
36
Data Sheet U13415EJ2V0DS
300
ns
1
µs
µPD780232
(b) Serial interface (2-wire serial mode)
(i)
2-wire serial mode (SCK3…Internal clock output)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCK3 cycle time
tKCY3
800
ns
SCK3 high-/low-level
width
tKH3
tKL3
tKCY3/2 – 50
ns
Delay time from SCK3↓
to SO3 output
tKSO3
C = 100 pFNote
300
ns
MAX.
Unit
Note C is the load capacitance of the SCK3 and SO3 output lines.
(ii) 2-wire serial mode (SCK3…External clock input)
Parameter
Symbol
Conditions
MIN.
TYP.
SCK3 cycle time
tKCY4
800
ns
SCK3 high-/lowlevel width
tKH4
tKL4
400
ns
Delay time from SCK3↓
to SO3 output
tKSO4
SCK3 rise/fall time
C = 100 pFNote
tR4
300
ns
1
µs
tF4
Note C is the load capacitance of the SO3 output line.
Data Sheet U13415EJ2V0DS
37
µPD780232
AC Timing Test Points (Excluding X1 Input)
0.8VDD
0.8VDD
Test points
0.2VDD
0.2VDD
Clock Timing
1/fX
tXL
tXH
VDD – 0.5 V (MIN.)
X1 input
0.4 V (MAX.)
TI Timing
tTIL
tTIH
TI
38
Data Sheet U13415EJ2V0DS
µPD780232
Serial Transfer Timing
3-wire serial mode:
tKCY1, 2
tKL1, 2
tKH1, 2
tR2
tF2
SCK1
tSIK1, 2
SI1
tKSI1, 2
Input data
tKSO1, 2
SO1
Output data
2-wire serial mode:
tKCY3,4
tKL3,4
tR4
tKH3,4
tF4
SCK3
tKSO3,4
SO3
A/D Converter Characteristics (TA = –40 to +85°C, AVDD = VDD = 4.0 to 5.5 V, AVSS = VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
Resolution
Overall
errorNote 1
Conversion
timeNote 2
Analog input voltage
tCONV
14
VIAN
AVSS
TYP.
MAX.
Unit
8
bit
±1.0
%
µs
AVDD
V
Notes 1. Quantization error (±1/2LSB) is not included. This parameter is indicated as the ratio to the full-scale
value.
2. Set the A/D conversion time to 14 µs or more.
Data Sheet U13415EJ2V0DS
39
µPD780232
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C)
Parameter
Data retention
Symbol
Conditions
VDDDR
MIN.
TYP.
2.0
MAX.
Unit
5.5
V
30
µA
supply voltage
Data retention
supply current
IDDDR
Release signal
tSREL
0.1
µs
0
set time
Oscillation stabili-
tWAIT
zation wait time
Release by RESET
217/fX
ms
Release by interrupt request
Note
ms
Note 212/fX, 214/fX to 217/fX can be selected by bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time
select register (OSTS).
Data Retention Timing (STOP Mode Release by RESET)
Internal reset operation
HALT mode
STOP mode
Operating mode
Data retention mode
VDD
VDDDR
tSREL
STOP instruction execution
RESET
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Request Signal)
HALT mode
STOP mode
Operating mode
Data retention mode
VDD
VDDDR
tSREL
STOP instruction execution
Standby release signal
(interrupt request)
tWAIT
40
Data Sheet U13415EJ2V0DS
µPD780232
Interrupt Request Input Timing
tINTL
tINTH
INTP0, INTP1
RESET Input Timing
tRSL
RESET
Data Sheet U13415EJ2V0DS
41
µPD780232
12. PACKAGE DRAWING
80-PIN PLASTIC QFP (14x14)
A
B
60
61
41
40
detail of lead end
S
C
D
R
Q
80
1
21
20
F
J
G
H
I
M
P
K
S
N
S
L
M
NOTE
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
A
17.20±0.20
B
14.00±0.20
C
14.00±0.20
D
17.20±0.20
F
0.825
G
0.825
H
I
0.32±0.06
0.13
J
0.65 (T.P.)
K
1.60±0.20
L
0.80±0.20
M
0.17 +0.03
−0.07
N
P
0.10
1.40±0.10
Q
0.125±0.075
R
3° +7°
−3°
S
1.70 MAX.
P80GC-65-8BT-1
42
Data Sheet U13415EJ2V0DS
µPD780232
13. RECOMMENDED SOLDERING CONDITIONS
The µPD780232 should be soldered and mounted under the following recommended conditions.
For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting
Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact an NEC sales representative.
Table 13-1. Surface Mounting Type Soldering Conditions
µPD780232GC-×××-8BT: 80-pin plastic QFP (14 × 14)
Soldering
Soldering Conditions
Recommended Method
Condition Symbol
Infrared reflow
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or
higher), Count: Two times or less
IR35-00-2
VPS
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or
higher), Count: Two times or less
VP15-00-2
Wave soldering
Solder bath temperature: 260°C max., Time: 10 seconds max., Count: once,
WS60-00-1
Preheating temperature: 120°C max. (package surface temperature)
Partial heating
Caution
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
—
Do not use different soldering methods together (except for partial heating).
Data Sheet U13415EJ2V0DS
43
µPD780232
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the µPD780232.
Also refer to (6) Notes on using development tools.
(1) Software Package
SP78K0
Software package common to 78K/0 Series
(2) Language Processing Software
RA78K0
Assembler package common to 78K/0 Series
CC78K0
C compiler package common to 78K/0 Series
DF780233
Device file for µPD780232 Subseries
CC78K0-L
C compiler library source file common to 78K/0 Series
(3) Flash Memory Writing Tools
Flashpro III
(FL-PR3, PG-FP3)
Dedicated flash programmer for on-chip flash memory microcontrollers
FA-80GC
Adapter for flash memory writing. Used by connecting to Flashpro III.
• For 80-pin plastic QFP (GC-8BT type)
(4) Debugging Tools
• When in-circuit emulator IE-78K0-NS(-A) is used
IE-78K0-NS(-A)
In-circuit emulator common to 78K/0 Series
IE-70000-MC-PS-B
Power supply unit for IE-78K0-NS
IE-78K0-NS-PA
Performance board to enhance/extend the functions of the IE-78K0-NS
IE-70000-98-IF-C
Adapter required when PC-9800 series (except notebook type) is used as host machine (C bus supported)
IE-70000-CD-IF-A
PC card and interface cable required when notebook-type PC is used as host machine (PCMCIA socket supported)
IE-70000-PC-IF-C
Adapter required when IBM PC/AT™ compatible is used as host machine (ISA bus supported)
IE-70000-PCI-IF-A
Adapter required when PC incorporating PCI bus is used as host machine
IE-780233-NS-EM4,
IE-78K0-NS-P01
Emulation board and I/O board to emulate the µPD780232 Subseries
NP-80GC
NP-80GC-TQ
NP-H80GC-TQ
Emulation probe for 80-pin plastic QFP (GC-8BT type)
EV-9200GC-80
Conversion socket to connect the NP-80GC and the target system board on which 80-pin plastic
QFP (GC-8BT type) can be mounted
TGC-080SBP
Conversion adapter to connect the NP-80GC-TQ or NP-H80GC-TQ and the target system board
on which 80-pin plastic QFP (GC-8BT type) can be mounted
ID78K0-NS
Integrated debugger for IE-78K0-NS
SM78K0
System simulator common to 78K/0 Series
DF780233
Device file for µPD780232 Subseries
44
Data Sheet U13415EJ2V0DS
µPD780232
• When in-circuit emulator IE-78001-R-A is used
IE-78001-R-A
In-circuit emulator common to 78K/0 Series
IE-70000-98-IF-C
Adapter required when PC-9800 series (except notebook type) is used as host machine
(C bus supported)
IE-70000-PC-IF-C
Adapter required when IBM PC/AT compatible is used as host machine (ISA bus supported)
IE-70000-PCI-IF-A
Adapter required when PC incorporating PCI bus is used as host machine
IE-70000-R-SV3
Interface adapter and cable required when EWS is used as host machine
IE-780233-NS-EM4,
IE-78K0-NS-P01
Emulation board and I/O board to emulate the µPD780232 Subseries
IE-78K0-R-EX1
Emulation probe conversion board required when using IE-780232-NS-EM1 on IE-78001-R-A
EP-78230GC-R
Emulation probe for 80-pin plastic QFP (GC-8BT type)
EV-9200GC-80
Conversion socket to connect the EP-78230GC-R and the target system board on which 80-pin
plastic QFP (GC-8BT type) can be mounted
ID78K0
Integrated debugger for IE-78001-R-A
SM78K0
System simulator common to 78K/0 Series
DF780233
Device file for µPD780232 Subseries
(5) Real-Time OSs
RX78K0
Real-time OS for 78K/0 Series
MX78K0
OS for 78K/0 Series
Data Sheet U13415EJ2V0DS
45
µPD780232
(6) Notes on using development tools
• The ID78K0-NS, ID78K0, and SM78K0 are used in combination with the DF780233.
• The CC78K0 and RX78K0 are used in combination with the RA78K0 and DF780233.
• The FL-PR3, FA-80GC, NP-80GC, NP-80GC-TQ, and NP-H80GC-TQ are products of Naito Densei Machida
Mfg. Co., Ltd (+81-45-475-4191).
• The TGK-080SBP is a product made by TOKYO ELETECH CORPORATION.
For further information, contact: Daimaru Kogyo, Ltd.
Tokyo Electronics Department (TEL +81-3-3820-7112)
Osaka Electronics Department (TEL +81-6-6244-6672)
• For third-party development tools, see the Single-Chip Microcontroller Development Tool Selection Guide
(U11069E).
• The host machines and OS suitable for each software are as follows:
Host Machine
[OS]
PC
EWS
HP9000 series 700™ [HP-UX™]
SPARCstation™ [SunOS™, Solaris™]
Software
PC-9800 series [Japanese Windows™]
IBM PC/AT compatibles
[Japanese/English Windows]
RA78K0
√Note
√
CC78K0
√Note
√
ID78K0-NS
√
—
ID78K0
√
—
SM78K0
√
—
RX78K0
√Note
√
MX78K0
√Note
√
Note DOS-based software
46
Data Sheet U13415EJ2V0DS
µPD780232
APPENDIX B. RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
Documents Related to Devices
Document Name
Document No.
µPD780232 Subseries User’s Manual
U13364E
µPD780232 Data Sheet
This manual
µPD78F0233 Data Sheet
U13322E
78K/0 Series Instructions User's Manual
U12326E
78K/0, 78K/0S Series Flash Memory Write Application Note
U14458E
Documents Related to Development Tools (User’s Manuals)
Document Name
RA78K0 Assembler Package
CC78K0 C Compiler
Document No.
Operation
U14445E
Language
U14446E
Structured Assembly Language
U11789E
Operation
U14297E
Language
U14298E
PG-FP3 Flash Memory Programmer
U13502E
IE-78K0-NS In-Circuit Emulator
U13731E
IE-78K0-NS-A In-Circuit Emulator
U14889E
IE-78001-R-A In-Circuit Emulator
U14142E
IE-78K0-R-EX1 In-Circuit Emulator
To be prepared
IE-780233-NS-EM4 Emulation Board
U14666E
EP-78230 Emulation Probe
EEU-1515
SM78K0S, SM78K0 System Simulator
Ver. 2.10 or Later Windows Based
Operation
U14611E
SM78K Series System Simulator Ver. 2.10 or Later
External Parts User Open
Interface Specifications
U15006E
ID78K0-NS Integrated Debugger Ver. 2.00 or Later
Windows Based
Operation
U14379E
ID78K0-NS, ID78K0S-NS Integrated Debugger
Ver. 2.20 or Later Windows Based
Operation
U14910E
ID78K0 Integrated Debugger Windows Based
Guide
U11649E
Reference
U11539E
Data Sheet U13415EJ2V0DS
47
µPD780232
Documents Related to Embedded Software (User’s Manuals)
Document Name
78K/0 Series Real-time OS
78K/0 Series OS MX78K0
Document No.
Fundamentals
U11537E
Installation
U11536E
Fundamentals
U12257E
Other Documents
Document Name
Document No.
SEMICONDUCTOR SELECTION GUIDE - Products & Package - (CD-ROM)
X13769E
Semiconductor Device Mounting Technology Manual
C10535E
Quality Grades on NEC Semiconductor Devices
C11531E
NEC Semiconductor Device Reliability/Quality Control System
C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
C11892E
Caution
The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.
48
Data Sheet U13415EJ2V0DS
µPD780232
[MEMO]
Data Sheet U13415EJ2V0DS
49
µPD780232
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
FIP and IEBus are trademarks of NEC Corporation.
Windows is either a registered trademark or trademark of Microsoft Corporation in the United States and/or
other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
50
Data Sheet U13415EJ2V0DS
µPD780232
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Velizy-Villacoublay, France
Tel: 01-3067-5800
Fax: 01-3067-5899
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Madrid Office
Madrid, Spain
Tel: 091-504-2787
Fax: 091-504-2860
Novena Square, Singapore
Tel: 253-8311
Fax: 250-3583
NEC Electronics (France) S.A.
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Taiwan Ltd.
NEC Electronics Italiana s.r.l.
NEC Electronics (Germany) GmbH
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division
Guarulhos-SP, Brasil
Tel: 11-6462-6810
Fax: 11-6462-6829
J01.2
Data Sheet U13415EJ2V0DS
51
µPD780232
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
• The information in this document is current as of February, 2001. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
• NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
• While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
• NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00.4